MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C - MAY 2007 - REVISED MARCH 2011 D Low Supply-Voltage Range, 1.8 V to 3.6 V D Ultra-Low Power Consumption: D D D D D D D D D - Active Mode: 280 A at 1 MHz, 2.2 V - Standby Mode: 1.1 A - Off Mode (RAM Retention): 0.2 A Five Power-Saving Modes Wake-Up From Standby Mode in Less Than 6 s 16-Bit RISC Architecture, 62.5-ns Instruction Cycle Time Three or Four 16-Bit Sigma-Delta Analog-to-Digital (A/D) Converters With Differential PGA Inputs 16-Bit Timer_B With Three Capture/Compare-With-Shadow Registers 16-Bit Timer_A With Three Capture/Compare Registers On-Chip Comparator Four Universal Serial Communication Interfaces (USCI) - USCI_A0 and USCI_A1 - Enhanced UART Supporting Auto-Baudrate Detection - IrDA Encoder and Decoder - Synchronous SPI - USCI_B0 and USCI_B1 - I2C - Synchronous SPI Integrated LCD Driver With Contrast Control For Up To 160 Segments D 32-Bit Hardware Multiplier D Brownout Detector D Supply Voltage Supervisor/Monitor With D D D D D Programmable Level Detection Serial Onboard Programming, No External Programming Voltage Needed Programmable Code Protection by Security Fuse Bootstrap Loader On Chip Emulation Module Family Members Include: MSP430F4783: 48KB + 256B Flash 2KB RAM 3 Sigma-Delta ADCs MSP430F4793: 60KB + 256B Flash 2.5KB RAM 3 Sigma-Delta ADCs MSP430F4784: 48KB + 256B Flash 2KB RAM 4 Sigma-Delta ADCs MSP430F4794: 60KB + 256B Flash 2.5KB RAM 4 Sigma-Delta ADCs MSP430F47x3 and MSP430F47x4 Available In 100-Pin Plastic Quad Flatpack (QFP) Package For Complete Module Descriptions, See the MSP430x4xx Family User's Guide, Literature Number SLAU056 description The Texas Instruments MSP430 family of ultra-low power microcontrollers consists of several devices featuring different sets of peripherals targeted for various applications. The architecture, combined with five low-power modes is optimized to achieve extended battery life in portable measurement applications. The device features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency. The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 6s. The MSP430F47xx series are microcontroller configurations targeted to single phase electricity meters with three or four 16-bit sigma-delta A/D converters. Each channel has a differential input pair and programmable input gain. Also integrated are two 16-bit timers, three universal serial communication interfaces (USCI), 72 I/O pins, and a liquid crystal driver (LCD) with integrated contrast control. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. These devices have limited built-in ESD protection. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright (c) 2011, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C - MAY 2007 - REVISED MARCH 2011 AVAILABLE OPTIONS PACKAGED DEVICES TA PLASTIC 100-PIN QFP (PZ) -40C to 85C MSP430F4783IPZ MSP430F4793IPZ MSP430F4784IPZ MSP430F4794IPZ DEVELOPMENT TOOL SUPPORT All MSP430 microcontrollers include an Embedded Emulation Module (EEM) allowing advanced debugging and programming through easy to use development tools. Recommended hardware options include the following: D Debugging and Programming Interface - MSP-FET430UIF (USB) - MSP-FET430PIF (Parallel Port) D Debugging and Programming Interface with Target Board - MSP-FET430U100 D Production Programmer - 2 MSP-GANG430 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C - MAY 2007 - REVISED MARCH 2011 pin designation, MSP430F47xxIPZ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 MSP430F47x4IPZ P2.4/UCA0TXD/UCA0SIMO P2.5/UCA0RXD/UCA0SOMI P2.6/CAOUT P2.7 P3.0/UCB0STE/UCA0CLK P3.1/UCB0SIMO/UCB0SDA P3.2/UCB0SOMI/UCB0SCL P3.3/UCB0CLK/UCA0STE P3.4 P3.5 P3.6 P3.7 P4.0/UCA1TXD/UCA1SIMO P4.1/UCA1RXD/UCA1SOMI DVSS2 DVCC2 LCDCAP/R33 P5.7/R23 P5.6/LCDREF/R13 P5.5/R03 P5.4/COM3 P5.3/COM2 P5.2/COM1 COM0 P4.2/UCB1STE/UCA1CLK/S39 P9.3/S14 P9.2/S15 P9.1/S16 P9.0/S17 P8.7/S18 P8.6/S19 P8.5/S20 P8.4/S21 P8.3/S22 P8.2/S23 P8.1/S24 P8.0/S25 P7.7/S26 P7.6/S27 P7.5/S28 P7.4/S29 P7.3/S30 P7.2/S31 P7.1/S32 P7.0/S33 P4.7/S34 P4.6/S35 P4.5/UCB1CLK/UCA1STE/S36 P4.4/UCB1SOMI/UCB1SCL/S37 P4.3/UCB1SIMO/UCB1SDA/S38 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 DVCC1 A0.0+ A0.0- A1.0+ A1.0- A2.0+ A2.0- XIN XOUT VREF NC P5.1/S0 S1 P10.7/S2 P10.6/S3 P10.5/S4 P10.4/S5 P10.3/S6 P10.2/S7 P10.1/S8 P10.0/S9 P9.7/S10 P9.6/S11 P9.5/S12 P9.4/S13 82 81 80 79 78 77 76 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 AVCC DVSS1 AVSS1 A3.0- A3.0+ P5.0/SVSIN RST/NMI TCK TMS TDI/TCLK TDO/TDI XT2IN XT2OUT P1.0/TA0 P1.1/TA0/MCLK P1.2/TA1 P1.3/TBOUTH/SVSOUT P1.4/TBCLK/SMCLK P1.5/TACLK/ACLK P1.6/CA0 P1.7/CA1 P2.0/TA2 P2.1/TB0 P2.2/TB1 P2.3/TB2 PZ PACKAGE (TOP VIEW) A3+ and A3- are not connected in MSP430x47x3 devices. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 3 MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C - MAY 2007 - REVISED MARCH 2011 MSP430F47x3 functional block diagram XIN XT2IN XOUT XT2OUT 2 2 Oscillators FLL+ DVCC1/2 DVSS1/2 AVCC AVSS P1.x/P2.x 2x8 SD16_A (w/o BUF) 3 Sigma- Delta A/D Converter ACLK SMCLK MCLK Flash_A RAM 60kB 48kB 2.5kB 2.0kB P3.x/P4.x P5.x 3x8 P7.x/P8.x P9.x/P10.x 4x8/2x16 Ports P1/P2 Comparator _A Ports Ports P3/P4 P7/P8 2x8 I/O P5 P9/P10 Interrupt capability & 3x8 I/O with 4x8/2x16 I/O pull-up/down pull-up/down pull-up/down Resistors Resistors Resistors MAB 16MHz CPU incl. 16 Registers MDB Emulation (2 BP) Brownout Protection JTAG Interface SVS/SVM Hardware Multiplier (32x32) MPY, MPYS, MAC, MACS Timer_B3 Watchdog WDT+ 15/16-Bit LCD_A Timer_A3 3 CC Registers 3 CC Registers, Shadow Reg Basic Timer 160 Segments 1,2,3,4 Mux USCI_A0 (UART/LIN, IrDA, SPI) USCI_A1 (UART/LIN, IrDA, SPI) USCI_B0 (SPI, I2C) USCI_B1 (SPI, I2C) P3.x/P4.x P5.x 3x8 P7.x/P8.x P9.x/P10.x 4x8/2x16 RST/NMI MSP430F47x4 functional block diagram XIN XT2IN XOUT XT2OUT 2 2 Oscillators FLL+ DVCC1/2 AVSS P1.x/P2.x SD16_A (w/o BUF) 4 Sigma- Delta A/D Converter ACLK SMCLK Flash_A RAM 60kB 48kB 2.5kB 2.0kB Ports P1/P2 Comparator _A Ports P7/P8 P9/P10 USCI_A0 (UART/LIN, IrDA, SPI) USCI_A1 (UART/LIN, IrDA, SPI) USCI_B0 (SPI, I2C) USCI_B1 (SPI, I2C) 2x8 I/O Interrupt capability & 3x8 I/O with 4x8/2x16 I/O pull-up/down pull-up/down pull-up/down Resistors Resistors Resistors MDB Brownout Protection SVS/SVM Hardware Multiplier (32x32) MPY, MPYS, MAC, MACS Timer_B3 Watchdog WDT+ 15/16-Bit LCD_A Timer_A3 3 CC Registers 3 CC Registers, Shadow Reg Basic Timer RST/NMI 4 Ports P3/P4 P5 MAB Emulation (2 BP) JTAG Interface AVCC 2x8 MCLK 16MHz CPU incl. 16 Registers DVSS1/2 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 160 Segments 1,2,3,4 Mux MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C - MAY 2007 - REVISED MARCH 2011 Terminal Functions TERMINAL NAME NO. I/O DESCRIPTION DVCC1 1 A0.0+ 2 I Digital supply voltage, positive terminal. SD16_A positive analog input A0.0 (see Note 1) A0.0- 3 I SD16_A negative analog input A0.0 (see Note 1) A1.0+ 4 I SD16_A positive analog input A1.0 (see Note 1) A1.0- 5 I SD16_A negative analog input A1.0 (see Note 1) A2.0+ 6 I SD16_A positive analog input A2.0 (see Note 1) A2.0- 7 I SD16_A negative analog input A2.0 (see Note 1) XIN 8 I Input port for crystal oscillator XT1. Standard or watch crystals can be connected. XOUT 9 O Output terminal of crystal oscillator XT1 VREF 10 I/O Input for an external reference voltage / Internal reference voltage output (can be used as mid-voltage) NC 11 P5.1/S0 12 I/O Internally not connected. Can be connected to VSS. General-purpose digital I/O / LCD segment output 0 S1 13 O LCD segment output 1 P10.7/S2 14 I/O General-purpose digital I/O / LCD segment output 2 P10.6/S3 15 I/O General-purpose digital I/O / LCD segment output 3 P10.5/S4 16 I/O General-purpose digital I/O / LCD segment output 4 P10.4/S5 17 I/O General-purpose digital I/O / LCD segment output 5 P10.3/S6 18 I/O General-purpose digital I/O / LCD segment output 6 P10.2/S7 19 I/O General-purpose digital I/O / LCD segment output 7 P10.1/S8 20 I/O General-purpose digital I/O / LCD segment output 8 P10.0/S9 21 I/O General-purpose digital I/O / LCD segment output 9 P9.7/S10 22 I/O General-purpose digital I/O / LCD segment output 10 P9.6/S11 23 I/O General-purpose digital I/O / LCD segment output 11 P9.5/S12 24 I/O General-purpose digital I/O / LCD segment output 12 P9.4/S13 25 I/O General-purpose digital I/O / LCD segment output 13 P9.3/S14 26 I/O General-purpose digital I/O / LCD segment output 14 P9.2/S15 27 I/O General-purpose digital I/O / LCD segment output 15 P9.1/S16 28 I/O General-purpose digital I/O / LCD segment output 16 P9.0/S17 29 I/O General-purpose digital I/O / LCD segment output 17 P8.7/S18 30 I/O General-purpose digital I/O / LCD segment output 18 P8.6/S19 31 I/O General-purpose digital I/O / LCD segment output 19 P8.5/S20 32 I/O General-purpose digital I/O / LCD segment output 20 P8.4/S21 33 I/O General-purpose digital I/O / LCD segment output 21 P8.3/S22 34 I/O General-purpose digital I/O / LCD segment output 22 P8.2/S23 35 I/O General-purpose digital I/O / LCD segment output 23 P8.1/S24 36 I/O General-purpose digital I/O / LCD segment output 24 P8.0/S25 37 I/O General-purpose digital I/O / LCD segment output 25 P7.7/S26 38 I/O General-purpose digital I/O / LCD segment output 26 P7.6/S27 39 I/O General-purpose digital I/O / LCD segment output 27 P7.5/S28 40 I/O General-purpose digital I/O / LCD segment output 28 P7.4/S29 41 I/O General-purpose digital I/O / LCD segment output 29 P7.3/S30 42 I/O General-purpose digital I/O / LCD segment output 30 NOTE 1: Open connection recommended for all unused analog inputs. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 5 MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C - MAY 2007 - REVISED MARCH 2011 Terminal Functions (Continued) TERMINAL NAME NO. I/O DESCRIPTION P7.2/S31 43 I/O General-purpose digital I/O / LCD segment output 31 P7.1/S32 44 I/O General-purpose digital I/O / LCD segment output 32 P7.0/S33 45 I/O General-purpose digital I/O / LCD segment output 33 P4.7/S34 46 I/O General-purpose digital I/O / LCD segment output 34 P4.6/S35 47 I/O General-purpose digital I/O / LCD segment output 35 P4.5/ UCB1CLK/UCA1STE/ S36 48 I/O General-purpose digital I/O / USCI_B1 clock input/output / USCI_A1 slave transmit enable / LCD segment output 36 P4.4/ UCB1SOMI/UCB1SCL/ S37 49 I/O General-purpose digital I/O / USCI_B1 slave out/master in in SPI mode, SCL I2C clock in I2C mode / LCD segment output 37 P4.3/ UCB1SIMO/UCB1SDA/ S38 50 I/O General-purpose digital I/O / USCI_B1 slave in/master out in SPI mode, SDA I2C data in I2C mode / LCD segment output 38 P4.2/ UCB1STE/UCA1CLK/ S39 51 I/O General-purpose digital I/O / USCI_B1 slave transmit enable / USCI_A1 clock input/output / LCD segment output 39 COM0 52 O COM0-3 are used for LCD backplanes. P5.2/COM1 53 I/O General-purpose digital I/O / common output, COM0-3 are used for LCD backplanes. P5.3/COM2 54 I/O General-purpose digital I/O / common output, COM0-3 are used for LCD backplanes. P5.4/COM3 55 I/O General-purpose digital I/O / common output, COM0-3 are used for LCD backplanes. P5.5/R03 56 I/O General-purpose digital I/O / Input port of lowest analog LCD level (V5) P5.6/LCDREF/R13 57 I/O General-purpose digital I/O / External reference voltage input for regulated LCD voltage / Input port of third most positive analog LCD level (V4 or V3) P5.7/R23 58 I/O General-purpose digital I/O / Input port of second most positive analog LCD level (V2) LCDCAP/R33 59 I DVCC2 60 Digital supply voltage, positive terminal. DVSS2 61 Digital supply voltage, negative terminal. P4.1/ UCA1RXD/UCA1SOMI 62 I/O General-purpose digital I/O / USCI_A1 receive data input in UART mode, slave out/master in in SPI mode P4.0/ UCA1TXD/UCA1SIMO 63 I/O General-purpose digital I/O / USCI_A1 transmit data output in UART mode, slave in/master out in SPI mode P3.7 64 I/O General-purpose digital I/O P3.6 65 I/O General-purpose digital I/O P3.5 66 I/O General-purpose digital I/O P3.4 67 I/O General-purpose digital I/O P3.3/ UCB0CLK/UCA0STE 68 I/O General-purpose digital I/O / USCI_B0 clock input/output / USCI_A0 slave transmit enable P3.2/ UCB0SOMI/UCB0SCL 69 I/O General-purpose digital I/O / USCI_B1 slave out/master in in SPI mode, SCL I2C clock in I2C mode P3.1/ UCB0SIMO/UCB0SDA 70 I/O General-purpose digital I/O / USCI_B1 slave in/master out in SPI mode, SDA I2C data in I2C mode P3.0/ UCB0STE/UCA0CLK 71 I/O General-purpose digital I/O / USCI_B0 slave transmit enable / USCI_A0 clock input/output P2.7 72 I/O General-purpose digital I/O P2.6/CAOUT 73 I/O General-purpose digital I/O / Comparator_A output 6 LCD Capacitor connection / Input/output port of most positive analog LCD level (V1) POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C - MAY 2007 - REVISED MARCH 2011 Terminal Functions (Continued) TERMINAL NAME NO. I/O DESCRIPTION P2.5/ UCA0RXD/UCA0SOMI 74 I/O General-purpose digital I/O / USCI_A0 receive data input in UART mode, slave out/master in in SPI mode P2.4/ UCA0TXD/UCA0SIMO 75 I/O General-purpose digital I/O / USCI_A0 transmit data output in UART mode, slave in/master out in SPI mode P2.3/TB2 76 I/O General-purpose digital I/O / Timer_B3 CCR2. Capture: CCI2A/CCI2B input, compare: Out2 output P2.2/TB1 77 I/O General-purpose digital I/O / Timer_B3 CCR1. Capture: CCI1A/CCI1B input, compare: Out1 output P2.1/TB0 78 I/O General-purpose digital I/O / Timer_B3 CCR0. Capture: CCI0A/CCI0B input, compare: Out0 output P2.0/TA2 79 I/O General-purpose digital I/O / Timer_A Capture: CCI2A input, compare: Out2 output P1.7/CA1 80 I/O General-purpose digital I/O / Comparator_A input P1.6/CA0 81 I/O General-purpose digital I/O / Comparator_A input P1.5/TACLK/ ACLK 82 I/O General-purpose digital I/O / Timer_A, clock signal TACLK input / ACLK output (divided by 1, 2, 4, or 8) P1.4/TBCLK/ SMCLK 83 I/O General-purpose digital I/O / input clock TBCLK--Timer_B3 / submain system clock SMCLK output P1.3/TBOUTH/ SVSOUT 84 I/O General-purpose digital I/O / switch all PWM digital output ports to high impedance--Timer_B3 TB0 to TB2 / SVS: output of SVS comparator P1.2/TA1 85 I/O General-purpose digital I/O / Timer_A, Capture: CCI1A input, compare: Out1 output P1.1/TA0/MCLK 86 I/O General-purpose digital I/O / Timer_A. Capture: CCI0B input / MCLK output. Note: TA0 is only an input on this pin / BSL receive P1.0/TA0 87 I/O General-purpose digital I/O / Timer_A. Capture: CCI0A input, compare: Out0 output / BSL transmit XT2OUT 88 O Output terminal of crystal oscillator XT2 XT2IN 89 I Input port for crystal oscillator XT2. Only standard crystals can be connected. TDO/TDI 90 I/O TDI/TCLK 91 I Test data input or test clock input. The device protection fuse is connected to TDI/TCLK. TMS 92 I Test mode select. TMS is used as an input port for device programming and test. TCK 93 I Test clock. TCK is the clock input port for device programming and test. RST/NMI 94 I Reset input or nonmaskable interrupt input port P5.0/SVSIN 95 I/O A3.0+ (MSP430x47x4 only) 96 I SD16_A positive analog input A3.0 (see Note 2) Not connected in MSP430x47x3 devices, open connection recommended. A3.0- (MSP430x47x4 only) 97 I SD16_A negative analog input A3.0 (see Note 2) Not connected in MSP430x47x3 devices, open connection recommended. AVSS 98 Analog supply voltage, negative terminal. DVSS1 99 Digital supply voltage, negative terminal. AVCC 100 Analog supply voltage, positive terminal. Must not power up prior to DVCC1/DVCC2. Test data output port. TDO/TDI data output or programming data input terminal General-purpose digital I/O / analog input to supply voltage supervisor NOTE 2: Open connection recommended for all unused analog inputs. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 7 MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C - MAY 2007 - REVISED MARCH 2011 short-form description CPU The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations, other than program-flow instructions, are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand. Program Counter PC/R0 Stack Pointer SP/R1 Status Register SR/CG1/R2 Constant Generator The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to-register operation execution time is one cycle of the CPU clock. Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and constant generator respectively. The remaining registers are general-purpose registers. Peripherals are connected to the CPU using data, address, and control buses, and can be handled with all instructions. instruction set The instruction set consists of 51 instructions with three formats and seven address modes. Each instruction can operate on word and byte data. Table 1 shows examples of the three types of instruction formats; the address modes are listed in Table 2. CG2/R3 General-Purpose Register R4 General-Purpose Register R5 General-Purpose Register R6 General-Purpose Register R7 General-Purpose Register R8 General-Purpose Register R9 General-Purpose Register R10 General-Purpose Register R11 General-Purpose Register R12 General-Purpose Register R13 General-Purpose Register R14 General-Purpose Register R15 Table 1. Instruction Word Formats Dual operands, source-destination e.g., ADD R4, R5 R4 + R5 ---> R5 Single operands, destination only e.g., CALL R8 PC -->(TOS), R8--> PC Relative jump, un/conditional e.g., JNE Jump-on-equal bit = 0 Table 2. Address Mode Descriptions ADDRESS MODE Indirect D D D D D Indirect autoincrement Register Indexed Symbolic (PC relative) Absolute Immediate NOTE: S = source 8 S D D D D D SYNTAX EXAMPLE MOV Rs, Rd MOV R10, R11 MOV X(Rn), Y(Rm) MOV 2(R5), 6(R6) MOV EDE, TONI OPERATION R10 --> R11 M(2+R5)--> M(6+R6) M(EDE) --> M(TONI) MOV &MEM, &TCDAT M(MEM) --> M(TCDAT) MOV @Rn, Y(Rm) MOV @R10, Tab(R6) M(R10) --> M(Tab+R6) D MOV @Rn+, Rm MOV @R10+, R11 M(R10) --> R11 R10 + 2--> R10 D MOV #X, TONI MOV #45, TONI D = destination POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 #45 --> M(TONI) MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C - MAY 2007 - REVISED MARCH 2011 operating modes The MSP430 has one active mode and five software-selectable low-power modes of operation. An interrupt event can wake up the device from any of the five low-power modes, service the request, and restore back to the low-power mode on return from the interrupt program. The following six operating modes can be configured by software: D Active mode AM - All clocks are active D Low-power mode 0 (LPM0) - CPU is disabled. - ACLK and SMCLK remain active. - MCLK is disabled. - FLL+ loop control remains active D Low-power mode 1(LPM1) - CPU is disabled. - FLL+ loop control is disabled. - ACLK and SMCLK remain active. - MCLK is disabled. D Low-power mode 2 (LPM2) - CPU is disabled. - MCLK, FLL+ loop control, and DCOCLK are disabled. - DCO's dc generator remains enabled. - ACLK remains active. D Low-power mode 3 (LPM3) - CPU is disabled. - MCLK, FLL+ loop control, and DCOCLK are disabled. - DCO's dc generator is disabled. - ACLK remains active. D Low-power mode 4 (LPM4) - CPU is disabled. - ACLK is disabled. - MCLK, FLL+ loop control, and DCOCLK are disabled. - DCO's dc generator is disabled. - Crystal oscillator is stopped. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 9 MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C - MAY 2007 - REVISED MARCH 2011 interrupt vector addresses The interrupt vectors and the power-up starting address are located in the address range 0FFFFh to 0FFE0h. The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence. If the reset vector (located at address 0FFFEh) contains 0FFFFh (e.g., flash is not programmed) the CPU goes into LPM4 immediately after power-up. INTERRUPT SOURCE INTERRUPT FLAG SYSTEM INTERRUPT WORD ADDRESS PRIORITY Power-Up External Reset Watchdog Flash Memory PC Out-of-Range (see Note 4) PORIFG RSTIFG WDTIFG KEYV (see Note 1) Reset 0FFFEh 15, highest NMI Oscillator Fault Flash Memory Access Violation NMIIFG (see Notes 1 and 3) OFIFG (see Notes 1 and 3) ACCVIFG (see Notes 1 and 3) (Non)maskable (Non)maskable (Non)maskable 0FFFCh 14 Timer_B3 TBCCR0 CCIFG (see Note 2) Maskable 0FFFAh 13 Timer_B3 TBCCR1 to TBCCR2 CCIFGs TBIFG (see Notes 1 and 2) Maskable 0FFF8h 12 Comparator_A CAIFG Maskable 0FFF6h 11 Watchdog Timer WDTIFG Maskable 0FFF4h 10 USCI_A0/B0 Receive UCA0RXIFG, UCB0RXIFG (see Note 1 and 5) Maskable 0FFF2h 9 USCI_A0/B0 Transmit UCA0TXIFG, UCB0TXIFG (see Note 1 and 6) Maskable 0FFF0h 8 SD16_A SD16CCTLx SD16OVIFG, SD16CCTLx SD16IFG (see Notes 1 and 2) Maskable 0FFEEh 7 Timer_A3 TACCR0 CCIFG (see Note 2) Maskable 0FFECh 6 Timer_A3 TACCR1 and TACCR2 CCIFGs, TAIFG (see Notes 1 and 2) Maskable 0FFEAh 5 I/O Port P1 (Eight Flags) P1IFG.0 to P1IFG.7 (see Notes 1 and 2) Maskable 0FFE8h 4 USCI_A1/B1 Receive UCA1RXIFG, UCB1RXIFG (see Notes 1 and 2) Maskable 0FFE6h 3 USCI_A1/B1 Transmit UCA1TXIFG, UCB1TXIFG (see Notes 1 and 2) Maskable 0FFE4h 2 I/O Port P2 (Eight Flags) P2IFG.0 to P2IFG.7 (see Notes 1 and 2) Maskable 0FFE2h 1 Basic Timer1 BTIFG Maskable 0FFE0h 0, lowest NOTES: 1. 2. 3. 4. 5. 6. 7. 8. 10 Multiple source flags Interrupt flags are located in the module. (Non)maskable: The individual interrupt-enable bit can disable an interrupt event, but the general interrupt enable cannot. A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h to 01FFh). In SPI mode: UCB0RXIFG. In I2C mode: UCALIFG, UCNACKIFG, ICSTTIFG, UCSTPIFG in register UCB0STAT. In UART/SPI mode: UCB0TXIFG. In I2C mode: UCB0RXIFG, UCB0TXIFG. In SPI mode: UCB1RXIFG. In I2C mode: UCALIFG, UCNACKIFG, ICSTTIFG, UCSTPIFG in register UCB1STAT. In UART/SPI mode: UCB1TXIFG. In I2C mode: UCB1RXIFG, UCB1TXIFG. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C - MAY 2007 - REVISED MARCH 2011 special function registers Most interrupt and module-enable bits are collected in the lowest address space. Special-function register bits not allocated to a functional purpose are not physically present in the device. This arrangement provides simple software access. interrupt enable 1 and 2 Address 7 6 00h 5 4 ACCVIE rw-0 3 2 1 0 NMIIE OFIE WDTIE rw-0 rw-0 rw-0 WDTIE Watchdog timer interrupt enable. Inactive if watchdog mode is selected. Active if watchdog timer is configured in interval timer mode. OFIE Oscillator fault enable NMIIE (Non)maskable interrupt enable ACCVIE Flash access violation interrupt enable Address 01h 7 6 5 4 3 2 1 0 BTIE UCB0TXIE UCB0RXIE UCA0TXIE UCA0RXIE rw-0 rw-0 rw-0 rw-0 rw-0 UCA0RXIE USCI_A0 receive interrupt enable UCA0TXIE USCI_A0 transmit interrupt enable UCB0RXIE USCI_B0 receive interrupt enable UCB0TXIE USCI_B0 transmit interrupt enable BTIE Basic timer interrupt enable POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 11 MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C - MAY 2007 - REVISED MARCH 2011 interrupt flag register 1 and 2 Address 7 6 5 02h 4 3 2 1 0 NMIIFG RSTIFG PORIFG OFIFG WDTIFG rw-0 rw-(0) rw-(1) rw-1 rw-(0) WDTIFG Set on watchdog timer overflow or security key violation. Reset on VCC power-up or a reset condition at RST/NMI pin in reset mode. OFIFG Flag set on oscillator fault RSTIFG External reset interrupt flag. Set on a reset condition at RST/NMI pin in reset mode. Reset on VCC power-up. PORIFG Power-on interrupt flag. Set on VCC power-up. NMIIFG Set via RST/NMI pin Address 7 03h UCA0RXIFG 6 5 3 2 1 0 BTIFG UCB0 TXIFG UCB0 RXIFG UCA0 TXIFG UCA0 RXIFG rw-0 rw-1 rw-0 rw-1 rw-0 USCI_A0 receive interrupt flag UCA0TXIFG USCI_A0 transmit interrupt flag UCB0RXIFG USCI_B0 receive interrupt flag UCB0TXIFG USCI_B0 transmit interrupt flag BTIFG Basic Timer1 interrupt flag Legend 4 rw: rw-0, 1: rw-(0, 1): Bit can be read and written. Bit can be read and written. It is Reset or Set by PUC. Bit can be read and written. It is Reset or Set by POR. SFR bit is not present in device 12 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C - MAY 2007 - REVISED MARCH 2011 memory organization MSP430F4783/MSP430F4784 MSP430F4793/MSP430F4794 Memory Main: interrupt vector Main: code memory Size Flash Flash 48KB 0FFFFh to 0FFE0h 0FFFFh to 04000h 60KB 0FFFFh to 0FFE0h 0FFFFh to 01100h Information memory Size Flash 256 Byte 010FFh to 01000h 256 Byte 010FFh to 01000h Boot memory Size ROM 1KB 0FFFh to 0C00h 1KB 0FFFh to 0C00h Size 2KB 09FFh to 0200h 2.5KB 0BFFh to 0200h 16-bit 8-bit 8-bit SFR 01FFh to 0100h 0FFh to 010h 0Fh to 00h 01FFh to 0100h 0FFh to 010h 0Fh to 00h RAM Peripherals bootstrap loader (BSL) The BSL enables users to program the flash memory or RAM using a UART serial interface. Access to device memory via the BSL is protected by user-defined password. For complete description of the features of the BSL and its implementation, see the application report Features of the MSP430 Bootstrap Loader, literature number SLAA089. BSL FUNCTION PZ PACKAGE PINS Data transmit 87 - P1.0 Data receive 86 - P1.1 flash memory, flash The flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. The CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include: D Flash memory has n segments of main memory and four segments of information memory (A to D) of 64 bytes each. Each segment in main memory is 512 bytes in size. D Segments 0 to n may be erased in one step, or each segment may be individually erased. D Segments A to D can be erased individually, or as a group with segments 0 to n. Segments A to D are also called information memory. D Segment A might contain calibration data. After reset, segment A is protected against programming or erasing. It can be unlocked but care should be taken not to erase this segment if the calibration data is required. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 13 MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C - MAY 2007 - REVISED MARCH 2011 peripherals Peripherals are connected to the CPU through data, address, and control buses and can be handled using all instructions. For complete module descriptions, see the MSP430x4xx Family User's Guide, literature number SLAU056. digital I/O There are nine 8-bit I/O ports implemented--ports P1 through P5 and P7 through P10. D D D D D D All individual I/O bits are independently programmable. Any combination of input, output, and interrupt conditions is possible. Edge-selectable interrupt input capability for all the eight bits of ports P1 and P2. Read/write access to port-control registers is supported by all instructions. Ports P7/P8 and P9/P10 can be accessed word-wise as ports PA and PB respectively. Each I/O has an individually programmable pullup/pulldown resistor. oscillator and system clock The clock system in the MSP430x47xx is supported by the FLL+ module, which includes support for a 32768-Hz watch crystal oscillator, an internal digitally-controlled oscillator (DCO), and a 8-MHz high-frequency crystal oscillator (XT1), plus a 16-MHz high-frequency crystal oscillator (XT2). The FLL+ clock module is designed to meet the requirements of both low system cost and low power consumption. The FLL+ features digital frequency-locked loop (FLL) hardware that, in conjunction with a digital modulator, stabilizes the DCO frequency to a programmable multiple of the watch crystal frequency. The internal DCO provides a fast turn-on clock source and stabilizes in less than 6 s. The FLL+ module provides the following clock signals: D D D D Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal or a high-frequency crystal Main clock (MCLK), the system clock used by the CPU Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules ACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, or ACLK/8 brownout, supply voltage supervisor (SVS) The brownout circuit is implemented to provide the proper internal reset signal to the device during power on and power off. The supply voltage supervisor circuitry detects if the supply voltage drops below a user selectable level and supports both supply voltage supervision (the device is automatically reset) and supply voltage monitoring (SVM, the device is not automatically reset). The CPU begins code execution after the brownout circuit releases the device reset. However, VCC may not have ramped to VCC(min) at that time. The user must ensure the default FLL+ settings are not changed until VCC reaches VCC(min). If desired, the SVS circuit can be used to determine when VCC reaches VCC(min). hardware multiplier The multiplication operation is supported by a dedicated peripheral module. The module performs operations with 32-bit, 24-bit, 16-bit, and 8-bit operands. The module is capable of supporting signed and unsigned multiplication as well as signed and unsigned multiply-and-accumulate operations. watchdog timer (WDT+) The primary function of the WDT+ module is to perform a controlled system restart after a software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed in an application, the module can be configured as an interval timer and can generate interrupts at selected time intervals. 14 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C - MAY 2007 - REVISED MARCH 2011 universal serial communication interfaces (USCI_A0, USCI_B0, USCI_A1, USCI_B1) The universal serial communication interface (USCI) module is used for serial data communication. The USCI module supports synchronous communication protocols such as SPI (3-pin or 4-pin), I2C, and asynchronous communication protocols such as UART, enhanced UART with automatic baudrate detection (LIN), and IrDA. USCI_A0 and USCI_A1 provide support for SPI (3-pin or 4-pin), UART, enhanced UART, and IrDA. USCI_B0 and USCI_B1 provide support for SPI (3-pin or 4-pin) and I2C. timer_A3 Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. TIMER_A3 SIGNAL CONNECTIONS INPUT PIN NUMBER DEVICE INPUT SIGNAL MODULE INPUT NAME 82 - P1.5 TACLK TACLK ACLK ACLK SMCLK SMCLK 82 - P1.5 TACLK INCLK 87 - P1.0 TA0 CCI0A 86 - P1.1 TA0 CCI0B DVSS GND 85 - P1.2 79 - P2.0 DVCC VCC TA1 CCI1A CAOUT (internal) CCI1B DVSS GND DVCC VCC TA2 CCI2A ACLK (internal) CCI2B DVSS GND DVCC VCC POST OFFICE BOX 655303 MODULE BLOCK MODULE OUTPUT SIGNAL Timer NA OUTPUT PIN NUMBER 87 - P1.0 CCR0 TA0 85 - P1.2 CCR1 TA1 79 - P2.0 CCR2 * DALLAS, TEXAS 75265 TA2 15 MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C - MAY 2007 - REVISED MARCH 2011 timer_B3 Timer_B3 is a 16-bit timer/counter with three capture/compare registers. Timer_B3 can support multiple capture/compares, PWM outputs, and interval timing. Timer_B3 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. TIMER_B3 SIGNAL CONNECTIONS INPUT PIN NUMBER DEVICE INPUT SIGNAL MODULE INPUT NAME 83 - P1.4 TBCLK TBCLK ACLK ACLK SMCLK SMCLK 83 - P1.4 TBCLK INCLK 78 - P2.1 TB0 CCI0A TB0 CCI0B DVSS GND 78 - P2.1 DVCC VCC 77 - P2.2 TB1 CCI1A 77 - P2.2 TB1 CCI1B DVSS GND 76 - P2.3 76 - P2.3 16 DVCC VCC TB2 CCI2A TB2 CCI2B DVSS GND DVCC VCC POST OFFICE BOX 655303 MODULE BLOCK MODULE OUTPUT SIGNAL Timer NA OUTPUT PIN NUMBER 78 - P2.1 CCR0 TB0 77 - P2.2 CCR1 TB1 76 - P2.3 CCR2 * DALLAS, TEXAS 75265 TB2 MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C - MAY 2007 - REVISED MARCH 2011 comparator_A The primary function of the comparator_A module is to support precision slope A/D conversions, battery-voltage supervision, and monitoring of external analog signals. SD16_A The SD16_A module integrates three (in MSP430F47x3) or four (in MSP430F47x4) independent 16-bit sigma-delta A/D converters. Each channel is designed with a fully differential analog input pair and programmable-gain amplifier input stage. In addition to external analog inputs, an internal VCC sense and temperature sensor are also available. Basic Timer1 The Basic Timer1 has two independent 8-bit timers that can be cascaded to form a 16-bit timer/counter. Both timers can be read and written by software. Basic Timer1 can be used to generate periodic interrupts and a clock for the LCD module. LCD driver with regulated charge pump The LCD_A driver generates the segment and common signals required to drive an LCD display. The LCD_A controller has dedicated data memory to hold segment drive information. Common and segment signals are generated as defined by the mode. Static, 2-MUX, 3-MUX, and 4-MUX LCDs are supported by this peripheral. The module can provide a LCD voltage independent of the supply voltage via an integrated charge pump. Furthermore, it is possible to control the level of the LCD voltage and, thus, contrast in software. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 17 MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C - MAY 2007 - REVISED MARCH 2011 peripheral file map PERIPHERALS WITH WORD ACCESS Watchdog Watchdog timer control WDTCTL 0120h Flash_A Flash control 4 Flash control 3 Flash control 2 Flash control 1 FCTL4 FCTL3 FCTL2 FCTL1 01BEh 012Ch 012Ah 0128h Timer_B3 _ Capture/compare register 2 TBCCR2 0196h Capture/compare register 1 TBCCR1 0194h Capture/compare register 0 TBCCR0 0192h Timer_B register TBR 0190h Capture/compare control 2 TBCCTL2 0186h Capture/compare control 1 TBCCTL1 0184h Capture/compare control 0 TBCCTL0 0182h Timer_B control TBCTL 0180h Timer_B interrupt vector TBIV 011Eh Capture/compare register 2 TACCR2 0176h Capture/compare register 1 TACCR1 0174h Capture/compare register 0 TACCR0 0172h Timer_A register TAR 0170h Capture/compare control 2 TACCTL2 0166h Capture/compare control 1 TACCTL1 0164h Capture/compare control 0 TACCTL0 0162h Timer_A control TACTL 0160h Timer_A interrupt vector TAIV 012Eh MPY32 control 0 MPY32CTL0 015Ch 64-bit result 3 - most significant word RES3 015Ah 64-bit result 2 RES2 0158h 64-bit result 1 RES1 0156h 64-bit result 0 - least significant word RES0 0154h Second 32-bit operand, high word OP2H 0152h Second 32-bit operand, low word OP2L 0150h Multiply signed + accumulate/ 32-bit operand1, high word MACS32H 014Eh Multiply signed + accumulate/ 32-bit operand1, low word MACS32L 014Ch Multiply + accumulate/ 32-bit operand1, high word MAC32H 014Ah Multiply + accumulate/ 32-bit operand1, low word MAC32L 0148h Multiply signed/32-bit operand1, high word MPYS32H 0146h Multiply signed/32-bit operand1, low word MPYS32L 0144h Multiply unsigned/32-bit operand1, high word MPY32H 0142h Multiply unsigned/32-bit operand1, low word MPY32L 0140h Timer_A3 _ 32-bit Hardware M lti li Multiplier 18 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C - MAY 2007 - REVISED MARCH 2011 peripheral file map (continued) PERIPHERALS WITH WORD ACCESS (CONTINUED) 32-bit Hardware Multiplier Sum extend SUMEXT 013Eh Result high word RESHI 013Ch Result low word RESLO 013Ah Second operand OP2 0138h Multiply signed + accumulate/operand1 MACS 0136h Multiply + accumulate/operand1 MAC 0134h Multiply signed/operand1 MPYS 0132h Multiply unsigned/operand1 MPY 0130h USCI_B0 (see also: Peripherals with Byte Access) USCI_B0 I2C own address UCB0I2COA 016Ch USCI_B0 I2C slave address UCB0I2CSA 016Eh USCI_B1 (see also: Peripherals with Byte Access) USCI_B1 I2C own address UCB1I2COA 017Ch USCI_B1 I2C slave address UCB1I2CSA 017Eh SD16_A _ (see also: ( l Peripherals with y Access)) Byte General control SD16CTL 0100h Channel 0 control SD16CCTL0 0102h Channel 1 control SD16CCTL1 0104h Channel 2 control SD16CCTL2 0106h Channel 3 control SD16CCTL3 0108h Interrupt vector word register SD16IV 0110h Channel 0 conversion memory SD16MEM0 0112h Channel 1 conversion memory SD16MEM1 0114h Channel 2 conversion memory SD16MEM2 0116h Channel 3 conversion memory SD16MEM3 0118h Port PA resistor enable PAREN 014h Port PA selection PASEL 03Eh Port PA direction PADIR 03Ch Port PA output PAOUT 03Ah Port PA input PAIN 038h Port PB resistor enable PBREN 016h Port PB selection PBSEL 00Eh Port PB direction PBDIR 00Ch Port PB output PBOUT 00Ah Port PB input PBIN 008h Port PA Port PB POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 19 MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C - MAY 2007 - REVISED MARCH 2011 peripheral file map (continued) PERIPHERALS WITH BYTE ACCESS 20 SD16_A (see also: Peripherals with Word Access) Channel 0 input control Channel 1 input control Channel 2 input control Channel 3 input control Channel 0 preload Channel 1 preload Channel 2 preload Channel 3 preload Reserved (internal SD16 Configuration 1) SD16INCTL0 SD16INCTL1 SD16INCTL2 SD16INCTL3 SD16PRE0 SD16PRE1 SD16PRE2 SD16PRE3 SD16CONF1 0B0h 0B1h 0B2h 0B3h 0B8h 0B9h 0BAh 0BBh 0BFh LCD_A LCD voltage control 1 LCD voltage control 0 LCD voltage port control 1 LCD voltage port control 0 LCD memory 20 : LCD memory 16 LCD memory 15 : LCD memory 1 LCD control and mode LCDAVCTL1 LCDAVCTL0 LCDAPCTL1 LCDAPCTL0 LCDM20 : LCDM16 LCDM15 : LCDM1 LCDACTL 0AFh 0AEh 0ADh 0ACh 0A4h : 0A0h 09Fh : 091h 090h USCI_A0 USCI_A0 transmit buffer USCI_A0 receive buffer USCI_A0 status USCI_A0 modulation control USCI_A0 baud rate control 1 USCI_A0 baud rate control 0 USCI_A0 control 1 USCI_A0 control 0 USCI_A0 IrDA receive control USCI_A0 IrDA transmit control USCI_A0 auto baud rate control UCA0TXBUF UCA0RXBUF UCA0STAT UCA0MCTL UCA0BR1 UCA0BR0 UCA0CTL1 UCA0CTL0 UCA0IRRCTL UCA0IRTCTL UCA0ABCTL 067h 066h 065h 064h 063h 062h 061h 060h 05Fh 05Eh 05Dh USCI_B0 USCI_B0 transmit buffer USCI_B0 receive buffer USCI_B0 status USCI_B1 I2C interrupt enable USCI_B0 bit rate control 1 USCI_B0 bit rate control 0 USCI_B0 control 1 USCI_B0 control 0 UCB0TXBUF UCB0RXBUF UCB0STAT UCB0I2CIE UCB0BR1 UCB0BR0 UCB0CTL1 UCB0CTL0 06Fh 06Eh 06Dh 06Ch 06Bh 06Ah 069h 068h USCI_A1 USCI_A1 transmit buffer USCI_A1 receive buffer USCI_A1 status USCI_A1 modulation control USCI_A1 baud rate control 1 USCI_A1 baud rate control 0 USCI_A1 control 1 USCI_A1 control 0 USCI_A1 IrDA receive control USCI_A1 IrDA transmit control USCI_A1 auto baud rate control USCI_A1 interrupt flag USCI_A1 interrupt enable UCA1TXBUF UCA1RXBUF UCA1STAT UCA1MCTL UCA1BR1 UCA1BR0 UCA1CTL1 UCA1CTL0 UCA1IRRCTL UCA1IRTCTL UCA1ABCTL UC1IFG UC1IE 0D7h 0D6h 0D5h 0D4h 0D3h 0D2h 0D1h 0D0h 0CFh 0CEh 0CDh 007h 006h POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C - MAY 2007 - REVISED MARCH 2011 peripheral file map (continued) PERIPHERALS WITH BYTE ACCESS (CONTINUED) USCI_B1 USCI_B1 transmit buffer USCI_B1 receive buffer USCI_B1 status USCI_B1 I2C interrupt enable USCI_B1 bit rate control 1 USCI_B1 bit rate control 0 USCI_B1 control 1 USCI_B1 control 0 USCI_A1 interrupt flag USCI_A1 interrupt enable UCB1TXBUF UCB1RXBUF UCB1STAT UCB1I2CIE UCB1BR1 UCB1BR0 UCB1CTL1 UCB1CTL0 UC1IFG UC1IE 0DFh 0DEh 0DDh 0DCh 0DBh 0DAh 0D9h 0D8h 007h 006h Comparator_A p _ Comparator_A port disable CAPD 05Bh Comparator_A control2 CACTL2 05Ah Comparator_A control1 CACTL1 059h BrownOUT, SVS SVS control register (reset by brownout signal) SVSCTL 056h FLL+ Clock FLL+ control 2 FLL_CTL2 055h FLL+ control 1 FLL_CTL1 054h FLL+ control 0 FLL_CTL0 053h System clock frequency control SCFQCTL 052h System clock frequency integrator SCFI1 051h System clock frequency integrator SCFI0 050h Basic Timer1 BT counter 2 BT counter 1 BT control BTCNT2 BTCNT1 BTCTL 047h 046h 040h Port P10 Port P10 resistor enable P10REN 017h Port P10 selection P10SEL 00Fh Port P10 direction P10DIR 00Dh Port P10 output P10OUT 00Bh Port P10 input P10IN 009h Port P9 resistor enable P9REN 016h Port P9 selection P9SEL 00Eh Port P9 direction P9DIR 00Ch Port P9 output P9OUT 00Ah Port P9 input P9IN 008h Port P8 resistor enable P8REN 015h Port P8 selection P8SEL 03Fh Port P8 direction P8DIR 03Dh Port P8 output P8OUT 03Bh Port P8 input P8IN 039h Port P7 resistor enable P7REN 014h Port P7 selection P7SEL 03Eh Port P7 direction P7DIR 03Ch Port P7 output P7OUT 03Ah Port P7 input P7IN 038h Port P9 Port P8 Port P7 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 21 MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C - MAY 2007 - REVISED MARCH 2011 peripheral file map (continued) PERIPHERALS WITH BYTE ACCESS (CONTINUED) Port P5 Port P4 Port P3 Port P2 Port P1 Special p functions 22 Port P5 resistor enable P5REN 012h Port P5 selection P5SEL 033h Port P5 direction P5DIR 032h Port P5 output P5OUT 031h Port P5 input P5IN 030h Port P4 resistor enable P4REN 011h Port P4 selection P4SEL 01Fh Port P4 direction P4DIR 01Eh Port P4 output P4OUT 01Dh Port P4 input P4IN 01Ch Port P3 resistor enable P3REN 010h Port P3 selection P3SEL 01Bh Port P3 direction P3DIR 01Ah Port P3 output P3OUT 019h Port P3 input P3IN 018h Port P2 resistor enable P2REN 02Fh Port P2 selection P2SEL 02Eh Port P2 interrupt enable P2IE 02Dh Port P2 interrupt-edge select P2IES 02Ch Port P2 interrupt flag P2IFG 02Bh Port P2 direction P2DIR 02Ah Port P2 output P2OUT 029h Port P2 input P2IN 028h Port P1 resistor enable P1REN 027h Port P1 selection P1SEL 026h Port P1 interrupt enable P1IE 025h Port P1 interrupt-edge select P1IES 024h Port P1 interrupt flag P1IFG 023h Port P1 direction P1DIR 022h Port P1 output P1OUT 021h Port P1 input P1IN 020h SFR interrupt flag2 IFG2 003h SFR interrupt flag1 IFG1 002h SFR interrupt enable2 IE2 001h SFR interrupt enable1 IE1 000h POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C - MAY 2007 - REVISED MARCH 2011 absolute maximum ratings (see Note 1) Voltage applied at VCC to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 4.1 V Voltage applied to any pin (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to VCC + 0.3 V Diode current at any device terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 mA Storage temperature, Tstg: (unprogrammed device, see Note 3) . . . . . . . . . . . . . . . . . . . . . . . -55C to 150C (programmed device, see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to 85C NOTES: 1. Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. All voltages referenced to VSS. The JTAG fuse-blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage is applied to the TDI/TCLK pin when blowing the JTAG fuse. 3. Higher temperature may be applied during board soldering process according to the current JEDEC J-STD-020 specification with peak reflow temperatures not higher than classified on the device label on the shipping boxes or reels. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 23 MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C - MAY 2007 - REVISED MARCH 2011 recommended operating conditions MIN NOM MAX UNIT Supply voltage during program execution, VCC (AVCC = DVCC = VCC) (see Note 1) 1.8 3.6 V Supply voltage during program execution, SVS enabled, PORON = 1, VCC (AVCC = DVCC = VCC) (see Notes 1, 2) 2.0 3.6 V Supply voltage during program/erase flash memory, VCC (AVCC = DVCC = VCC) (see Note 1) 2.2 3.6 V -40 85 C VCC = 1.8 V, Duty Cycle = 50% 10% dc 4.15 MHz VCC = 2.2 V, Duty Cycle = 50% 10% dc 7.5 MHz VCC = 2.7 V, Duty Cycle = 50% 10% dc 12 VCC 3.3 V, Duty Cycle = 50% 10% dc 16 Supply voltage, VSS 0 Operating free-air temperature range, TA Processor frequency fSYSTEM (Maximum MCLK frequency) (see Notes 3, 4 and Figure 1) V MHz NOTES: 1. It is recommended to power AVCC and DVCC from the same source. A maximum difference of 0.3V between AVCC and DVCC can be tolerated during power up and operation. 2. The minimum operating supply voltage is defined according to the trip point where POR is going active by decreasing supply voltage. POR is going inactive when the supply voltage is raised abve minimum supply voltage plus the hysteresis of the SVS circuitry. 3. The MSP430 CPU is clocked directly with MCLK. Both the high and low phase of MCLK must not exceed the pulse width of the specified maximum frequency. 4. Modules might have a different maximum input clock specification. Refer to the specification of the respective module in this datasheet. System Frequency -MHz 16 MHz 12 MHz 7.5 MHz 4.15 MHz 1.8 V IIIIIIIII IIIIIIIII IIIIIIIII IIIIIIIII IIIIIIIII IIIIIIIII IIIIIIIII IIIIIIIII IIIIIIIII IIIIIIIII 2.2 V 2.7 V 3.3 V II II II II II II Legend: Supply voltage range, during flash memory programming Supply voltage range, during program execution 3.6 V Supply Voltage -V NOTE: Minimum processor frequency is defined by system clock. Flash program or erase operations require a minimum VCC of 2.2 V. Figure 1. Operating Area 24 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C - MAY 2007 - REVISED MARCH 2011 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) supply current into AVCC + DVCC excluding external current PARAMETER TEST CONDITIONS TYP MAX VCC = 2.2 V 280 350 VCC = 3 V 420 560 VCC = 2.2 V 45 70 VCC = 3 V 75 110 VCC = 2.2 V 11 14 VCC = 3 V 17 22 TA = -40C 1.0 2.0 TA = 25C 1.1 2.0 2.0 3.0 TA = 85C 3.0 6.0 TA = -40C 1.2 3.0 1.3 3.0 2.5 3.5 TA = 85C 3.5 7.5 TA = -40C 3.5 5.5 TA = 25C 3.5 5.5 5.5 7.0 TA = 85C 11.0 17.0 TA = -40C 4.0 8.0 4.0 6.5 6.0 8.0 TA = 85C 13.0 20.0 TA = -40C 0.1 1.0 TA = 25C 0.2 1.0 1.0 2.0 Active mode, (see Note 1) f((MCLK)) = f(SMCLK) ( ) = 1 MHz, 32 768 Hz f(ACLK) = 32, XTS_FLL = 0, SELM = (0, 1) (Program executes from flash) TA = -40C 40C to 85C I(LPM0) Low power mode, (LPM0) Low-power (see Notes 1, 4) TA = -40C 40C to 85C I(LPM2) Low-power mode, (LPM2), f(MCLK) = f (SMCLK) = 0 MHz, MHz f(ACLK) = 32, 768 Hz, SCG0 = 0 (see Notes 2, 4) TA = -40C 40C to 85C I(AM) I(LPM3) Low power mode, mode (LPM3) Low-power f(MCLK) = f(SMCLK) = 0 MHz, f(ACLK) = 32, 768 Hz, SCG0 = 1 Basic Timer1 enabled, ACLK selected LCD A enabled LCD_A enabled, LCDCPEN = 0 0, (static mode, fLCD = f(ACLK) /32) (see Notes 2, 3, 4) TA = 60C TA = 25C TA = 60C I(LPM3) Low-power Low power mode, mode (LPM3) f(MCLK) = f(SMCLK) = 0 MHz, f(ACLK) = 32, 768 Hz, SCG0 = 1 Basic Timer1 enabled, ACLK selected LCD A enabled LCD_A enabled, LCDCPEN = 0 0, (4-mux mode, fLCD = f(ACLK) /32) (see Notes 2, 3, 4) TA = 60C TA = 25C TA = 60C I(LPM4) Low-power mode, mode (LPM4) f(MCLK) = 0 MHz, f(SMCLK) = 0 MHz, f(ACLK) = 0 Hz, SCG0 = 1 ( (see Notes N t 2, 2 4) TA = 60C UNIT A A VCC = 2 2.2 2V VCC = 3 V VCC = 2 2.2 2V VCC = 3 V VCC = 2 2.2 2V TA = 85C 1.8 5.0 TA = -40C 0.1 2.0 TA = 25C 0.2 2.0 1.5 2.5 2.0 6.0 TA = 60C VCC = 3 V TA = 85C NOTES: 1. 2. 3. 4. MIN A A A A A A A A A A A A A A A A Timer_A is clocked by f(DCOCLK) = f(DCO) = 1 MHz. All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current. All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current. The LPM3 currents are characterized with a Micro Crystal CC4V-T1A (9 pF) crystal and OSCCAPx = 1h. Current for brownout included. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 25 MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C - MAY 2007 - REVISED MARCH 2011 typical characteristics - active mode supply current (into VCC) 10.0 7.0 fDCO = 12 MHz 6.0 5.0 fDCO = 8 MHz 4.0 3.0 2.0 TA = 25 C Active Mode Current - mA Active Mode Current - mA fDCO = 16 MHz 8.0 4.0 3.0 VCC = 3 V TA = 85 C VCC = 2.2 V fDCO = 1 MHz 2.0 2.5 3.0 3.5 4.0 0.0 0.0 VCC - Supply Voltage - V Figure 2. Active mode current vs VCC, TA = 25C 26 TA = 25 C 2.0 1.0 1.0 0.0 1.5 TA = 85 C 5.0 9.0 POST OFFICE BOX 655303 4.0 8.0 12.0 16.0 fDCO - DCO Frequency - MHz Figure 3. Active mode current vs DCO frequency * DALLAS, TEXAS 75265 MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C - MAY 2007 - REVISED MARCH 2011 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) Schmitt-trigger inputs - Ports P1 through P5, P7 through P10, RST/NMI, JTAG: TCK, TMS, TDI/TCLK, TDO/TDI PARAMETER VIT+ VIT- TEST CONDITIONS Positive-going P iti i input i t th threshold h ld voltage N ti i input i t threshold th h ld Negative-going voltage Vhys Input voltage hysteresis (VIT+ - VIT-) RPull Pull-up/pull-down resistor (not RST/NMI and JTAG pins) For pull-up: VIN = VSS, For pull-down: VIN = VCC CI Input Capacitance VIN = VSS or VCC VCC MIN MAX UNIT 0.45 0.75 VCC 2.2 V 1.00 1.65 3V 1.35 2.25 0.25 0.55 2.2 V 0.55 1.20 3V 0.75 1.65 2.2 V 0.2 1.0 3V 0.3 1.0 20 TYP 35 50 5 V VCC V V kW pF inputs - Ports P1, P2 PARAMETER t(int) External interrupt timing TEST CONDITIONS Port P1, P2: P1.x to P2.x, External trigger puls width to set interrupt flag, (see Note 1) VCC 2.2 V/3 V MIN MAX 20 UNIT ns NOTES: 1. An external signal sets the interrupt flag every time the minimum interrupt puls width t(int) is met. It may be set even with trigger signals shorter than t(int). leakage current - Ports P1 through P5, P7 through P10 PARAMETER Ilkg(Px.x) High-impedance leakage current TEST CONDITIONS see Notes 1 and 2 VCC 2.2 V/3 V MIN MAX UNIT 50 nA NOTES: 1. The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted. 2. The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup/pulldown resistor is disabled. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 27 MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C - MAY 2007 - REVISED MARCH 2011 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) outputs - Ports P1 through P5, P7 through P10 PARAMETER VOH VOL High level output voltage High-level Low level output voltage Low-level VCC MIN I(OHmax) = -1.5 mA (see Notes 1) TEST CONDITIONS 2.2 V VCC-0.25 MAX VCC UNIT I(OHmax) = -6 mA (see Notes 2) 2.2 V VCC-0.6 VCC I(OHmax) = -1.5 mA (see Notes 1) 3V VCC-0.25 VCC I(OHmax) = -6 mA (see Notes 2) 3V VCC-0.6 VCC I(OLmax) = 1.5 mA (see Notes 1) 2.2 V VSS VSS+0.25 I(OLmax) = 6 mA (see Notes 2) 2.2 V VSS VSS+0.6 I(OLmax) = 1.5 mA (see Notes 1) 3V VSS VSS+0.25 I(OLmax) = 6 mA (see Notes 2) 3V VSS VSS+0.6 V V NOTES: 1. The maximum total current, IOHmax and IOLmax, for all outputs combined, should not exceed 12 mA to hold the maximum voltage drop specified. 2. The maximum total current, IOHmax and IOLmax, for all outputs combined, should not exceed 48 mA to hold the maximum voltage drop specified. output frequency - Ports P1 through P5, P7 through P10 PARAMETER fPx.y Port output frequency (with load) TEST CONDITIONS P1.4/TBCLK/SMCLK, pF, RL = 1 kW against VCC/2 CL = 20 pF (see Note 1 and 2) MAX UNIT 2.2 V VCC MIN 10 MHz 3V 12 MHz P1.1/TA0/MCLK, P1.5/TACLK/ACLK, 2.2 V 12 MHz fPort_CLK Clock output frequency P1 4/TBCLK/SMCLK P1.4/TBCLK/SMCLK, 3V 16 MHz CL = 20 pF (see Note 2) NOTES: 1. Alternatively a resistive divider with 2 times 2 kW between VCC and VSS is used as load. The output is connected to the center tap of the divider. 2. The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency. 28 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C - MAY 2007 - REVISED MARCH 2011 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) typical characteristics - outputs TYPICAL LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE TYPICAL LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE 55.0 VCC = 2.2 V P2.4 I OL - Typical Low-Level Output Current - mA I OL - Typical Low-Level Output Current - mA 30.0 TA = 25C 25.0 TA = 85C 20.0 15.0 10.0 5.0 0.0 0.0 0.5 1.0 1.5 2.0 VCC = 3 V P2.4 50.0 45.0 TA = 25C 40.0 TA = 85C 35.0 30.0 25.0 20.0 15.0 10.0 5.0 0.0 0.0 2.5 0.5 VOL - Low-Level Output Voltage - V TYPICAL HIGH-LEVEL OUTPUT CURRENT vs HIGH-LEVEL OUTPUT VOLTAGE 2.5 3.0 3.5 0.0 VCC = 2.2 V P2.4 I OH - Typical High-Level Output Current - mA I OH - Typical High-Level Output Current - mA 2.0 TYPICAL HIGH-LEVEL OUTPUT CURRENT vs HIGH-LEVEL OUTPUT VOLTAGE 0.0 -5.0 -10.0 -15.0 -20.0 TA = 85C -25.0 TA = 25C 0.5 1.5 Figure 5 Figure 4 -30.0 0.0 1.0 VOL - Low-Level Output Voltage - V 1.0 1.5 2.0 2.5 -5.0 VCC = 3 V P2.4 -10.0 -15.0 -20.0 -25.0 -30.0 -35.0 -40.0 -45.0 TA = 85C -50.0 -55.0 0.0 TA = 25C 0.5 VOH - High-Level Output Voltage - V 1.0 1.5 2.0 2.5 3.0 3.5 VOH - High-Level Output Voltage - V Figure 7 Figure 6 NOTE: One output loaded at a time. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 29 MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C - MAY 2007 - REVISED MARCH 2011 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) POR/brownout reset (BOR) (see Notes 1 and 2) PARAMETER TEST CONDITIONS VCC(start) (see Figure 8) dVCC/dt 3 V/s V(B_IT-) (see Figure 8 through Figure 10) dVCC/dt 3 V/s Vhys(B_IT-) (see Figure 8) dVCC/dt 3 V/s td(BOR) (see Figure 8) t(reset) Pulse length needed at RST/NMI pin to accepted reset internally VCC MIN TYP MAX 0.7 x V(B_IT-) 70 2.2 V/3 V 2 130 UNIT V 1.71 V 180 mV 2000 s s NOTES: 1. The current consumption of the brownout module is already included in the ICC current consumption data. The voltage level V(B_IT-) + Vhys(B_IT-) is 1.8V. 2. During power up, the CPU begins code execution following a period of td(BOR) after VCC = V(B_IT-) + Vhys(B_IT-). The default FLL+ settings must not be changed until VCC VCC(min), where VCC(min) is the minimum supply voltage for the desired operating frequency. See the MSP430x4xx Family User's Guide (SLAU056) for more information on the brownout/SVS circuit. VCC Vhys(B_IT-) V(B_IT-) VCC(start) 1 0 t d(BOR) Figure 8. POR/Brownout Reset (BOR) vs Supply Voltage 30 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C - MAY 2007 - REVISED MARCH 2011 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) typical characteristics - POR/brownout reset (BOR) VCC 3V 2 VCC(drop) - V VCC = 3 V Typical Conditions t pw 1.5 1 VCC(drop) 0.5 0 0.001 1 1000 1 ns tpw - Pulse Width - s 1 ns tpw - Pulse Width - s Figure 9. VCC(drop) Level With a Square Voltage Drop to Generate a POR/Brownout Signal VCC 2 t pw 3V VCC(drop) - V VCC = 3 V 1.5 Typical Conditions 1 VCC(drop) 0.5 0 0.001 tf = tr 1 1000 tf tr tpw - Pulse Width - s tpw - Pulse Width - s Figure 10. VCC(drop) Level With a Triangle Voltage Drop to Generate a POR/Brownout Signal POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 31 MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C - MAY 2007 - REVISED MARCH 2011 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) SVS (supply voltage supervisor/monitor) (see Note 1) PARAMETER t(SVSR) TEST CONDITIONS MIN dVCC/dt > 30 V/ms (see Figure 11) MAX 150 dVCC/dt 30 V/ms 2000 td(SVSon) SVSon, switch from VLD = 0 to VLD 0, VCC = 3 V tsettle VLD 0 (see Note 2) V(SVSstart) VLD 0, VCC/dt 3 V/s (see Figure 11) 150 1.55 VLD = 1 VCC/dt 3 V/s (see Figure 11) VLD = 2 .. 14 Vhys(SVS_IT-) VCC/dt 3 V/s (see Figure 11), external voltage applied on A7 VCC/dt 3 V/s (see Figure 11) V(SVS_IT-) (SVS IT ) VCC/dt 3 V/s (see Figure 11), external voltage applied on A7 ICC(SVS) (see Note 1) TYP 5 VLD = 15 70 120 s 12 s 1.7 V 155 mV V(SVS_IT-) x 0.001 V(SVS_IT-) x 0.016 4.4 10.4 1.8 1.9 2.05 VLD = 2 1.94 2.1 2.25 VLD = 3 2.05 2.2 2.37 VLD = 4 2.14 2.3 2.48 VLD = 5 2.24 2.4 2.6 VLD = 6 2.33 2.5 2.71 VLD = 7 2.46 2.65 2.86 VLD = 8 2.58 2.8 3 VLD = 9 2.69 2.9 3.13 VLD = 10 2.83 3.05 3.29 VLD = 11 2.94 3.2 3.42 VLD = 12 3.11 3.35 3.61 VLD = 13 3.24 3.5 3.76 VLD = 14 3.43 3.7 3.99 VLD = 15 1.1 1.2 1.3 10 15 s 300 VLD = 1 VLD 0, VCC = 2.2 V/3 V UNIT mV V A The recommended operating voltage range is limited to 3.6 V. NOTES: 1. The current consumption of the SVS module is not included in the ICC current consumption data. 2. tsettle is the settling time that the comparator output needs to have a stable level after VLD is switched VLD 0 to a different VLD value somewhere between 2 and 15. The overdrive is assumed to be > 50 mV. 32 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C - MAY 2007 - REVISED MARCH 2011 typical characteristics Software Sets VLD>0: SVS is Active VCC V(SVS_IT-) V(SVSstart) Vhys(SVS_IT-) Vhys(B_IT-) V(B_IT-) VCC(start) BrownOut Region Brownout Region Brownout 1 0 td(BOR) SVSOut t d(BOR) SVS Circuit is Active From VLD > to VCC < V(B_IT-) 1 0 td(SVSon) Set POR 1 td(SVSR) undefined 0 Figure 11. SVS Reset (SVSR) vs Supply Voltage VCC 3V t pw 2 Rectangular Drop VCC(min) VCC(min)- V 1.5 Triangular Drop 1 1 ns 1 ns VCC 0.5 t pw 3V 0 1 10 100 1000 tpw - Pulse Width - s VCC(min) tf = tr tf tr t - Pulse Width - s Figure 12. VCC(min) With a Square Voltage Drop and a Triangle Voltage Drop to Generate an SVS Signal POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 33 MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C - MAY 2007 - REVISED MARCH 2011 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) DCO PARAMETER TEST CONDITIONS VCC f(DCOCLK) N(DCO) = 01Eh, FN_8 = FN_4 = FN_3 = FN_2 = 0, D = 2, DCOPLUS = 0 f(DCO = 2) FN 8 = FN_4 FN_8 FN 4 = FN_3 FN 3 = FN_2 FN 2 = 0, 0 DCOPLUS = 1 f(DCO = 27) FN 8 = FN_4 FN_8 FN 4 = FN_3 FN 3 = FN_2 FN 2 = 0, 0 DCOPLUS = 1 FN_8 = FN_4 = FN_3 = 0, FN_2 = 1, DCOPLUS = 1 f(DCO = 2) f(DCO = 27) FN 8 = FN_4 FN 4 = FN_3 FN 3 = 0, 0 FN_2 FN 2 = 1 FN_8 1, DOPLUS = 1 f(DCO = 2) FN 8 = FN_4 FN_8 FN 4 = 0, 0 FN_3 FN 3 = 1, 1 FN_2 FN 2 = x, x DCOPLUS = 1 f(DCO = 27) FN 8 = FN_4 FN_8 FN 4 = 0, 0 FN_3 FN 3 = 1, 1 FN_2 FN 2 = x, x DCOPLUS = 1 f(DCO = 2) FN 8 = 0, FN_8 0 FN_4 FN 4 = 1, 1 FN_3 FN 3 = FN_2 FN 2 = x, x DCOPLUS = 1 f(DCO = 27) FN 8 = 0, FN_8 0 FN_4 FN 4 = 1, 1 FN_3 FN 3 = FN_2 FN 2 = x, x DCOPLUS = 1 f(DCO = 2) FN 8 = 1, 1 FN_4 FN 4 = FN_3 FN 3 = FN_2 FN 2 = xx, DCOPLUS = 1 FN_8 f(DCO = 27) FN 8 = 1, FN_8 1 FN_4 FN 4 = FN_3 FN 3 = FN_2 FN 2 = xx, DCOPLUS = 1 Sn Step size between adjacent DCO taps: Sn = fDCO(Tap n+1) / fDCO(Tap n) (see Figure 14 for taps 21 to 27) MIN 2.2 V/3 V 0.3 0.65 1.25 3V 0.3 0.7 1.3 2.2 V 2.5 5.6 10.5 3V 2.7 6.1 11.3 2.2 V 0.7 1.3 2.3 3V 0.8 1.5 2.5 2.2 V 5.7 10.8 18 3V 6.5 12.1 20 2.2 V 1.2 2 3 3V 1.3 2.2 3.5 9 15.5 25 3V 10.3 17.9 28.5 2.2 V 1.8 2.8 4.2 3V 2.1 3.4 5.2 2.2 V f f f (DCO) f (DCO3V) 13.5 21.5 33 3V 16 26.6 41 2.2 V 2.8 4.2 6.2 3V 4.2 6.3 9.2 2.2 V 21 32 46 3V 30 46 70 1.06 1.11 TAP = 27 1.07 1.17 Drift with VCC variation, N(DCO) = 01Eh, FN_8 = FN_4 = FN_3 = FN_2 = 0, D = 2, DCOPLUS = 0 2.2 V -0.2 -0.3 -0.4 3V -0.2 -0.3 -0.4 0 5 15 40 60 2.2 V/3 V MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz %/_C %/V (DCO) (DCO205C) 1.0 1.0 0 1.8 2.4 3.0 3.6 VCC - V -40 -20 0 20 Figure 13. DCO Frequency vs Supply Voltage VCC and vs Ambient Temperature 34 UNIT MHz 1 < TAP 20 Temperature drift, N(DCO) = 01Eh, FN_8 = FN_4 = FN_3 = FN_2 = 0, D = 2, DCOPLUS = 0 DV MAX 1 2.2 V 2.2 V Dt TYP POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 85 TA - C MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C - MAY 2007 - REVISED MARCH 2011 Sn - Stepsize Ratio between DCO Taps electrical characteristics over recommended operating free-air temperature (unless otherwise noted) 1.17 IIIIIIIIIIIII IIIIIIIIIIIII IIIIIIIIIIIII IIIIIIIIIIIII IIIIIIIIIIIII IIIIIIIIIIIII IIIIIIIIIIIII IIIIIIIIIIIII IIIIIIIIIIIII IIIIIIIIIIIII Max 1.11 1.07 1.06 Min 1 20 27 DCO Tap Figure 14. DCO Tap Step Size f(DCO) Legend Tolerance at Tap 27 DCO Frequency Adjusted by Bits 29 to 2 5 in SCFI1 {N (DCO)} Tolerance at Tap 2 Overlapping DCO Ranges: uninterrupted frequency range FN_2=0 FN_3=0 FN_4=0 FN_8=0 FN_2=1 FN_3=0 FN_4=0 FN_8=0 FN_2=x FN_3=1 FN_4=0 FN_8=0 FN_2=x FN_3=x FN_4=1 FN_8=0 FN_2=x FN_3=x FN_4=x FN_8=1 Figure 15. Five Overlapping DCO Ranges Controlled by FN_x Bits POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 35 MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C - MAY 2007 - REVISED MARCH 2011 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) crystal oscillator, LFXT1, low-frequency modes (see Note 4) PARAMETER TEST CONDITIONS VCC MIN fLFXT1, LF LFXT1 oscillator crystal frequency, LF mode XTS_FLL = 0, LFXT1DIG = 0 1.8 V-3.6 V fLFXT1, LF, logic LFXT1 oscillator logic level square-wave input frequency, LF mode XTS_FLL = 0, LFXT1DIG = 1, XCAPx = 0 1.8 V-3.6 V OALF CL, eff Oscillation allowance for LF crystals Integrated effective load capacitance LF mode capacitance, (see Note 1) 10, 000 TYP MAX UNIT 32, 768 Hz 32, 768 Hz XTS_FLL = 0, LFXT1DIG = 0, fLFXT1, LF = 32,768 kHz, CL, eff = 6 pF 500 XTS_FLL = 0, LFXT1DIG = 0, fLFXT1, LF = 32,768 kHz, CL, eff = 12 pF 200 kW XTS_FLL = 0, XCAPx = 0 1 XTS_FLL = 0, XCAPx = 1 5.5 XTS_FLL = 0, XCAPx = 2 8.5 XTS_FLL = 0, XCAPx = 3 11 Duty Cycle LF mode XTS_FLL = 0, Measured at P1.4/ACLK, fLFXT1, LF = 32, 768 Hz 2.2 V/3 V 30 fFault, LF Oscillator fault frequency, LF mode (see Note 3) XTS_FLL = 0 (see Note 2) 2.2 V/3 V 10 pF 50 70 % 10, 000 Hz NOTES: 1. Includes parasitic bond and package capacitance (approximately 2pF per pin). Since the PCB adds additional capacitance it is recommended to verify the correct load by measuring the ACLK frequency. For a correct setup the effective load capacitance should always match the specification of the used crystal. 2. Measured with logic level input frequency but also applies to operation with crystals. 3. Frequencies below the MIN specification will set the fault flag, frequencies above the MAX specification will not set the fault flag. Frequencies in between might set the flag. 4. To improve EMI on the LFXT1 oscillator the following guidelines should be observed. - Keep as short of a trace as possible between the device and the crystal. - Design a good ground plane around the oscillator pins. - Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT. - Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins. - Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins. - If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins. - Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other documentation. This signal is no longer required for the serial programming adapter. crystal oscillator, LFXT1, high-frequency mode PARAMETER TEST CONDITIONS fXT1 XT1 oscillator crystal frequency XTS_FLL XTS FLL = 1, 1 Ceramic resonator fXT1 XT1 oscillator crystal frequency XTS_FLL XTS FLL = 1, 1 Crystal CL, eff Integrated effective Load Capacitance (see Note 1) XTS_FLL = 1, XCAPx = 0 (see Note 2) Duty Cycle Measured at P1.4/ACLK VCC MIN TYP MAX 1.8 V-3.6 V 0.45 4 2.7 V-3.6 V 0.45 8 1.8 V-3.6 V 1 4 2.7 V-3.6 V 1 8 1 2.2 V/3 V 40 50 UNIT MHz MHz pF 60 % NOTES: 1. Includes parasitic bond and package capacitance (approximately 2pF per pin). Since the PCB adds additional capacitance it is recommended to verify the correct load by measuring the ACLK frequency. For a correct setup the effective load capacitance should always match the specification of the used crystal. 2. Requires external capacitors at both terminals. Values are specified by crystal manufacturers. 36 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C - MAY 2007 - REVISED MARCH 2011 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) crystal oscillator, XT2 oscillator (see Note 5) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT fXT2, 0 XT2 oscillator crystal frequency, mode 0 XT2Sx = 0 1.8 V - 3.6 V 0.4 1 MHz fXT2, 1 XT2 oscillator crystal frequency, mode 1 XT2Sx = 1 1.8 V - 3.6 V 1 4 MHz 1.8 V - 3.6 V 2 10 fXT2, 2 XT2 oscillator ill t crystal t l ffrequency, mode 2 XT2Sx = 2 2.2 V - 3.6 V 2 12 3.0 V - 3.6 V 2 16 1.8 V - 3.6 V 0.4 10 2.2 V - 3.6 V 0.4 12 3.0 V - 3.6 V 0.4 16 fXT2, logic XT2 oscillator ill t llogic i llevell square-wave input frequency XT2Sx = 3 XT2Sx = 0, fXT2 = 1 MHz, CL, eff = 15 pF OAXT2 CL, eff Oscillation allowance for HF crystals (see Figure 16) Integrated effective load capacitance (see Note 1) Duty cycle fFault, XT2 Oscillator fault frequency (see Note 4) MHz MHz 2700 XT2Sx = 1 fLFXT1, HF = 4 MHz, CL, eff = 15 pF 800 XT2Sx = 2 fLFXT1, HF = 16 MHz, CL, eff = 15 pF 300 (see Note 2) W 1 pF Measured at P1.4/ACLK, fXT2 = 10 MHz 2.2 V/3 V 40 50 60 Measured at P1.4/ACLK, fXT2 = 16 MHz 3V 40 50 60 XT2Sx = 3 (see Note 3) 2.2 V/3 V 30 % 300 kHz NOTES: 1. Includes parasitic bond and package capacitance (approximately 2pF per pin). Since the PCB adds additional capacitance it is recommended to verify the correct load by measuring the ACLK frequency. For a correct setup the effective load capacitance should always match the specification of the used crystal. 2. Requires external capacitors at both terminals. Values are specified by crystal manufacturers. 3. Measured with logic level input frequency but also applies to operation with crystals. 4. Frequencies below the MIN specification will set the fault flag, frequencies above the MAX specification will not set the fault flag. Frequencies in between might set the flag. 5. To improve EMI on the XT2 oscillator the following guidelines should be observed. - Keep traces as short as possible between the device and the crystal. - Design a good ground plane around the oscillator pins. - Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT. - Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins. - Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins. - If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins. - Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other documentation. This signal is no longer required for the serial programming adapter. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 37 MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C - MAY 2007 - REVISED MARCH 2011 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) typical characteristics - XT2 oscillator Oscillation Allowance - Ohms 100000.00 10000.00 1000.00 XT2Sx = 2 100.00 XT2Sx = 0 XT2Sx = 1 10.00 0.10 1.00 10.00 100.00 Crystal Frequency - MHz Figure 16. Oscillation Allowance vs Crystal Frequency, CL, eff = 15 pF, TA = 25C 38 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C - MAY 2007 - REVISED MARCH 2011 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) wake-up LPM3 PARAMETER TEST CONDITIONS MIN TYP f = 1 MHz td(LPM3) f = 2 MHz Delay time MAX UNIT 6 6 VCC = 2.2 V/3 V f = 3 MHz s 6 LCD_A PARAMETER TEST CONDITIONS VCC(LCD) Supply voltage range Charge pump enabled (LCDCPEN = 1, VLCDx > 0000) CLCD Capacitor on LCDCAP (see Note 1) Charge pump enabled (LCDCPEN = 1, VLCDx > 0000) ICC(LCD) Supply current VLCD(typ) = 3V, LCDCPEN = 1, VLCDx = 1000, All segments on, fLCD = fACLK/32, No LCD connected (see Note 2), TA = 25C fLCD LCD frequency VLCD RLCD LCD voltage LCD driver output impedance VCC 2.2 V MIN 2.2 4.7 TYP MAX 3.6 A 3.8 1.1 VCC VLCDx = 0001 2.60 VLCDx = 0010 2.66 VLCDx = 0011 2.72 VLCDx = 0100 2.78 VLCDx = 0101 2.84 VLCDx = 0110 2.90 VLCDx = 0111 2.96 VLCDx = 1000 3.02 VLCDx = 1001 3.08 VLCDx = 1010 3.14 VLCDx = 1011 3.20 VLCDx = 1100 3.26 VLCDx = 1101 3.32 VLCDx = 1110 3.38 VLCDx = 1111 3.44 2.2 V V F VLCDx = 0000 VLCD = 3V, LCDCPEN = 1, VLCDx = 1000, ILOAD = 10A UNIT kHz V 3.60 10 k NOTES: 1. Enabling the internal charge pump with an external capacitor smaller than the minimum specified might damage the device. 2. Connecting an actual display will increase the current consumption depending on the size of the LCD. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 39 MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C - MAY 2007 - REVISED MARCH 2011 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) Comparator_A (see Note 1) PARAMETER TEST CONDITIONS I(CC) CAON = 1 1, CARSEL = 0 0, CAREF = 0 I(Refladder/RefDiode) CAON = 1, CARSEL = 0, CAREF = 1/2/3 1/2/3, No load at P1.6/CA0 and P1.7/CA1 V(Ref025) V(Ref050) Voltage @ 0.25 V V CC MIN TYP MAX 2.2 V 25 40 3V 45 60 2.2 V 30 50 3V 45 80 node PCA0 = 1, CARSEL = 1, CAREF = 1, No load at P1.6/CA0 and P1.7/CA1 2.2 V/3 V 0.23 0.24 0.25 node PCA0 = 1, CARSEL = 1, CAREF = 2, No load at P1.6/CA0 and P1.7/CA1 2.2 V/3 V 0.47 0.48 0.5 2.2 V 390 480 540 3V 400 490 550 CC V CC Voltage @ 0.5 V VCC CC UNIT A A A A V(RefVT) See Figure 17 and Figure 18 PCA0 = 1, CARSEL = 1, CAREF = 3, P1 6/CA0 and P1.7/CA1, P1 7/CA1 No load at P1.6/CA0 TA = 85C VIC Common-mode input voltage range CAON = 1 2.2 V/3 V 0 VCC-1 Vp-VS Offset voltage See Note 2 2.2 V/3 V -30 30 mV Vhys Input hysteresis CAON = 1 2.2 V/3 V 0 0.7 1.4 mV TA = 25 25C, C, Overdrive 10 mV, without filter: CAF = 0 2.2 V 80 165 300 3V 70 120 240 TA = 25 25C C Overdrive 10 mV, with filter: CAF = 1 2.2 V 1.4 1.9 2.8 3V 0.9 1.5 2.2 t(response LH and HL), see Note 3 mV V ns ss NOTES: 1. The leakage current for the Comparator_A terminals is identical to Ilkg(Px.x) specification. 2. The input offset voltage can be cancelled by using the CAEX bit to invert the Comparator_A inputs on successive measurements. The two successive measurements are then summed together. 3. The response time is measured at P1.6/CA0 with an input voltage step and the Comparator_A already enabled (CAON = 1). If CAON is set at the same time, a settling time of up to 300 ns is added to the response time. 40 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C - MAY 2007 - REVISED MARCH 2011 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) typical characteristics REFERENCE VOLTAGE vs FREE-AIR TEMPERATURE REFERENCE VOLTAGE vs FREE-AIR TEMPERATURE 650 650 VCC = 2.2 V 600 VREF - Reference Voltage - mV VREF - Reference Voltage - mV VCC = 3 V Typical 550 500 450 400 -45 -25 -5 15 35 55 75 600 Typical 550 500 450 400 -45 95 -25 TA - Free-Air Temperature - C 0 15 35 55 75 95 TA - Free-Air Temperature - C Figure 17. V(RefVT) vs Temperature 0V -5 Figure 18. V(RefVT) vs Temperature VCC CAF 1 CAON Low-Pass Filter V+ V- + _ 0 0 1 1 To Internal Modules CAOUT Set CAIFG Flag 2 s Figure 19. Block Diagram of Comparator_A Module VCAOUT Overdrive V- 400 mV V+ t(response) Figure 20. Overdrive Definition POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 41 MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C - MAY 2007 - REVISED MARCH 2011 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) Timer_A PARAMETER fTA Timer A clock frequency Timer_A tTA, cap Timer_A, capture timing TEST CONDITIONS Internal: SMCLK, ACLK, External: TACLK TACLK, INCLK INCLK, Duty Cycle = 50% 10% TA0, TA1, TA2 VCC MIN MAX 2.2 V 10 3V 16 UNIT MHz 2.2 V/3 V 20 ns Timer_B PARAMETER fTB Timer B clock frequency Timer_B tTB, cap Timer_B, capture timing 42 TEST CONDITIONS Internal: SMCLK, ACLK, External: TBCLK, TBCLK Duty Cycle = 50% 10% TB0, TB1, TB2 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 VCC MIN MAX 2.2 V 10 3V 16 UNIT MHz 2.2 V/3 V 20 ns MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C - MAY 2007 - REVISED MARCH 2011 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) USCI (UART mode) PARAMETER fUSCI USCI input clock frequency fBITCLK BITCLK clock frequency (equals Baudrate in MBaud) t UART receive deglitch time (see Note 1) TEST CONDITIONS VCC MIN TYP Internal: SMCLK, ACLK External: UCLK Duty Cycle = 50% 10% 2.2V /3 V MAX UNIT fSYSTEM MHz 1 MHz 2.2 V 50 150 600 ns 3V 50 100 600 ns NOTES: 1. Pulses on the UART receive input (UCxRX) shorter than the UART receive deglich time are suppressed. To ensure that pulses are correctly recognized their width should exceed the maximum specification of the deglitch time. USCI (SPI master mode) (see Figure 21 and Figure 22) PARAMETER fUSCI USCI input clock frequency tSU, MI SOMI input data setup time tHD, MI VCC UCLK edge to SIMO valid, CL = 20 pF SIMO output data valid time f UCxCLK + MIN SMCLK, ACLK Duty Cycle = 50% 10% SOMI input data hold time tVALID, MO NOTE: TEST CONDITIONS MAX UNIT fSYSTEM MHz 2.2 V 110 ns 3V 75 ns 2.2 V 0 ns 3V 0 ns 2.2 V 30 ns 3V 20 ns 1 with t LOHI w max(t VALID,MO(USCI) ) t SU,SI(Slave), t SU,MI(USCI) ) t VALID,SO(Slave)). 2t LOHI For the slave's parameters tSU, SI(Slave) and tVALID, SO(Slave) see the SPI parameters of the attached slave. USCI (SPI slave mode) (see Figure 23 and Figure 24) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT tSTE, LEAD STE lead time STE low to clock 2.2 V/3 V tSTE, LAG STE lag time Last clock to STE high 2.2 V/3 V tSTE, ACC STE access time STE low to SOMI data out 2.2 V/3 V 50 ns tSTE, DIS STE disable time STE high to SOMI high impedance 2.2 V/3 V 50 ns tSU, SI SIMO input data setup time tHD, SI SIMO input data hold time tVALID, SO NOTE: SOMI output data valid time f UCxCLK + UCLK edge to SOMI valid, CL = 20 pF 50 ns 10 ns 2.2 V 20 ns 3V 15 ns 2.2 V 10 ns 3V 10 ns 2.2 V 75 110 ns 3V 50 75 ns 1 with t LOHI w max(t VALID,MO(Master) ) t SU,SI(USCI), t SU,MI(Master) ) t VALID,SO(USCI)) . 2t LOHI For the master's parameters tSU, MI(Master) and tVALID, MO(Master) see the SPI parameters of the attached master. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 43 MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C - MAY 2007 - REVISED MARCH 2011 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) 1/fUCxCLK CKPL=0 UCLK CKPL=1 tLO/HI tLO/HI tSU,MI tHD,MI SOMI tVALID,MO SIMO Figure 21. SPI Master Mode, CKPH = 0 1/fUCxCLK CKPL=0 UCLK CKPL=1 tLO/HI tLO/HI tSU,MI SOMI tVALID,MO SIMO Figure 22. SPI Master Mode, CKPH = 1 44 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 tHD,MI MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C - MAY 2007 - REVISED MARCH 2011 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) tSTE,LEAD tSTE,LAG STE 1/fUCxCLK CKPL=0 UCLK CKPL=1 tLO/HI tLO/HI tSU,SI tHD,SI SIMO tSTE,ACC tVALID,SO tSTE,DIS SOMI Figure 23. SPI Slave Mode, CKPH = 0 tSTE,LEAD tSTE,LAG STE 1/fUCxCLK CKPL=0 UCLK CKPL=1 tLO/HI tLO/HI tSU,SI tHD,SI SIMO tSTE,ACC tVALID,SO tSTE,DIS SOMI Figure 24. SPI Slave Mode, CKPH = 1 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 45 MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C - MAY 2007 - REVISED MARCH 2011 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) USCI (I2C mode) (see Figure 25) PARAMETER fUSCI USCI input clock frequency fSCL SCL clock frequency TEST CONDITIONS VCC MIN TYP Internal: SMCLK, ACLK External: UCLK Duty cycle = 50% 10% 2.2 V/3 V 0 fSCL 100 kHz 2.2 V/3 V 4.0 fSCL > 100 kHz 2.2 V/3 V 0.6 fSCL 100 kHz 2.2 V/3 V 4.7 fSCL > 100 kHz 2.2 V/3 V 0.6 MAX UNIT fSYSTEM MHz 400 kHz tHD, STA Hold time (repeated) START tSU, STA Setup time for a repeated START tHD, DAT Data hold time 2.2 V/3 V 0 ns tSU, DAT Data setup time 2.2 V/3 V 250 ns tSU, STO Setup time for STOP 2.2 V/3 V 4.0 us 2.2 V 50 150 600 tSP Pulse width of spikes suppressed by input filter 3V 50 100 600 tHD,STA tSU,STA tHD,STA SDA 1/fSCL tSP SCL tSU,DAT tSU,STO tHD,DAT Figure 25. I2C Mode Timing 46 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 us us ns MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C - MAY 2007 - REVISED MARCH 2011 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) SD16_A, power supply and recommended operating conditions PARAMETER AVCC Analog supply voltage ISD16 Analog supply t 1 active ti current: SD16 A channel SD16_A including internal reference fSD16 Analog front-end input clock frequency TEST CONDITIONS VCC MIN AVCC = DVCC AVSS = DVSS = 0V TYP MAX 2.5 3.6 SD16LP = 0, fSD16 = 1 MHz, SD16OSR = 256 GAIN: 1, 2 3V 730 1050 GAIN: 4, 8, 16 3V 810 1150 GAIN: 32 3V 1160 1700 SD16LP = 1, 0 5 MHz MHz, fSD16 = 0.5 SD16OSR = 256 GAIN: 1 3V 720 1030 GAIN: 32 3V 810 1150 1.1 SD16LP = 0 (Low power mode disabled) 3V 0.03 1 SD16LP = 1 (Low power mode enabled) 3V 0.03 0.5 UNIT V A MHz SD16_A, input range (see Note 1) PARAMETER VID, FSR VID Differential full scale input voltage range Differential input voltage range for specified performance (see Note 2) TEST CONDITIONS VCC Bipolar mode, SD16UNI = 0 Unipolar mode, SD16UNI = 1 SD16REFON = 1 MIN TYP MAX -VREF/2GAIN +VREF/2GAIN 0 +VREF/2GAIN SD16GAINx = 1 500 SD16GAINx = 2 250 SD16GAINx = 4 125 SD16GAINx = 8 62 SD16GAINx = 16 31 SD16GAINx = 32 15 UNIT mV mV ZI Input impedance (one input pin to AVSS) fSD16 = 1 MHz ZID Differential input impedance (IN+ to IN-) fSD16 = 1 MHz VI Absolute input voltage range AVSS -1V AVCC V VIC Common-mode input voltage range AVSS -1V AVCC V SD16GAINx = 1 3V 200 SD16GAINx = 32 3V 75 SD16GAINx = 1 3V 300 400 SD16GAINx = 32 3V 100 150 k k NOTES: 1. All parameters pertain to each SD16_A channel. 2. The analog input range depends on the reference voltage applied to VREF. If VREF is sourced externally, the full-scale range is defined by VFSR+ = +(VREF/2)/GAIN and VFSR- = -(VREF/2)/GAIN. The analog input range should not exceed 80% of VFSR+ or VFSR-. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 47 MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C - MAY 2007 - REVISED MARCH 2011 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) SD16_A, performance (fSD16 = 1MHz, SD16OSRx = 256, SD16REFON = 1) PARAMETER SINAD G Signal to noise + Signal-to-noise distortion ratio Nominal gain EOS Offset error dEOS/dT Offset error temperature coefficient CMRR Common mode rejection Common-mode ratio TEST CONDITIONS VCC MIN TYP MAX SD16GAINx = 1, Signal Amplitude VPP = 500 mV 3V 83 85 SD16GAINx = 2, Signal Amplitude VPP = 250 mV 3V 81 84 3V 76 79 3V 70 75 SD16GAINx = 16, Signal Amplitude VPP = 31 mV 3V 66 70 SD16GAINx = 32, Signal Amplitude VPP = 15 mV 3V 62 65 SD16GAINx = 1 3V 0.97 1.00 1.02 SD16GAINx = 2 3V 1.90 1.96 2.02 3.96 SD16GAINx = 4, Signal Amplitude VPP = 125 mV SD16GAINx = 8, Signal Amplitude VPP = 62 mV fIN = 50 Hz, 100 Hz (see Notes 1 and 2) UNIT dB SD16GAINx = 4 3V 3.76 3.86 SD16GAINx = 8 3V 7.36 7.62 7.84 SD16GAINx = 16 3V 14.56 15.04 15.52 SD16GAINx = 32 3V 27.20 28.35 29.76 SD16GAINx = 1 3V 0.2 SD16GAINx = 32 3V 1.5 %FSR ppm FSR/_C SD16GAINx = 1 3V 4 20 SD16GAINx = 32 3V 20 100 SD16GAINx = 1, Common-mode input signal: VID = 500 mV, fIN = 50 Hz, 100 Hz 3V >90 SD16GAINx = 32, Common-mode input signal: VID = 16 mV, fIN = 50 Hz, 100 Hz 3V >75 dB AC PSRR AC power supply rejection ratio SD16GAINx = 1, VCC = 3V 100mV, fVcc = 50 Hz 3V >80 dB XT Crosstalk SD16GAINx = 1, VID = 500 mV, fIN = 50 Hz, 100 Hz 3V <-100 dB NOTES: 1. The following voltages were applied to the SD16 inputs: VIN, A+(t) = 1.2V + VPP/2 x sin(2 x fIN x t) VIN, A-(t) = 1.2V - VPP/2 x sin(2 x fIN x t) resulting in a differential voltage of Vdiff = VIN, A+(t) - VIN, A-(t) = VPP x sin(2 x fIN x t) 2. The SINAD performance of the SD16_A maybe degraded. See errata sheet. 48 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C - MAY 2007 - REVISED MARCH 2011 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) typical characteristics - SD16_A SNR/SINAD performance over OSR 100.0 SNR/SINAD - dB 95.0 90.0 SNR 85.0 SINAD 80.0 75.0 70.0 65.0 60.0 55.0 50.0 10.00 100.00 1000.00 OSR Figure 26. SNR/SINAD performance over OSR, fSD16 = 1MHz, SD16REFON = 1, SD16GAINx = 1 VIN(t) = 1.2V + 500mV y sin(2p y 50Hz y t) SD16_A, temperature sensor and built-in VCC sense PARAMETER TCSensor Sensor temperature coefficient VOffset, sensor Sensor offset voltage VSensor Sensor output S t t voltage lt (see Note 2) VCC, Sense VCC divider at input 5 RSource, VCC Source resistance of VCC divider at input 5 TEST CONDITIONS VCC MIN 1.18 TYP 1.32 -100 MAX UNIT 1.46 mV/K 100 mV Temperature sensor voltage at TA = 85C 3V 435 475 515 Temperature sensor voltage at TA = 25C 3V 355 395 435 Temperature sensor voltage at TA = 0C 3V 320 360 400 0.08 1/11 0.10 fSD16 = 32kHz, SD16OSRx = 256, SD16REFON = 1 500 mV VCC k NOTES: 1. The following formula can be used to calculate the temperature sensor output voltage: VSensor, typ = TCSensor ( 273 + T [C] ) + VOffset, sensor [mV] 2. Results based on characterization and/or production test, not TCSensor or VOffset, sensor. Measured with fSD16 = 1MHz, SD16OSRx = 256, SD16REFON = 1. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 49 MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C - MAY 2007 - REVISED MARCH 2011 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) SD16_A, built-in voltage reference PARAMETER TEST CONDITIONS VCC VREF Internal reference voltage SD16REFON = 1, SD16VMIDON = 0 3V IREF Reference supply current SD16REFON = 1, SD16VMIDON = 0 3V TC Temperature coefficient SD16REFON = 1, SD16VMIDON = 0 (see Note 1) 3V CREF VREF load capacitance SD16REFON = 1, SD16VMIDON = 0 (see Note 2) ILOAD VREF(I) maximum load current SD16REFON = 1, SD16VMIDON = 0 3V tON Turn on time SD16REFON = 0->1, SD16VMIDON = 0, CREF = 100nF 3V DC PSR DC Power Supply Rejection VREF/VCC SD16REFON = 1, SD16VMIDON = 0, VCC = 2.5V - 3.6V MIN 1.14 TYP MAX UNIT 1.20 1.26 V 175 260 A 18 50 ppm/K 100 nF 200 5 nA ms 100 uV/V NOTES: 1. Calculated using the box method: (MAX(-40...85C) - MIN(-40...85C)) / MIN(-40...85C) / (85C - (-40C)) 2. There is no capacitance required on VREF. However, a capacitance of at least 100nF is recommended to reduce any reference voltage noise. SD16_A, reference output buffer PARAMETER TEST CONDITIONS VCC VREF, BUF Reference buffer output voltage SD16REFON = 1, SD16VMIDON = 1 3V 1.2 IREF, BUF Reference Supply + Reference output buffer quiescent current SD16REFON = 1, SD16VMIDON = 1 3V 385 CREF(O) Required load capacitance on VREF SD16REFON = 1, SD16VMIDON = 1 ILOAD, Max Maximum load current on VREF SD16REFON = 1, SD16VMIDON = 1 3V Maximum voltage variation vs. load current |ILOAD| = 0 to 1mA 3V Turn on time SD16REFON = 0->1, SD16VMIDON = 0->1, CREF = 470nF 3V tON MIN TYP MAX UNIT V 600 470 A nF -15 1 mA +15 mV s 100 SD16_A, external reference input PARAMETER TEST CONDITIONS VCC VREF(I) Input voltage range SD16REFON = 0 3V IREF(I) Input current SD16REFON = 0 3V 50 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 MIN 1.0 TYP 1.25 MAX UNIT 1.5 V 50 nA MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C - MAY 2007 - REVISED MARCH 2011 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) flash memory PARAMETER VCC(PGM/ TEST CONDITIONS VCC MIN Program and Erase supply voltage TYP 2.2 MAX UNIT 3.6 V 476 kHz 5 mA 7 mA 10 ms ERASE) fFTG Flash Timing Generator frequency IPGM Supply current from VCC during program 2.2 V/3.6 V 257 3 IERASE Supply current from VCC during erase 2.2 V/3.6 V 3 tCPT Cumulative program time (see Note 1) 2.2 V/3.6 V tCMErase Cumulative mass erase time 2.2 V/3.6 V 20 104 Program/Erase endurance TJ = 25C ms 105 tRetention Data retention duration tWord Word or byte program time 30 tBlock, 0 Block program time for 1st byte or word 25 tBlock, 1-63 Block program time for each additional byte or word tBlock, End Block program end-sequence wait time tMass Erase Mass erase time tSeg Erase Segment erase time cycles 100 years 18 see Note 2 tFTG 6 10593 4819 NOTES: 1. The cumulative program time must not be exceeded when writing to a 64-byte flash block. This parameter applies to all programming methods: individual word/byte write and block write modes. 2. These values are hardwired into the Flash Controller's state machine (tFTG = 1/fFTG). RAM PARAMETER V(RAMh) TEST CONDITIONS RAM retention supply voltage (see Note 1) MIN CPU halted TYP MAX 1.6 UNIT V NOTE 1: This parameter defines the minimum supply voltage VCC when the data in RAM remains unchanged. No program execution should happen during this supply voltage condition. JTAG interface TEST CONDITIONS PARAMETER fTCK TCK input frequency see Note 1 RInternal Internal pull-up resistance on TMS, TCK, TDI/TCLK see Note 2 VCC MIN 2.2 V 0 3V 0 2.2 V/ 3 V 20 NOM MAX UNIT 5 MHz 10 MHz 35 50 k MIN MAX NOTES: 1. fTCK may be restricted to meet the timing requirements of the module selected. 2. TMS, TDI/TCLK, and TCK pull-up resistors are implemented in all versions. JTAG fuse (see Note 1) TEST CONDITIONS PARAMETER VCC(FB) Supply voltage during fuse-blow condition VFB Voltage level on TDI/TCLK for fuse-blow: F versions IFB Supply current into TDI/TCLK during fuse blow tFB Time to blow fuse TA = 25C VCC 2.5 6 UNIT V 7 V 100 mA 1 ms NOTES: 1. Once the fuse is blown, no further access to the MSP430 JTAG/Test and emulation features is possible. The JTAG block is switched to bypass mode. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 51 MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C - MAY 2007 - REVISED MARCH 2011 APPLICATION INFORMATION Port P1, P1.0 to P1.5, input/output with Schmitt trigger Pad Logic DVSS DVSS CAPD.x P1REN.x P1DIR.x 0 P1OUT.x 0 1 0 DVCC 1 Bus Keeper P1SEL.x EN P1IN.x EN Module X IN D P1IE.x P1IRQ.x EN Q P1IFG.x P1SEL.x P1IES.x 52 1 Direction 0: Input 1: Output 1 Module X OUT DVSS Set Interrupt Edge Select POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 P1.0/TA0 P1.1/TA0/MCLK P1.2/TA1 P1.3/TBOUTH/SVSOUT P1.4/TBCLK/SMCLK P1.5/TACLK/ACLK MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C - MAY 2007 - REVISED MARCH 2011 Port P1 (P1.0 to P1.5) pin functions (P1 X) PIN NAME (P1.X) P1.0/TA0 CONTROL BITS / SIGNALS X 0 FUNCTION P1.0 (I/O) Timer_A3.CCI0A P1.1/TA0/MCLK 1 2 3 4 5 1 0 1 1 0 X 1 P1.1 (I/O) I: 0, O: 1 0 0 Timer_A3.CCI0B 0 1 0 MCLK 1 1 0 P1.2 (I/O) X X 1 I: 0, O: 1 0 0 0 1 0 Timer_A3.TA1 1 1 0 Input buffer disabled (see Note 2) X X 1 I: 0, O: 1 0 0 Timer_B7.TBOUTH 0 1 0 SVSOUT 1 1 0 P1.3 (I/O) P1.4 (I/O) Timer_B7.TBCLK P1.5/TACLK/ACLK 0 0 X Input buffer disabled (see Note 2) P1.4/TBCLK/SMCLK CAPD.x 0 Input buffer disabled (see Note 2) Timer_A3.CCI1A P1.3/ TBOUTH/SVSOUT P1SEL.x I: 0, O: 1 Timer_A3.TA0 Input buffer disabled (see Note 2) P1.2/TA1 P1DIR.x X X 1 I: 0, O: 1 0 0 0 1 0 SMCLK 1 1 0 Input buffer disabled (see Note 2) X X 1 I: 0, O: 1 0 0 Timer_A3.TACLK 0 1 0 ACLK 1 1 0 Input buffer disabled (see Note 2) X X 1 P1.5 (I/O) NOTES: 1. X: Don't care. 2. Setting the CAPD.x bit disables the output driver as well as the input schmitt trigger to prevent parasitic cross currents when applying analog signals. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 53 MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C - MAY 2007 - REVISED MARCH 2011 Port P1, P1.6, P1.7, input/output with Schmitt trigger Pad Logic To Comparator_A From Comparator_A CAPD.x P1REN.x P1DIR.x 0 0 Module X OUT 1 0 1 1 Direction 0: Input 1: Output 1 P1OUT.x DVSS DVCC P1.6/CA0 P1.7/CA1 Bus Keeper P1SEL.x EN P1IN.x EN Module X IN D P1IE.x P1IRQ.x EN Q P1IFG.x Set Interrupt Edge Select P1SEL.x P1IES.x Port P1 (P1.6 and P1.7) pin functions PIN NAME (P1.X) (P1 X) P1.6/CA0 CONTROL BITS / SIGNALS X 6 FUNCTION P1DIR.x P1.6 (I/O) CA0 (see Note 2) P1.7/CA1 7 P1.7 (I/O) CA1 (see Note 2) P1SEL.x CAPD.x I: 0, O: 1 0 0 X X 1 I: 0, O: 1 0 0 X X 1 NOTES: 1. X: Don't care. 2. Setting the CAPD.x bit disables the output driver as well as the input schmitt trigger to prevent parasitic cross currents when applying analog signals. 54 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C - MAY 2007 - REVISED MARCH 2011 port P2, P2.0, P2.6 to P2.7, input/output with Schmitt trigger DVSS P2REN.x P2DIR.x 0 0 Module X OUT 1 0 DVCC 1 1 Direction 0: Input 1: Output 1 P2OUT.x DVSS Bus Keeper P2SEL.x P2.0/TA2 P2.6/CAOUT P2.7 EN P2IN.x EN Module X IN D P2IE.x EN P2IRQ.x Q Set P2IFG.x Interrupt Edge Select P2SEL.x P2IES.x Port P2 (P2.0, P2.6 and P2.7) pin functions PIN NAME (P2.X) (P2 X) P2.0/TA2 P2.6/CAOUT P2.7 CONTROL BITS / SIGNALS X 0 6 7 FUNCTION P2DIR.x P2SEL.x I: 0, O: 1 0 Timer_A3.CCI2A 0 1 Timer_A3.TA2 1 1 I: 0, O: 1 0 N/A 0 1 CAOUT 1 1 I: 0, O: 1 0 N/A 0 1 DVSS 1 1 P2.0 (I/O) P2.6 (I/O) P2.7 (I/O) NOTES: 1. N/A: Not available or not applicable 2. Setting TBOUTH causes all Timer_B outputs to be set to high impedance. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 55 MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C - MAY 2007 - REVISED MARCH 2011 port P2, P2.1 to P2.3, input/output with Schmitt trigger Timer_B Output Tristate Logic P1.3/TBOUTH/SVSOUT P1SEL.3 P1DIR.3 P2REN.x P2DIR.x 0 0 Module X OUT 1 0 1 1 Direction 0: Input 1: Output 1 P2OUT.x DVSS DVCC Bus Keeper P2SEL.x P2.1/TB0 P2.2/TB1 P2.3/TB2 EN P2IN.x EN Module X IN D P2IE.x P2IRQ.x EN Q P2IFG.x P2SEL.x P2IES.x Set Interrupt Edge Select Port P2 (P2.1 to P2.3) pin functions PIN NAME (P2.X) (P2 X) P2.1/TB0 P2.2/TB1 P2.3/TB3 CONTROL BITS / SIGNALS X 1 2 3 FUNCTION P2.1 (I/O) P2SEL.x I: 0, O: 1 0 Timer_B7.CCI0A and Timer_B7.CCI0B 0 1 Timer_B7.TB0 (see Note 2) 1 1 P2.2 (I/O) I: 0, O: 1 0 Timer_B7.CCI1A and Timer_B7.CCI1B 0 1 Timer_B7.TB1 (see Note 2) 1 1 P2.3 (I/O) I: 0, O: 1 0 Timer_B7.CCI2A and Timer_B7.CCI2B 0 1 Timer_B7.TB3 (see Note 2) 1 1 NOTES: 1. N/A: Not available or not applicable 2. Setting TBOUTH causes all Timer_B outputs to be set to high impedance. 56 P2DIR.x POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C - MAY 2007 - REVISED MARCH 2011 port P2, P2.4 to P2.5, input/output with Schmitt trigger DVSS P2REN.x P2DIR.x USCI Direction Control 0 P2OUT.x 0 Module X OUT 1 DVSS 0 DVCC 1 1 Direction 0: Input 1: Output 1 Bus Keeper P2SEL.x P2.4/UCA0TXD/UCA0SIMO P2.5/UCA0RXD/UCA0SOMI EN P2IN.x EN Module X IN D P2IE.x P2IRQ.x EN Q P2IFG.x P2SEL.x P2IES.x Set Interrupt Edge Select Port P2 (P2.4 and P2.5) pin functions CONTROL BITS / SIGNALS PIN NAME (P2.X) (P2 X) X P2.4/ UCA0TXD/UCA0SIMO 4 P2.5/ UCA0RXD/UCA0SOMI 5 FUNCTION P2.4 (I/O) UCA0TXD/UCA0SIMO (see Note 1, 2) P2.5 (I/O) UCA0RXD/UCA0SOMI (see Note 1, 2) P2DIR.x P2SEL.x I: 0, O: 1 0 X 1 I: 0, O: 1 0 X 1 NOTES: 1. X: Don't care. 2. The pin direction is controlled by the USCI module. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 57 MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C - MAY 2007 - REVISED MARCH 2011 port P3, P3.0 to P3.3, input/output with Schmitt trigger Pad Logic DVSS P3REN.x P3DIR.x USCI Direction Control 0 P3OUT.x 0 Module X OUT 1 DVSS 0 DVCC 1 1 Direction 0: Input 1: Output 1 Bus Keeper P3SEL.x P3.0/UCB0STE/UCA0CLK P3.1/UCB0SIMO/UCB0SDA P3.2/UCB0SOMI/UCB0SCL P3.3/UCB0CLK/UCA0STE EN P3IN.x EN Module X IN D Port P3 (P3.0 to P3.3) pin functions PIN NAME (P3.X) (P3 X) CONTROL BITS / SIGNALS X P3.0/ UCA0CLK/UCB0STE 0 P3.1/ UCB0SIMO/ UCB0SDA 1 P3.2/ UCB0SOMI/ UCB0SCL 2 P3.3/ UCB0CLK/UCA0STE 3 FUNCTION P3.0 (I/O) UCA0CLK/UCB0STE (see Notes 1, 2, 3) P3.1 (I/O) UCB0SIMO/UCB0SDA (see Notes 1, 2, 4) P3.2 (I/O) UCB0SOMI/UCB0SCL (see Notes 1, 2, 4) P3.3 (I/O) UCB0CLK (see Notes 1, 2, 5) P3DIR.x P3SEL.x I: 0, O: 1 0 X 1 I: 0, O: 1 0 X 1 I: 0, O: 1 0 X 1 I: 0, O: 1 0 X 1 NOTES: 1. X: Don't care. 2. The pin direction is controlled by the USCI module. 3. UCA0CLK function takes precedence over UCB0STE function. If the pin is required as UCA0CLK input or output USCI_B0 will be forced to 3-wire SPI mode even if 4-wire SPI mode is selected. 4. In case the I2C functionality is selected the output drives only the logical 0 to VSS level. 5. UCB0CLK function takes precedence over UCA0STE function. If the pin is required as UCB0CLK input or output USCI_A0 will be forced to 3-wire SPI mode even if 4-wire SPI mode is selected. 58 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C - MAY 2007 - REVISED MARCH 2011 port P3, P3.4 to P3.7, input/output with Schmitt trigger Pad Logic DVSS P3REN.x P3DIR.x 0 0 Module X OUT 1 0 1 1 Direction 0: Input 1: Output 1 P3OUT.x DVSS DVCC Bus Keeper P3SEL.x P3.4 P3.5 P3.6 P3.7 EN P3IN.x EN Module X IN D Port P3 (P3.4 to P3.7) pin functions PIN NAME (P3.X) (P3 X) P3.4 P3.5 P3.6 P3.7 CONTROL BITS / SIGNALS X 4 5 6 7 FUNCTION P3DIR.x P3SEL.x I: 0, O: 1 0 N/A 0 1 DVSS 1 1 I: 0, O: 1 0 N/A 0 1 DVSS 1 1 P3.4 (I/O) P3.5 (I/O) P3.6 (I/O) I: 0, O: 1 0 N/A 0 1 DVSS 1 1 P3.7 (I/O) I: 0, O: 1 0 N/A 0 1 DVSS 1 1 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 59 MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C - MAY 2007 - REVISED MARCH 2011 port P4, P4.0 to P4.1, input/output with Schmitt trigger Pad Logic DVSS P4REN.x P4DIR.x USCI Direction Control 0 P4OUT.x 0 Module X OUT 1 DVSS 0 DVCC 1 1 Direction 0: Input 1: Output 1 Bus Keeper P4SEL.x P4.0/UCA1TXD/UCA1SIMO P4.1/UCA1RXD/UCA1SOMI EN P4IN.x EN Module X IN D Port P4 (P4.0 to P4.1) pin functions CONTROL BITS / SIGNALS PIN NAME (P4.X) (P4 X) X P4.0/ UCA1TXD/UCA1SIMO 0 P4.1/ UCA1RXD/UCA1SOMI 1 FUNCTION P4.0 (I/O) UCA1TXD/UCA1SIMO (see Notes 1, 2) P4.1 (I/O) UCA1RXD/UCA1SOMI (see Notes 1, 2) NOTES: 1. X: Don't care. 2. The pin direction is controlled by the USCI module. 60 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 P4DIR.x P4SEL.x I: 0, O: 1 0 X 1 I: 0, O: 1 0 X 1 MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C - MAY 2007 - REVISED MARCH 2011 port P4, P4.2 to P4.5, input/output with Schmitt trigger Pad Logic Segment Sz LCDS... P4REN.x P4DIR.x USCI Direction Control 0 P4OUT.x 0 Module X OUT 1 DVSS 0 DVCC 1 1 Direction 0: Input 1: Output 1 P4.2/UCB1STE/UCA1CLK/S39 P4.3/UCB1SIMO/UCB1SDA/S38 P4.4/UCB1SOMI/UCB1SCL/S37 P4.5/UCB1CLK/UCA1STE/S36 Bus Keeper P4SEL.x EN P4IN.x EN Module X IN D Port P4 (P4.2 to P4.5) pin functions CONTROL BITS / SIGNALS PIN NAME (P4.X) (P4 X) X P4.2/ UCA1CLK/UCB1STE/ S39 2 P4.3/ UCB1SIMO/UCB1SDA/ S38 3 P4.4/ UCB1SOMI/UCB1SCL/ S37 4 P4.5/ UCB1CLK/UCA1STE/ S36 5 FUNCTION P4.2 (I/O) P4DIR.x P4SEL.x LCDS36 I: 0, O: 1 0 0 UCA1CLK/UCB1STE (see Notes 2, 3) X 1 0 S39 X X 1 P4.3 (I/O) I: 0, O: 1 0 0 UCB1SIMO/UCB1SDA (see Notes 2, 4) X 1 0 S38 X X 1 P4.4 (I/O) I: 0, O: 1 0 0 UCB1SOMI/UCB1SCL (see Notes 2, 4) X 1 0 S37 X X 1 P4.5 (I/O) I: 0, O: 1 0 0 UCB1CLK/UCA1STE (see Notes 2, 5) X 1 0 S36 X X 1 NOTES: 1. X: Don't care. 2. The pin direction is controlled by the USCI module. 3. UCA1CLK function takes precedence over UCB1STE function. If the pin is required as UCA1CLK input or output USCI_B1 will be forced to 3-wire SPI mode even if 4-wire SPI mode is selected. 4. In case the I2C functionality is selected the output drives only the logical 0 to VSS level. 5. UCB1CLK function takes precedence over UCA1STE function. If the pin is required as UCB1CLK input or output USCI_A1 will be forced to 3-wire SPI mode even if 4-wire SPI mode is selected. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 61 MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C - MAY 2007 - REVISED MARCH 2011 port P4, P4.6 to P4.7, input/output with Schmitt trigger Pad Logic Segment Sz LCDS... P4REN.x P4DIR.x 0 0 Module X OUT 1 0 1 1 Direction 0: Input 1: Output 1 P4OUT.x DVSS DVCC P4.6/S35 P4.7/S34 Bus Keeper P4SEL.x EN P4IN.x EN Module X IN D Port P4 (P4.6 to P4.7) pin functions PIN NAME (P4.X) (P4 X) CONTROL BITS / SIGNALS X P4.6/S35 6 P4.7/S34 7 FUNCTION P4.6 (I/O) S35 P4.7 (I/O) S34 NOTES: 1. X: Don't care. 62 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 P4DIR.x P4SEL.x LCDS32 I: 0, O: 1 0 0 X X 1 I: 0, O: 1 0 0 X X 1 MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C - MAY 2007 - REVISED MARCH 2011 port P5, P5.0, input/output with Schmitt trigger Pad Logic To SVS P5REN.x DVSS DVCC P5DIR.x 0 1 P5OUT.x DVSS 0 1 1 Direction 0: Input 1: Output 0 1 P5.0/SVSIN Bus Keeper EN P5SEL.x P5IN.x Port P5 (P5.0) pin functions PIN NAME (P5.X) (P5 X) P5.0/SVSIN CONTROL BITS / SIGNALS X 0 FUNCTION P5DIR.x P5SEL.x P5.0 (I/O) (see Note 1) I: 0, O: 1 0 SVSIN (see Notes 1, 3) X 1 NOTES: 1. X: Don't care. 2. N/A: Not available or not applicable. 3. Setting the P5SEL.x bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying analog signals. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 63 MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C - MAY 2007 - REVISED MARCH 2011 port P5, P5.1, input/output with Schmitt trigger Pad Logic Segment S0 LCDS0 P5REN.1 P5DIR.1 0 0 Module X OUT 1 0 1 1 Direction 0: Input 1: Output 1 P5OUT.1 DVSS DVCC P5.1/S0 Bus Keeper P5SEL.1 EN P5IN.1 EN Module X IN D Port P5 (P5.1) pin functions PIN NAME (P5.X) (P5 X) P5.1/S0 CONTROL BITS / SIGNALS X 1 FUNCTION P5DIR.x P5SEL.x LCDS0 I: 0, O: 1 0 0 N/A 0 1 0 DVSS 1 1 0 S0 X X 1 P5.1 (I/O) NOTES: 1. X: Don't care. 2. N/A: Not available or not applicable. 64 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C - MAY 2007 - REVISED MARCH 2011 port P5, P5.2 to P5.7, input/output with Schmitt trigger Pad Logic LCD Signal P5REN.x P5DIR.x 0 0 DVSS 1 0 1 1 Direction 0: Input 1: Output 1 P5OUT.x DVSS DVCC Bus Keeper P5SEL.x EN P5IN.x P5.2/COM1 P5.3/COM2 P5.4/COM3 P5.5/R03 P5.6/LCDREF/R13 P5.7/R23 Port P5 (P5.2 to P5.4) pin functions PIN NAME (P5.X) (P5 X) CONTROL BITS / SIGNALS X P5.2/COM1 2 P5.3/COM2 3 P5.4/COM3 4 FUNCTION P5.2 (I/O) COM1 (see Note 2) P5.3 (I/O) COM2 (see Note 2) P5.4 (I/O) COM3 (see Note 2) P5.5/R03 5 P5.5 (I/O) R03 (see Note 2) P5.6/LCDREF/R13 6 P5.7/R23 7 P5.6 (I/O) R13 or LCDREF (see Notes 2, 3) P5.7 (I/O) R23 (see Note 2) P5DIR.x P5SEL.x I: 0, O: 1 0 X 1 I: 0, O: 1 0 X 1 I: 0, O: 1 0 X 1 I: 0, O: 1 0 X 1 I: 0, O: 1 0 X 1 I: 0, O: 1 0 X 1 NOTES: 1. X: Don't care. 2. Setting the P5SEL.x bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying analog signals. 3. External reference for the LCD_A charge pump is applied when VLCDREFx = 01. Otherwise R13 is selected. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 65 MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C - MAY 2007 - REVISED MARCH 2011 port P7 to port P10, input/output with Schmitt trigger Pad Logic Segment Sz LCDS... PyREN.x PyDIR.x 0 0 Module X OUT 1 0 1 Py.x/Sz Bus Keeper PySEL.x EN PyIN.x EN Module X IN 66 1 Direction 0: Input 1: Output 1 PyOUT.x DVSS DVCC D POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C - MAY 2007 - REVISED MARCH 2011 Port P7 (P7.0 to P7.1) pin functions (P7 X) PIN NAME (P7.X) P7.0/S33 CONTROL BITS / SIGNALS X 0 FUNCTION P7.0 (I/O) S33 P7.1/S32 1 P7.1 (I/O) S32 P7DIR.x P7SEL.x LCDS32 I: 0, O: 1 0 0 X X 1 I: 0, O: 1 0 0 X X 1 NOTES: 1. X: Don't care. Port P7 (P7.4 to P7.5) pin functions PIN NAME (P7.X) (P7 X) P7.2/S31 CONTROL BITS / SIGNALS X 2 FUNCTION P7.2 (I/O) S31 P7.3/S30 3 P7.3 (I/O) S30 P7.4/S29 4 P7.5/S28 5 P7.4 (I/O) S29 P7.5 (I/O) S28 P7DIR.x P7SEL.x LCDS28 I: 0, O: 1 0 0 X X 1 I: 0, O: 1 0 0 X X 1 I: 0, O: 1 0 0 X X 1 I: 0, O: 1 0 0 X X 1 NOTES: 1. X: Don't care. Port P7 (P7.6 to P7.7) pin functions PIN NAME (P7.X) (P7 X) CONTROL BITS / SIGNALS X P7.6/S27 6 P7.7/S26 7 FUNCTION P7.6 (I/O) S27 P7.7 (I/O) S26 P7DIR.x P7SEL.x LCDS24 I: 0, O: 1 0 0 X X 1 I: 0, O: 1 0 0 X X 1 NOTES: 1. X: Don't care. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 67 MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C - MAY 2007 - REVISED MARCH 2011 Port P8 (P8.0 to P8.1) pin functions (P8 X) PIN NAME (P8.X) P8.0/S25 CONTROL BITS / SIGNALS X 0 FUNCTION P8.0 (I/O) S25 P8.1/S24 1 P8.0 (I/O) S24 P8DIR.x P8SEL.x LCDS24 I: 0, O: 1 0 0 X X 1 I: 0, O: 1 0 0 X X 1 NOTES: 1. X: Don't care. Port P8 (P8.2 to P8.5) pin functions PIN NAME (P8.X) (P8 X) P8.2/S23 CONTROL BITS / SIGNALS X 2 FUNCTION P8.2 (I/O) S23 P8.3/S22 3 P8.3 (I/O) S22 P8.4/S21 4 P8.5/S20 5 P8.4 (I/O) S21 P8.5 (I/O) S23 P8DIR.x P8SEL.x LCDS20 I: 0, O: 1 0 0 X X 1 I: 0, O: 1 0 0 X X 1 I: 0, O: 1 0 0 X X 1 I: 0, O: 1 0 0 X X 1 NOTES: 1. X: Don't care. Port P8 (P8.6 to P8.7) pin functions PIN NAME (P8.X) (P8 X) CONTROL BITS / SIGNALS X P8.6/S19 6 P8.7/S18 7 FUNCTION P8.6 (I/O) S19 P8.7 (I/O) S18 NOTES: 1. X: Don't care. 68 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 P8DIR.x P8SEL.x LCDS16 I: 0, O: 1 0 0 X X 1 I: 0, O: 1 0 0 X X 1 MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C - MAY 2007 - REVISED MARCH 2011 Port P9 (P9.0 to P9.1) pin functions (P9 X) PIN NAME (P9.X) P9.0/S17 CONTROL BITS / SIGNALS X 0 FUNCTION P9.0 (I/O) S17 (see Note 1) P9.1/S16 1 P9.1 (I/O) S16 (see Note 1) P9DIR.x P9SEL.x LCDS16 I: 0, O: 1 0 0 X X 1 I: 0, O: 1 0 0 X X 1 NOTES: 1. X: Don't care. Port P9 (P9.2 to P9.5) pin functions PIN NAME (P9.X) (P9 X) P9.2/S15 CONTROL BITS / SIGNALS X 2 FUNCTION P9.2 (I/O) S15 P9.3/S14 3 P9.3 (I/O) S14 P9.4/S13 4 P9.5/S12 5 P9.4 (I/O) S13 P9.5 (I/O) S12 P9DIR.x P9SEL.x LCDS12 I: 0, O: 1 0 0 X X 1 I: 0, O: 1 0 0 X X 1 I: 0, O: 1 0 0 X X 1 I: 0, O: 1 0 0 X X 1 NOTES: 1. X: Don't care. Port P9 (P9.6 to P9.7) pin functions PIN NAME (P9.X) (P9 X) CONTROL BITS / SIGNALS X P9.6/S11 6 P9.7/S10 7 FUNCTION P9.6 (I/O) S11 P9.7 (I/O) S10 P9DIR.x P9SEL.x LCDS8 I: 0, O: 1 0 0 X X 1 I: 0, O: 1 0 0 X X 1 NOTES: 1. X: Don't care. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 69 MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C - MAY 2007 - REVISED MARCH 2011 Port P10 (P10.0 to P10.1) pin functions X) PIN NAME (P10 (P10.X) P10.0/S8 CONTROL BITS / SIGNALS X 0 FUNCTION P10.0 (I/O) S8 P10.1/S7 1 P10.1 (I/O) S7 P10DIR.x P10SEL.x LCDS8 I: 0, O: 1 0 0 X X 1 I: 0, O: 1 0 0 X X 1 NOTES: 1. X: Don't care. Port P10 (P10.2 to P10.5) pin functions PIN NAME (P10 (P10.X) X) P10.2/S7 CONTROL BITS / SIGNALS X 2 FUNCTION P10.2 (I/O) S7 P10.3/S6 3 P10.3 (I/O) S6 P10.4/S5 4 P10.5/S4 5 P10.4 (I/O) S5 P10.5 (I/O) S4 P10DIR.x P10SEL.x LCDS4 I: 0, O: 1 0 0 X X 1 I: 0, O: 1 0 0 X X 1 I: 0, O: 1 0 0 X X 1 I: 0, O: 1 0 0 X X 1 NOTES: 1. X: Don't care. Port P10 (P10.6 to P10.7) pin functions PIN NAME (P10 (P10.X) X) CONTROL BITS / SIGNALS X P10.6/S3 6 P10.7/S2 7 FUNCTION P10.6 (I/O) S3 P10.7 (I/O) S2 NOTES: 1. X: Don't care. 70 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 P10DIR.x P10SEL.x LCDS0 I: 0, O: 1 0 0 X X 1 I: 0, O: 1 0 0 X X 1 MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C - MAY 2007 - REVISED MARCH 2011 JTAG pins (TMS, TCK, TDI/TCLK, TDO/TDI), input/output with Schmitt trigger or output TDO Controlled by JTAG Controlled by JTAG TDO/TDI JTAG Controlled by JTAG DVCC TDI Burn and Test Fuse TDI/TCLK Test and Emulation DVCC TMS Module TMS DVCC TCK TCK RST/NMI Tau ~ 50 ns Brownout TCK POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 G D U S G D U S 71 MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C - MAY 2007 - REVISED MARCH 2011 JTAG fuse check mode Devices that have the fuse on the TDI/TCLK terminal have a fuse check mode that tests the continuity of the fuse the first time the JTAG port is accessed after a power-on reset (POR). When activated, a fuse-check current (I(TF) ) of 1 mA at 3 V can flow from the TDI/TCLK pin to ground if the fuse is not burned. Care must be taken to avoid accidentally activating the fuse check mode and increasing overall system power consumption. Activation of the fuse-check mode occurs with the first negative edge on the TMS pin after power up or if the TMS is being held low during power up. The second positive edge on the TMS pin deactivates the fuse-check mode. After deactivation, the fuse-check mode remains inactive until another POR occurs. After each POR the fuse check mode has the potential to be activated. The fuse check current only flows when the fuse check mode is active and the TMS pin is in a low state (see Figure 27). Therefore, the additional current flow can be prevented by holding the TMS pin high (default condition). The JTAG pins are terminated internally and, therefore, do not require external termination. Time TMS Goes Low After POR TMS ITDI/TCLK I(TF) Figure 27. Fuse-Check Mode Current 72 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 MSP430F47x3, MSP430F47x4 MIXED SIGNAL MICROCONTROLLER SLAS545C - MAY 2007 - REVISED MARCH 2011 Data Sheet Revision History Literature Number Summary SLAS545 PRODUCT PREVIEW data sheet SLAS545A PRODUCTION DATA data sheet SLAS545B Section DEVELOPMENT TOOL SUPPORT added, page 2. Split XT1 frequency ranges depending on supply voltage range, page 36. Added parameter fLFXT1, LF, logic to LFXT1, low frequency modes characteristics, page 36. SLAS545C Changed limits on td(SVSon) parameter (page 32) NOTE: Page and figure numbers refer to the specified revision and may differ in other revisions. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 73 PACKAGE OPTION ADDENDUM www.ti.com 2-Apr-2012 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) MSP430F4783IPZ ACTIVE LQFP PZ 100 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR MSP430F4783IPZR ACTIVE LQFP PZ 100 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR MSP430F4784IPZ ACTIVE LQFP PZ 100 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR MSP430F4784IPZR ACTIVE LQFP PZ 100 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR MSP430F4793IPZ ACTIVE LQFP PZ 100 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR MSP430F4793IPZR ACTIVE LQFP PZ 100 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR MSP430F4794IPZ ACTIVE LQFP PZ 100 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR MSP430F4794IPZR ACTIVE LQFP PZ 100 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR MSP430F4794SNIPZ OBSOLETE LQFP PZ 100 TBD Call TI Call TI MSP430F4794SNIPZR OBSOLETE LQFP PZ 100 TBD Call TI Call TI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com (3) 2-Apr-2012 MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant MSP430F4783IPZR LQFP PZ 100 1000 330.0 24.4 17.4 17.4 2.0 20.0 24.0 Q2 MSP430F4784IPZR LQFP PZ 100 1000 330.0 24.4 17.4 17.4 2.0 20.0 24.0 Q2 MSP430F4793IPZR LQFP PZ 100 1000 330.0 24.4 17.4 17.4 2.0 20.0 24.0 Q2 MSP430F4794IPZR LQFP PZ 100 1000 330.0 24.4 17.4 17.4 2.0 20.0 24.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) MSP430F4783IPZR LQFP PZ 100 1000 367.0 367.0 45.0 MSP430F4784IPZR LQFP PZ 100 1000 367.0 367.0 45.0 MSP430F4793IPZR LQFP PZ 100 1000 367.0 367.0 45.0 MSP430F4794IPZR LQFP PZ 100 1000 367.0 367.0 45.0 Pack Materials-Page 2 MECHANICAL DATA MTQF013A - OCTOBER 1994 - REVISED DECEMBER 1996 PZ (S-PQFP-G100) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 75 0,08 M 51 76 50 100 26 1 0,13 NOM 25 12,00 TYP Gage Plane 14,20 SQ 13,80 16,20 SQ 15,80 0,05 MIN 1,45 1,35 0,25 0- 7 0,75 0,45 Seating Plane 0,08 1,60 MAX 4040149 /B 11/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as "components") are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI's terms and conditions of sale of semiconductor products. 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