MSP430F47x3, MSP430F47x4
MIXED SIGNAL MICROCONTROLLER
SLAS545C − MAY 2007 − REVISED MARCH 2011
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DLow Supply-Voltage Range, 1.8 V to 3.6 V
DUltra-Low Power Consumption:
− Active Mode: 280 μA at 1 MHz, 2.2 V
− Standby Mode: 1.1 μA
− Off Mode (RAM Retention): 0.2 μA
DFive Power-Saving Modes
DWake-Up From Standby Mode in Less
Than 6 μs
D16-Bit RISC Architecture,
62.5-ns Instruction Cycle Time
DThree or Four 16-Bit Sigma-Delta
Analog-to-Digital (A/D) Converters With
Differential PGA Inputs
D16-Bit Timer_B With Three
Capture/Compare-With-Shadow Registers
D16-Bit Timer_A With Three
Capture/Compare Registers
DOn-Chip Comparator
DFour Universal Serial Communication
Interfaces (USCI)
− USCI_A0 and USCI_A1
− Enhanced UART Supporting
Auto-Baudrate Detection
− IrDA Encoder and Decoder
− Synchronous SPI
− USCI_B0 and USCI_B1
− I2C
− Synchronous SPI
DIntegrated LCD Driver With Contrast
Control For Up To 160 Segments
D32-Bit Hardware Multiplier
DBrownout Detector
DSupply Voltage Supervisor/Monitor With
Programmable Level Detection
DSerial Onboard Programming,
No External Programming Voltage Needed
Programmable Code Protection by Security
Fuse
DBootstrap Loader
DOn Chip Emulation Module
DFamily Members Include:
MSP430F4783: 48KB + 256B Flash
2KB RAM
3 Sigma-Delta ADCs
MSP430F4793: 60KB + 256B Flash
2.5KB RAM
3 Sigma-Delta ADCs
MSP430F4784: 48KB + 256B Flash
2KB RAM
4 Sigma-Delta ADCs
MSP430F4794: 60KB + 256B Flash
2.5KB RAM
4 Sigma-Delta ADCs
MSP430F47x3 and MSP430F47x4 Available
In 100-Pin Plastic Quad Flatpack (QFP)
Package
DFor Complete Module Descriptions, See the
MSP430x4xx Family User’s Guide,
Literature Number SLAU056
description
The Texas Instruments MSP430 family of ultra-low power microcontrollers consists of several devices featuring
different sets of peripherals targeted for various applications. The architecture, combined with five low-power
modes is optimized to achieve extended battery life in portable measurement applications. The device features
a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code
efficiency. The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less
than 6μs.
The MSP430F47xx series are microcontroller configurations targeted to single phase electricity meters with
three or four 16-bit sigma-delta A/D converters. Each channel has a differential input pair and programmable
input gain. Also integrated are two 16-bit timers, three universal serial communication interfaces (USCI), 72 I/O
pins, and a liquid crystal driver (LCD) with integrated contrast control.
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range
from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage
because very small parametric changes could cause the device not to meet its published specifications. These devices have limited
built-in ESD protection.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 2011, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
MSP430F47x3, MSP430F47x4
MIXED SIGNAL MICROCONTROLLER
SLAS545C − MAY 2007 − REVISED MARCH 2011
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
AVAILABLE OPTIONS
PACKAGED DEVICES
TAPLASTIC 100-PIN QFP
(PZ)
−40°C to 85°C
MSP430F4783IPZ
MSP430F4793IPZ
MSP430F4784IPZ
MSP430F4794IPZ
DEVELOPMENT TOOL SUPPORT
All MSP430 microcontrollers include an Embedded Emulation Module (EEM) allowing advanced debugging
and programming through easy to use development tools. Recommended hardware options include the
following:
DDebugging and Programming Interface
− MSP−FET430UIF (USB)
− MSP−FET430PIF (Parallel Port)
DDebugging and Programming Interface with Target Board
− MSP−FET430U100
DProduction Programmer
− MSP−GANG430
MSP430F47x3, MSP430F47x4
MIXED SIGNAL MICROCONTROLLER
SLAS545C − MAY 2007 − REVISED MARCH 2011
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
pin designation, MSP430F47xxIPZ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
P1.7/CA1
A3.0+
P5.0/SVSIN
RST/NMI
XT2IN
XT2OUT
P1.3/TBOUTH/SVSOUT
P1.4/TBCLK/SMCLK
P1.5/TACLK/ACLK
P1.6/CA0
P2.3/TB2
P9.3/S14
P9.2/S15
P9.1/S16
P9.0/S17
P8.7/S18
P8.5/S20
P8.0/S25
P7.7/S26
P7.6/S27
P7.5/S28
P7.4/S29
P7.2/S31
P4.7/S34
P7.3/S30
PZ PACKAGE
(TOP VIEW)
P1.0/TA0
TDI/TCLK
TDO/TDI
P8.4/S21
SS1
DV
A3.0−
P1.2/TA1
P8.1/S24
P4.6/S35
DVCC1
A0.0+
A0.0−
A1.0+
A1.0−
A2.0+
A2.0−
XIN
XOUT
VREF
NC
P5.1/S0
S1
P10.7/S2
P10.6/S3
P10.5/S4
P10.4/S5
P10.3/S6
P10.2/S7
P10.1/S8
P10.0/S9
P9.7/S10
P9.6/S11
P9.5/S12
P9.4/S13
P2.4/UCA0TXD/UCA0SIMO
P2.5/UCA0RXD/UCA0SOMI
P2.6/CAOUT
P2.7
P3.0/UCB0STE/UCA0CLK
P3.1/UCB0SIMO/UCB0SDA
P3.2/UCB0SOMI/UCB0SCL
P3.3/UCB0CLK/UCA0STE
P3.4
P3.5
P3.6
P3.7
P4.0/UCA1TXD/UCA1SIMO
P4.1/UCA1RXD/UCA1SOMI
DVSS2
DVCC2
LCDCAP/R33
P5.7/R23
P5.6/LCDREF/R13
P5.5/R03
P5.4/COM3
P5.3/COM2
P5.2/COM1
COM0
P4.2/UCB1STE/UCA1CLK/S39
P8.6/S19
P8.3/S22
P8.2/S23
P7.0/S33
P7.1/S32
P4.5/UCB1CLK/UCA1STE/S36
P4.4/UCB1SOMI/UCB1SCL/S37
P4.3/UCB1SIMO/UCB1SDA/S38
CC
AV
SS1
AV
TCK
TMS
P1.1/TA0/MCLK
P2.0/TA2
P2.1/TB0
P2.2/TB1
MSP430F47x4IPZ
A3+ and A3− are not connected in MSP430x47x3 devices.
MSP430F47x3, MSP430F47x4
MIXED SIGNAL MICROCONTROLLER
SLAS545C − MAY 2007 − REVISED MARCH 2011
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430F47x3 functional block diagram
Oscillators
FLL+
RAM
2.5kB
2.0kB
Brownout
Protection
SVS/SVM
RST/NMI
DVCC1/2 DVSS1/2
MCLK
Watchdog
WDT+
15/16−Bit
Timer_A3
3CC
Registers
16MHz
CPU
incl. 16
Registers
Emulation
(2 BP)
Basic Timer
JTAG
Interface
LCD_A
160
Segments
1,2,3,4 Mux
Ports P1/P2
2x8 I/O
Interrupt
capability &
pull−up/down
Resistors
USCI_A0
(UART/LIN,
IrDA, SPI)
USCI_B0
(SPI, I2C)
Comparator
_A
Flash_A
60kB
48kB
Hardware
Multiplier
(32x32)
MPY,
MPYS,
MAC,
MACS
Timer_B3
3CC
Registers,
Shadow
Reg
USCI_A1
(UART/LIN,
IrDA, SPI)
USCI_B1
(SPI, I2C)
AVCC AVSS P1.x/P2.x
2x8
SMCLK
ACLK
MDB
MAB
SD16_A
(w/o BUF)
3
Sigma−
Delta A/D
Converter
Ports
P3/P4
P5
3x8 I/O with
pull−up/down
Resistors
Ports
P7/P8
P9/P10
4x8/2x16 I/O
pull−up/down
Resistors
P3.x/P4.x
P5.x
3x8
P7.x/P8.x
P9.x/P10.x
4x8/2x16
XOUT
XT2OUT
XIN
XT2IN
22
MSP430F47x4 functional block diagram
Oscillators
FLL+
RAM
2.5kB
2.0kB
Brownout
Protection
SVS/SVM
RST/NMI
DVCC1/2 DVSS1/2
MCLK
Watchdog
WDT+
15/16−Bit
Timer_A3
3CC
Registers
16MHz
CPU
incl. 16
Registers
Emulation
(2 BP)
Basic Timer
JTAG
Interface
LCD_A
160
Segments
1,2,3,4 Mux
Ports P1/P2
2x8 I/O
Interrupt
capability &
pull−up/down
Resistors
USCI_A0
(UART/LIN,
IrDA, SPI)
USCI_B0
(SPI, I2C)
Comparator
_A
Flash_A
60kB
48kB
Hardware
Multiplier
(32x32)
MPY,
MPYS,
MAC,
MACS
Timer_B3
3CC
Registers,
Shadow
Reg
USCI_A1
(UART/LIN,
IrDA, SPI)
USCI_B1
(SPI, I2C)
AVCC AVSS P1.x/P2.x
2x8
SMCLK
ACLK
MDB
MAB
SD16_A
(w/o BUF)
4
Sigma−
Delta A/D
Converter
Ports
P3/P4
P5
3x8 I/O with
pull−up/down
Resistors
Ports
P7/P8
P9/P10
4x8/2x16 I/O
pull−up/down
Resistors
P3.x/P4.x
P5.x
3x8
P7.x/P8.x
P9.x/P10.x
4x8/2x16
XOUT
XT2OUT
XIN
XT2IN
22
MSP430F47x3, MSP430F47x4
MIXED SIGNAL MICROCONTROLLER
SLAS545C − MAY 2007 − REVISED MARCH 2011
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME NO. I/O DESCRIPTION
DVCC1 1Digital supply voltage, positive terminal.
A0.0+ 2 I SD16_A positive analog input A0.0 (see Note 1)
A0.0− 3 I SD16_A negative analog input A0.0 (see Note 1)
A1.0+ 4 I SD16_A positive analog input A1.0 (see Note 1)
A1.0− 5 I SD16_A negative analog input A1.0 (see Note 1)
A2.0+ 6 I SD16_A positive analog input A2.0 (see Note 1)
A2.0− 7 I SD16_A negative analog input A2.0 (see Note 1)
XIN 8 I Input port for crystal oscillator XT1. Standard or watch crystals can be connected.
XOUT 9 O Output terminal of crystal oscillator XT1
VREF 10 I/O Input for an external reference voltage /
Internal reference voltage output (can be used as mid-voltage)
NC 11 Internally not connected. Can be connected to VSS.
P5.1/S0 12 I/O General-purpose digital I/O / LCD segment output 0
S1 13 O LCD segment output 1
P10.7/S2 14 I/O General-purpose digital I/O / LCD segment output 2
P10.6/S3 15 I/O General-purpose digital I/O / LCD segment output 3
P10.5/S4 16 I/O General-purpose digital I/O / LCD segment output 4
P10.4/S5 17 I/O General-purpose digital I/O / LCD segment output 5
P10.3/S6 18 I/O General-purpose digital I/O / LCD segment output 6
P10.2/S7 19 I/O General-purpose digital I/O / LCD segment output 7
P10.1/S8 20 I/O General-purpose digital I/O / LCD segment output 8
P10.0/S9 21 I/O General-purpose digital I/O / LCD segment output 9
P9.7/S10 22 I/O General-purpose digital I/O / LCD segment output 10
P9.6/S11 23 I/O General-purpose digital I/O / LCD segment output 11
P9.5/S12 24 I/O General-purpose digital I/O / LCD segment output 12
P9.4/S13 25 I/O General-purpose digital I/O / LCD segment output 13
P9.3/S14 26 I/O General-purpose digital I/O / LCD segment output 14
P9.2/S15 27 I/O General-purpose digital I/O / LCD segment output 15
P9.1/S16 28 I/O General-purpose digital I/O / LCD segment output 16
P9.0/S17 29 I/O General-purpose digital I/O / LCD segment output 17
P8.7/S18 30 I/O General-purpose digital I/O / LCD segment output 18
P8.6/S19 31 I/O General-purpose digital I/O / LCD segment output 19
P8.5/S20 32 I/O General-purpose digital I/O / LCD segment output 20
P8.4/S21 33 I/O General-purpose digital I/O / LCD segment output 21
P8.3/S22 34 I/O General-purpose digital I/O / LCD segment output 22
P8.2/S23 35 I/O General-purpose digital I/O / LCD segment output 23
P8.1/S24 36 I/O General-purpose digital I/O / LCD segment output 24
P8.0/S25 37 I/O General-purpose digital I/O / LCD segment output 25
P7.7/S26 38 I/O General-purpose digital I/O / LCD segment output 26
P7.6/S27 39 I/O General-purpose digital I/O / LCD segment output 27
P7.5/S28 40 I/O General-purpose digital I/O / LCD segment output 28
P7.4/S29 41 I/O General-purpose digital I/O / LCD segment output 29
P7.3/S30 42 I/O General-purpose digital I/O / LCD segment output 30
NOTE 1: Open connection recommended for all unused analog inputs.
MSP430F47x3, MSP430F47x4
MIXED SIGNAL MICROCONTROLLER
SLAS545C − MAY 2007 − REVISED MARCH 2011
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Terminal Functions (Continued)
TERMINAL
I/O
DESCRIPTION
NAME NO. I/O DESCRIPTION
P7.2/S31 43 I/O General-purpose digital I/O / LCD segment output 31
P7.1/S32 44 I/O General-purpose digital I/O / LCD segment output 32
P7.0/S33 45 I/O General-purpose digital I/O / LCD segment output 33
P4.7/S34 46 I/O General-purpose digital I/O / LCD segment output 34
P4.6/S35 47 I/O General-purpose digital I/O / LCD segment output 35
P4.5/
UCB1CLK/UCA1STE/
S36
48 I/O
General-purpose digital I/O /
USCI_B1 clock input/output / USCI_A1 slave transmit enable /
LCD segment output 36
P4.4/
UCB1SOMI/UCB1SCL/
S37
49 I/O
General-purpose digital I/O /
USCI_B1 slave out/master in in SPI mode, SCL I2C clock in I2C mode /
LCD segment output 37
P4.3/
UCB1SIMO/UCB1SDA/
S38
50 I/O
General-purpose digital I/O /
USCI_B1 slave in/master out in SPI mode, SDA I2C data in I2C mode /
LCD segment output 38
P4.2/
UCB1STE/UCA1CLK/
S39
51 I/O
General-purpose digital I/O /
USCI_B1 slave transmit enable / USCI_A1 clock input/output /
LCD segment output 39
COM0 52 O COM0−3 are used for LCD backplanes.
P5.2/COM1 53 I/O General-purpose digital I/O / common output, COM0−3 are used for LCD backplanes.
P5.3/COM2 54 I/O General-purpose digital I/O / common output, COM0−3 are used for LCD backplanes.
P5.4/COM3 55 I/O General-purpose digital I/O / common output, COM0−3 are used for LCD backplanes.
P5.5/R03 56 I/O General-purpose digital I/O / Input port of lowest analog LCD level (V5)
P5.6/LCDREF/R13 57 I/O General-purpose digital I/O / External reference voltage input for regulated LCD voltage / Input port
of third most positive analog LCD level (V4 or V3)
P5.7/R23 58 I/O General-purpose digital I/O / Input port of second most positive analog LCD level (V2)
LCDCAP/R33 59 I LCD Capacitor connection / Input/output port of most positive analog LCD level (V1)
DVCC2 60 Digital supply voltage, positive terminal.
DVSS2 61 Digital supply voltage, negative terminal.
P4.1/
UCA1RXD/UCA1SOMI 62 I/O General-purpose digital I/O /
USCI_A1 receive data input in UART mode, slave out/master in in SPI mode
P4.0/
UCA1TXD/UCA1SIMO 63 I/O General-purpose digital I/O /
USCI_A1 transmit data output in UART mode, slave in/master out in SPI mode
P3.7 64 I/O General-purpose digital I/O
P3.6 65 I/O General-purpose digital I/O
P3.5 66 I/O General-purpose digital I/O
P3.4 67 I/O General-purpose digital I/O
P3.3/
UCB0CLK/UCA0STE 68 I/O General-purpose digital I/O /
USCI_B0 clock input/output / USCI_A0 slave transmit enable
P3.2/
UCB0SOMI/UCB0SCL 69 I/O General-purpose digital I/O /
USCI_B1 slave out/master in in SPI mode, SCL I2C clock in I2C mode
P3.1/
UCB0SIMO/UCB0SDA 70 I/O General-purpose digital I/O /
USCI_B1 slave in/master out in SPI mode, SDA I2C data in I2C mode
P3.0/
UCB0STE/UCA0CLK 71 I/O General-purpose digital I/O /
USCI_B0 slave transmit enable / USCI_A0 clock input/output
P2.7 72 I/O General-purpose digital I/O
P2.6/CAOUT 73 I/O General-purpose digital I/O / Comparator_A output
MSP430F47x3, MSP430F47x4
MIXED SIGNAL MICROCONTROLLER
SLAS545C − MAY 2007 − REVISED MARCH 2011
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Terminal Functions (Continued)
TERMINAL
I/O
DESCRIPTION
NAME NO. I/O DESCRIPTION
P2.5/
UCA0RXD/UCA0SOMI 74 I/O General-purpose digital I/O / USCI_A0 receive data input in UART mode, slave out/master in in SPI
mode
P2.4/
UCA0TXD/UCA0SIMO 75 I/O General-purpose digital I/O / USCI_A0 transmit data output in UART mode, slave in/master out in
SPI mode
P2.3/TB2 76 I/O General-purpose digital I/O / Timer_B3 CCR2. Capture: CCI2A/CCI2B input, compare: Out2 output
P2.2/TB1 77 I/O General-purpose digital I/O / Timer_B3 CCR1. Capture: CCI1A/CCI1B input, compare: Out1 output
P2.1/TB0 78 I/O General-purpose digital I/O / Timer_B3 CCR0. Capture: CCI0A/CCI0B input, compare: Out0 output
P2.0/TA2 79 I/O General-purpose digital I/O / Timer_A Capture: CCI2A input, compare: Out2 output
P1.7/CA1 80 I/O General-purpose digital I/O / Comparator_A input
P1.6/CA0 81 I/O General-purpose digital I/O / Comparator_A input
P1.5/TACLK/
ACLK 82 I/O General-purpose digital I/O / Timer_A, clock signal TACLK input /
ACLK output (divided by 1, 2, 4, or 8)
P1.4/TBCLK/
SMCLK 83 I/O General-purpose digital I/O / input clock TBCLK—Timer_B3 /
submain system clock SMCLK output
P1.3/TBOUTH/
SVSOUT 84 I/O General-purpose digital I/O / switch all PWM digital output ports to high impedance—Timer_B3 TB0
to TB2 / SVS: output of SVS comparator
P1.2/TA1 85 I/O General-purpose digital I/O / Timer_A, Capture: CCI1A input, compare: Out1 output
P1.1/TA0/MCLK 86 I/O General-purpose digital I/O / Timer_A. Capture: CCI0B input / MCLK output.
Note: TA0 is only an input on this pin / BSL receive
P1.0/TA0 87 I/O General-purpose digital I/O / Timer_A. Capture: CCI0A input, compare: Out0 output / BSL transmit
XT2OUT 88 O Output terminal of crystal oscillator XT2
XT2IN 89 I Input port for crystal oscillator XT2. Only standard crystals can be connected.
TDO/TDI 90 I/O Test data output port. TDO/TDI data output or programming data input terminal
TDI/TCLK 91 I Test data input or test clock input. The device protection fuse is connected to TDI/TCLK.
TMS 92 I Test mode select. TMS is used as an input port for device programming and test.
TCK 93 I Test clock. TCK is the clock input port for device programming and test.
RST/NMI 94 I Reset input or nonmaskable interrupt input port
P5.0/SVSIN 95 I/O General-purpose digital I/O / analog input to supply voltage supervisor
A3.0+
(MSP430x47x4 only) 96 I SD16_A positive analog input A3.0 (see Note 2)
Not connected in MSP430x47x3 devices, open connection recommended.
A3.0−
(MSP430x47x4 only) 97 I SD16_A negative analog input A3.0 (see Note 2)
Not connected in MSP430x47x3 devices, open connection recommended.
AVSS 98 Analog supply voltage, negative terminal.
DVSS1 99 Digital supply voltage, negative terminal.
AVCC 100 Analog supply voltage, positive terminal. Must not power up prior to DVCC1/DVCC2.
NOTE 2: Open connection recommended for all unused analog inputs.
General-Purpose Register
Program Counter
Stack Pointer
Status Register
Constant Generator
General-Purpose Register
General-Purpose Register
General-Purpose Register
PC/R0
SP/R1
SR/CG1/R2
CG2/R3
R4
R5
R12
R13
General-Purpose Register
General-Purpose Register
R6
R7
General-Purpose Register
General-Purpose Register
R8
R9
General-Purpose Register
General-Purpose Register
R10
R11
General-Purpose Register
General-Purpose Register
R14
R15
MSP430F47x3, MSP430F47x4
MIXED SIGNAL MICROCONTROLLER
SLAS545C − MAY 2007 − REVISED MARCH 2011
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
short-form description
CPU
The MSP430 CPU has a 16-bit RISC architecture
that is highly transparent to the application. All
operations, other than program-flow instructions,
are performed as register operations in
conjunction with seven addressing modes for
source operand and four addressing modes for
destination operand.
The CPU is integrated with 16 registers that
provide reduced instruction execution time. The
register-to-register operation execution time is
one cycle of the CPU clock.
Four of the registers, R0 to R3, are dedicated as
program counter, stack pointer, status register,
and constant generator respectively. The
remaining registers are general-purpose
registers.
Peripherals are connected to the CPU using data,
address, and control buses, and can be handled
with all instructions.
instruction set
The instruction set consists of 51 instructions with
three formats and seven address modes. Each
instruction can operate on word and byte data.
Table 1 shows examples of the three types of
instruction formats; the address modes are listed
in Table 2.
Table 1. Instruction Word Formats
Dual operands, source-destination e.g., ADD R4, R5 R4 + R5 −−−> R5
Single operands, destination only e.g., CALL R8 PC −−>(TOS), R8−−> PC
Relative jump, un/conditional e.g., JNE Jump-on-equal bit = 0
Table 2. Address Mode Descriptions
ADDRESS MODE S D SYNTAX EXAMPLE OPERATION
Register DDMOV Rs, Rd MOV R10, R11 R10 −−> R11
Indexed D D MOV X(Rn), Y(Rm) MOV 2(R5), 6(R6) M(2+R5)−−> M(6+R6)
Symbolic (PC relative) D D MOV EDE, TONI M(EDE) −−> M(TONI)
Absolute D D MOV &MEM, &TCDAT M(MEM) −−> M(TCDAT)
Indirect DMOV @Rn, Y(Rm) MOV @R10, Tab(R6) M(R10) −−> M(Tab+R6)
Indirect
autoincrement DMOV @Rn+, Rm MOV @R10+, R11 M(R10) −−> R11
R10 + 2−−> R10
Immediate DMOV #X, TONI MOV #45, TONI #45 −−> M(TONI)
NOTE: S = source D = destination
MSP430F47x3, MSP430F47x4
MIXED SIGNAL MICROCONTROLLER
SLAS545C − MAY 2007 − REVISED MARCH 2011
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
operating modes
The MSP430 has one active mode and five software-selectable low-power modes of operation. An interrupt
event can wake up the device from any of the five low-power modes, service the request, and restore back to
the low-power mode on return from the interrupt program.
The following six operating modes can be configured by software:
DActive mode AM
− All clocks are active
DLow-power mode 0 (LPM0)
− CPU is disabled.
− ACLK and SMCLK remain active.
− MCLK is disabled.
− FLL+ loop control remains active
DLow-power mode 1(LPM1)
− CPU is disabled.
− FLL+ loop control is disabled.
− ACLK and SMCLK remain active.
− MCLK is disabled.
DLow-power mode 2 (LPM2)
− CPU is disabled.
− MCLK, FLL+ loop control, and DCOCLK are disabled.
− DCO’s dc generator remains enabled.
− ACLK remains active.
DLow-power mode 3 (LPM3)
− CPU is disabled.
− MCLK, FLL+ loop control, and DCOCLK are disabled.
− DCO’s dc generator is disabled.
− ACLK remains active.
DLow-power mode 4 (LPM4)
− CPU is disabled.
− ACLK is disabled.
− MCLK, FLL+ loop control, and DCOCLK are disabled.
− DCO’s dc generator is disabled.
− Crystal oscillator is stopped.
MSP430F47x3, MSP430F47x4
MIXED SIGNAL MICROCONTROLLER
SLAS545C − MAY 2007 − REVISED MARCH 2011
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
interrupt vector addresses
The interrupt vectors and the power-up starting address are located in the address range 0FFFFh to 0FFE0h.
The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.
If the reset vector (located at address 0FFFEh) contains 0FFFFh (e.g., flash is not programmed) the CPU goes
into LPM4 immediately after power-up.
INTERRUPT SOURCE INTERRUPT FLAG SYSTEM INTERRUPT WORD
ADDRESS PRIORITY
Power-Up
External Reset
Watchdog
Flash Memory
PC Out−of−Range (see Note 4)
PORIFG
RSTIFG
WDTIFG
KEYV
(see Note 1)
Reset 0FFFEh 15, highest
NMI
Oscillator Fault
Flash Memory Access Violation
NMIIFG (see Notes 1 and 3)
OFIFG (see Notes 1 and 3)
ACCVIFG (see Notes 1 and 3)
(Non)maskable
(Non)maskable
(Non)maskable
0FFFCh 14
Timer_B3 TBCCR0 CCIFG (see Note 2) Maskable 0FFFAh 13
Timer_B3 TBCCR1 to TBCCR2 CCIFGs
TBIFG (see Notes 1 and 2) Maskable 0FFF8h 12
Comparator_A CAIFG Maskable 0FFF6h 11
Watchdog Timer WDTIFG Maskable 0FFF4h 10
USCI_A0/B0 Receive UCA0RXIFG, UCB0RXIFG
(see Note 1 and 5)
Maskable 0FFF2h 9
USCI_A0/B0 Transmit UCA0TXIFG, UCB0TXIFG
(see Note 1 and 6)
Maskable 0FFF0h 8
SD16_A SD16CCTLx SD16OVIFG,
SD16CCTLx SD16IFG
(see Notes 1 and 2)
Maskable 0FFEEh 7
Timer_A3 TACCR0 CCIFG (see Note 2) Maskable 0FFECh 6
Timer_A3 TACCR1 and TACCR2 CCIFGs,
TAIFG (see Notes 1 and 2) Maskable 0FFEAh 5
I/O Port P1
(Eight Flags)
P1IFG.0 to P1IFG.7
(see Notes 1 and 2) Maskable 0FFE8h 4
USCI_A1/B1 Receive UCA1RXIFG, UCB1RXIFG
(see Notes 1 and 2)
Maskable 0FFE6h 3
USCI_A1/B1 Transmit UCA1TXIFG, UCB1TXIFG
(see Notes 1 and 2)
Maskable 0FFE4h 2
I/O Port P2
(Eight Flags)
P2IFG.0 to P2IFG.7
(see Notes 1 and 2) Maskable 0FFE2h 1
Basic Timer1 BTIFG Maskable 0FFE0h 0, lowest
NOTES: 1. Multiple source flags
2. Interrupt flags are located in the module.
3. (Non)maskable: The individual interrupt-enable bit can disable an interrupt event, but the general interrupt enable cannot.
4. A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h to 01FFh).
5. In SPI mode: UCB0RXIFG. In I2C mode: UCALIFG, UCNACKIFG, ICSTTIFG, UCSTPIFG in register UCB0STAT.
6. In UART/SPI mode: UCB0TXIFG. In I2C mode: UCB0RXIFG, UCB0TXIFG.
7. In SPI mode: UCB1RXIFG. In I2C mode: UCALIFG, UCNACKIFG, ICSTTIFG, UCSTPIFG in register UCB1STAT.
8. In UART/SPI mode: UCB1TXIFG. In I2C mode: UCB1RXIFG, UCB1TXIFG.
MSP430F47x3, MSP430F47x4
MIXED SIGNAL MICROCONTROLLER
SLAS545C − MAY 2007 − REVISED MARCH 2011
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
special function registers
Most interrupt and module-enable bits are collected in the lowest address space. Special-function register bits
not allocated to a functional purpose are not physically present in the device. This arrangement provides simple
software access.
interrupt enable 1 and 2
Address 7 6 543210
00h ACCVIE NMIIE OFIE WDTIE
rw−0 rw−0 rw−0 rw−0
WDTIE Watchdog timer interrupt enable. Inactive if watchdog mode is selected. Active if watchdog
timer is configured in interval timer mode.
OFIE Oscillator fault enable
NMIIE (Non)maskable interrupt enable
ACCVIE Flash access violation interrupt enable
Address 7 6 543210
01h BTIE UCB0TXIE UCB0RXIE UCA0TXIE UCA0RXIE
rw−0 rw−0 rw−0 rw−0 rw−0
UCA0RXIE USCI_A0 receive interrupt enable
UCA0TXIE USCI_A0 transmit interrupt enable
UCB0RXIE USCI_B0 receive interrupt enable
UCB0TXIE USCI_B0 transmit interrupt enable
BTIE Basic timer interrupt enable
MSP430F47x3, MSP430F47x4
MIXED SIGNAL MICROCONTROLLER
SLAS545C − MAY 2007 − REVISED MARCH 2011
12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
interrupt flag register 1 and 2
Address 7 6 543210
02h NMIIFG RSTIFG PORIFG OFIFG WDTIFG
rw−0 rw−(0) rw−(1) rw−1 rw−(0)
WDTIFG Set on watchdog timer overflow or security key violation.
Reset on VCC power-up or a reset condition at RST/NMI pin in reset mode.
OFIFG Flag set on oscillator fault
RSTIFG External reset interrupt flag. Set on a reset condition at RST/NMI pin in reset mode. Reset
on VCC power-up.
PORIFG Power-on interrupt flag. Set on VCC power-up.
NMIIFG Set via RST/NMI pin
Address 7 6 543210
03h BTIFG UCB0
TXIFG
UCB0
RXIFG
UCA0
TXIFG
UCA0
RXIFG
rw−0 rw−1 rw−0 rw−1 rw−0
UCA0RXIFG USCI_A0 receive interrupt flag
UCA0TXIFG USCI_A0 transmit interrupt flag
UCB0RXIFG USCI_B0 receive interrupt flag
UCB0TXIFG USCI_B0 transmit interrupt flag
BTIFG Basic Timer1 interrupt flag
Legend rw:
rw-0, 1:
Bit can be read and written.
Bit can be read and written. It is Reset or Set by PUC.
Bit can be read and written. It is Reset or Set by POR.
rw-(0, 1):
SFR bit is not present in device
MSP430F47x3, MSP430F47x4
MIXED SIGNAL MICROCONTROLLER
SLAS545C − MAY 2007 − REVISED MARCH 2011
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
memory organization
MSP430F4783/MSP430F4784 MSP430F4793/MSP430F4794
Memory
Main: interrupt vector
Main: code memory
Size
Flash
Flash
48KB
0FFFFh to 0FFE0h
0FFFFh to 04000h
60KB
0FFFFh to 0FFE0h
0FFFFh to 01100h
Information memory Size
Flash
256 Byte
010FFh to 01000h
256 Byte
010FFh to 01000h
Boot memory Size
ROM
1KB
0FFFh to 0C00h
1KB
0FFFh to 0C00h
RAM Size 2KB
09FFh to 0200h
2.5KB
0BFFh to 0200h
Peripherals 16-bit
8-bit
8-bit SFR
01FFh to 0100h
0FFh to 010h
0Fh to 00h
01FFh to 0100h
0FFh to 010h
0Fh to 00h
bootstrap loader (BSL)
The BSL enables users to program the flash memory or RAM using a UART serial interface. Access to device
memory via the BSL is protected by user-defined password. For complete description of the features of the BSL
and its implementation, see the application report Features of the MSP430 Bootstrap Loader, literature number
SLAA089.
BSL FUNCTION PZ PACKAGE PINS
Data transmit 87 - P1.0
Data receive 86 - P1.1
flash memory, flash
The flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. The
CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include:
DFlash memory has n segments of main memory and four segments of information memory (A to D) of 64
bytes each. Each segment in main memory is 512 bytes in size.
DSegments 0 to n may be erased in one step, or each segment may be individually erased.
DSegments A to D can be erased individually, or as a group with segments 0 to n.
Segments A to D are also called information memory.
DSegment A might contain calibration data. After reset, segment A is protected against programming or
erasing. It can be unlocked but care should be taken not to erase this segment if the calibration data is
required.
MSP430F47x3, MSP430F47x4
MIXED SIGNAL MICROCONTROLLER
SLAS545C − MAY 2007 − REVISED MARCH 2011
14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
peripherals
Peripherals are connected to the CPU through data, address, and control buses and can be handled using all
instructions. For complete module descriptions, see the MSP430x4xx Family User’s Guide, literature number
SLAU056.
digital I/O
There are nine 8-bit I/O ports implemented—ports P1 through P5 and P7 through P10.
DAll individual I/O bits are independently programmable.
DAny combination of input, output, and interrupt conditions is possible.
DEdge-selectable interrupt input capability for all the eight bits of ports P1 and P2.
DRead/write access to port-control registers is supported by all instructions.
DPorts P7/P8 and P9/P10 can be accessed word-wise as ports PA and PB respectively.
DEach I/O has an individually programmable pullup/pulldown resistor.
oscillator and system clock
The clock system in the MSP430x47xx is supported by the FLL+ module, which includes support for a 32768-Hz
watch crystal oscillator, an internal digitally-controlled oscillator (DCO), and a 8-MHz high-frequency crystal
oscillator (XT1), plus a 16-MHz high-frequency crystal oscillator (XT2). The FLL+ clock module is designed to
meet the requirements of both low system cost and low power consumption. The FLL+ features digital
frequency-locked loop (FLL) hardware that, in conjunction with a digital modulator, stabilizes the DCO frequency
to a programmable multiple of the watch crystal frequency. The internal DCO provides a fast turn-on clock
source and stabilizes in less than 6 μs. The FLL+ module provides the following clock signals:
DAuxiliary clock (ACLK), sourced from a 32768-Hz watch crystal or a high-frequency crystal
DMain clock (MCLK), the system clock used by the CPU
DSub-Main clock (SMCLK), the sub-system clock used by the peripheral modules
DACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, or ACLK/8
brownout, supply voltage supervisor (SVS)
The brownout circuit is implemented to provide the proper internal reset signal to the device during power on
and power off. The supply voltage supervisor circuitry detects if the supply voltage drops below a user selectable
level and supports both supply voltage supervision (the device is automatically reset) and supply voltage
monitoring (SVM, the device is not automatically reset).
The CPU begins code execution after the brownout circuit releases the device reset. However, VCC may not
have ramped to VCC(min) at that time. The user must ensure the default FLL+ settings are not changed until VCC
reaches VCC(min). If desired, the SVS circuit can be used to determine when VCC reaches VCC(min).
hardware multiplier
The multiplication operation is supported by a dedicated peripheral module. The module performs operations
with 32-bit, 24-bit, 16-bit, and 8-bit operands. The module is capable of supporting signed and unsigned
multiplication as well as signed and unsigned multiply-and-accumulate operations.
watchdog timer (WDT+)
The primary function of the WDT+ module is to perform a controlled system restart after a software problem
occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed
in an application, the module can be configured as an interval timer and can generate interrupts at selected time
intervals.
MSP430F47x3, MSP430F47x4
MIXED SIGNAL MICROCONTROLLER
SLAS545C − MAY 2007 − REVISED MARCH 2011
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
universal serial communication interfaces (USCI_A0, USCI_B0, USCI_A1, USCI_B1)
The universal serial communication interface (USCI) module is used for serial data communication. The USCI
module supports synchronous communication protocols such as SPI (3-pin or 4-pin), I2C, and asynchronous
communication protocols such as UART, enhanced UART with automatic baudrate detection (LIN), and IrDA.
USCI_A0 and USCI_A1 provide support for SPI (3-pin or 4-pin), UART, enhanced UART, and IrDA.
USCI_B0 and USCI_B1 provide support for SPI (3-pin or 4-pin) and I2C.
timer_A3
Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
TIMER_A3 SIGNAL CONNECTIONS
INPUT PIN
NUMBER
DEVICE INPUT
SIGNAL
MODULE INPUT
NAME MODULE BLOCK MODULE OUTPUT
SIGNAL
OUTPUT PIN
NUMBER
82 - P1.5 TACLK TACLK
ACLK ACLK
Timer
NA
SMCLK SMCLK Timer NA
82 - P1.5 TACLK INCLK
87 - P1.0 TA0 CCI0A 87 - P1.0
86 - P1.1 TA0 CCI0B
CCR0
TA0
DVSS GND CCR0 TA0
DVCC VCC
85 - P1.2 TA1 CCI1A 85 - P1.2
CAOUT (internal) CCI1B
CCR1
TA1
DVSS GND CCR1 TA1
DVCC VCC
79 - P2.0 TA2 CCI2A 79 - P2.0
ACLK (internal) CCI2B
CCR2
TA2
DVSS GND CCR2 TA2
DVCC VCC
MSP430F47x3, MSP430F47x4
MIXED SIGNAL MICROCONTROLLER
SLAS545C − MAY 2007 − REVISED MARCH 2011
16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
timer_B3
Timer_B3 is a 16-bit timer/counter with three capture/compare registers. Timer_B3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_B3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
TIMER_B3 SIGNAL CONNECTIONS
INPUT PIN
NUMBER
DEVICE INPUT
SIGNAL
MODULE INPUT
NAME MODULE BLOCK MODULE OUTPUT
SIGNAL
OUTPUT PIN
NUMBER
83 - P1.4 TBCLK TBCLK
ACLK ACLK
Timer
NA
SMCLK SMCLK Timer NA
83 - P1.4 TBCLK INCLK
78 - P2.1 TB0 CCI0A 78 - P2.1
78 - P2.1 TB0 CCI0B
CCR0
TB0
DVSS GND CCR0 TB0
DVCC VCC
77 - P2.2 TB1 CCI1A 77 - P2.2
77 - P2.2 TB1 CCI1B
CCR1
TB1
DVSS GND CCR1 TB1
DVCC VCC
76 - P2.3 TB2 CCI2A 76 - P2.3
76 - P2.3 TB2 CCI2B
CCR2
TB2
DVSS GND CCR2 TB2
DVCC VCC
MSP430F47x3, MSP430F47x4
MIXED SIGNAL MICROCONTROLLER
SLAS545C − MAY 2007 − REVISED MARCH 2011
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
comparator_A
The primary function of the comparator_A module is to support precision slope A/D conversions, battery-voltage
supervision, and monitoring of external analog signals.
SD16_A
The SD16_A module integrates three (in MSP430F47x3) or four (in MSP430F47x4) independent 16-bit
sigma−delta A/D converters. Each channel is designed with a fully differential analog input pair and
programmable-gain amplifier input stage. In addition to external analog inputs, an internal VCC sense and
temperature sensor are also available.
Basic Timer1
The Basic Timer1 has two independent 8-bit timers that can be cascaded to form a 16-bit timer/counter. Both
timers can be read and written by software. Basic Timer1 can be used to generate periodic interrupts and a clock
for the LCD module.
LCD driver with regulated charge pump
The LCD_A driver generates the segment and common signals required to drive an LCD display. The LCD_A
controller has dedicated data memory to hold segment drive information. Common and segment signals are
generated as defined by the mode. Static, 2-MUX, 3-MUX, and 4-MUX LCDs are supported by this peripheral.
The module can provide a LCD voltage independent of the supply voltage via an integrated charge pump.
Furthermore, it is possible to control the level of the LCD voltage and, thus, contrast in software.
MSP430F47x3, MSP430F47x4
MIXED SIGNAL MICROCONTROLLER
SLAS545C − MAY 2007 − REVISED MARCH 2011
18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
peripheral file map
PERIPHERALS WITH WORD ACCESS
Watchdog Watchdog timer control WDTCTL 0120h
Flash_A Flash control 4
Flash control 3
Flash control 2
Flash control 1
FCTL4
FCTL3
FCTL2
FCTL1
01BEh
012Ch
012Ah
0128h
Timer_B3 Capture/compare register 2 TBCCR2 0196h
_
Capture/compare register 1 TBCCR1 0194h
Capture/compare register 0 TBCCR0 0192h
Timer_B register TBR 0190h
Capture/compare control 2 TBCCTL2 0186h
Capture/compare control 1 TBCCTL1 0184h
Capture/compare control 0 TBCCTL0 0182h
Timer_B control TBCTL 0180h
Timer_B interrupt vector TBIV 011Eh
Timer_A3 Capture/compare register 2 TACCR2 0176h
_
Capture/compare register 1 TACCR1 0174h
Capture/compare register 0 TACCR0 0172h
Timer_A register TAR 0170h
Capture/compare control 2 TACCTL2 0166h
Capture/compare control 1 TACCTL1 0164h
Capture/compare control 0 TACCTL0 0162h
Timer_A control TACTL 0160h
Timer_A interrupt vector TAIV 012Eh
32-bit Hardware
M lti li
MPY32 control 0 MPY32CTL0 015Ch
Multiplier 64-bit result 3 − most significant word RES3 015Ah
64-bit result 2 RES2 0158h
64-bit result 1 RES1 0156h
64-bit result 0 − least significant word RES0 0154h
Second 32-bit operand, high word OP2H 0152h
Second 32-bit operand, low word OP2L 0150h
Multiply signed + accumulate/
32-bit operand1, high word
MACS32H 014Eh
Multiply signed + accumulate/
32-bit operand1, low word
MACS32L 014Ch
Multiply + accumulate/
32-bit operand1, high word
MAC32H 014Ah
Multiply + accumulate/
32-bit operand1, low word
MAC32L 0148h
Multiply signed/32-bit operand1, high word MPYS32H 0146h
Multiply signed/32-bit operand1, low word MPYS32L 0144h
Multiply unsigned/32-bit operand1, high word MPY32H 0142h
Multiply unsigned/32-bit operand1, low word MPY32L 0140h
MSP430F47x3, MSP430F47x4
MIXED SIGNAL MICROCONTROLLER
SLAS545C − MAY 2007 − REVISED MARCH 2011
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
peripheral file map (continued)
PERIPHERALS WITH WORD ACCESS (CONTINUED)
32-bit Hardware Sum extend SUMEXT 013Eh
Multiplier Result high word RESHI 013Ch
Result low word RESLO 013Ah
Second operand OP2 0138h
Multiply signed + accumulate/operand1 MACS 0136h
Multiply + accumulate/operand1 MAC 0134h
Multiply signed/operand1 MPYS 0132h
Multiply unsigned/operand1 MPY 0130h
USCI_B0
(
see also:
USCI_B0 I2C own address UCB0I2COA 016Ch
(see
also:
Peripherals with
Byte Access) USCI_B0 I2C slave address UCB0I2CSA 016Eh
USCI_B1
(
see also:
USCI_B1 I2C own address UCB1I2COA 017Ch
(see
also:
Peripherals with
Byte Access) USCI_B1 I2C slave address UCB1I2CSA 017Eh
SD16_A
(l
General control SD16CTL 0100h
_
(see also:
Peripherals with
Channel 0 control SD16CCTL0 0102h
Peripherals
with
Byte Access) Channel 1 control SD16CCTL1 0104h
y)
Channel 2 control SD16CCTL2 0106h
Channel 3 control SD16CCTL3 0108h
Interrupt vector word register SD16IV 0110h
Channel 0 conversion memory SD16MEM0 0112h
Channel 1 conversion memory SD16MEM1 0114h
Channel 2 conversion memory SD16MEM2 0116h
Channel 3 conversion memory SD16MEM3 0118h
Port PA Port PA resistor enable PAREN 014h
Port PA selection PASEL 03Eh
Port PA direction PADIR 03Ch
Port PA output PAOUT 03Ah
Port PA input PAIN 038h
Port PB Port PB resistor enable PBREN 016h
Port PB selection PBSEL 00Eh
Port PB direction PBDIR 00Ch
Port PB output PBOUT 00Ah
Port PB input PBIN 008h
MSP430F47x3, MSP430F47x4
MIXED SIGNAL MICROCONTROLLER
SLAS545C − MAY 2007 − REVISED MARCH 2011
20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
peripheral file map (continued)
PERIPHERALS WITH BYTE ACCESS
SD16_A
(see also:
Peripherals with
Word Access)
Channel 0 input control
Channel 1 input control
Channel 2 input control
Channel 3 input control
Channel 0 preload
Channel 1 preload
Channel 2 preload
Channel 3 preload
Reserved (internal SD16 Configuration 1)
SD16INCTL0
SD16INCTL1
SD16INCTL2
SD16INCTL3
SD16PRE0
SD16PRE1
SD16PRE2
SD16PRE3
SD16CONF1
0B0h
0B1h
0B2h
0B3h
0B8h
0B9h
0BAh
0BBh
0BFh
LCD_A LCD voltage control 1
LCD voltage control 0
LCD voltage port control 1
LCD voltage port control 0
LCD memory 20
:
LCD memory 16
LCD memory 15
:
LCD memory 1
LCD control and mode
LCDAVCTL1
LCDAVCTL0
LCDAPCTL1
LCDAPCTL0
LCDM20
:
LCDM16
LCDM15
:
LCDM1
LCDACTL
0AFh
0AEh
0ADh
0ACh
0A4h
:
0A0h
09Fh
:
091h
090h
USCI_A0 USCI_A0 transmit buffer
USCI_A0 receive buffer
USCI_A0 status
USCI_A0 modulation control
USCI_A0 baud rate control 1
USCI_A0 baud rate control 0
USCI_A0 control 1
USCI_A0 control 0
USCI_A0 IrDA receive control
USCI_A0 IrDA transmit control
USCI_A0 auto baud rate control
UCA0TXBUF
UCA0RXBUF
UCA0STAT
UCA0MCTL
UCA0BR1
UCA0BR0
UCA0CTL1
UCA0CTL0
UCA0IRRCTL
UCA0IRTCTL
UCA0ABCTL
067h
066h
065h
064h
063h
062h
061h
060h
05Fh
05Eh
05Dh
USCI_B0 USCI_B0 transmit buffer
USCI_B0 receive buffer
USCI_B0 status
USCI_B1 I2C interrupt enable
USCI_B0 bit rate control 1
USCI_B0 bit rate control 0
USCI_B0 control 1
USCI_B0 control 0
UCB0TXBUF
UCB0RXBUF
UCB0STAT
UCB0I2CIE
UCB0BR1
UCB0BR0
UCB0CTL1
UCB0CTL0
06Fh
06Eh
06Dh
06Ch
06Bh
06Ah
069h
068h
USCI_A1 USCI_A1 transmit buffer
USCI_A1 receive buffer
USCI_A1 status
USCI_A1 modulation control
USCI_A1 baud rate control 1
USCI_A1 baud rate control 0
USCI_A1 control 1
USCI_A1 control 0
USCI_A1 IrDA receive control
USCI_A1 IrDA transmit control
USCI_A1 auto baud rate control
USCI_A1 interrupt flag
USCI_A1 interrupt enable
UCA1TXBUF
UCA1RXBUF
UCA1STAT
UCA1MCTL
UCA1BR1
UCA1BR0
UCA1CTL1
UCA1CTL0
UCA1IRRCTL
UCA1IRTCTL
UCA1ABCTL
UC1IFG
UC1IE
0D7h
0D6h
0D5h
0D4h
0D3h
0D2h
0D1h
0D0h
0CFh
0CEh
0CDh
007h
006h
MSP430F47x3, MSP430F47x4
MIXED SIGNAL MICROCONTROLLER
SLAS545C − MAY 2007 − REVISED MARCH 2011
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
peripheral file map (continued)
PERIPHERALS WITH BYTE ACCESS (CONTINUED)
USCI_B1 USCI_B1 transmit buffer
USCI_B1 receive buffer
USCI_B1 status
USCI_B1 I2C interrupt enable
USCI_B1 bit rate control 1
USCI_B1 bit rate control 0
USCI_B1 control 1
USCI_B1 control 0
USCI_A1 interrupt flag
USCI_A1 interrupt enable
UCB1TXBUF
UCB1RXBUF
UCB1STAT
UCB1I2CIE
UCB1BR1
UCB1BR0
UCB1CTL1
UCB1CTL0
UC1IFG
UC1IE
0DFh
0DEh
0DDh
0DCh
0DBh
0DAh
0D9h
0D8h
007h
006h
Comparator_A Comparator_A port disable CAPD 05Bh
p
_
Comparator_A control2 CACTL2 05Ah
Comparator_A control1 CACTL1 059h
BrownOUT, SVS SVS control register (reset by brownout signal) SVSCTL 056h
FLL+ Clock FLL+ control 2 FLL_CTL2 055h
FLL+ control 1 FLL_CTL1 054h
FLL+ control 0 FLL_CTL0 053h
System clock frequency control SCFQCTL 052h
System clock frequency integrator SCFI1 051h
System clock frequency integrator SCFI0 050h
Basic Timer1 BT counter 2
BT counter 1
BT control
BTCNT2
BTCNT1
BTCTL
047h
046h
040h
Port P10 Port P10 resistor enable P10REN 017h
Port P10 selection P10SEL 00Fh
Port P10 direction P10DIR 00Dh
Port P10 output P10OUT 00Bh
Port P10 input P10IN 009h
Port P9 Port P9 resistor enable P9REN 016h
Port P9 selection P9SEL 00Eh
Port P9 direction P9DIR 00Ch
Port P9 output P9OUT 00Ah
Port P9 input P9IN 008h
Port P8 Port P8 resistor enable P8REN 015h
Port P8 selection P8SEL 03Fh
Port P8 direction P8DIR 03Dh
Port P8 output P8OUT 03Bh
Port P8 input P8IN 039h
Port P7 Port P7 resistor enable P7REN 014h
Port P7 selection P7SEL 03Eh
Port P7 direction P7DIR 03Ch
Port P7 output P7OUT 03Ah
Port P7 input P7IN 038h
MSP430F47x3, MSP430F47x4
MIXED SIGNAL MICROCONTROLLER
SLAS545C − MAY 2007 − REVISED MARCH 2011
22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
peripheral file map (continued)
PERIPHERALS WITH BYTE ACCESS (CONTINUED)
Port P5 Port P5 resistor enable P5REN 012h
Port P5 selection P5SEL 033h
Port P5 direction P5DIR 032h
Port P5 output P5OUT 031h
Port P5 input P5IN 030h
Port P4 Port P4 resistor enable P4REN 011h
Port P4 selection P4SEL 01Fh
Port P4 direction P4DIR 01Eh
Port P4 output P4OUT 01Dh
Port P4 input P4IN 01Ch
Port P3 Port P3 resistor enable P3REN 010h
Port P3 selection P3SEL 01Bh
Port P3 direction P3DIR 01Ah
Port P3 output P3OUT 019h
Port P3 input P3IN 018h
Port P2 Port P2 resistor enable P2REN 02Fh
Port P2 selection P2SEL 02Eh
Port P2 interrupt enable P2IE 02Dh
Port P2 interrupt-edge select P2IES 02Ch
Port P2 interrupt flag P2IFG 02Bh
Port P2 direction P2DIR 02Ah
Port P2 output P2OUT 029h
Port P2 input P2IN 028h
Port P1 Port P1 resistor enable P1REN 027h
Port P1 selection P1SEL 026h
Port P1 interrupt enable P1IE 025h
Port P1 interrupt-edge select P1IES 024h
Port P1 interrupt flag P1IFG 023h
Port P1 direction P1DIR 022h
Port P1 output P1OUT 021h
Port P1 input P1IN 020h
Special functions SFR interrupt flag2 IFG2 003h
p
SFR interrupt flag1 IFG1 002h
SFR interrupt enable2 IE2 001h
SFR interrupt enable1 IE1 000h
MSP430F47x3, MSP430F47x4
MIXED SIGNAL MICROCONTROLLER
SLAS545C − MAY 2007 − REVISED MARCH 2011
23
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings (see Note 1)
Voltage applied at VCC to VSS −0.3 V to 4.1 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage applied to any pin (see Note 2) −0.3 V to VCC + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Diode current at any device terminal . ±2 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature, Tstg: (unprogrammed device, see Note 3) −55°C to 150°C. . . . . . . . . . . . . . . . . . . . . . .
(programmed device, see Note 3) −40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . .
NOTES: 1. Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended
operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
2. All voltages referenced to VSS. The JTAG fuse-blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage
is applied to the TDI/TCLK pin when blowing the JTAG fuse.
3. Higher temperature may be applied during board soldering process according to the current JEDEC J-STD-020 specification with
peak reflow temperatures not higher than classified on the device label on the shipping boxes or reels.
MSP430F47x3, MSP430F47x4
MIXED SIGNAL MICROCONTROLLER
SLAS545C − MAY 2007 − REVISED MARCH 2011
24 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions
MIN NOM MAX UNIT
Supply voltage during program execution,
VCC (AVCC = DVCC = VCC) (see Note 1) 1.8 3.6 V
Supply voltage during program execution, SVS enabled, PORON = 1,
VCC (AVCC = DVCC = VCC) (see Notes 1, 2) 2.0 3.6 V
Supply voltage during program/erase flash memory,
VCC (AVCC = DVCC = VCC) (see Note 1) 2.2 3.6 V
Supply voltage, VSS 0 V
Operating free-air temperature range, TA−40 85 °C
VCC = 1.8 V,
Duty Cycle = 50% ±10% dc 4.15 MHz
Processor frequency fSYSTEM (Maximum MCLK frequency)
VCC = 2.2 V,
Duty Cycle = 50% ±10% dc 7.5 MHz
Processor
frequency
fSYSTEM
(Maximum
MCLK
frequency)
(see Notes 3, 4 and Figure 1) VCC = 2.7 V,
Duty Cycle = 50% ±10% dc 12
MHz
VCC ≥ 3.3 V,
Duty Cycle = 50% ±10% dc 16
MHz
NOTES: 1. It is recommended to power AVCC and DVCC from the same source. A maximum difference of 0.3V between AVCC and DVCC can
be tolerated during power up and operation.
2. The minimum operating supply voltage is defined according to the trip point where POR is going active by decreasing supply voltage.
POR is going inactive when the supply voltage is raised abve minimum supply voltage plus the hysteresis of the SVS circuitry.
3. The MSP430 CPU is clocked directly with MCLK.
Both the high and low phase of MCLK must not exceed the pulse width of the specified maximum frequency.
4. Modules might have a different maximum input clock specification. Refer to the specification of the respective module in this
datasheet.
ÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏ
4.15 MHz
12 MHz
16 MHz
1.8 V 2.2 V 2.7 V 3.3 V 3.6 V
Supply Voltage −V
System Frequency −MHz
ÏÏ
ÏÏ
ÏÏ
ÏÏ
ÏÏ
ÏÏ
Supply voltage range,
during flash memory
programming
Supply voltage range,
during program execution
Legend:
7.5 MHz
NOTE: Minimum processor frequency is defined by system clock. Flash program or erase operations require a minimum VCC of 2.2 V.
Figure 1. Operating Area
MSP430F47x3, MSP430F47x4
MIXED SIGNAL MICROCONTROLLER
SLAS545C − MAY 2007 − REVISED MARCH 2011
25
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
supply current into AVCC + DVCC excluding external current
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
I
Active mode, (see Note 1)
f(MCLK) = f(SMCLK) = 1 MHz,
f32 768 Hz
T40°Cto85°C
VCC = 2.2 V 280 350
A
I(AM)
()()
f(ACLK) = 32, 768 Hz
XTS_FLL = 0, SELM = (0, 1)
(Program executes from flash)
TA = −40°C to 85°C
VCC = 3 V 420 560
μA
I
Low-power mode, (LPM0)
T40°Cto85°C
VCC = 2.2 V 45 70
A
I(LPM0)
Low power
mode
,
(LPM0)
(see Notes 1, 4) TA = −40°C to 85°CVCC = 3 V 75 110 μA
I
Low-power mode, (LPM2),
f f 0 MHz
T40°Cto85°C
VCC = 2.2 V 11 14
A
I(LPM2) f(MCLK) = f (SMCLK) = 0 MHz,
f(ACLK) = 32, 768 Hz, SCG0 = 0 (see Notes 2, 4)
TA = −40°C to 85°CVCC = 3 V 17 22 μA
Low power mode (LPM3)
TA = −40°C 1.0 2.0
Low-power mode, (LPM3)
f(MCLK)
=
f(SMCLK)
=
0 MHz,
TA = 25°C
V22V
1.1 2.0
A
f
(MCLK) =
f
(SMCLK) =
0
MHz
,
f
(
ACLK
)
= 32, 768 Hz, SCG0 = 1 TA = 60°CVCC = 2.2 V 2.0 3.0 μA
I
f(ACLK)
32,
768
Hz,
SCG0
1
Basic Timer1 enabled, ACLK selected
LCD A enabled LCDCPEN 0
TA = 85°C 3.0 6.0
I(LPM3) LCD_A enabled, LCDCPEN = 0,
(static mode, fLCD
=
f(ACLK) /32)
TA = −40°C 1.2 3.0
(static
mode
,
f
LCD =
f
(ACLK)
/32)
(see Notes 2, 3, 4) TA = 25°C
V3V
1.3 3.0
A
(see
Notes
2,
3,
4)
TA = 60°CVCC = 3 V 2.5 3.5 μA
TA = 85°C 3.5 7.5
Low power mode (LPM3)
TA = −40°C 3.5 5.5
Low-power mode, (LPM3)
f(MCLK)
=
f(SMCLK)
=
0 MHz,
TA = 25°C
V22V
3.5 5.5
A
f
(MCLK) =
f
(SMCLK) =
0
MHz
,
f
(
ACLK
)
= 32, 768 Hz, SCG0 = 1 TA = 60°CVCC = 2.2 V 5.5 7.0 μA
I
f(ACLK)
32,
768
Hz,
SCG0
1
Basic Timer1 enabled, ACLK selected
LCD A enabled LCDCPEN 0
TA = 85°C 11.0 17.0
I(LPM3) LCD_A enabled, LCDCPEN = 0,
(4
−
mux mode, fLCD
=
f(ACLK) /32)
TA = −40°C 4.0 8.0
(4
−
mux
mode
,
f
LCD =
f
(ACLK)
/32)
(see Notes 2, 3, 4) TA = 25°C
V3V
4.0 6.5
A
(see
Notes
2,
3,
4)
TA = 60°CVCC = 3 V 6.0 8.0 μA
TA = 85°C 13.0 20.0
TA = −40°C 0.1 1.0
TA = 25°C
V22V
0.2 1.0
A
Low-power mode (LPM4)
TA = 60°CVCC = 2.2 V 1.0 2.0 μA
I
L
ow-power mo
d
e,
(LPM4)
f
(MCLK)
= 0 MHz, f
(SMCLK)
= 0 MHz, TA = 85°C 1.8 5.0
I(LPM4)
f(MCLK)
=
0
MHz
,
f(SMCLK)
=
0
MHz
,
f(ACLK) = 0 Hz, SCG0 = 1
(Nt24)
TA = −40°C 0.1 2.0
(ACLK)
(see Notes 2, 4) TA = 25°C
V3V
0.2 2.0
A
TA = 60°CVCC = 3 V 1.5 2.5 μA
TA = 85°C 2.0 6.0
NOTES: 1. Timer_A is clocked by f(DCOCLK) = f(DCO) = 1 MHz. All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
2. All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
3. The LPM3 currents are characterized with a Micro Crystal CC4V−T1A (9 pF) crystal and OSCCAPx = 1h.
4. Current for brownout included.
MSP430F47x3, MSP430F47x4
MIXED SIGNAL MICROCONTROLLER
SLAS545C − MAY 2007 − REVISED MARCH 2011
26 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
typical characteristics − active mode supply current (into VCC)
0.0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10.0
1.5 2.0 2.5 3.0 3.5 4.0
VCC − Supply Voltage − V
Active Mode Current − mA
Figure 2. Active mode current vs VCC, TA = 25°C
fDCO = 1 MHz
fDCO = 8 MHz
fDCO = 12 MHz
fDCO = 16 MHz
0.0
1.0
2.0
3.0
4.0
5.0
0.0 4.0 8.0 12.0 16.0
fDCO − DCO Frequency − MHz
Active Mode Current − mA
Figure 3. Active mode current vs DCO frequency
TA = 25 °C
TA = 85 °C
VCC = 2.2 V
VCC = 3 V
TA = 25 °C
TA = 85 °C
MSP430F47x3, MSP430F47x4
MIXED SIGNAL MICROCONTROLLER
SLAS545C − MAY 2007 − REVISED MARCH 2011
27
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
Schmitt-trigger inputs − Ports P1 through P5, P7 through P10, RST/NMI, JTAG: TCK, TMS, TDI/TCLK, TDO/TDI
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
P iti i i t th h ld
0.45 0.75 VCC
VIT+
Positive-going input threshold
voltage
2.2 V 1.00 1.65
V
VIT+
vo
lt
age
3 V 1.35 2.25 V
Nti iitthhld
0.25 0.55 VCC
VIT−
Negative-going input threshold
voltage
2.2 V 0.55 1.20
V
VIT
−vo
lt
age
3 V 0.75 1.65 V
V
Input volta
g
e h
y
steresis (VIT+ − 2.2 V 0.2 1.0
V
Vhys
Input
voltage
hysteresis
(VIT
+
VIT−)3 V 0.3 1.0 V
RPull
Pull−up/pull−down resistor
(not RST/NMI and JTAG pins)
For pull−up: VIN = VSS,
For pull−down: VIN = VCC 20 35 50 kW
CIInput Capacitance VIN = VSS or VCC 5 pF
inputs − Ports P1, P2
PARAMETER TEST CONDITIONS VCC MIN MAX UNIT
t(int) External interrupt timing
Port P1, P2: P1.x to P2.x, External
trigger puls width to set interrupt flag,
(see Note 1)
2.2 V/3 V 20 ns
NOTES: 1. An external signal sets the interrupt flag every time the minimum interrupt puls width t(int) is met. It may be set even with trigger signals
shorter than t(int).
leakage current − Ports P1 through P5, P7 through P10
PARAMETER TEST CONDITIONS VCC MIN MAX UNIT
Ilkg(Px.x) High-impedance leakage current see Notes 1 and 2 2.2 V/3 V ±50 nA
NOTES: 1. The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted.
2. The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup/pulldown resistor is
disabled.
MSP430F47x3, MSP430F47x4
MIXED SIGNAL MICROCONTROLLER
SLAS545C − MAY 2007 − REVISED MARCH 2011
28 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
outputs − Ports P1 through P5, P7 through P10
PARAMETER TEST CONDITIONS VCC MIN MAX UNIT
I(OHmax) = −1.5 mA (see Notes 1) 2.2 V VCC−0.25 VCC
V
High level output voltage
I(OHmax) = −6 mA (see Notes 2) 2.2 V VCC−0.6 VCC
V
VOH High-level output voltage I(OHmax) = −1.5 mA (see Notes 1) 3 V VCC−0.25 VCC
V
I(OHmax) = −6 mA (see Notes 2) 3 V VCC−0.6 VCC
I(OLmax) = 1.5 mA (see Notes 1) 2.2 V VSS VSS+0.25
V
Low level output voltage
I(OLmax) = 6 mA (see Notes 2) 2.2 V VSS VSS+0.6
V
VOL Low-level output voltage I(OLmax) = 1.5 mA (see Notes 1) 3 V VSS VSS+0.25 V
I(OLmax) = 6 mA (see Notes 2) 3 V VSS VSS+0.6
NOTES: 1. The maximum total current, IOHmax and IOLmax, for all outputs combined, should not exceed ±12 mA to hold the maximum
voltage drop specified.
2. The maximum total current, IOHmax and IOLmax, for all outputs combined, should not exceed ±48 mA to hold the maximum
voltage drop specified.
output frequency − Ports P1 through P5, P7 through P10
PARAMETER TEST CONDITIONS VCC MIN MAX UNIT
f
Port output frequenc
y
(with P1.4/TBCLK/SMCLK,
C20 pF R 1kWagainst V /2
2.2 V 10 MHz
fPx.y
Port
output
frequency
(with
load) CL = 20 pF, RL = 1 kW against VCC/2
(see Note 1 and 2) 3 V 12 MHz
f
Clock output frequency
P1.1/TA0/MCLK, P1.5/TACLK/ACLK,
P1 4/TBCLK/SMCLK
2.2 V 12 MHz
fPort_CLK Clock output frequency P1.4/TBCLK/SMCLK,
CL = 20 pF (see Note 2) 3 V 16 MHz
NOTES: 1. Alternatively a resistive divider with 2 times 2 kW between VCC and VSS is used as load. The output is connected to the center tap
of the divider.
2. The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.
MSP430F47x3, MSP430F47x4
MIXED SIGNAL MICROCONTROLLER
SLAS545C − MAY 2007 − REVISED MARCH 2011
29
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
typical characteristics − outputs
Figure 4
VOL − Low-Level Output Voltage − V
0.0
5.0
10.0
15.0
20.0
25.0
30.0
0.0 0.5 1.0 1.5 2.0 2.5
VCC = 2.2 V
P2.4
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
TA = 25°C
TA = 85°C
OL
I − Typical Low-Level Output Current − mA
Figure 5
VOL − Low-Level Output Voltage − V
0.0
5.0
10.0
15.0
20.0
25.0
30.0
35.0
40.0
45.0
50.0
55.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
VCC = 3 V
P2.4
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
TA = 25°C
TA = 85°C
OL
I − Typical Low-Level Output Current − mA
Figure 6
VOH − High-Level Output Voltage − V
−30.0
−25.0
−20.0
−15.0
−10.0
−5.0
0.0
0.0 0.5 1.0 1.5 2.0 2.5
VCC = 2.2 V
P2.4
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
TA = 25°C
TA = 85°C
OH
I − Typical High-Level Output Current − mA
Figure 7
VOH − High-Level Output Voltage − V
−55.0
−50.0
−45.0
−40.0
−35.0
−30.0
−25.0
−20.0
−15.0
−10.0
−5.0
0.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
VCC = 3 V
P2.4
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
TA = 25°C
TA = 85°C
OH
I − Typical High-Level Output Current − mA
NOTE: One output loaded at a time.
MSP430F47x3, MSP430F47x4
MIXED SIGNAL MICROCONTROLLER
SLAS545C − MAY 2007 − REVISED MARCH 2011
30 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
POR/brownout reset (BOR) (see Notes 1 and 2)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
VCC(start) (see Figure 8) dVCC/dt ≤ 3 V/s 0.7 × V(B_IT−) V
V(B_IT−) (see Figure 8 through Figure 10) dVCC/dt ≤ 3 V/s 1.71 V
Vhys(B_IT−) (see Figure 8) dVCC/dt ≤ 3 V/s 70 130 180 mV
td(BOR) (see Figure 8) 2000 μs
t(reset)
Pulse length needed at RST/NMI pin
to accepted reset internally 2.2 V/3 V 2μs
NOTES: 1. The current consumption of the brownout module is already included in the ICC current consumption data.
The voltage level V(B_IT−) + Vhys(B_IT−) is ≤ 1.8V.
2. During power up, the CPU begins code execution following a period of td(BOR) after VCC = V(B_IT−) + Vhys(B_IT−). The default FLL+
settings must not be changed until VCC ≥ VCC(min), where VCC(min) is the minimum supply voltage for the desired operating frequency.
See the MSP430x4xx Family User’s Guide (SLAU056) for more information on the brownout/SVS circuit.
0
1
td(BOR)
VCC
V(B_IT−)
Vhys(B_IT−)
VCC(start)
Figure 8. POR/Brownout Reset (BOR) vs Supply Voltage
MSP430F47x3, MSP430F47x4
MIXED SIGNAL MICROCONTROLLER
SLAS545C − MAY 2007 − REVISED MARCH 2011
31
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
typical characteristics − POR/brownout reset (BOR)
VCC(drop)
VCC
3 V
tpw
0
0.5
1
1.5
2
0.001 1 1000
Typical Conditions
1 ns 1 ns
tpw − Pulse Width − μs
VCC(drop) − V
tpw − Pulse Width − μs
VCC = 3 V
Figure 9. VCC(drop) Level With a Square Voltage Drop to Generate a POR/Brownout Signal
VCC
0
0.5
1
1.5
2
VCC(drop)
tpw
tpw − Pulse Width − μs
VCC(drop)− V
3 V
0.001 1 1000 tftr
tpw − Pulse Width − μs
tf = tr
Typical Conditions
VCC = 3 V
Figure 10. VCC(drop) Level With a Triangle Voltage Drop to Generate a POR/Brownout Signal
MSP430F47x3, MSP430F47x4
MIXED SIGNAL MICROCONTROLLER
SLAS545C − MAY 2007 − REVISED MARCH 2011
32 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
SVS (supply voltage supervisor/monitor) (see Note 1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
dVCC/dt > 30 V/ms (see Figure 11) 5 150
μs
t(SVSR) dVCC/dt ≤ 30 V/ms 2000 μs
td(SVSon) SVSon, switch from VLD = 0 to VLD ≠ 0, VCC = 3 V 150 300 μs
tsettle VLD ≠ 0 (see Note 2) 12 μs
V(SVSstart) VLD ≠ 0, VCC/dt ≤ 3 V/s (see Figure 11) 1.55 1.7 V
VLD = 1 70 120 155 mV
Vh
y
s
(
SVS_IT−
)
VCC/dt ≤ 3 V/s (see Figure 11) VLD = 2 .. 14 V(SVS_IT−)
x 0.001
V(SVS_IT−)
x 0.016
Vhys(SVS
_
IT
−
)
VCC/dt ≤ 3 V/s (see Figure 11), external voltage applied
on A7 VLD = 15 4.4 10.4 mV
VLD = 1 1.8 1.9 2.05
VLD = 2 1.94 2.1 2.25
VLD = 3 2.05 2.2 2.37
VLD = 4 2.14 2.3 2.48
VLD = 5 2.24 2.4 2.6
VLD = 6 2.33 2.5 2.71
VCC/dt ≤3 V/s (see Figure 11)
VLD = 7 2.46 2.65 2.86
V(SVS IT )
VCC/dt ≤ 3 V/s (see Figure 11) VLD = 8 2.58 2.8 3
V
V
(SVS_IT−) VLD = 9 2.69 2.9 3.13
V
VLD = 10 2.83 3.05 3.29
VLD = 11 2.94 3.2 3.42
VLD = 12 3.11 3.35 3.61†
VLD = 13 3.24 3.5 3.76†
VLD = 14 3.43 3.7†3.99†
VCC/dt ≤ 3 V/s (see Figure 11), external voltage applied
on A7 VLD = 15 1.1 1.2 1.3
ICC(SVS)
(see Note 1) VLD ≠ 0, VCC = 2.2 V/3 V 10 15 μA
†The recommended operating voltage range is limited to 3.6 V.
NOTES: 1. The current consumption of the SVS module is not included in the ICC current consumption data.
2. tsettle is the settling time that the comparator output needs to have a stable level after VLD is switched VLD ≠ 0 to a different VLD
value somewhere between 2 and 15. The overdrive is assumed to be > 50 mV.
MSP430F47x3, MSP430F47x4
MIXED SIGNAL MICROCONTROLLER
SLAS545C − MAY 2007 − REVISED MARCH 2011
33
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
typical characteristics
VCC(start)
VCC
V(B_IT−)
Brownout
Region
V(SVSstart)
V(SVS_IT−)
Software Sets VLD>0:
SVS is Active
td(SVSR)
undefined
Vhys(SVS_IT−)
0
1
td(BOR)
Brownout
0
1
td(SVSon)
td(BOR)
0
1
Set POR
Brown-
Out
Region
SVS Circuit is Active From VLD > to VCC < V(B_IT−)
SVSOut
Vhys(B_IT−)
Figure 11. SVS Reset (SVSR) vs Supply Voltage
0
0.5
1
1.5
2
VCC
VCC
1 ns 1 ns
VCC(min)
tpw
tpw − Pulse Width − μs
VCC(min)− V
3 V
1 10 1000
tftr
t − Pulse Width − μs
100
tpw
3 V
tf = tr
Rectangular Drop
Triangular Drop
VCC(min)
Figure 12. VCC(min) With a Square Voltage Drop and a Triangle Voltage Drop to Generate an SVS Signal
MSP430F47x3, MSP430F47x4
MIXED SIGNAL MICROCONTROLLER
SLAS545C − MAY 2007 − REVISED MARCH 2011
34 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
DCO
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
f(DCOCLK) N(DCO) = 01Eh, FN_8 = FN_4 = FN_3 = FN_2 = 0, D = 2, DCOPLUS = 0 2.2 V/3 V 1 MHz
f
FN 8 FN 4 FN 3 FN 2 0 DCOPLUS 1
2.2 V 0.3 0.65 1.25
MHz
f(DCO = 2) FN_8 = FN_4 = FN_3 = FN_2 = 0, DCOPLUS = 1 3 V 0.3 0.7 1.3 MHz
f
FN 8 FN 4 FN 3 FN 2 0 DCOPLUS 1
2.2 V 2.5 5.6 10.5
MHz
f(DCO = 27) FN_8 = FN_4 = FN_3 = FN_2 = 0, DCOPLUS = 1 3 V 2.7 6.1 11.3 MHz
f
FN_8 = FN_4 = FN_3 = 0, FN_2 = 1, DCOPLUS = 1 2.2 V 0.7 1.3 2.3
MHz
f(DCO = 2)
FN
_
8
=
FN
_
4
=
FN
_
3
=
0
,
FN
_
2
=
1
,
DCOPLUS
=
1
3 V 0.8 1.5 2.5 MHz
f
FN 8 FN 4 FN 3 0 FN 2 1 DOPLUS 1
2.2 V 5.7 10.8 18
MHz
f(DCO = 27) FN_8 = FN_4 = FN_3 = 0, FN_2 = 1, DOPLUS = 1 3 V 6.5 12.1 20 MHz
f
FN 8 FN 4 0 FN 3 1 FN 2 x DCOPLUS 1
2.2 V 1.2 2 3
MHz
f(DCO = 2) FN_8 = FN_4 = 0, FN_3 = 1, FN_2 = x, DCOPLUS = 1 3 V 1.3 2.2 3.5 MHz
f
FN 8 FN 4 0 FN 3 1 FN 2 x DCOPLUS 1
2.2 V 9 15.5 25
MHz
f(DCO = 27) FN_8 = FN_4 = 0, FN_3 = 1, FN_2 = x, DCOPLUS = 1 3 V 10.3 17.9 28.5 MHz
f
FN 8 0 FN 4 1 FN 3 FN 2 x DCOPLUS 1
2.2 V 1.8 2.8 4.2
MHz
f(DCO = 2) FN_8 = 0, FN_4 = 1, FN_3 = FN_2 = x, DCOPLUS = 1 3 V 2.1 3.4 5.2 MHz
f
FN 8 0 FN 4 1 FN 3 FN 2 x DCOPLUS 1
2.2 V 13.5 21.5 33
MHz
f(DCO = 27) FN_8 = 0, FN_4 = 1, FN_3 = FN_2 = x, DCOPLUS = 1 3 V 16 26.6 41 MHz
f
FN 8 1 FN 4 FN 3 FN 2 x DCOPLUS 1
2.2 V 2.8 4.2 6.2
MHz
f(DCO = 2) FN_8 = 1, FN_4 = FN_3 = FN_2 = x, DCOPLUS = 1 3 V 4.2 6.3 9.2 MHz
f
FN 8 1 FN 4 FN 3 FN 2 x DCOPLUS 1
2.2 V 21 32 46
MHz
f(DCO = 27) FN_8 = 1, FN_4 = FN_3 = FN_2 = x, DCOPLUS = 1 3 V 30 46 70 MHz
S
Step size between adjacent DCO taps:
S f /f
1 < TAP ≤ 20 1.06 1.11
SnSn = fDCO(Tap n+1) / fDCO(Tap n)
(see Figure 14 for taps 21 to 27) TAP = 27 1.07 1.17
D
t
Temperature drift, N
(
D
CO)
= 01Eh, FN_8 = FN_4 = FN_3 = FN_2 = 0, 2.2 V –0.2 –0.3 –0.4
%/_C
Dt
Temperature
drift
,
N(DCO)
=
01Eh
,
FN
_
8
=
FN
_
4
=
FN
_
3
=
FN
_
2
=
0
,
D = 2, DCOPLUS = 0 3 V –0.2 –0.3 –0.4 %/_C
DV
Drift with VCC variation, N(DCO) = 01Eh, FN_8 = FN_4 = FN_3 = FN_2 = 0,
D = 2, DCOPLUS = 0 2.2 V/3 V 0 5 15 %/V
TA − °CVCC − V
f(DCO)
f(DCO205C)
f(DCO)
f(DCO3V)
1.8 3.02.4 3.6
1.0
20 6040 85
1.0
0−20−400
Figure 13. DCO Frequency vs Supply Voltage VCC and vs Ambient Temperature
MSP430F47x3, MSP430F47x4
MIXED SIGNAL MICROCONTROLLER
SLAS545C − MAY 2007 − REVISED MARCH 2011
35
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
12720
1.11
1.17
DCO Tap
Sn - Stepsize Ratio between DCO Taps
Min
Max
1.07
1.06
Figure 14. DCO Tap Step Size
FN_2=0
FN_3=0
FN_4=0
FN_8=0
FN_2=1
FN_3=0
FN_4=0
FN_8=0
FN_2=x
FN_3=1
FN_4=0
FN_8=0
FN_2=x
FN_3=x
FN_4=1
FN_8=0
FN_2=x
FN_3=x
FN_4=x
FN_8=1
Legend
Tolerance at Tap 27
Tolerance at Tap 2
DCO Frequency
Adjusted by Bits
29 to 2 5 in SCFI1 {N (DCO)}
Overlapping DCO Ranges:
uninterrupted frequency range
f(DCO)
Figure 15. Five Overlapping DCO Ranges Controlled by FN_x Bits
MSP430F47x3, MSP430F47x4
MIXED SIGNAL MICROCONTROLLER
SLAS545C − MAY 2007 − REVISED MARCH 2011
36 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
crystal oscillator, LFXT1, low-frequency modes (see Note 4)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
fLFXT1, LF
LFXT1 oscillator crystal
frequency, LF mode XTS_FLL = 0, LFXT1DIG = 0 1.8 V−3.6 V 32, 768 Hz
fLFXT1, LF, logic
LFXT1 oscillator logic level
square-wave input frequency,
LF mode
XTS_FLL = 0, LFXT1DIG = 1,
XCAPx = 0 1.8 V−3.6 V 10, 000 32, 768 Hz
OA
Oscillation allowance for LF
XTS_FLL = 0, LFXT1DIG = 0,
fLFXT1, LF = 32,768 kHz,
CL, eff = 6 pF
500
kW
OALF
Oscillation
allowance
for
LF
crystals XTS_FLL = 0, LFXT1DIG = 0,
fLFXT1, LF = 32,768 kHz,
CL, eff = 12 pF
200
kW
XTS_FLL = 0, XCAPx = 0 1
C
Integrated effective load
capacitance LF mode
XTS_FLL = 0, XCAPx = 1 5.5
pF
CL, eff capacitance, LF mode
(see
N
o
t
e
1
)
XTS_FLL = 0, XCAPx = 2 8.5 pF
(see
Note
1)
XTS_FLL = 0, XCAPx = 3 11
Duty Cycle LF mode
XTS_FLL = 0,
Measured at P1.4/ACLK,
fLFXT1, LF = 32, 768 Hz
2.2 V/3 V 30 50 70 %
fFault, LF
Oscillator fault frequency,
LF mode (see Note 3) XTS_FLL = 0 (see Note 2) 2.2 V/3 V 10 10, 000 Hz
NOTES: 1. Includes parasitic bond and package capacitance (approximately 2pF per pin).
Since the PCB adds additional capacitance it is recommended to verify the correct load by measuring the ACLK frequency. For a
correct setup the effective load capacitance should always match the specification of the used crystal.
2. Measured with logic level input frequency but also applies to operation with crystals.
3. Frequencies below the MIN specification will set the fault flag, frequencies above the MAX specification will not set the fault flag.
Frequencies in between might set the flag.
4. To improve EMI on the LFXT1 oscillator the following guidelines should be observed.
− Keep as short of a trace as possible between the device and the crystal.
− Design a good ground plane around the oscillator pins.
− Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
− Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
− Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.
− If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.
− Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other
documentation. This signal is no longer required for the serial programming adapter.
crystal oscillator, LFXT1, high-frequency mode
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
f
XT1 oscillator crystal frequency
XTS FLL 1 Ceramic resonator
1.8 V−3.6 V 0.45 4
MHz
fXT1 XT1 oscillator crystal frequency XTS_FLL = 1, Ceramic resonator 2.7 V−3.6 V 0.45 8 MHz
f
XT1 oscillator crystal frequency
XTS FLL 1 Crystal
1.8 V−3.6 V 1 4
MHz
fXT1 XT1 oscillator crystal frequency XTS_FLL = 1, Crystal 2.7 V−3.6 V 1 8 MHz
CL, eff
Integrated effective Load
Capacitance (see Note 1)
XTS_FLL = 1, XCAPx = 0
(see Note 2) 1 pF
Duty Cycle Measured at P1.4/ACLK 2.2 V/3 V 40 50 60 %
NOTES: 1. Includes parasitic bond and package capacitance (approximately 2pF per pin).
Since the PCB adds additional capacitance it is recommended to verify the correct load by measuring the ACLK frequency. For a
correct setup the effective load capacitance should always match the specification of the used crystal.
2. Requires external capacitors at both terminals. Values are specified by crystal manufacturers.
MSP430F47x3, MSP430F47x4
MIXED SIGNAL MICROCONTROLLER
SLAS545C − MAY 2007 − REVISED MARCH 2011
37
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
crystal oscillator, XT2 oscillator (see Note 5)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
fXT2, 0
XT2 oscillator crystal frequency,
mode 0 XT2Sx = 0 1.8 V − 3.6 V 0.4 1 MHz
fXT2, 1
XT2 oscillator crystal frequency,
mode 1 XT2Sx = 1 1.8 V − 3.6 V 1 4 MHz
XT2 ill t t l f
1.8 V − 3.6 V 2 10
fXT2, 2
XT2 oscillator crystal frequency,
mode 2
XT2Sx = 2 2.2 V − 3.6 V 2 12 MHz
fXT2
,
2
mo
d
e
2
XT2Sx
2
3.0 V − 3.6 V 2 16
MHz
XT2 ill t l i l l
1.8 V − 3.6 V 0.4 10
fXT2, lo
g
ic
XT2 oscillator logic level
square
-
wave input frequency
XT2Sx = 3 2.2 V − 3.6 V 0.4 12 MHz
fXT2
,
logic
square-wave
i
npu
t
f
requency
XT2Sx
3
3.0 V − 3.6 V 0.4 16
MHz
XT2Sx = 0,
fXT2 = 1 MHz, CL, eff = 15 pF 2700
OAXT2 Oscillation allowance for HF
crystals (see Figure 16)
XT2Sx = 1
fLFXT1, HF = 4 MHz,
CL, eff = 15 pF
800 W
crystals
(see
Figure
16)
XT2Sx = 2
fLFXT1, HF = 16 MHz,
CL, eff = 15 pF
300
CL, eff
Integrated effective load
capacitance (see Note 1) (see Note 2) 1 pF
Duty cycle
Measured at P1.4/ACLK,
fXT2 = 10 MHz 2.2 V/3 V 40 50 60
%
Duty cycle Measured at P1.4/ACLK,
fXT2 = 16 MHz 3 V 40 50 60
%
fFault, XT2
Oscillator fault frequency
(see Note 4) XT2Sx = 3 (see Note 3) 2.2 V/3 V 30 300 kHz
NOTES: 1. Includes parasitic bond and package capacitance (approximately 2pF per pin).
Since the PCB adds additional capacitance it is recommended to verify the correct load by measuring the ACLK frequency. For a
correct setup the effective load capacitance should always match the specification of the used crystal.
2. Requires external capacitors at both terminals. Values are specified by crystal manufacturers.
3. Measured with logic level input frequency but also applies to operation with crystals.
4. Frequencies below the MIN specification will set the fault flag, frequencies above the MAX specification will not set the fault flag.
Frequencies in between might set the flag.
5. To improve EMI on the XT2 oscillator the following guidelines should be observed.
− Keep traces as short as possible between the device and the crystal.
− Design a good ground plane around the oscillator pins.
− Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
− Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
− Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.
− If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.
− Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other
documentation. This signal is no longer required for the serial programming adapter.
MSP430F47x3, MSP430F47x4
MIXED SIGNAL MICROCONTROLLER
SLAS545C − MAY 2007 − REVISED MARCH 2011
38 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
typical characteristics − XT2 oscillator
Crystal Frequency − MHz
10.00
100.00
1000.00
10000.00
100000.00
0.10 1.00 10.00 100.00
Oscillation Allowance − Ohms
XT2Sx = 0
XT2Sx = 2
XT2Sx = 1
Figure 16. Oscillation Allowance vs Crystal Frequency, CL, eff = 15 pF, TA = 25°C
MSP430F47x3, MSP430F47x4
MIXED SIGNAL MICROCONTROLLER
SLAS545C − MAY 2007 − REVISED MARCH 2011
39
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
wake-up LPM3
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
f = 1 MHz 6
td
(
LPM3
)
Delay time f = 2 MHz VCC = 2.2 V/3 V 6μs
td(LPM3)
Delay
time
f = 3 MHz
VCC
=
2.2
V/3
V
6
μs
LCD_A
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
VCC(LCD) Supply voltage range Charge pump enabled
(LCDCPEN = 1, VLCDx > 0000) 2.2 3.6 V
CLCD Capacitor on LCDCAP
(see Note 1) Charge pump enabled
(LCDCPEN = 1, VLCDx > 0000) 4.7 μF
ICC(LCD) Supply current
VLCD(typ) = 3V, LCDCPEN = 1, VLCDx = 1000,
All segments on, fLCD = fACLK/32,
No LCD connected (see Note 2), TA = 25°C2.2 V 3.8 μA
fLCD LCD frequency 1.1 kHz
VLCDx = 0000 VCC
VLCDx = 0001 2.60
VLCDx = 0010 2.66
VLCDx = 0011 2.72
VLCDx = 0100 2.78
VLCDx = 0101 2.84
VLCDx = 0110 2.90
V
LCD voltage
VLCDx = 0111 2.96
V
VLCD LCD voltage VLCDx = 1000 3.02 V
VLCDx = 1001 3.08
VLCDx = 1010 3.14
VLCDx = 1011 3.20
VLCDx = 1100 3.26
VLCDx = 1101 3.32
VLCDx = 1110 3.38
VLCDx = 1111 3.44 3.60
RLCD LCD driver output
impedance VLCD = 3V, LCDCPEN = 1,
VLCDx = 1000, ILOAD = ±10μA2.2 V 10 kΩ
NOTES: 1. Enabling the internal charge pump with an external capacitor smaller than the minimum specified might damage the device.
2. Connecting an actual display will increase the current consumption depending on the size of the LCD.
MSP430F47x3, MSP430F47x4
MIXED SIGNAL MICROCONTROLLER
SLAS545C − MAY 2007 − REVISED MARCH 2011
40 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
Comparator_A (see Note 1)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
I
CAON 1 CARSEL 0 CAREF 0
2.2 V 25 40
A
I(CC) CAON = 1, CARSEL = 0, CAREF = 0 3 V 45 60 μA
I
CAON = 1, CARSEL = 0, CAREF =
1/2/3
2.2 V 30 50
A
I(Refladder/RefDiode) 1/2/3,
No load at P1.6/CA0 and P1.7/CA1 3 V 45 80 μA
V(Ref025)
Voltage @ 0.25 VCC node
VCC
PCA0 = 1, CARSEL = 1, CAREF = 1,
No load at P1.6/CA0 and P1.7/CA1 2.2 V/3 V 0.23 0.24 0.25
V(Ref050)
Voltage @ 0.5 VCC node
VCC
PCA0 = 1, CARSEL = 1, CAREF = 2,
No load at P1.6/CA0 and P1.7/CA1 2.2 V/3 V 0.47 0.48 0.5
V
See Fi
g
ure 17 and PCA0 = 1, CARSEL = 1, CAREF = 3,
No load at P1 6/CA0 and P1 7/CA1
2.2 V 390 480 540
mV
V(RefVT)
See
Figure
17
and
Figure 18 No load at P1.6/CA0 and P1.7/CA1,
TA = 85°C3 V 400 490 550 mV
VIC
Common-mode input
voltage range CAON = 1 2.2 V/3 V 0 VCC−1 V
Vp−VSOffset voltage See Note 2 2.2 V/3 V −30 30 mV
Vhys Input hysteresis CAON = 1 2.2 V/3 V 0 0.7 1.4 mV
TA = 25°C, 2.2 V 80 165 300
ns
tsee Note 3
TA
=
25 C
,
Overdrive 10 mV, without filter: CAF = 0 3 V 70 120 240 ns
t(response LH and HL), see Note 3 TA = 25°C2.2 V 1.4 1.9 2.8
s
TA
=
25 C
Overdrive 10 mV, with filter: CAF = 1 3 V 0.9 1.5 2.2 μs
NOTES: 1. The leakage current for the Comparator_A terminals is identical to Ilkg(Px.x) specification.
2. The input offset voltage can be cancelled by using the CAEX bit to invert the Comparator_A inputs on successive measurements.
The two successive measurements are then summed together.
3. The response time is measured at P1.6/CA0 with an input voltage step and the Comparator_A already enabled (CAON = 1). If CAON
is set at the same time, a settling time of up to 300 ns is added to the response time.
MSP430F47x3, MSP430F47x4
MIXED SIGNAL MICROCONTROLLER
SLAS545C − MAY 2007 − REVISED MARCH 2011
41
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
typical characteristics
TA − Free-Air Temperature − °C
400
450
500
550
600
650
−45 −25 −5 15 35 55 75 95
VCC = 3 V
Figure 17. V
(
RefVT
)
vs Temperature
VREF − Reference Voltage − mV
Typical
REFERENCE VOLTAGE
vs
FREE-AIR TEMPERATURE
Figure 18. V
(
RefVT
)
vs Temperature
TA − Free-Air Temperature − °C
400
450
500
550
600
650
−45 −25 −5 15 35 55 75 95
VCC = 2.2 V
Typical
REFERENCE VOLTAGE
vs
FREE-AIR TEMPERATURE
VREF − Reference Voltage − mV
_
+
CAON
0
1
V+ 0
1
CAF
Low-Pass Filter
τ ≈ 2 μs
To Internal
Modules
Set CAIFG
Flag
CAOUT
V−
VCC
1
0 V
0
Figure 19. Block Diagram of Comparator_A Module
Overdrive VCAOUT
t(response)
V+
V−
400 mV
Figure 20. Overdrive Definition
MSP430F47x3, MSP430F47x4
MIXED SIGNAL MICROCONTROLLER
SLAS545C − MAY 2007 − REVISED MARCH 2011
42 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
Timer_A
PARAMETER TEST CONDITIONS VCC MIN MAX UNIT
f
Timer A clock frequency
Internal: SMCLK, ACLK,
External: TACLK INCLK
2.2 V 10
MHz
fTA Timer_A clock frequency External: TACLK, INCLK,
Duty Cycle = 50% ±10% 3 V 16
MHz
tTA, cap Timer_A, capture timing TA0, TA1, TA2 2.2 V/3 V 20 ns
Timer_B
PARAMETER TEST CONDITIONS VCC MIN MAX UNIT
f
Timer B clock frequency
Internal: SMCLK, ACLK,
External: TBCLK
2.2 V 10
MHz
fTB Timer_B clock frequency External: TBCLK,
Duty Cycle = 50% ±10% 3 V 16
MHz
tTB, cap Timer_B, capture timing TB0, TB1, TB2 2.2 V/3 V 20 ns
MSP430F47x3, MSP430F47x4
MIXED SIGNAL MICROCONTROLLER
SLAS545C − MAY 2007 − REVISED MARCH 2011
43
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
USCI (UART mode)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
fUSCI USCI input clock frequency
Internal: SMCLK, ACLK
External: UCLK
Duty Cycle = 50% ± 10%
fSYSTEM MHz
fBITCLK
BITCLK clock frequency
(equals Baudrate in MBaud) 2.2V /3 V 1 MHz
t
UART receive de
g
litch time 2.2 V 50 150 600 ns
tτ
UART
receive
deglitch
time
(see Note 1) 3 V 50 100 600 ns
NOTES: 1. Pulses on the UART receive input (UCxRX) shorter than the UART receive deglich time are suppressed. To ensure that pulses are
correctly recognized their width should exceed the maximum specification of the deglitch time.
USCI (SPI master mode) (see Figure 21 and Figure 22)
PARAMETER TEST CONDITIONS VCC MIN MAX UNIT
fUSCI USCI input clock frequency SMCLK, ACLK
Duty Cycle = 50% ± 10% fSYSTEM MHz
t
SOMI input data setup time
2.2 V 110 ns
tSU, MI SOMI input data setup time 3 V 75 ns
t
SOMI input data hold time
2.2 V 0 ns
tHD, MI SOMI input data hold time 3 V 0 ns
t
SIMO output data valid time
UCLK ed
g
e to SIMO valid, 2.2 V 30 ns
tVALID, MO SIMO output data valid time
UCLK
edge
to
SIMO
valid
,
CL = 20 pF 3 V 20 ns
NOTE: fUCxCLK +1
2tLOńHI
with tLOńHI wmax(tVALID,MO(USCI) )tSU,SI(Slave), tSU,MI(USCI) )tVALID,SO(Slave)).
For the slave’s parameters tSU, SI(Slave) and tVALID, SO(Slave) see the SPI parameters of the attached slave.
USCI (SPI slave mode) (see Figure 23 and Figure 24)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
tSTE, LEAD
STE lead time
STE low to clock 2.2 V/3 V 50 ns
tSTE, LAG
STE lag time
Last clock to STE high 2.2 V/3 V 10 ns
tSTE, ACC
STE access time
STE low to SOMI data out 2.2 V/3 V 50 ns
tSTE, DIS
STE disable time
STE high to SOMI high impedance 2.2 V/3 V 50 ns
t
SIMO input data setup time
2.2 V 20 ns
tSU, SI SIMO input data setup time 3 V 15 ns
t
SIMO input data hold time
2.2 V 10 ns
tHD, SI SIMO input data hold time 3 V 10 ns
t
SOMI output data valid time
UCLK ed
g
e to SOMI valid, 2.2 V 75 110 ns
tVALID, SO SOMI output data valid time
UCLK
edge
to
SOMI
valid
,
CL = 20 pF 3 V 50 75 ns
NOTE: fUCxCLK +1
2tLOńHI
with tLOńHI wmax(tVALID,MO(Master) )tSU,SI(USCI), tSU,MI(Master) )tVALID,SO(USCI)).
For the master’s parameters tSU, MI(Master) and tVALID, MO(Master) see the SPI parameters of the attached master.
MSP430F47x3, MSP430F47x4
MIXED SIGNAL MICROCONTROLLER
SLAS545C − MAY 2007 − REVISED MARCH 2011
44 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
UCLK
CKPL=0
CKPL=1
SIMO
1/fUCxCLK
tLO/HI tLO/HI
SOMI
tSU,MI
tHD,MI
tVALID,MO
Figure 21. SPI Master Mode, CKPH = 0
UCLK
CKPL=0
CKPL=1
SIMO
1/fUCxCLK
tLO/HI tLO/HI
SOMI
tSU,MI
tHD,MI
tVALID,MO
Figure 22. SPI Master Mode, CKPH = 1
MSP430F47x3, MSP430F47x4
MIXED SIGNAL MICROCONTROLLER
SLAS545C − MAY 2007 − REVISED MARCH 2011
45
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
STE
UCLK
CKPL=0
CKPL=1
SOMI
tSTE,ACC tSTE,DIS
1/fUCxCLK
tLO/HI tLO/HI
SIMO
tSU,SI
tHD,SI
tVALID,SO
tSTE,LEAD tSTE,LAG
Figure 23. SPI Slave Mode, CKPH = 0
STE
UCLK
CKPL=0
CKPL=1
tSTE,LEAD tSTE,LAG
tSTE,ACC tSTE,DIS
tLO/HI tLO/HI
tSU,SI
tHD,SI
tVALID,SO
SOMI
SIMO
1/fUCxCLK
Figure 24. SPI Slave Mode, CKPH = 1
MSP430F47x3, MSP430F47x4
MIXED SIGNAL MICROCONTROLLER
SLAS545C − MAY 2007 − REVISED MARCH 2011
46 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
USCI (I2C mode) (see Figure 25)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
fUSCI USCI input clock frequency
Internal: SMCLK, ACLK
External: UCLK
Duty cycle = 50% ± 10%
fSYSTEM MHz
fSCL SCL clock frequency 2.2 V/3 V 0 400 kHz
t
Hold time (repeated) START
fSCL ≤ 100 kHz 2.2 V/3 V 4.0
us
tHD, STA Hold time (repeated) START fSCL > 100 kHz 2.2 V/3 V 0.6 us
t
Setup time for a repeated START
fSCL ≤ 100 kHz 2.2 V/3 V 4.7
us
tSU, STA Setup time for a repeated START fSCL > 100 kHz 2.2 V/3 V 0.6 us
tHD, DAT Data hold time 2.2 V/3 V 0 ns
tSU, DAT Data setup time 2.2 V/3 V 250 ns
tSU, STO Setup time for STOP 2.2 V/3 V 4.0 us
t
Pulse width of spikes suppressed by input filter
2.2 V 50 150 600
ns
tSP Pulse width of spikes suppressed by input filter 3 V 50 100 600 ns
SDA
SCL
1/fSCL
tHD,DAT
tSU,DAT
tHD,STA tSU,STA tHD,STA
tSU,STO
tSP
Figure 25. I2C Mode Timing
MSP430F47x3, MSP430F47x4
MIXED SIGNAL MICROCONTROLLER
SLAS545C − MAY 2007 − REVISED MARCH 2011
47
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
SD16_A, power supply and recommended operating conditions
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
AVCC
Analog supply
voltage
AVCC = DVCC
AVSS = DVSS = 0V 2.5 3.6 V
SD16LP
=
0,
GAIN: 1, 2 3 V 730 1050
Analog supply
t1 ti
SD16LP
=
0
,
fSD16 = 1 MHz, GAIN: 4, 8, 16 3 V 810 1150
ISD16
current: 1 active
SD16 A channel
fSD16
1
MHz,
SD16OSR = 256 GAIN: 32 3 V 1160 1700
μA
I
SD16
SD16
_
A
channel
including internal
reference
SD16LP = 1,
f0 5 MHz
GAIN: 1 3 V 720 1030
μ
A
reference fSD16 = 0.5 MHz,
SD16OSR = 256 GAIN: 32 3 V 810 1150
f
Analog front-end
input clock
SD16LP = 0 (Low power mode disabled) 3 V 0.03 1 1.1
MHz
fSD16 input clock
frequency SD16LP = 1 (Low power mode enabled) 3 V 0.03 0.5 MHz
SD16_A, input range (see Note 1)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
V
Differential full scale Bipolar mode, SD16UNI = 0 −VREF/2GAIN +VREF/2GAIN
mV
VID, FSR
Differential
full
scale
input voltage range Unipolar mode, SD16UNI = 1 0 +VREF/2GAIN mV
SD16GAINx = 1 ±500
Differential input SD16GAINx = 2 ±250
V
Differential
input
voltage range for
specified
SD16REFON 1
SD16GAINx = 4 ±125
mV
VID specified
performance
SD16REFON = 1 SD16GAINx = 8 ±62 mV
performance
(see Note 2) SD16GAINx = 16 ±31
(see
Note
2)
SD16GAINx = 32 ±15
Z
Input impedance
(one input pin to
f1 MHz
SD16GAINx = 1 3 V 200
kΩ
ZI(one input pin to
AVSS)
fSD16 = 1 MHz SD16GAINx = 32 3 V 75 kΩ
Z
Differential input
impedance
f1 MHz
SD16GAINx = 1 3 V 300 400
kΩ
ZID impedance
(IN+ to IN−)
fSD16 = 1 MHz SD16GAINx = 32 3 V 100 150 kΩ
VI
Absolute input
voltage range AVSS -1V AVCC V
VIC
Common-mode
input voltage range AVSS -1V AVCC V
NOTES: 1. All parameters pertain to each SD16_A channel.
2. The analog input range depends on the reference voltage applied to VREF
. If VREF is sourced externally, the full-scale range
is defined by VFSR+ = +(VREF/2)/GAIN and VFSR− = −(VREF/2)/GAIN. The analog input range should not exceed 80% of
VFSR+ or VFSR−.
MSP430F47x3, MSP430F47x4
MIXED SIGNAL MICROCONTROLLER
SLAS545C − MAY 2007 − REVISED MARCH 2011
48 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
SD16_A, performance (fSD16 = 1MHz, SD16OSRx = 256, SD16REFON = 1)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
SD16GAINx = 1,
Signal Amplitude VPP = 500 mV 3 V 83 85
SD16GAINx = 2,
Signal Amplitude VPP = 250 mV 3 V 81 84
SINAD
Si
g
nal-to-noise +
SD16GAINx = 4,
Signal Amplitude VPP = 125 mV f
IN
= 50 Hz, 100 Hz 3 V 76 79
dB
SINAD
Signal to noise
+
distortion ratio SD16GAINx = 8,
Signal Amplitude VPP = 62 mV
fIN
=
50
Hz
,
100
Hz
(see Notes 1 and 2) 3 V 70 75
dB
SD16GAINx = 16,
Signal Amplitude VPP = 31 mV 3 V 66 70
SD16GAINx = 32,
Signal Amplitude VPP = 15 mV 3 V 62 65
SD16GAINx = 1 3 V 0.97 1.00 1.02
SD16GAINx = 2 3 V 1.90 1.96 2.02
G
SD16GAINx = 4 3 V 3.76 3.86 3.96
GNominal gain SD16GAINx = 8 3 V 7.36 7.62 7.84
SD16GAINx = 16 3 V 14.56 15.04 15.52
SD16GAINx = 32 3 V 27.20 28.35 29.76
E
Offset error
SD16GAINx = 1 3 V ±0.2
%FSR
EOS Offset error SD16GAINx = 32 3 V ±1.5 %FSR
dE /dT
Offset error temperature SD16GAINx = 1 3 V ±4±20 ppm
dEOS/dT
Offset
error
temperature
coefficient SD16GAINx = 32 3 V ±20 ±100
ppm
FSR/_C
CMRR
Common-mode rejection
SD16GAINx = 1, Common-mode input signal:
VID = 500 mV, fIN = 50 Hz, 100 Hz 3 V >90
dB
CMRR
Common mode
rejection
ratio SD16GAINx = 32, Common-mode input signal:
VID = 16 mV, fIN = 50 Hz, 100 Hz 3 V >75
dB
AC PSRR AC power supply
rejection ratio SD16GAINx = 1, VCC = 3V ± 100mV, fVcc = 50 Hz 3 V >80 dB
XTCrosstalk SD16GAINx = 1, VID = 500 mV, fIN = 50 Hz, 100 Hz 3 V <−100 dB
NOTES: 1. The following voltages were applied to the SD16 inputs:
VIN, A+(t) = 1.2V + VPP/2 × sin(2π × fIN × t)
VIN, A−(t) = 1.2V − VPP/2 × sin(2π × fIN × t)
resulting in a differential voltage of Vdiff = VIN, A+(t) − VIN, A−(t) = VPP × sin(2π × fIN × t)
2. The SINAD performance of the SD16_A maybe degraded. See errata sheet.
MSP430F47x3, MSP430F47x4
MIXED SIGNAL MICROCONTROLLER
SLAS545C − MAY 2007 − REVISED MARCH 2011
49
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
typical characteristics − SD16_A SNR/SINAD performance over OSR
OSR
50.0
55.0
60.0
65.0
70.0
75.0
80.0
85.0
90.0
95.0
100.0
10.00 100.00 1000.00
SNR/SINAD − dB
Figure 26. SNR/SINAD performance over OSR, fSD16 = 1MHz, SD16REFON = 1, SD16GAINx = 1
VIN(t) = 1.2V + 500mV y sin(2p y 50Hz y t)
SINAD
SNR
SD16_A, temperature sensor and built-in VCC sense
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
TCSensor
Sensor temperature
coefficient 1.18 1.32 1.46 mV/K
VOffset, sensor Sensor offset voltage −100 100 mV
Sttlt
Temperature sensor voltage at TA = 85°C3 V 435 475 515
VSensor
Sensor output voltage
(see Note 2)
Temperature sensor voltage at TA = 25°C3 V 355 395 435 mV
VSensor
(
see
N
o
t
e
2)
Temperature sensor voltage at TA = 0°C3 V 320 360 400
mV
VCC, Sense VCC divider at input 5 fSD16 = 32kHz, SD16OSRx = 256, SD16REFON = 1 0.08 1/11 0.10 VCC
RSource, VCC
Source resistance of
VCC divider at input 5 500 kΩ
NOTES: 1. The following formula can be used to calculate the temperature sensor output voltage:
VSensor, typ = TCSensor ( 273 + T [°C] ) + VOffset, sensor [mV]
2. Results based on characterization and/or production test, not TCSensor or VOffset, sensor.
Measured with fSD16 = 1MHz, SD16OSRx = 256, SD16REFON = 1.
MSP430F47x3, MSP430F47x4
MIXED SIGNAL MICROCONTROLLER
SLAS545C − MAY 2007 − REVISED MARCH 2011
50 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
SD16_A, built-in voltage reference
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
VREF
Internal reference
voltage SD16REFON = 1, SD16VMIDON = 0 3 V 1.14 1.20 1.26 V
IREF
Reference supply
current SD16REFON = 1, SD16VMIDON = 0 3 V 175 260 μA
TC Temperature coefficient SD16REFON = 1, SD16VMIDON = 0 (see Note 1) 3 V 18 50 ppm/K
CREF VREF load capacitance SD16REFON = 1, SD16VMIDON = 0 (see Note 2) 100 nF
ILOAD
VREF(I) maximum load
current SD16REFON = 1, SD16VMIDON = 0 3 V ±200 nA
tON Turn on time SD16REFON = 0−>1, SD16VMIDON = 0,
CREF = 100nF 3 V 5 ms
DC PSR DC Power Supply
Rejection ΔVREF/ΔVCC
SD16REFON = 1, SD16VMIDON = 0,
VCC = 2.5V - 3.6V 100 uV/V
NOTES: 1. Calculated using the box method: (MAX(-40...85°C) − MIN(-40...85°C)) / MIN(−40...85°C) / (85°C − (-40°C))
2. There is no capacitance required on VREF
. However, a capacitance of at least 100nF is recommended to reduce any reference
voltage noise.
SD16_A, reference output buffer
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
VREF, BUF
Reference buffer output
voltage SD16REFON = 1, SD16VMIDON = 1 3 V 1.2 V
IREF, BUF
Reference Supply +
Reference output buffer
quiescent current
SD16REFON = 1, SD16VMIDON = 1 3 V 385 600 μA
CREF(O)
Required load
capacitance on VREF SD16REFON = 1, SD16VMIDON = 1 470 nF
ILOAD, Max
Maximum load current
on VREF SD16REFON = 1, SD16VMIDON = 1 3 V ±1 mA
Maximum voltage
variation vs. load current |ILOAD| = 0 to 1mA 3 V −15 +15 mV
tON Turn on time SD16REFON = 0−>1, SD16VMIDON = 0−>1,
CREF = 470nF 3 V 100 μs
SD16_A, external reference input
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
VREF(I) Input voltage range SD16REFON = 0 3 V 1.0 1.25 1.5 V
IREF(I) Input current SD16REFON = 0 3 V 50 nA
MSP430F47x3, MSP430F47x4
MIXED SIGNAL MICROCONTROLLER
SLAS545C − MAY 2007 − REVISED MARCH 2011
51
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
flash memory
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
VCC(PGM/
ERASE) Program and Erase supply voltage 2.2 3.6 V
fFTG Flash Timing Generator frequency 257 476 kHz
IPGM Supply current from VCC during program 2.2 V/3.6 V 3 5 mA
IERASE Supply current from VCC during erase 2.2 V/3.6 V 3 7 mA
tCPT Cumulative program time (see Note 1) 2.2 V/3.6 V 10 ms
tCMErase Cumulative mass erase time 2.2 V/3.6 V 20 ms
Program/Erase endurance 104105cycles
tRetention Data retention duration TJ = 25°C 100 years
tWord Word or byte program time 30
tBlock, 0Block program time for 1st byte or word 25
tBlock, 1-63 Block program time for each additional byte or word
see Note 2
18
t
tBlock, End Block program end-sequence wait time see Note 2 6tFTG
tMass Erase Mass erase time 10593
tSeg Erase Segment erase time 4819
NOTES: 1. The cumulative program time must not be exceeded when writing to a 64-byte flash block. This parameter applies to all programming
methods: individual word/byte write and block write modes.
2. These values are hardwired into the Flash Controller’s state machine (tFTG = 1/fFTG).
RAM
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V(RAMh) RAM retention supply voltage (see Note 1) CPU halted 1.6 V
NOTE 1: This parameter defines the minimum supply voltage VCC when the data in RAM remains unchanged. No program execution should
happen during this supply voltage condition.
JTAG interface
PARAMETER TEST
CONDITIONS VCC MIN NOM MAX UNIT
f
TCK input frequency
see Note 1
2.2 V 0 5 MHz
fTCK TCK input frequency see Note 1 3 V 0 10 MHz
RInternal Internal pull-up resistance on TMS, TCK, TDI/TCLK see Note 2 2.2 V/ 3 V 20 35 50 kΩ
NOTES: 1. fTCK may be restricted to meet the timing requirements of the module selected.
2. TMS, TDI/TCLK, and TCK pull-up resistors are implemented in all versions.
JTAG fuse (see Note 1)
PARAMETER TEST
CONDITIONS VCC MIN MAX UNIT
VCC(FB) Supply voltage during fuse-blow condition TA = 25°C 2.5 V
VFB Voltage level on TDI/TCLK for fuse-blow: F versions 6 7 V
IFB Supply current into TDI/TCLK during fuse blow 100 mA
tFB Time to blow fuse 1 ms
NOTES: 1. Once the fuse is blown, no further access to the MSP430 JTAG/Test and emulation features is possible. The JTAG block is switched
to bypass mode.
MSP430F47x3, MSP430F47x4
MIXED SIGNAL MICROCONTROLLER
SLAS545C − MAY 2007 − REVISED MARCH 2011
52 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
Port P1, P1.0 to P1.5, input/output with Schmitt trigger
Bus
Keeper
EN
Direction
0: Input
1: Output
P1SEL.x
1
0
P1DIR.x
P1IN.x
P1IRQ.x
D
EN
Module X IN
1
0
Module X OUT
P1OUT.x
Interrupt
Edge
Select
Q
EN
Set
P1SEL.x
P1IES.x
P1IFG.x
P1IE.x
P1.0/TA0
P1.1/TA0/MCLK
P1.2/TA1
P1.3/TBOUTH/SVSOUT
P1.4/TBCLK/SMCLK
P1.5/TACLK/ACLK
1
0
DVSS
DVCC
P1REN.x
CAPD.x
Pad Logic
DVSS
DVSS
1
MSP430F47x3, MSP430F47x4
MIXED SIGNAL MICROCONTROLLER
SLAS545C − MAY 2007 − REVISED MARCH 2011
53
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Port P1 (P1.0 to P1.5) pin functions
PIN NAME (P1 X)
X
FUNCTION
CONTROL BITS / SIGNALS
PIN NAME (P1.X) X FUNCTION P1DIR.x P1SEL.x CAPD.x
P1.0/TA0 0 P1.0 (I/O) I: 0, O: 1 0 0
Timer_A3.CCI0A 0 1 0
Timer_A3.TA0 1 1 0
Input buffer disabled (see Note 2) X X 1
P1.1/TA0/MCLK 1 P1.1 (I/O) I: 0, O: 1 0 0
Timer_A3.CCI0B 0 1 0
MCLK 1 1 0
Input buffer disabled (see Note 2) X X 1
P1.2/TA1 2 P1.2 (I/O) I: 0, O: 1 0 0
Timer_A3.CCI1A 0 1 0
Timer_A3.TA1 1 1 0
Input buffer disabled (see Note 2) X X 1
P1.3/ 3 P1.3 (I/O) I: 0, O: 1 0 0
TBOUTH/SVSOUT Timer_B7.TBOUTH 0 1 0
SVSOUT 1 1 0
Input buffer disabled (see Note 2) X X 1
P1.4/TBCLK/SMCLK 4 P1.4 (I/O) I: 0, O: 1 0 0
Timer_B7.TBCLK 0 1 0
SMCLK 1 1 0
Input buffer disabled (see Note 2) X X 1
P1.5/TACLK/ACLK 5 P1.5 (I/O) I: 0, O: 1 0 0
Timer_A3.TACLK 0 1 0
ACLK 1 1 0
Input buffer disabled (see Note 2) X X 1
NOTES: 1. X: Don’t care.
2. Setting the CAPD.x bit disables the output driver as well as the input schmitt trigger to prevent parasitic cross currents when applying
analog signals.
MSP430F47x3, MSP430F47x4
MIXED SIGNAL MICROCONTROLLER
SLAS545C − MAY 2007 − REVISED MARCH 2011
54 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Port P1, P1.6, P1.7, input/output with Schmitt trigger
Bus
Keeper
EN
Direction
0: Input
1: Output
P1SEL.x
1
0
P1DIR.x
P1IN.x
P1IRQ.x
D
EN
Module X IN
1
0
Module X OUT
P1OUT.x
Interrupt
Edge
Select
Q
EN
Set
P1SEL.x
P1IES.x
P1IFG.x
P1IE.x
P1.6/CA0
P1.7/CA1
1
0
DVSS
DVCC
P1REN.x
CAPD.x
Pad Logic
From Comparator_A
To Comparator_A
1
Port P1 (P1.6 and P1.7) pin functions
PIN NAME (P1 X)
X
FUNCTION
CONTROL BITS / SIGNALS
PIN NAME (P1.X) X FUNCTION P1DIR.x P1SEL.x CAPD.x
P1.6/CA0 6 P1.6 (I/O) I: 0, O: 1 0 0
CA0 (see Note 2) X X 1
P1.7/CA1 7 P1.7 (I/O) I: 0, O: 1 0 0
CA1 (see Note 2) X X 1
NOTES: 1. X: Don’t care.
2. Setting the CAPD.x bit disables the output driver as well as the input schmitt trigger to prevent parasitic cross currents when applying
analog signals.
MSP430F47x3, MSP430F47x4
MIXED SIGNAL MICROCONTROLLER
SLAS545C − MAY 2007 − REVISED MARCH 2011
55
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
port P2, P2.0, P2.6 to P2.7, input/output with Schmitt trigger
Bus
Keeper
EN
Direction
0: Input
1: Output
P2SEL.x
1
0
P2DIR.x
P2IN.x
P2IRQ.x
D
EN
Module X IN
1
0
Module X OUT
P2OUT.x
Interrupt
Edge
Select
Q
EN
Set
P2SEL.x
P2IES.x
P2IFG.x
P2IE.x
P2.0/TA2
P2.6/CAOUT
P2.7
1
0
DVSS
DVCC
P2REN.x
DVSS
1
Port P2 (P2.0, P2.6 and P2.7) pin functions
PIN NAME (P2 X)
X
FUNCTION
CONTROL BITS / SIGNALS
PIN NAME (P2.X) X FUNCTION P2DIR.x P2SEL.x
P2.0/TA2 0 P2.0 (I/O) I: 0, O: 1 0
Timer_A3.CCI2A 0 1
Timer_A3.TA2 1 1
P2.6/CAOUT 6 P2.6 (I/O) I: 0, O: 1 0
N/A 0 1
CAOUT 1 1
P2.7 7 P2.7 (I/O) I: 0, O: 1 0
N/A 0 1
DVSS 1 1
NOTES: 1. N/A: Not available or not applicable
2. Setting TBOUTH causes all Timer_B outputs to be set to high impedance.
MSP430F47x3, MSP430F47x4
MIXED SIGNAL MICROCONTROLLER
SLAS545C − MAY 2007 − REVISED MARCH 2011
56 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
port P2, P2.1 to P2.3, input/output with Schmitt trigger
Bus
Keeper
EN
Direction
0: Input
1: Output
P2SEL.x
1
0
P2DIR.x
P2IN.x
P2IRQ.x
D
EN
Module X IN
1
0
Module X OUT
P2OUT.x
Interrupt
Edge
Select
Q
EN
Set
P2SEL.x
P2IES.x
P2IFG.x
P2IE.x
P2.1/TB0
P2.2/TB1
P2.3/TB2
1
0
DVSS
DVCC
P2REN.x
1
P1DIR.3
P1SEL.3
P1.3/TBOUTH/SVSOUT
Timer_B Output Tristate Logic
Port P2 (P2.1 to P2.3) pin functions
PIN NAME (P2 X)
X
FUNCTION
CONTROL BITS / SIGNALS
PIN NAME (P2.X) X FUNCTION P2DIR.x P2SEL.x
P2.1/TB0 1 P2.1 (I/O) I: 0, O: 1 0
Timer_B7.CCI0A and Timer_B7.CCI0B 0 1
Timer_B7.TB0 (see Note 2) 1 1
P2.2/TB1 2 P2.2 (I/O) I: 0, O: 1 0
Timer_B7.CCI1A and Timer_B7.CCI1B 0 1
Timer_B7.TB1 (see Note 2) 1 1
P2.3/TB3 3 P2.3 (I/O) I: 0, O: 1 0
Timer_B7.CCI2A and Timer_B7.CCI2B 0 1
Timer_B7.TB3 (see Note 2) 1 1
NOTES: 1. N/A: Not available or not applicable
2. Setting TBOUTH causes all Timer_B outputs to be set to high impedance.
MSP430F47x3, MSP430F47x4
MIXED SIGNAL MICROCONTROLLER
SLAS545C − MAY 2007 − REVISED MARCH 2011
57
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
port P2, P2.4 to P2.5, input/output with Schmitt trigger
Bus
Keeper
EN
Direction
0: Input
1: Output
P2SEL.x
1
0
P2DIR.x
P2IN.x
P2IRQ.x
D
EN
Module X IN
1
0
Module X OUT
P2OUT.x
Interrupt
Edge
Select
Q
EN
Set
P2SEL.x
P2IES.x
P2IFG.x
P2IE.x
P2.4/UCA0TXD/UCA0SIMO
P2.5/UCA0RXD/UCA0SOMI
1
0
DVSS
DVCC
P2REN.x
1
DVSS
USCI Direction
Control
Port P2 (P2.4 and P2.5) pin functions
PIN NAME (P2 X)
X
FUNCTION
CONTROL BITS / SIGNALS
PIN NAME (P2.X) X FUNCTION P2DIR.x P2SEL.x
P2.4/ 4 P2.4 (I/O) I: 0, O: 1 0
UCA0TXD/UCA0SIMO UCA0TXD/UCA0SIMO (see Note 1, 2) X 1
P2.5/ 5 P2.5 (I/O) I: 0, O: 1 0
UCA0RXD/UCA0SOMI UCA0RXD/UCA0SOMI (see Note 1, 2) X 1
NOTES: 1. X: Don’t care.
2. The pin direction is controlled by the USCI module.
MSP430F47x3, MSP430F47x4
MIXED SIGNAL MICROCONTROLLER
SLAS545C − MAY 2007 − REVISED MARCH 2011
58 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
port P3, P3.0 to P3.3, input/output with Schmitt trigger
Bus
Keeper
EN
Direction
0: Input
1: Output
P3SEL.x
1
0
P3DIR.x
P3IN.x
D
EN
Module X IN
1
0
Module X OUT
P3OUT.x
P3.0/UCB0STE/UCA0CLK
P3.1/UCB0SIMO/UCB0SDA
P3.2/UCB0SOMI/UCB0SCL
P3.3/UCB0CLK/UCA0STE
1
0
DVSS
DVCC
P3REN.x
Pad Logic
1
USCI Direction
Control
DVSS
Port P3 (P3.0 to P3.3) pin functions
PIN NAME (P3 X)
X
FUNCTION
CONTROL BITS / SIGNALS
PIN NAME (P3.X) X FUNCTION P3DIR.x P3SEL.x
P3.0/ 0 P3.0 (I/O) I: 0, O: 1 0
UCA0CLK/UCB0STE UCA0CLK/UCB0STE (see Notes 1, 2, 3) X 1
P3.1/
UCB0SIMO/
1P3.1 (I/O) I: 0, O: 1 0
U
C
B0
S
IM
O/
UCB0SDA UCB0SIMO/UCB0SDA (see Notes 1, 2, 4) X 1
P3.2/
UCB0SOMI/
2P3.2 (I/O) I: 0, O: 1 0
U
C
B0
SO
MI
/
UCB0SCL UCB0SOMI/UCB0SCL (see Notes 1, 2, 4) X 1
P3.3/ 3 P3.3 (I/O) I: 0, O: 1 0
UCB0CLK/UCA0STE UCB0CLK (see Notes 1, 2, 5) X 1
NOTES: 1. X: Don’t care.
2. The pin direction is controlled by the USCI module.
3. UCA0CLK function takes precedence over UCB0STE function. If the pin is required as UCA0CLK input or output USCI_B0 will be
forced to 3-wire SPI mode even if 4-wire SPI mode is selected.
4. In case the I2C functionality is selected the output drives only the logical 0 to VSS level.
5. UCB0CLK function takes precedence over UCA0STE function. If the pin is required as UCB0CLK input or output USCI_A0 will be
forced to 3-wire SPI mode even if 4-wire SPI mode is selected.
MSP430F47x3, MSP430F47x4
MIXED SIGNAL MICROCONTROLLER
SLAS545C − MAY 2007 − REVISED MARCH 2011
59
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
port P3, P3.4 to P3.7, input/output with Schmitt trigger
Bus
Keeper
EN
Direction
0: Input
1: Output
P3SEL.x
1
0
P3DIR.x
P3IN.x
D
EN
Module X IN
1
0
Module X OUT
P3OUT.x
P3.4
P3.5
P3.6
P3.7
1
0
DVSS
DVCC
P3REN.x
Pad Logic
1
DVSS
Port P3 (P3.4 to P3.7) pin functions
PIN NAME (P3 X)
X
FUNCTION
CONTROL BITS / SIGNALS
PIN NAME (P3.X) X FUNCTION P3DIR.x P3SEL.x
P3.4 4 P3.4 (I/O) I: 0, O: 1 0
N/A 0 1
DVSS 1 1
P3.5 5 P3.5 (I/O) I: 0, O: 1 0
N/A 0 1
DVSS 1 1
P3.6 6 P3.6 (I/O) I: 0, O: 1 0
N/A 0 1
DVSS 1 1
P3.7 7 P3.7 (I/O) I: 0, O: 1 0
N/A 0 1
DVSS 1 1
MSP430F47x3, MSP430F47x4
MIXED SIGNAL MICROCONTROLLER
SLAS545C − MAY 2007 − REVISED MARCH 2011
60 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
port P4, P4.0 to P4.1, input/output with Schmitt trigger
Bus
Keeper
EN
Direction
0: Input
1: Output
P4SEL.x
1
0
P4DIR.x
P4IN.x
D
EN
Module X IN
1
0
Module X OUT
P4OUT.x
P4.0/UCA1TXD/UCA1SIMO
P4.1/UCA1RXD/UCA1SOMI
1
0
DVSS
DVCC
P4REN.x
Pad Logic
1
USCI Direction
Control
DVSS
Port P4 (P4.0 to P4.1) pin functions
PIN NAME (P4 X)
X
FUNCTION
CONTROL BITS / SIGNALS
PIN NAME (P4.X) X FUNCTION P4DIR.x P4SEL.x
P4.0/ 0 P4.0 (I/O) I: 0, O: 1 0
UCA1TXD/UCA1SIMO UCA1TXD/UCA1SIMO (see Notes 1, 2) X 1
P4.1/ 1 P4.1 (I/O) I: 0, O: 1 0
UCA1RXD/UCA1SOMI UCA1RXD/UCA1SOMI (see Notes 1, 2) X 1
NOTES: 1. X: Don’t care.
2. The pin direction is controlled by the USCI module.
MSP430F47x3, MSP430F47x4
MIXED SIGNAL MICROCONTROLLER
SLAS545C − MAY 2007 − REVISED MARCH 2011
61
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
port P4, P4.2 to P4.5, input/output with Schmitt trigger
Bus
Keeper
EN
Direction
0: Input
1: Output
P4SEL.x
1
0
P4DIR.x
P4IN.x
D
EN
Module X IN
1
0
Module X OUT
P4OUT.x
P4.2/UCB1STE/UCA1CLK/S39
P4.3/UCB1SIMO/UCB1SDA/S38
P4.4/UCB1SOMI/UCB1SCL/S37
P4.5/UCB1CLK/UCA1STE/S36
1
0
DVSS
DVCC
P4REN.x
Pad Logic
LCDS...
Segment Sz
1
USCI Direction
Control
Port P4 (P4.2 to P4.5) pin functions
PIN NAME (P4 X)
X
FUNCTION
CONTROL BITS / SIGNALS
PIN NAME (P4.X) X FUNCTION P4DIR.x P4SEL.x LCDS36
P4.2/ 2 P4.2 (I/O) I: 0, O: 1 0 0
UCA1CLK/UCB1STE/
S39
UCA1CLK/UCB1STE (see Notes 2, 3) X 1 0
S39 S39 X X 1
P4.3/ 3 P4.3 (I/O) I: 0, O: 1 0 0
UCB1SIMO/UCB1SDA/
S38
UCB1SIMO/UCB1SDA (see Notes 2, 4) X 1 0
S38 S38 X X 1
P4.4/ 4 P4.4 (I/O) I: 0, O: 1 0 0
UCB1SOMI/UCB1SCL/
S37
UCB1SOMI/UCB1SCL (see Notes 2, 4) X 1 0
S37 S37 X X 1
P4.5/ 5 P4.5 (I/O) I: 0, O: 1 0 0
UCB1CLK/UCA1STE/
S36
UCB1CLK/UCA1STE (see Notes 2, 5) X 1 0
S36 S36 X X 1
NOTES: 1. X: Don’t care.
2. The pin direction is controlled by the USCI module.
3. UCA1CLK function takes precedence over UCB1STE function. If the pin is required as UCA1CLK input or output USCI_B1 will be
forced to 3-wire SPI mode even if 4-wire SPI mode is selected.
4. In case the I2C functionality is selected the output drives only the logical 0 to VSS level.
5. UCB1CLK function takes precedence over UCA1STE function. If the pin is required as UCB1CLK input or output USCI_A1 will be
forced to 3-wire SPI mode even if 4-wire SPI mode is selected.
MSP430F47x3, MSP430F47x4
MIXED SIGNAL MICROCONTROLLER
SLAS545C − MAY 2007 − REVISED MARCH 2011
62 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
port P4, P4.6 to P4.7, input/output with Schmitt trigger
Bus
Keeper
EN
Direction
0: Input
1: Output
P4SEL.x
1
0
P4DIR.x
P4IN.x
D
EN
Module X IN
1
0
Module X OUT
P4OUT.x
P4.6/S35
P4.7/S34
1
0
DVSS
DVCC
P4REN.x
Pad Logic
LCDS...
Segment Sz
1
Port P4 (P4.6 to P4.7) pin functions
PIN NAME (P4 X)
X
FUNCTION
CONTROL BITS / SIGNALS
PIN NAME (P4.X) X FUNCTION P4DIR.x P4SEL.x LCDS32
P4.6/S35 6 P4.6 (I/O) I: 0, O: 1 0 0
S35 X X 1
P4.7/S34 7 P4.7 (I/O) I: 0, O: 1 0 0
S34 X X 1
NOTES: 1. X: Don’t care.
MSP430F47x3, MSP430F47x4
MIXED SIGNAL MICROCONTROLLER
SLAS545C − MAY 2007 − REVISED MARCH 2011
63
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
port P5, P5.0, input/output with Schmitt trigger
Bus
Keeper
EN
Direction
0: Input
1: Output
P5SEL.x
1
0
P5DIR.x
P5IN.x
1
0
DVSS
P5OUT.x
P5.0/SVSIN
1
0
DVSS
DVCC
P5REN.x
Pad Logic
To SVS
1
Port P5 (P5.0) pin functions
PIN NAME (P5 X)
X
FUNCTION
CONTROL BITS / SIGNALS
PIN NAME (P5.X) X FUNCTION P5DIR.x P5SEL.x
P5.0/SVSIN 0 P5.0 (I/O) (see Note 1) I: 0, O: 1 0
SVSIN (see Notes 1, 3) X 1
NOTES: 1. X: Don’t care.
2. N/A: Not available or not applicable.
3. Setting the P5SEL.x bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
MSP430F47x3, MSP430F47x4
MIXED SIGNAL MICROCONTROLLER
SLAS545C − MAY 2007 − REVISED MARCH 2011
64 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
port P5, P5.1, input/output with Schmitt trigger
Bus
Keeper
EN
Direction
0: Input
1: Output
P5SEL.1
1
0
P5DIR.1
P5IN.1
D
EN
Module X IN
1
0
Module X OUT
P5OUT.1
P5.1/S0
1
0
DVSS
DVCC
P5REN.1
Pad Logic
LCDS0
Segment S0
1
Port P5 (P5.1) pin functions
PIN NAME (P5 X)
X
FUNCTION
CONTROL BITS / SIGNALS
PIN NAME (P5.X) X FUNCTION P5DIR.x P5SEL.x LCDS0
P5.1/S0 1 P5.1 (I/O) I: 0, O: 1 0 0
N/A 0 1 0
DVSS 1 1 0
S0 X X 1
NOTES: 1. X: Don’t care.
2. N/A: Not available or not applicable.
MSP430F47x3, MSP430F47x4
MIXED SIGNAL MICROCONTROLLER
SLAS545C − MAY 2007 − REVISED MARCH 2011
65
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
port P5, P5.2 to P5.7, input/output with Schmitt trigger
Bus
Keeper
EN
Direction
0: Input
1: Output
P5SEL.x
1
0
P5DIR.x
P5IN.x
1
0
DVSS
P5OUT.x
P5.2/COM1
P5.3/COM2
P5.4/COM3
P5.5/R03
P5.6/LCDREF/R13
P5.7/R23
1
0
DVSS
DVCC
P5REN.x
Pad Logic
LCD Signal
1
Port P5 (P5.2 to P5.4) pin functions
PIN NAME (P5 X)
X
FUNCTION
CONTROL BITS / SIGNALS
PIN NAME (P5.X) X FUNCTION P5DIR.x P5SEL.x
P5.2/COM1 2 P5.2 (I/O) I: 0, O: 1 0
COM1 (see Note 2) X 1
P5.3/COM2 3 P5.3 (I/O) I: 0, O: 1 0
COM2 (see Note 2) X 1
P5.4/COM3 4 P5.4 (I/O) I: 0, O: 1 0
COM3 (see Note 2) X 1
P5.5/R03 5 P5.5 (I/O) I: 0, O: 1 0
R03 (see Note 2) X 1
P5.6/LCDREF/R13 6 P5.6 (I/O) I: 0, O: 1 0
R13 or LCDREF (see Notes 2, 3) X 1
P5.7/R23 7 P5.7 (I/O) I: 0, O: 1 0
R23 (see Note 2) X 1
NOTES: 1. X: Don’t care.
2. Setting the P5SEL.x bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
3. External reference for the LCD_A charge pump is applied when VLCDREFx = 01. Otherwise R13 is selected.
MSP430F47x3, MSP430F47x4
MIXED SIGNAL MICROCONTROLLER
SLAS545C − MAY 2007 − REVISED MARCH 2011
66 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
port P7 to port P10, input/output with Schmitt trigger
Bus
Keeper
EN
Direction
0: Input
1: Output
PySEL.x
1
0
PyDIR.x
PyIN.x
D
EN
Module X IN
1
0
Module X OUT
PyOUT.x
Py.x/Sz
1
0
DVSS
DVCC
PyREN.x
Pad Logic
LCDS...
Segment Sz
1
MSP430F47x3, MSP430F47x4
MIXED SIGNAL MICROCONTROLLER
SLAS545C − MAY 2007 − REVISED MARCH 2011
67
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Port P7 (P7.0 to P7.1) pin functions
PIN NAME (P7 X)
X
FUNCTION
CONTROL BITS / SIGNALS
PIN NAME (P7.X) X FUNCTION P7DIR.x P7SEL.x LCDS32
P7.0/S33 0 P7.0 (I/O) I: 0, O: 1 0 0
S33 X X 1
P7.1/S32 1 P7.1 (I/O) I: 0, O: 1 0 0
S32 X X 1
NOTES: 1. X: Don’t care.
Port P7 (P7.4 to P7.5) pin functions
PIN NAME (P7 X)
X
FUNCTION
CONTROL BITS / SIGNALS
PIN NAME (P7.X) X FUNCTION P7DIR.x P7SEL.x LCDS28
P7.2/S31 2 P7.2 (I/O) I: 0, O: 1 0 0
S31 X X 1
P7.3/S30 3 P7.3 (I/O) I: 0, O: 1 0 0
S30 X X 1
P7.4/S29 4 P7.4 (I/O) I: 0, O: 1 0 0
S29 X X 1
P7.5/S28 5 P7.5 (I/O) I: 0, O: 1 0 0
S28 X X 1
NOTES: 1. X: Don’t care.
Port P7 (P7.6 to P7.7) pin functions
PIN NAME (P7 X)
X
FUNCTION
CONTROL BITS / SIGNALS
PIN NAME (P7.X) X FUNCTION P7DIR.x P7SEL.x LCDS24
P7.6/S27 6 P7.6 (I/O) I: 0, O: 1 0 0
S27 X X 1
P7.7/S26 7 P7.7 (I/O) I: 0, O: 1 0 0
S26 X X 1
NOTES: 1. X: Don’t care.
MSP430F47x3, MSP430F47x4
MIXED SIGNAL MICROCONTROLLER
SLAS545C − MAY 2007 − REVISED MARCH 2011
68 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Port P8 (P8.0 to P8.1) pin functions
PIN NAME (P8 X)
X
FUNCTION
CONTROL BITS / SIGNALS
PIN NAME (P8.X) X FUNCTION P8DIR.x P8SEL.x LCDS24
P8.0/S25 0 P8.0 (I/O) I: 0, O: 1 0 0
S25 X X 1
P8.1/S24 1 P8.0 (I/O) I: 0, O: 1 0 0
S24 X X 1
NOTES: 1. X: Don’t care.
Port P8 (P8.2 to P8.5) pin functions
PIN NAME (P8 X)
X
FUNCTION
CONTROL BITS / SIGNALS
PIN NAME (P8.X) X FUNCTION P8DIR.x P8SEL.x LCDS20
P8.2/S23 2 P8.2 (I/O) I: 0, O: 1 0 0
S23 X X 1
P8.3/S22 3 P8.3 (I/O) I: 0, O: 1 0 0
S22 X X 1
P8.4/S21 4 P8.4 (I/O) I: 0, O: 1 0 0
S21 X X 1
P8.5/S20 5 P8.5 (I/O) I: 0, O: 1 0 0
S23 X X 1
NOTES: 1. X: Don’t care.
Port P8 (P8.6 to P8.7) pin functions
PIN NAME (P8 X)
X
FUNCTION
CONTROL BITS / SIGNALS
PIN NAME (P8.X) X FUNCTION P8DIR.x P8SEL.x LCDS16
P8.6/S19 6 P8.6 (I/O) I: 0, O: 1 0 0
S19 X X 1
P8.7/S18 7 P8.7 (I/O) I: 0, O: 1 0 0
S18 X X 1
NOTES: 1. X: Don’t care.
MSP430F47x3, MSP430F47x4
MIXED SIGNAL MICROCONTROLLER
SLAS545C − MAY 2007 − REVISED MARCH 2011
69
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Port P9 (P9.0 to P9.1) pin functions
PIN NAME (P9 X)
X
FUNCTION
CONTROL BITS / SIGNALS
PIN NAME (P9.X) X FUNCTION P9DIR.x P9SEL.x LCDS16
P9.0/S17 0 P9.0 (I/O) I: 0, O: 1 0 0
S17 (see Note 1) X X 1
P9.1/S16 1 P9.1 (I/O) I: 0, O: 1 0 0
S16 (see Note 1) X X 1
NOTES: 1. X: Don’t care.
Port P9 (P9.2 to P9.5) pin functions
PIN NAME (P9 X)
X
FUNCTION
CONTROL BITS / SIGNALS
PIN NAME (P9.X) X FUNCTION P9DIR.x P9SEL.x LCDS12
P9.2/S15 2 P9.2 (I/O) I: 0, O: 1 0 0
S15 X X 1
P9.3/S14 3 P9.3 (I/O) I: 0, O: 1 0 0
S14 X X 1
P9.4/S13 4 P9.4 (I/O) I: 0, O: 1 0 0
S13 X X 1
P9.5/S12 5 P9.5 (I/O) I: 0, O: 1 0 0
S12 X X 1
NOTES: 1. X: Don’t care.
Port P9 (P9.6 to P9.7) pin functions
PIN NAME (P9 X)
X
FUNCTION
CONTROL BITS / SIGNALS
PIN NAME (P9.X) X FUNCTION P9DIR.x P9SEL.x LCDS8
P9.6/S11 6 P9.6 (I/O) I: 0, O: 1 0 0
S11 X X 1
P9.7/S10 7 P9.7 (I/O) I: 0, O: 1 0 0
S10 X X 1
NOTES: 1. X: Don’t care.
MSP430F47x3, MSP430F47x4
MIXED SIGNAL MICROCONTROLLER
SLAS545C − MAY 2007 − REVISED MARCH 2011
70 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Port P10 (P10.0 to P10.1) pin functions
PIN NAME (P10 X)
X
FUNCTION
CONTROL BITS / SIGNALS
PIN NAME (P10.X) X FUNCTION P10DIR.x P10SEL.x LCDS8
P10.0/S8 0 P10.0 (I/O) I: 0, O: 1 0 0
S8 X X 1
P10.1/S7 1 P10.1 (I/O) I: 0, O: 1 0 0
S7 X X 1
NOTES: 1. X: Don’t care.
Port P10 (P10.2 to P10.5) pin functions
PIN NAME (P10 X)
X
FUNCTION
CONTROL BITS / SIGNALS
PIN NAME (P10.X) X FUNCTION P10DIR.x P10SEL.x LCDS4
P10.2/S7 2 P10.2 (I/O) I: 0, O: 1 0 0
S7 X X 1
P10.3/S6 3 P10.3 (I/O) I: 0, O: 1 0 0
S6 X X 1
P10.4/S5 4 P10.4 (I/O) I: 0, O: 1 0 0
S5 X X 1
P10.5/S4 5 P10.5 (I/O) I: 0, O: 1 0 0
S4 X X 1
NOTES: 1. X: Don’t care.
Port P10 (P10.6 to P10.7) pin functions
PIN NAME (P10 X)
X
FUNCTION
CONTROL BITS / SIGNALS
PIN NAME (P10.X) X FUNCTION P10DIR.x P10SEL.x LCDS0
P10.6/S3 6 P10.6 (I/O) I: 0, O: 1 0 0
S3 X X 1
P10.7/S2 7 P10.7 (I/O) I: 0, O: 1 0 0
S2 X X 1
NOTES: 1. X: Don’t care.
MSP430F47x3, MSP430F47x4
MIXED SIGNAL MICROCONTROLLER
SLAS545C − MAY 2007 − REVISED MARCH 2011
71
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
JTAG pins (TMS, TCK, TDI/TCLK, TDO/TDI), input/output with Schmitt trigger or output
TDI
TDO
TMS
TDI/TCLK
TDO/TDI
Controlled
by JTAG
TCK
TMS
TCK
DVCC
Controlled by JTAG
Test
JTAG
and
Emulation
Module
DVCC
DVCC
Burn and Test
Fuse
RST/NMI
G
D
S
U
G
D
S
U
TCK
Tau ~ 50 ns
Brownout
Controlled by JTAG
MSP430F47x3, MSP430F47x4
MIXED SIGNAL MICROCONTROLLER
SLAS545C − MAY 2007 − REVISED MARCH 2011
72 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
JTAG fuse check mode
Devices that have the fuse on the TDI/TCLK terminal have a fuse check mode that tests the continuity of the
fuse the first time the JTAG port is accessed after a power-on reset (POR). When activated, a fuse-check current
(I(TF) ) of 1 mA at 3 V can flow from the TDI/TCLK pin to ground if the fuse is not burned. Care must be taken
to avoid accidentally activating the fuse check mode and increasing overall system power consumption.
Activation of the fuse-check mode occurs with the first negative edge on the TMS pin after power up or if the
TMS is being held low during power up. The second positive edge on the TMS pin deactivates the fuse-check
mode. After deactivation, the fuse-check mode remains inactive until another POR occurs. After each POR the
fuse check mode has the potential to be activated.
The fuse check current only flows when the fuse check mode is active and the TMS pin is in a low state (see
Figure 27). Therefore, the additional current flow can be prevented by holding the TMS pin high (default
condition). The JTAG pins are terminated internally and, therefore, do not require external termination.
Time TMS Goes Low After POR
TMS
I(TF)
ITDI/TCLK
Figure 27. Fuse-Check Mode Current
MSP430F47x3, MSP430F47x4
MIXED SIGNAL MICROCONTROLLER
SLAS545C − MAY 2007 − REVISED MARCH 2011
73
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Data Sheet Revision History
Literature
Number Summary
SLAS545 PRODUCT PREVIEW data sheet
SLAS545A PRODUCTION DATA data sheet
SLAS545B
Section DEVELOPMENT TOOL SUPPORT added, page 2.
Split XT1 frequency ranges depending on supply voltage range, page 36.
Added parameter fLFXT1, LF, logic to LFXT1, low frequency modes characteristics, page 36.
SLAS545C Changed limits on td(SVSon) parameter (page 32)
NOTE: Page and figure numbers refer to the specified revision and may differ in other revisions.
PACKAGE OPTION ADDENDUM
www.ti.com 2-Apr-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
MSP430F4783IPZ ACTIVE LQFP PZ 100 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F4783IPZR ACTIVE LQFP PZ 100 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F4784IPZ ACTIVE LQFP PZ 100 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F4784IPZR ACTIVE LQFP PZ 100 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F4793IPZ ACTIVE LQFP PZ 100 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F4793IPZR ACTIVE LQFP PZ 100 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F4794IPZ ACTIVE LQFP PZ 100 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F4794IPZR ACTIVE LQFP PZ 100 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430F4794SNIPZ OBSOLETE LQFP PZ 100 TBD Call TI Call TI
MSP430F4794SNIPZR OBSOLETE LQFP PZ 100 TBD Call TI Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
PACKAGE OPTION ADDENDUM
www.ti.com 2-Apr-2012
Addendum-Page 2
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
MSP430F4783IPZR LQFP PZ 100 1000 330.0 24.4 17.4 17.4 2.0 20.0 24.0 Q2
MSP430F4784IPZR LQFP PZ 100 1000 330.0 24.4 17.4 17.4 2.0 20.0 24.0 Q2
MSP430F4793IPZR LQFP PZ 100 1000 330.0 24.4 17.4 17.4 2.0 20.0 24.0 Q2
MSP430F4794IPZR LQFP PZ 100 1000 330.0 24.4 17.4 17.4 2.0 20.0 24.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
MSP430F4783IPZR LQFP PZ 100 1000 367.0 367.0 45.0
MSP430F4784IPZR LQFP PZ 100 1000 367.0 367.0 45.0
MSP430F4793IPZR LQFP PZ 100 1000 367.0 367.0 45.0
MSP430F4794IPZR LQFP PZ 100 1000 367.0 367.0 45.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
MECHANICAL DATA
MTQF013A – OCTOBER 1994 – REVISED DECEMBER 1996
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PZ (S-PQFP-G100) PLASTIC QUAD FLATPACK
4040149/B 1 1/96
50
26 0,13 NOM
Gage Plane
0,25
0,45
0,75
0,05 MIN
0,27
51
25
75
1
12,00 TYP
0,17
76
100
SQ
SQ
15,80
16,20
13,80
1,35
1,45
1,60 MAX
14,20
0°–7°
Seating Plane
0,08
0,50 M
0,08
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
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