CY7C402-25LMB - Cypress Semiconductor

64 x 4 Cascadable FIFO

64 x 5 Cascadable FIFO

CY7C401/CY7C403

CY7C402/CY7C404

Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600

March 1986 - Revised Apr il 1995

Features

• 64 x 4 (CY7C401 and CY7C403)

64 x 5 (CY7C402 and CY7C404)

Hi g h -speed firs t-in firs t-out m emory (FI F O)

• Processed with hi gh-speed CMO S for optim um

speed/power

•25-MHz data rates

• 50-ns bubble- through tim e—2 5 MHz

• Exp andable in wor d width and/or length

• 5-v ol t power supply ± 10% tolerance, bo th commer ci al

and military

• Independent asynchronous inputs and outputs

• TTL- compatible interface

• Output enable function available on CY7C403 and

CY7C404

• Capable of withstanding greater than 2001V electrostat-

ic discharge

• Pin com patible wit h MMI 67401A/67402A

Functional Description

The CY7C401 and CY7C403 are asynchronous first-in

fi rst -out (FI FOs) organi zed as 64 fou r- bit word s. The CY7C402

and CY7C404 are similar FIFOs organized as 64 five-bit

words. Both the CY7C403 and CY7C404 have an output en-

able (OE) function.

The devices accept 4- or 5-bit words at the data input (DI0 –

DIn) under the control of the shift in (SI) input. The stored

words stack up at the output (DO0 – DOn) in the order they

were entered. A read command on the shift out (SO) input

causes th e ne xt to l ast wor d to mo ve to t he output and all dat a

shift s down once in the stack. The inpu t ready (IR) signal acts

as a fla g to i ndicate when the i nput is rea dy to accept ne w data

(HIGH), to indicat e when the FIF O is full (LO W), and t o provide

a sig nal for a cascadi ng. The out put r ead y (O R) si gnal i s a flag

to indicate the output contains valid data (HIGH), to indicate

the FIFO is empty (LOW), and to provide a signal for cascad-

ing.

Parallel expansion for wider words is accomplished by logically

ANDing the IR and OR sig nals to f orm compos it e signals .

Serial expansion is accomplished by tying the data inputs of

one device to the data outputs of the previous device. The IR

pin of the receiving device is connected to the SO pin of the

sending device, and the OR pin of the sending device is con-

nected to t he SI pin of the receiv ing device.

Reading and writi ng operation s are completely asynchronous ,

allowing the FIFO to be used as a buffer between two digital

machines of widely differing operating frequencies. The

25-MHz operation makes these FIFOs ideal for high-speed

communi cation and controller applicat ions.

CY7C402

CY7C404

Logic Block Diagram Pin Configurations

C401–1

C401–2

C401–3

(CY7C401) NC

(CY7C403) OE

DI0

DI1

VCC

DO0

DO1

DO3

DO2

DI2

DI3

GND

321 19

910111213

VCC

DI 0

DI 1

DI 2DO 0

DO 1

DO 2

GND

INPUT

CONTROL

LOGIC

DATAIN

DI0

DI1

DI2

DI3

(DI4)

MASTER

RESET

WRITE MULTIPLEXER

WRITE POINTER

READ MULTIPLEXER

READ POINTER

MEMORY

ARRAY

OUTPUT

CONTROL

LOGIC

DATAIN

OUTPUT

ENABLE OE

DO0

DO1

DO2

DO3

(DO4)

DI 0

DI 1

VCC

DO0

DO1

DO3

DO4

DO2

DI 2

DI3

DI4

CY7C401

CY7C403

(CY7C402) NC

(CY7C404) OE

910 MRGND

NC/OE

DI3

CY7C401

CY7C403

C401–4

321 19

910111213

VCC

GND

NC/OE

DI4

C401–5

DI 0

DI 1

DI 2

DO0

DO1

DO2

DO3

DI 3

CY7C402

CY7C404

LCC

DIP

LCC

DIP

Sele c tion Gu ide

7C401/2–5 7C40X–10 7C40X–15 7C40X–25

Operating Fr equency (MHz) 510 15 25

Maximum Operating

Current (mA) Commercial 75 75 75 75

Military 90 90 90

CY7C401/CY7C403

CY7C402/CY7C404

Maximum Ratings

(Above which the useful l ife may be impair ed. For user guide-

li nes, not tes ted.)

Storage Temperature ... .. ....... ....... ...... ....... .–65°C to +150°C

Ambient Temperature with

Power Applied.............................................–55°C to +125 °C

Supply Vo ltage to Ground Pot ential... ...... ......–0.5V to +7.0V

DC Voltage Appli ed to Outputs

in High Z State............................................... –0.5V to +7.0V

DC Input Voltage............................................ –3.0V to +7.0V

Power Dissip ation ..........................................................1.0W

Output Current, into Outputs (LO W)............................ 20 mA

Static Discharge Voltage ...... ......... ............. ...............>2001V

(per MIL- STD-883, Method 3015 )

Latch-Up Current.....................................................>200 mA

Operating Range

Range Ambient

Temperature VCC

Commercial 0°C to +70°C 5V ±10%

Military[1] –55°C to +125°C 5V ±10%

Electrical Characteristics Over the Operating Range (Unless Otherwi se Noted)[2]

7C40X–10, 1 5, 25

Parameter Description Test Conditions Min. Max. Unit

VOH Output HI GH Voltage VCC = Min., IOH = –4.0 mA 2.4 V

VOL O utput LOW Voltage VCC = Min., IOL = 8.0 mA 0.4 V

VIH Input HIGH Voltage 2.0 6.0 V

VIL Input LOW Voltage –3.0 0.8 V

IIX Input Leakage Current GND ≤ VI ≤ VCC –10 +10 µA

VCD[3] Input Di ode Clamp Voltage[3]

IOZ Outpu t Leakage Current GND ≤ VOUT ≤ VCC, VCC = 5.5V

Output Disabled (CY7C403 and CY7C404) –50 +50 µA

IOS Output Short Circuit Current[4] VCC = Max., VOUT = GND –90 mA

ICC Power Supply Current VCC = Max., IOUT = 0 mA Commercial 75 mA

Military 90 mA

Capacitance[5]

Parameter Description Test Conditions Max. Unit

CIN Input Capacitance TA = 25°C, f = 1 MHz,

VCC = 4.5V 5pF

COUT Output Capacitance 7pF

Notes:

1. TA is the “instant on” case temperature.

2. See the last page of this specification for Group A subgroup testing informati on.

3. The CMOS process does not provide a clamp diode. However, the FIFO is insensitive to –3V dc input levels and –5V undershoot pulses of less than 10 ns

(meas ured at 50% output).

4. For test purposes, not more than one output at a time should be shorted. Short circuit test duration should not exceed 30 seconds.

5. Tested initially and after any design or process changes that ma y affect these parameters.

CY7C401/CY7C403

CY7C402/CY7C404

AC Test Loads a nd Waveforms

C401–6 C401–7

90%

10%

3.0V

GND

90%

10%

ALL INPUT PULSES

OUTPUT

30 pF

INCLUDING

JIG AND

SCOPE

OUTPUT

5 pF

INCLUDING

JIG AND

SCOPE

(a) (b)

≤5ns ≤5ns

OUTPUT 1.73V C401–8

R1 437Ω

272ΩR2

272Ω

R1 437Ω

167Ω

Equivalent to: THÉ VENIN EQUIVALENT

Switching Charac teris t ics Ov er the Operat ing Range[2, 6]

Test

Conditions

7C401–5

7C402–5 7C40X–10 7C40X–15 7C40X–25[7]

Parameter Description Min. Max. Min. Max. Min. Max. Min. Max. Unit

fOOperating Frequency Note 8 510 15 25 MHz

tPHSI SI HI GH Time 20 20 20 11 ns

tPLSI SO LOW Time 45 30 25 20 ns

tSSI Da ta Set-Up to SI Note 9 0 0 0 0 ns

tHSI Data Hold from SI Note 9 60 40 30 20 ns

tDLIR Delay, SI HIGH to IR LOW 75 40 35 21/22 ns

tDHIR Delay, SI LOW to IR HIGH 75 45 40 28/30 ns

tPHSO SO HIGH Time 20 20 20 11 ns

tPLSO SO LOW Time 45 25 25 20 ns

tDLOR Delay, SO HIGH to OR LOW 75 40 35 19/21 ns

tDHOR Delay, SO LOW to OR HIGH 80 55 40 34/37 ns

tSOR Data Set-Up to OR HIGH 0 0 0 0 ns

tHSO Data Hold from SO LOW 5 5 5 5 ns

tBT Bub ble-Thr ough Time 200 10 95 10 65 10 50/60 ns

tSIR Data Set-Up to IR Note 10 5 5 5 5 ns

tHIR Data Hold from IR Note 10 30 30 30 20 ns

tPIR Input Ready Pulse HIGH 20 20 20 15 ns

tPOR Output Ready Pulse HIGH 20 20 20 15 ns

tPMR MR P uls e W idt h 40 30 25 25 ns

tDSI MR HIGH to SI HIGH 40 35 25 10 ns

tDOR MR LOW to OR LOW 85 40 35 35 ns

tDIR MR LOW to IR HIGH 85 40 35 35 ns

tLZMR MR LOW to Output LOW Note 11 50 40 35 25 ns

tOOE Outp ut Val id f rom O E LO W —35 30 20 ns

tHZOE Output High Z from OE HI GH Note 12 —30 25 15 ns

Notes:

6. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V and output loading of the specified IOL/IOH and 30- pF load

capacita nce, as i n part ( a) of AC Test Loa ds and Waveforms.

7. Commercial/Military

8. I/fO > tPHSI + tDHIR, I/fO > tPHSO + tDHOR

9. tSSI and tHSI apply when memory is not full.

10. tSIR and tHIR apply when memory is full, SI is high and minimum bubble-through (tBT) conditions exist.

11. All data outputs will be at LOW level after reset goes HIGH until data is entered i nto the FIFO.

12. HIGH-Z transiti ons are referenced to the steady-state VOH –500 mV and VOL +500 mV levels on the output. tHZOE is tested with 5-pF load capacitance as

in part (b) of AC Te st Loads and Wa veforms.

CY7C401/CY7C403

CY7C402/CY7C404

Operational Description

Concept

Unlike traditional FIFOs, these devices are designed using a

dual-port memory, read and write pointer, and control logic.

The r ead and writ e point ers a re in cremented b y the SO an d SI

respectiv ely. The avail ability of an empty space to shift in dat a

is i ndicated by the IR signal, whil e the prese nce of data at the

outpu t is indicated by t he OR signal. The conventi onal concept

of bubble-through is absent. Instead, the delay for input data

to appear at the output is the time requir ed to move a pointer

and propagate an OR signal. The output enable (OE ) sig nal

provides the c apability to OR tie multiple FIFOs together on

a com mo n bus.

Resetting the FIFO

Upon power-up, the FIFO must be reset with a master reset

(MR) si gnal. This causes the FIFO to enter an empty condi tion

signified by the OR signal be ing LOW at t he same time the IR

sign al i s HIGH. In this condition, the da ta out puts (DO0 – DO n)

will be in a LOW state.

Shift ing Data In

Data i s shi fted in on the risi ng ed ge of t he SI sig nal. This l oads

input data into the fi rs t word locat io n o f th e FIFO . On th e f allin g

edge of the SI signal, the write pointer is moved to the next

word position and the IR signal goes HIGH, indicating the

readiness to accept new data. If the FIFO is full, the IR will

remain LOW unti l a word of data is shifted out.

Shift ing Data Out

Data is shifted out of the FIFO on the falling edge of the SO

sign al. This causes the i nternal rea d p ointer to be advanced to

the n e xt wor d loca ti on. I f data is pre sent, v alid data wi ll ap pear

on the outputs and the OR signal will go HIGH. If data is not

present, the OR signal will stay LOW indicating the FIFO is

empty. Upon the rising edge of SO, the OR si gnal goes LOW.

The data outputs of the FIFO should be sampled with

edge-sensitive type D flip-flops (or equivalent), using the SO

signal as the clock input t o the flip-fl op.

Bubble-Through

Two bubble- through conditions exist. The first is when the de-

vice is empty. After a word is shifted into an empty devi ce, the

data propagat es to the out put. After a delay, the OR flag goes

HIGH, indicating valid data at the output.

The second bubble-through condition occ urs when the device

is full. Shif ting data out creates an empty location t hat propa-

gates to the input. After a delay, the IR flag goes HIGH. If the

SI signal is HIGH at this time, data on the input will be shifted

in.

Possible Minimum Pulse Width Violation at t he Boundary

Conditions

If t he handshak in g signal s IR and O R are not pr operly us ed to

generate the SI and SO signals, it is possible to violate the

mini mum (ef fe ctiv e) SI and SO positiv e pul se widt hs at the full

and empty boundaries.

When this vi olation occurs, the operati on o f the FIFO is unpre-

dictabl e. It must then be re set, and all data i s lost.

Applicat ion of the 7C403–25/7C404–25 at 25 MHz

Application of the CY7C403 or CY7C404 Cypress CMOS

FIFOs requires knowledge of characteristics that are not easily

specified in a datasheet, but which are necessary for reliable

operation under all conditions, so we will specify them her e.

When an empty FIFO is filled with initial information at m axi-

mum “sh ift in” SI frequ ency, fol lo wed b y immed iate sh ifti ng out

of the data also at maximum “s hift out” SO frequency, the de-

signer must be aware of a window of time which follows the

initial rising edge of the OR signal, during which time the SO

signal is not recognized. This condition exists only at

high-speed operation where m ore than one SO may be gen-

erated inside the prohibited window. This condition does not

inhibit the operation of the FIFO at full-frequency operation, but

rather delays the full 25-MHz operation until after the window

has passed.

There are several implementation techniques for managing

the windo w so that all SO signals are re cognized:

1. The fir st i nvolves del aying SO operati on such that it does

not occur in the critical window. This can be accomplished

by causing a f ixed delay of 40 ns “initi ated by t he SI signal

only when the FI FO is empty” to inhibit or gate the SO ac-

tivi ty. However, this r equires tha t th e SO operation be at

least tempor arily synchronized with the in put SI oper ation.

In synchronous applicati ons this m ay w ell be pos sible a nd

a valid solution.

2. Another solution not uncommon in synchronous applica-

tions is to only beg in shifting dat a out of the FIFO when it is

more than half full. This is a com mo n method of FIFO ap-

plic ation, as earlier FIFOs could not be operated at maxi-

mum f requenc y when near f ull or em pty. Alth ough Cypr ess

FIFOs do not have this lim itation, any system designed in

this manner will not encounter the window condi tion de-

scribed above.

3. The windo w ma y also be managed b y not allo win g the firs t

SO signal to occur until the window in question has passed.

This can be accomplished by delaying the SO 40 ns from

the rising edge of the initi al OR signal. This however in-

volves t he requir em ent t hat this only occurs o n the first oc-

curren ce of data being loaded i nto the FIFO from an empty

condition and therefore requires t he knowledge of IR and

SI conditions as well as SO.

4. Handshaki ng with the OR signal is a thir d method of a v oid -

ing the window in question. Wit h this technique the rising

edge of SO, or the fact that SO signal i s HIGH, will cause

the OR signal to go LO W. The SO signal is not tak en LO W

again, advancing the internal pointer to t he next data, until

the OR signal goes LOW. Thi s ensures that the SO pulse

that is initiated in the window will be automatically extended

long enough to be r ecognized.

5. There remains the decision as to what signal wi ll be used

to l atch t he data f rom the out put o f the FI FO int o the rece iv-

ing sourc e. The leadi ng edge of t he SO signal is most ap-

propria te because data is guaranteed to be stable prior to

and after the SO leading edge for each FIFO. This is a

solution for any number of FIFOs in parallel.

Any of the above solutions will ensure the correct oper ation of

a Cypress FI FO at 25 MH z. The s pecif ic impl ement ati on is l eft

to the designer and is dependent on the specific application

needs.

CY7C401/CY7C403

CY7C402/CY7C404

Switching Wavefor ms

Data In Timing Diagram

Data OutTiming Diagram

Bubble Through, Data Out To DataIn Diagram

C401–9

C401–10

C401–11

SHIFT IN

I/fOI/fO

tPHSI tPLSI tDHIR

tDLIR

INPUT READY

tHSI

tSSI

DATA IN

SHIFT OUT

I/fOI/fO

tPHSO tPLSO tDHOR

tDLOR

OUTPUT READY

tHSO

DATA OUT

tSOR

SHIFT IN

INPUT READY

DATA IN

SHIFT OUT

tBT

tPIR

tHIR

tSIR

CY7C401/CY7C403

CY7C402/CY7C404

Switching Wavefor ms (cont inued)

tHZOE

Bubble Through, Data In To Data Out Diagram

Master Reset Timing Diagram

Output Enable Timing Diagram

C401–12

C401–13

C401–14

SHIFT OUT

OUT PUT READY

DATA OUT

S HIFT IN

tBT tPOR

tSOR

INPUT READY

DATA OUT

SHIFT IN

tPMR

MASTER RESET tDIR

OUT PUT READY

tDOR

tDSI

tLZMR

OUT PUT ENABLE

DATA OUT

tOOE

NOTE 10

CY7C401/CY7C403

CY7C402/CY7C404

Typical DC and A C Characte ris ti cs

1.2

1.0

0.6

0.4

4.0 4.5 5.0 5.5 6.0

1.6

1.4

1.2

1.0

0.8

–55 25 125

1.4

1.0

0.8

0.0 1.0 2.0 3.0 4.0

OUTPUT SOURCE CURRENT (mA)

SUPPLY VOLTAGE(V)

NORMALIZED SUPPLY CURRENT

vs. SUPPLY VOLTAGE

NORMALIZED FREQUENCY

vs. AMBIENT TEMPERATURE

NORMALIZED SUPPLY CURRENT

vs. AMBIENT TEMPERATURE

AMBIENTTEMPERATURE (°C) OUTPUT VOLTAGE (V)

OUTPUT SOURCE CURRENT

vs. OUTPUT VOLTAGE

0.8

1.3

1.2

1.1

1.0

0.9

0.8

4.0 4.5 5.0 5.5 6.0

NORMALIZED FREQUENCY

vs. SUPPLY VOLTAGE 140

120

0.0 1.0 2.0 3.0 4.0

OUTPUT SINK CURRENT (mA)

OUTPUT SINK CURRENT

vs. OUTPUT VOLTAGE

0.0

NORMALIZED I

NORMALIZED I CC

VCC =5.0V

TA=25°C

0.60.7

1.6

1.4

1.2

0 200 400 600 800

CAPACITANCE (pF)

TYPICAL FREQUENCY CHANGE

vs. OUTPUT LOADING

0153035

NORMALIZED ICC

FREQUENCY (MHz)

NORMALIZED ICC

vs. FREQUENCY

1.0 1000 0.0

SUPPLY VOLTAGE (V) AMBIENT TEMPERATURE (°C) OUTPUT VOLTAGE (V)

VCC =5.5V

VIN =5.0V

0.8

0.7

VIN =5.0V

TA=25°C

VCC =5.0V

TA=25°C

1.2

100

1.5

1.3

1.1

0.9

1.1

1.0

NORMALIZED FREQUENCY

510 2025 C401–15

CY7C401/CY7C403

CY7C402/CY7C404

FIFO Expansion[13, 14, 15, 16, 17]

Notes:

13. When the memory is empty, the last word read will remain on the outputs until the master reset is strobed or a new data word bubbles through to the output.

However, OR will remain LOW, indicating data at the output is not valid.

14. When the output data changes as a result of a pulse on SO, the OR signal alwa ys goes LOW before ther e is an y change in output data, and stays LO W until

the new data has appeared on the outputs. Anytime OR is HIGH, there is valid, stable data on the outputs.

15. If SO is held HIGH while the memory is empty and a word is written into the input, that word will ripple through the memory to the output. OR will go HIGH

for one internal cycle (at least t ORL) and then go back LO W agai n. The stored word will remain on the outputs. If more words are written into the FIFO,

they will line up behind the first word and will not appear on the outputs until SO has been brought LOW.

16. When the master reset is brought LO W, the outputs are cleared to LO W , IR goes HIGH and OR goes LO W. If SI is HIGH when the master reset goes HIGH,

then the data on the inputs will be written into the memory and IR will return to the LOW state until SI is brought LOW. If SI is LO W when the master reset

is ended, then IR will go HIGH, but the data on the inputs will not enter the memory until SI goes HIGH.

17. All Cypress FIFOs will cascade with other Cypress FIFOs. However, hey may not cascade with pi n-compatible FIFOs from other manufacturers.

18. FIFOs can be easily cascaded to any desired depth. The handshaking and associated timing between the FIFOs are handled by the inherent timing of the

devices.

19. FIFOs are expandable in depth and width. However, in forming wider words two external gates are required to generate composite input and output ready

flags. This need is due to the variation of delays of the FIFOs.

ORSI

DI0

DI1

DI2

DI3

DO0

DO1

DO2

DO3

ORSI

DI0

DI1

DI2

DI3

DO0

DO1

DO2

DO3

OUTPUT READYSHIFT IN SHIFT OUTINPUT READY

DATA IN DATA OUT

MR C401–16

ORSI

DI0

DI1

DI2

DI3

DO0

DO1

DO2

DO3

ORSI

DI0

DI1

DI2

DI3

DO0

DO1

DO2

DO3

ORSI

DI0

DI1

DI2

DI3

DO0

DO1

DO2

DO3

COMPOSITE

OUTPUT READY

ORSI

DI0

DI1

DI2

DI3

DO0

DO1

DO2

DO3

ORSI

DI0

DI1

DI2

DI3

DO0

DO1

DO2

DO3

ORSI

DI0

DI1

DI2

DI3

DO0

DO1

DO2

DO3

ORSI

DI0

DI1

DI2

DI3

DO0

DO1

DO2

DO3

ORSI

DI0

DI1

DI2

DI3

DO0

DO1

DO2

DO3

ORSI

DI0

DI1

DI2

DI3

DO0

DO1

DO2

DO3

SHIFT OUT

COMPOSITE

INPUT READY

SHIFT IN

C401–17

128 x 4 Applicat ion [18]

192 x 12 Application[19]

CY7C401/CY7C403

CY7C402/CY7C404

Ordering Information

Speed

(MHz) Ordering Code Package

Name Pac kage Type Operating

Range

5CY7C401–5PC P1 16-Lead (300-Mil) Molded DIP Commercial

10 CY7C401–10DC D2 16-Lead (300-Mil) CerDIP Comm ercial

CY7C401–10PC P1 16-Lead (300-Mil) Molded DIP

CY7C401–10DMB D2 16-Lead (300-Mil) CerDIP Military

CY7C401–10LMB L61 20-Pin Square Leadless Chip Carrier

15 CY7C401–15DC D2 16-Lead (300-Mil) CerDIP Commercial

CY7C401–15PC P1 16-Lead (300-Mil) Molded DIP

CY7C401–15DMB D2 16-Lead (300-Mil) CerDIP Military

CY7C401–15LMB L61 20-Pin Square Leadless Chip Carrier

25 CY7C401–25DC D2 16-Lead (300-Mil) CerDIP Commercial

CY7C401–25PC P1 16-Lead (300-Mil) Molded DIP

CY7C401–25DMB D2 16-Lead (300-Mil) CerDIP Military

CY7C401–25LMB L61 20-Pin Square Leadless Chip Carrier

Speed

(MHz) Ordering Code Package

Name Pac kage Type Operating

Range

5CY7C402–5PC P3 18-Lead (300-Mil) Molded DIP Commercial

10 CY7C402–10DC D4 18-Lead (300-Mil) CerDIP Comm ercial

CY7C402–10PC P3 20-Pin Square Leadless Chip Carrier

CY7C402–10DMB D4 18-Lead (300-Mil) CerDIP Military

CY7C402–10LMB L61 20-Pin Square Leadless Chip Carrier

15 CY7C402–15DC D4 18-Lead (300-Mil) CerDIP Commercial

CY7C402–15PC P3 18-Lead (300-Mil) Molded DIP

CY7C402–15DMB D4 18-Lead (300-Mil) CerDIP Military

CY7C402–15LMB L61 20-Pin Square Leadless Chip Carrier

25 CY7C402–25DC D4 18-Lead (300-Mil) CerDIP Commercial

CY7C402–25PC P3 18-Lead (300-Mil) Molded DIP

CY7C402–25DMB D4 18-Lead (300-Mil) CerDIP Military

CY7C402–25LMB L61 20-Pin Square Leadless Chip Carrier

CY7C401/CY7C403

CY7C402/CY7C404

Ordering Information (continued)

Speed

(MHz) Ordering Code Package

Name Pac kage Type Operating

Range

10 CY7C403–10DC D2 16-Lead (300-Mil) CerDIP Commercial

CY7C403–10PC P1 16-Lead (300-Mil) Molded DIP

CY7C403–10DMB D2 16-Lead (300-Mil) CerDIP Military

CY7C403–10LMB L61 20-Pin Square Leadless Chip Carrier

15 CY7C403–15DC D2 16-Lead (300-Mil) CerDIP Commercial

CY7C403–15PC P1 16-Lead (300-Mil) Molded DIP

CY7C403–15DMB D2 16-Lead (300-Mil) CerDIP Military

CY7C403–15LMB L61 20-Pin Square Leadless Chip Carrier

25 CY7C403–25DC D2 16-Lead (300-Mil) CerDIP Commercial

CY7C403–25PC P1 16-Lead (300-Mil) Molded DIP

CY7C403–25DMB D2 16-Lead (300-Mil) CerDIP Military

CY7C403–25LMB L61 20-Pin Square Leadless Chip Carrier

Speed

(MHz) Ordering Code Package

Name Pac kage Type Operating

Range

10 CY7C404–10DC D4 18-Lead (300-Mil) CerDIP Commercial

CY7C404–10PC P3 18-Lead (300-Mil) Molded DIP

CY7C404–10DMB D4 18-Lead (300-Mil) CerDIP Military

CY7C404–10LMB L61 20-Pin Square Leadless Chip Carrier

15 CY7C404–15DC D4 18-Lead (300-Mil) CerDIP Commercial

CY7C404–15PC P3 18-Lead (300-Mil) Molded DIP

CY7C404–15DMB D4 18-Lead (300-Mil) CerDIP Military

CY7C404–15LMB L61 20-Pin Square Leadless Chip Carrier

25 CY7C404–25DC D4 18-Lead (300-Mil) CerDIP Commercial

CY7C404–25PC P3 18-Lead (300-Mil) Molded DIP

CY7C404–25DMB D4 18-Lead (300-Mil) CerDIP Military

CY7C404–25LMB L61 20-Pin Square Leadless Chip Carrier

CY7C401/CY7C403

CY7C402/CY7C404

MILITARY SPECIFICATIONS

Group A Subgroup Tes ting

Document #: 38–00040–H

DC Characteristics

Parameters Subgroups

VOH 1, 2, 3

VOL 1, 2, 3

VIH 1, 2, 3

VIL Max. 1, 2, 3

IIX 1, 2, 3

IOZ 1, 2, 3

IOS 1, 2, 3

ICC 1, 2, 3

Switching Characteristics

Parameters Subgroups

fO7, 8, 9, 10, 11

tPHSI 7, 8, 9, 10, 11

tPLSI 7, 8, 9, 10, 11

tSSI 7, 8, 9, 10, 11

tHSI 7, 8, 9, 10, 11

tDLIR 7, 8, 9, 10, 11

tDHIR 7, 8, 9, 10, 11

tPHSO 7, 8, 9, 10, 11

tPLSO 7, 8, 9, 10, 11

tDLOR 7, 8, 9, 10, 11

tDHOR 7, 8, 9, 10, 11

tSOR 7, 8, 9, 10, 11

tHSO 7, 8, 9, 10, 11

tBT 7, 8, 9, 10, 11

tSIR 7, 8, 9, 10, 11

tHIR 7, 8, 9, 10, 11

tPIR 7, 8, 9, 10, 11

tPOR 7, 8, 9, 10, 11

tPMR 7, 8, 9, 10, 11

tDSI 7, 8, 9, 10, 11

tDOR 7, 8, 9, 10, 11

tDIR 7, 8, 9, 10, 11

tLZMR 7, 8, 9, 10, 11

tOOE 7, 8, 9, 10, 11

tHZOE 7, 8, 9, 10, 11

CY7C401/CY7C403

CY7C402/CY7C404

Package Di ag r ams

16-Lead (300-Mil) CerDIP D2

MIL-STD-1835 D-2 Con f ig .A 18-Lead (300-Mil) CerDIP D4

MIL-STD-1835 D-8 Config.A

20-Pin Square Leadless Chip Carrier L61

MIL-STD-1835 C–2A

CY7C401/CY7C403

CY7C402/CY7C404

of any circuit ry other tha n circu itry emb odied i n a Cyp res s Sem iconductor product. Nor does it con vey or imply any lice nse under patent or other rights. Cypress Semi condu ctor does not authorize

its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

Package Di ag r ams (continued)

16-Lead (300-Mil) Molded DIP P1

18-Lead (300-Mil) Molded DIP P3