NSP4201MR6T1G - ON SEMICONDUCTOR

June, 2017 − Rev. 1 1Publication Order Number:

NSP4201MR6/D

NSP4201MR6

ESD and Surge Protection

Device

Low Clamping Voltage Surge Protection

Diode Array

The NSP4201MR6 surge protector is designed to protect high speed

data lines from ESD, EFT, and lightning surges.

Features

•Protection for the Following IEC Standards:

IEC 61000−4−2 (ESD) ±30 kV (Contact)

IEC 61000−4−5 (Lightning) 25 A (8/20 ms)

•Low Clamping Voltage

•Low Leakage

•UL Flammability Rating of 94 V−0

•SZ Prefix for Automotive and Other Applications Requiring Unique

Site and Control Change Requirements; AEC−Q101 Qualified and

PPAP Capable

•These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS

Compliant

Typical Applications

•High Speed Communication Line Protection

•USB 1.1 and 2.0 Power and Data Line Protection

•Digital Video Interface (DVI)

•Monitors and Flat Panel Displays

MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)

Rating Symbol Value Unit

Peak Power Dissipation

8/20 ms @ TA = 25°C (Note 1) Ppk 500 W

Operating Junction Temperature Range TJ−40 to +125 °C

Storage Temperature Range Tstg −55 to +150 °C

Lead Solder Temperature −

Maximum (10 Seconds) TL260 °C

IEC 61000−4−2 Air (ESD)

IEC 61000−4−2 Contact (ESD) ESD ±30

±30 kV

IEC 61000−4−4 (5/50 ns) EFT 40 A

Stresses exceeding those listed in the Maximum Ratings table may damage the

device. If any of these limits are exceeded, device functionality should not be

assumed, damage may occur and reliability may be af fected.

1. Non−repetitive current pulse per Figure 1 (Pin 5 to Pin 2)

See Application Note AND8308/D for further description of

survivability specs.

MARKING DIAGRAM

Device Package Shipping

ORDERING INFORMATION

TSOP−6

CASE 318G

PIN CONFIGURATION AND SCHEMATIC

6 I/O

5 VP

4 I/O

I/O 1

VN 2

I/O 3

www.onsemi.com

42 = Specific Device Code

M = Date Code

G= Pb−Free Package

42 MG

NSP4201MR6T1G TSOP−6

(Pb−Free) 3000 / Tape &

Reel

†For information on tape and reel specifications,

including part orientation and tape sizes, please

refer to our Tape and Reel Packaging Specification

Brochure, BRD8011/D.

*Date Code orientation may vary

depending upon manufacturing location.

SZNSP4201MR6T1G TSOP−6

(Pb−Free) 3000 / Tape &

Reel

(Note: Microdot may be in either location)

NSP4201MR6

www.onsemi.com

ELECTRICAL CHARACTERISTICS

(TA = 25°C unless otherwise noted)

Symbol Parameter

IPP Maximum Reverse Peak Pulse Current

VCClamping Voltage @ IPP

VRWM Working Peak Reverse Voltage

IRMaximum Reverse Leakage Current @ VRWM

VBR Breakdown Voltage @ IT

ITTest Current

IFForward Current

VFForward Voltage @ IF

Ppk Peak Power Dissipation

CCapacitance @ VR = 0 and f = 1.0 MHz

*See Application Note AND8308/D for detailed explanations of

datasheet parameters.

Uni−Directional Surge Protection

IPP

VRWM

VCVBR VF

ELECTRICAL CHARACTERISTICS (TJ=25°C unless otherwise specified)

Parameter Symbol Conditions Min Typ Max Unit

Reverse Working Voltage VRWM (Note 2) 5.0 V

Breakdown Voltage VBR IT=1 mA, (Note 3) 6.0 V

Reverse Leakage Current IRVRWM = 5 V 1.0 mA

Clamping Voltage

(tp = 8/20 ms per Figure 1) VCIPP = 1 A, Any I/O to GND 8.5 V

IPP = 5 A, Any I/O to GND 9.0

IPP = 8 A, Any I/O to GND 10

IPP = 25 A, Any I/O to GND 12

Junction Capacitance CJVR = 0 V, f=1 MHz between I/O Pins and GND 3.0 5.0 pF

Junction Capacitance CJVR = 0 V, f=1 MHz between I/O Pins 1.5 3.0 pF

2. Surge protection devices are normally selected according to the working peak reverse voltage ( VRWM), which should be equal or greater

than the DC or continuous peak operating voltage level.

3. VBR is measured at pulse test current IT.

Figure 1. IEC61000−4−5 8/20 ms Pulse Waveform

100

0020406080

t, TIME (ms)

% OF PEAK PULSE CURRENT

PULSE WIDTH (tP) IS DEFINED

AS THAT POINT WHERE THE

PEAK CURRENT DECAY = 8 ms

PEAK VALUE IRSM @ 8 ms

HALF VALUE IRSM/2 @ 20 ms

Figure 2. Clamping Voltage vs. Peak Pulse Current

(tp = 8/20 ms per Figure 1)

005

PEAK PULSE CURRENT (A)

CLAMPING VOLTAGE (V)

10 15 20 25

I/O−GND

NSP4201MR6

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Figure 3. IEC61000−4−2 +8 kV Contact Clamping

Voltage Figure 4. IEC61000−4−2 −8 kV Contact Clamping

Voltage

TIME (ns)

VOLTAGE (V)

−20

100

−20 0 20 40 60 80 100 120 140 TIME (ns)

VOLTAGE (V)

−100

−80

−60

−40

−20

−20 0 20 40 60 80 100 120 140

IEC 61000−4−2 Spec.

Level Test Volt-

age (kV)

First Peak

Current

(A) Current at

30 ns (A) Current at

60 ns (A)

1 2 7.5 4 2

2 4 15 8 4

3 6 22.5 12 6

4 8 30 16 8

Ipeak

90%

10%

IEC61000−4−2 W aveform

100%

I @ 30 ns

I @ 60 ns

tP = 0.7 ns to 1 ns

Figure 5. IEC61000−4−2 Spec

Figure 6. Diagram of ESD Test Setup

50 W

Cable

Surge Protection Oscilloscope

ESD Gun

The following is taken from Application Note

AND8308/D − Interpretation of Datasheet Parameters

for ESD Devices.

ESD Voltage Clamping

For sensitive circuit elements it is important to limit the

voltage that an IC will be exposed to during an ESD event

to as low a voltage as possible. The ESD clamping voltage

is the voltage drop across the ESD protection diode during

an ESD event per the IEC61000−4−2 waveform. Since the

IEC61000−4−2 was written as a pass/fail spec for larger

systems such as cell phones or laptop computers it is not

clearly defined in the spec how to specify a clamping voltage

at the device level. ON Semiconductor has developed a way

to examine the entire voltage waveform across the ESD

protection diode over the time domain of an ESD pulse in the

form of an oscilloscope screenshot, which can be found on

the datasheets for all ESD protection diodes. For more

information on how ON Semiconductor creates these

screenshots and how to interpret them please refer to

AND8307/D.

NSP4201MR6

www.onsemi.com

TYPICAL PERFORMANCE CUR VES

(TJ = 25°C unless otherwise noted)

Figure 7. Pulse Derating Curve

100

00 25 50 75 100 125 150 175 200

TA, AMBIENT TEMPERATURE (°C)

Figure 8. Junction Capacitance vs Reverse Voltage

5.0

2.5

0.0 01

VBR, REVERSE VOLTAGE (V)

JUNCTION CAPACITANCE (pF)

234

I/O−I/O

I/O−GND

PEAK POWER DISSIPATION (%)

4.5

2.0

4.0

1.5

3.5

1.0

3.0

0.5

Figure 9. RF Insertion Loss

NSP4201MR6

www.onsemi.com

TYPICAL APPLICATIONS

Figure 10. Protection for Ethernet 10/100 (Differential mode)

PHY

Ethernet

(10/100)

Coupling

Transformers

NSP4201MR6

RJ45

Connector

N/C N/C

TX+

TX−

RX+

RX−

TX+

TX−

RX+

RX−

GND

VCC

T1/E1

TRANCEIVER

RTIP

RRING

TRING

TTIP

R2 R3

NSP4201MR6

VCC

Figure 11. TI/E1 Interface Protection

NSP4201MR6

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PACKAGE DIMENSIONS

TSOP−6

CASE 318G−02

ISSUE V

ÉÉ

456

0.05

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH. MINIMUM

LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL.

4. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD FLASH,

PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS, OR

GATE BURRS SHALL NOT EXCEED 0.15 PER SIDE. DIMENSIONS D

AND E1 ARE DETERMINED AT DATUM H.

5. PIN ONE INDICATOR MUST BE LOCATED IN THE INDICATED ZONE.

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

DIM

AMIN NOM MAX

MILLIMETERS

0.90 1.00 1.10

A1 0.01 0.06 0.10

b0.25 0.38 0.50

c0.10 0.18 0.26

D2.90 3.00 3.10

E2.50 2.75 3.00

e0.85 0.95 1.05

L0.20 0.40 0.60

0.25 BSC

L2 −

0°10°

1.30 1.50 1.70

RECOMMENDED

NOTE 5

SEATING

PLANE

GAUGE

PLANE

DETAIL Z

0.60

3.20 0.95

0.95

PITCH

DIMENSIONS: MILLIMETERS

NSP4201MR6/D

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