1 November 01, 2001
UL62H256A
F32768 x 8 bit static CMOS RAM
F35 and 55 ns Access Time
FCommon data inputs and
data outputs
FThree-state outputs
FTyp. operating supply current
35 ns: 45mA
55 ns: 30mA
FStandby current < 50 µA at 125° C
FTTL/CMOS-compatible
FPower supply voltage 3.3 V
FOperating temperature range
-40 °C to 85 °C
-40 °C to 125 °C
FCECC 90000 Qua lity Standard
FESD protection > 2000 V
(MIL STD 883C M3015.7)
FLatch-up im mun ity >100 mA
FPackage: SOP28 (300/330 mil)
The UL62H256A is a static RAM
manufactured using a CMOS pro-
cess technology with the following
operating modes:
- Read - Standby
- Write - Data Retention
The memory array is based on a
6-Transistor cell.
The circuit is activated by the fal-
ling edge of E. The address and
control inputs open simul taneously.
According to the information of W
and G, the data inputs, or outputs,
are active. In a Read cycle, the
data outputs are activated by the
falling edge of G, afterwards the
data word will be available at the
outputs DQ0-DQ7. After the
address change, the data outputs
go High-Z until the new informa tion
is available. T he data outputs have
no preferred state. The R ead cycle
is finished by the falling edge of W,
or by the rising edge of E, respec-
tively.
Data retention is guaranteed down
to 2 V. With the exception of E, all
inputs consist of NOR gates, so
that no pull-up/pull-down resistors
are required.
Low Voltage Automotive Fast 32K x 8 SRAM
Pin Configuration
Top View
Signal Name Signal Descripti on
A0 - A14 Address Inputs
DQ0 - DQ7 Data In/Out
EChip Enable
GOutput En able
WWrite Enable
VCC Power Supply
Voltage
VSS Ground
Pin Descript ion
1
A14 VCC28
2A12 W
27
4A6 A825
5A5 A924
3A7 A1326
6A4 A1123
7A3 G
22
8A2 A1021
12DQ1 DQ517
9A1 E
20
10
A0 DQ719
11DQ0 DQ618
13DQ2 DQ416
14VSS DQ315
SOP
Features Description
2 November 01, 200 1
UL62H256A
a Stresses greater than those listed under „Absolute Maximum Ratings“ may cause permanent damage to the device. This is a stress rating
only, and functional operation of the device at condition above those indicated in the operational sections of this specificatio n is n ot im plie d.
Exposure to absolute maximum rating conditions for extended periods may affect reliability
b Maximum voltage is 4.6 V
c Not more than 1 output should be shorted at the same time. Duration of the short circuit should not exceed 30 s.
*H or L
Operati ng Mod e E W G DQ0 - DQ7
Standby/not selected H * * High-Z
Internal Read L H H High-Z
R ead L H L Data Outputs Low-Z
Write L L * Da ta In p uts Hig h-Z
Tr uth Ta ble
Block Diagram
Maxim um Ratings a Symbol Min. Max. Unit
Power Supply Voltage VCC -0.3 4.6 V
Input Voltage VI-0.5 VCC + 0.5 bV
Outpu t Vol tage VO-0.5 VCC + 0.5 bV
Power Dissipa tion PD-1W
Operating Temperature K-Type
A-Type Ta-40
-40 85
125 °C
Storage Temperature Tstg -65 150 °C
Outpu t Short-Circuit Current
at VCC = 3.3 V and VO = 0 V c| IOS |100mA
Characteristics
All voltages a re referenced to VSS = 0 V (ground).
All characteristics are valid in the power su pply voltage ra nge and i n the ope rat ing temperature range spe cifie d.
Dynamic m easurem ents are based on a ris e and fall time of 5 ns, measured between 10 % and 90 % of VI,as well as
input levels of VIL = 0 V and VIH = 3 V. The tim ing refere nce level of all input and out put signals is 1.5 V,
with the exception of the tdis-times and ten-tim es, in which c ases transi tion is m easured ±200 mV from steady-state voltage.
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
VCC VSS W GE
Row Address
Inputs
Column Address
Inputs
Address
Change
Detector
Column Decoder Row Decoder
Se ns e Amp lifie r /
Write Control Logic
Clock
Generator
Co mmo n Data I/O
Memory Cell
Array
512 Ro ws x
64 x 8 Columns
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
3 November 01, 2001
UL62H256A
Recommended
Operating Conditions Symbol Conditions Min. Max. Unit
Power Supply Voltage VCC 3.0 3.6 V
Input Low V ol t age d VIL -0.3 0.6 V
Input High V o ltage VIH 2.2 VCC + 0.3 V
Electrical Characteristic s Symbol Co nd itions Min. Max. Unit
Suppl y Current - Operating Mode
Suppl y Current - Standby Mode
(CMOS level)
Suppl y Current - Standby Mode
(TT L lev e l)
ICC(OP)
ICC(SB)
ICC(SB)1
VCC
VIL
VIH
tcW
tcW
tcW
VCC
VE
VCC
VE
K-Type
A-Type
= 3.6 V
= 0.6 V
= 2.2 V
= 35 ns
= 55 ns
= 70 ns
= 3.6 V
= VCC - 0.2 V
= 3.6 V
= 2.2 V
90
70
60
50
10
20
mA
mA
mA
µA
mA
mA
Outpu t High Voltage
Outpu t Low Voltage
VOH
VOL
VCC
IOH
VCC
IOL
= 3.0 V
=-1 mA
= 3.0 V
= 2.1 mA
2.4
0.4
V
V
Input High Leakage Current
Input Low Leakage Current
IIH
IIL
VCC
VIH
VCC
VIL
= 3.6 V
= 3.6 V
= 3.6 V
= 0 V -2
A
µA
Outpu t High Current
Outpu t Low Current
IOH
IOL
VCC
VOH
VCC
VOL
= 3.0 V
= 2.4 V
= 3.0 V
= 0.4 V 2.1
-1 mA
mA
Outpu t Leakage Current
High at Three-State Outputs
Low at Three-St ate Outputs
IOHZ
IOLZ
VCC
VOH
VCC
VOL
= 3.6 V
= 3.6 V
= 3.6 V
=0 V -2
A
µA
d -2 V at Pulse Width 30 ns
4 November 01, 200 1
UL62H256A
Switching Characteristics
Read Cycle
Symbol 35 55 Unit
Alt. IEC Min. Max. Min. Max.
Read Cycle Time tRC tcR 35 55 ns
Address Access Time to Data Valid tAA ta(A) 35 55 ns
Chip Enable Access Tim e to Data Valid tACE ta(E) 35 55 ns
G LOW to Data Valid tOE ta(G) 15 25 ns
E HIGH to Output in High-Z tHZCE tdis(E) 12 15 ns
G HIGH to Output in High-Z tHZOE tdis(G) 12 15 ns
E LOW to Output in Low-Z tLZCE ten(E) 33ns
G LOW to Output in Low-Z tLZOE ten(G) 00ns
Output Hold Ti me from Address Change tOH tv(A) 33ns
E LOW to Power-Up Time tPU 00ns
E HIGH to Power-Down Time tPD 35 55 ns
Switching Characteristics
Write Cycle
Symbol 35 55 Unit
Alt. IEC Min. Max. Min. Max.
Write Cycle Ti me tWC tcW 35 55 ns
Write Pulse Width tWP tw(W) 20 35 ns
Wr ite Setup Time tWP tsu(W) 20 35 ns
Address Setup Time tAS tsu(A) 00ns
Address Valid to End of Write tAW tsu(A-WH) 25 40 ns
Chip Enable Setup Time tCW tsu(E) 25 40 ns
Pulse Width Chip Enable to End of Write tCW tw(E) 25 40 ns
Da ta Se tu p Time tDS tsu(D) 15 25 ns
Data Hold Time tDH th(D) 00ns
Address Hold from End of Write tAH th(A) 00ns
W LOW to Output in High-Z tHZWE tdis(W) 15 20 ns
G HIGH to Output in High-Z tHZOE tdis(G) 12 15 ns
W HIGH to Output in Low-Z tLZWE ten(W) 00ns
G LOW to Output in Low-Z tLZOE ten(G) 00ns
5 November 01, 2001
UL62H256A
Data Retention Mode
E - controlled
Data Retention
3.0 V
tsu(DR) trec
VCC
E
VCC(DR) 2 V
0 V
2.2 V
2.2 V
VCC(DR) - 0.2 V VE(DR) VCC(DR) + 0.3 V
Data Retention
Characteristics Symbol Conditions Min. Typ. Max. Unit
Alt. IEC
Data Retention Sup ply Voltage VCC(DR) 2V
Data Retention Supply Current ICC(DR) VCC(DR) = 2 V
VE = VCC(DR) - 0.2 V 30 µA
Data Retention Setup Time tCDR tsu(DR) See Data Retention
Waveforms (above) 0ns
Operating Recovery T i m e tRtrec tcR ns
Test Configuration for Functional Check
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
VIH
VIL
VSS
VCC
3.3 V
1213
1375
VO
Inpu t level a ccordi ng to the
relevant test measurem ent
Simultaneous measure-
ment of all 8 output pins
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
E
W
G
30 pF e
e In measurement of tdis(E),tdis(W), ten(E), ten(W), ten(G) the capacitance is 5 pF.
6 November 01, 200 1
UL62H256A
Capacitance Conditions Symbol Min. Max. Unit
Input Capacit ance VCC
VI
f
Ta
= 3.3 V
= VSS
= 1 MHz
= 25 °C
CI7pF
Output Capacitance Co7pF
IC Code Numbers
UL62H256A SA35
Type
Package
S = SOP28 300 m il
S1 = SOP 28 330 mi l
Opera tin g Temperatur e Range
K = -40 to 85 °C
A = -40 to 125 °C
Access Time
35 = 35 ns
55 = 55 ns
The date of manufacture is given by the last 4 digits of the mark, the first 2 digits indicating the year, and the last 2
digits the c al endar week.
All pins not under test must be connec ted with ground by capacitors.
7 November 01, 2001
UL62H256A
tPU
tdis(G)
tdis(E)
tcR
Previous Data Valid Output Data Valid
Ad dres s Va lid
Addres s Valid
tsu(A)
High-Z
ten(E)
ten(G)
ta(G)
ta(E)
Read Cycle 1: Ai-con trolled (during Read Cycle : E = G = VIL, W = VIH)
Read Cycle 2: G-, E- controlled (during Read Cycle: W = VIH)
ta(A)
tcR
tv(A)
Ai
DQi
Output
Ai
G
DQi
Output tPD
ICC(OP)
ICC(SB) 50 % 50 %
Ou tp ut Data Valid
E
8 November 01, 200 1
UL62H256A
Write Cycle1: W-controlled
th(D)
Ai
E
W
DQi
Input
G
DQi
Output
tcW
tsu(E) th(A)
tw(W)
tsu(A) tsu(D)
tdis(W) ten(W)
Address
In p ut Da ta Valid
High-Z
tsu(A-WH)
Write Cycle 2: E-co ntrolled
Inp ut D ata Vali d
tsu(A)
th(D)
Ai
E
W
DQi
Input
G
DQi
Output
tcW
tw(E) th(A)
tsu(W)
tsu(D)
tdis(W)
t
en(E)
High-Z
Address Valid
tdis(G)
L- to H- l e v e l undefined H- to L-l e ve l
The information describes the type of component and shall not be considered as assured characteristics.Terms of
delivery and rights to change design reserved.
Zentrum Mikroelektronik Dresden AG
Grenzstra ße 28 D-01109 Dresden P. O. B. 80 01 34 D-01101 Dresden Germany
Phone: +49 351 8822 306 Fax: +49 351 8822 337 Email: sales@zmd.de http://www.zmd.de
November 01, 2001
UL62H256A
LIFE SUPPO R T POLICY
ZMD products are not designed, intended, or authorized for use as components in systems intended for surgical
imp lant into the body, or other applications in tended to supp ort or s ustain life, o r for any other ap plication in which
the failure of the ZMD product could create a situation where personal injury or death may occur.
Components used in life-support devices or systems must be expressly authorized by ZMD for such purpose.
LIMITED WARRANTY
The information in this document has been carefully checked and is believed to be reliable. However Zentrum
Mikroelektronik Dresden AG (ZMD) makes no guarantee or warranty concerning the accuracy of said information
and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon it.
The i nfo rmation in this doc um ent desc ribes the type o f com pone nt and shall not be co nsidered a s assure d charac -
teristics.
ZMD does not guarantee that the use of any information contained herein will not infringe upon the patent, trade-
mark, copyright, mask work right or other rights of third parties, and no patent or licence is implied hereby. This
document does not in any way extent ZMD’s warranty on any product beyond that set forth in i t s s tandard terms and
con ditions of sale.
ZM D reserves term s of del ivery and reserv es the right to make cha nges in t he products or specifications, or bot h,
presented in this publication at any time and without notice.