DS4830A General Description The DS4830A is a low-power, 16-bit microcontroller with a unique peripheral set supporting optical applications that require high-resolution conversion of many analog signals and digital signal processing (DSP) of those signals, high-speed data communication to an external host, and ultra-low power dissipation. A wide variety of optical transceiver controller applications is supported without need of external circuitry, thereby minimizing cost and PCB area. Power dissipation and throughput are optimized through the use of a programmable round-robin analog-to-digital converter (ADC) and 10-bit fast comparator, which operate completely independently of the core and significantly relieve core overhead. A dual multiply/accumulate (MAC) is included to minimize interrupt service timing/design complexity. Ten 16-bit PWM channels are included to provide an unprecedented level of precision in digital powercontrol applications. The DS4830A provides a complete optical control, calibration, and monitor solution compatible with SFF-8472. Additional resources include a fast/accurate ADC, fast comparators with an internal comparison digital-to-analog converter (DAC), eight independent 12-bit DACs, an accurate internal temperature sensor, two fast sample/ holds with various programmable options, and a multiprotocol serial master/slave interface. An independent, 400kHz-compliant, slave I2C interface with four configurable slave addresses facilitates communication to a host, in addition to password-protected in-system programming of the on-chip flash. Extensive design-in and applications support are available, including comprehensive user's and programmer's guides, complete reference designs with documented code, and in-depth application notes showing numerous code examples in both C and assembly language. Firmware development is supported by third-party vendors. Applications PON Diplexers and Triplexers: GPON, 10GEPON, XPON OLT, ONU Optical Transceivers: XFP, SFP, SFP+, QSFP+, CSFP, 40G, 100G Ordering Information appears at end of data sheet. 19-6870; Rev 1; 1/17 Optical Microcontroller Benefits and Features 16-Bit Low Power Microcontroller Slave Communication Interface: 400kHz without Clock Stretching I2C-Compatible 2-Wire or SPI Master Communication Interface: 400kHz I2CCompatible 2-Wire, SPI, or Maxim 3-Wire Laser Driver Pin-Compatible with DS4830 32KWords Flash Program Memory 2KWords Data RAM 4KWords ROM Memory 32-Level Stack Memory 2.85V to 3.63V Operating Voltage Range 8 Independent 12-Bit Voltage DACs with 2.5V Internal Reference or External Reference 10 x 16-Bit PWM Channels * Supports 4-Channel TECC H-Bridge Control * Boost/Buck DC-DC Control * 1MHz Switching Frequency 13-Bit ADC with 26-Input Mux * 40ksps * Individual Channel Averaging Option Two Independent Sample/Holds with Individual Channel Averaging Option * 1V Full Scale * 300ns Sample Time Fast Temperature Measurement with Averaging Option * Internal Temperature Sensor, 2C 10-Bit Fast Comparator with 16 Input Mux 31 GPIO Pins Internal 20MHz Oscillator Up to 133MHz External Clock for PWM and Timers Two 16-Bit Timers and One Programmable Watchdog Timer Maskable Interrupt Sources Fast Hardware CRC-8 for Packet Error Checking (PEC) I2C and JTAG Bootloader Four Software Interrupts Supply Voltage Monitor (SVM) and Brownout Monitor JTAG Port with In-System Debug and Programming Low Power Consumption (16mA) with All Analog Active 5mm x 5mm, 40-Pin TQFN Package DS4830A Optical Microcontroller Absolute Maximum Ratings VDD to GND........................................................-0.3V to +3.97V SCL, SDA, RST...................................................-0.3V to +3.63V All Other Pins to GND except REG18 and REG274............................-0.3V to (VDD + 0.5V)* Continous Sink Current....................... 20mA per pin, 50mA total Continous Source Current................... 20mA per pin, 50mA total Continuous Power Dissipation (TA = +70C) TQFN (derate 27.8mW/C above + 70C)..............2222.2mW Operating Temperature Range.............................-40C to +85C Storage Temperature Range..............................-55C to +125C Lead Temperature (soldering, 10s).............................. ...+300C Soldering Temperature (reflow).................................... ...+260C *Subject to not exceeding +3.97V. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Package Information 40 TQFN Package Code T4055+2 Outline Number 21-0140 Land Pattern Number 90-0016 For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a "+", "#", or "-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. Recommended Operating Conditions (TA = -40C to +85C, unless otherwise noted.) (Note 1) PARAMETER SYMBOL MAX UNITS 2.85 3.63 V VIH 0.7 x VDD VDD + 0.3 V VIL -0.3 0.3 x VDD V VDD Operating Voltage VDD Input Logic-High Input Logic-Low www.maximintegrated.com CONDITIONS (Note 2) MIN TYP Maxim Integrated 2 DS4830A Optical Microcontroller DC Electrical Characteristics (VDD = 2.85V to 3.63V, TA = -40C to +85C, unless otherwise noted. Typical values are at VDD = 3.3V, TA = +25C.) (Note 1) PARAMETER SYMBOL ICPU Supply Current CONDITIONS MIN CPU mode, all analog disabled (Notes 3, 4) IFASTCOMP 2.5 ISAMPLEHOLDS Both sample/hold IDACS Brownout Hysteresis MAX UNITS 7.25 mA 1.5 IADC Brownout Voltage TYP 2.5 Per channel (Note 5) 0.7 VBO Monitors VDD (Note 2) 2.62 V VBOH Monitors VDD (Note 2) 110 mV 1.8V Regulator Initial Voltage VREG18 (Note 2) 1.71 1.8 1.89 V 2.74V Regulator Initial Voltage VREG270 (Note 2) 2.68 2.74 2.80 V fOSCPERIPHERAL TA = +25C (Note 6) 20 fMOSC-CORE TA = +25C (Note 6) 10 Clock Error fERR TA = -40C to +85C External Clock Input fXCLK Clock Frequencies Voltage Range: GP[15:0], SHEN, DACPW[7:0], REFINA, REFINB VRANGE MHz 20 (Note 2) Output Logic-Low: All Pins VOL1 IOL = 4mA (Note 2) Output Logic-High: All Pins Except GP2, GP3, SCL, SDA VOH1 IOH = -4mA (Note 2) Pullup Current: All Pins Except GP2, GP3, SCL, SDA IPU1 VPIN = 0V -0.3 5 % 133 MHz VDD + 0.3 0.4 VDD - 0.5 V V 55 A GPIO Drive Strength, Extra Strong Outputs: GP0, GP1, MCS, PWM8, PWM9 RHISt 9 22 RLOSt 8 22 GPIO Drive Strength, Strong Outputs: MSDI, DACPW3, DACPW6 RHIA 17 32 RLOA 12 32 RHIB 27 46 RLOB 31 52 GPIO Drive Strength, Excluding Strong GPIO Outputs V DAC DAC Resolution DACR DAC Internal Reference Accuracy DACREFACC DAC Internal Reference Power-Up Speed tDACPUP Reference Input Full-Scale Range (REFINA, REFINB) REFFS www.maximintegrated.com 12 (Note 5) Bits -1.25 99% settled +1.25 10 1 % s 2.5 V Maxim Integrated 3 DS4830A Optical Microcontroller DC Electrical Characteristics (continued) (VDD = 2.85V to 3.63V, TA = -40C to +85C, unless otherwise noted. Typical values are at VDD = 3.3V, TA = +25C.) (Note 1) PARAMETER DAC Operating Current DAC Integral Nonlinearity DAC Differential Nonlinearity SYMBOL IDACS CONDITIONS Per channel DACINL (Note 5) DACDNL Not production tested (Notes 5, 7) DAC Offset VOFFSET-DAC At code "0" DAC Source Load Regulation IDAC-SOURCE 0 to full-scale output, VDD = 3.3V RDAC-SINK 0 to 0.5V output, limited by output buffer impedance IDAC-SINK 0.5V to full-scale output DAC Sink Capability and Sink Load Regulation DAC Settling Time tDAC MIN TYP MAX UNITS See the DC Electrical Characteristics mA 5 LSB 0 1 LSB 18 mV 3 mV/mA 500 5 Output load capacitance between 33pF to 270pF, from 10% to 90% 10 mV/mA s FAST COMPARATOR Fast Comparator Resolution FCR 10 Bits Fast Comparator Internal Reference Accuracy FCREFTC 0.2 % Fast Comparator Operating Current IFASTCOMP See the DC Electrical Characteristics mA Fast Comparator Full Scale VFS-COMP 2.42 V TA = +25C Fast Comparator Integral Nonlinearity INL Differential mode, 2.2nF capacitor at input (Note 7) 2 LSB Fast Comparator Differential Nonlinearity DNL Differential mode, 2.2nF capacitor at input (Note 8) 0.5 LSB 2 LSB Fast Comparator Offset VOFFSET- Fast Comparator Input Impedance RIN-COMP 15 M Fast Comparator Input Capacitance CIN-COMP 4 pF fCOMP 625 ksps Fast Comparator Sample Rate COMP ADC ADC Resolution ADC Internal Reference Accuracy Reference Output Accuracy ADC Operating Current ADCR VFS 1.2V (Note 9) ADCREFACC REFOUT 13 Bits -0.85 10k < REFOUT load, CMAX= 2.2nF IADC 1.214 1.225 +0.85 % 1.236 V See the DC Electrical Characteristics mA ADC Full-Scale 1 VFS-ADC1 Factory calibrated 1.2 V ADC Full-Scale 2 VFS-ADC2 Factory calibrated 0.6 V ADC Full-Scale 3 VFS-ADC3 Factory calibrated 2.4 V www.maximintegrated.com Maxim Integrated 4 DS4830A Optical Microcontroller DC Electrical Characteristics (continued) (VDD = 2.85V to 3.63V, TA = -40C to +85C, unless otherwise noted. Typical values are at VDD = 3.3V, TA = +25C.) (Note 1) PARAMETER ADC Full-Scale 4 SYMBOL VFS-ADC4 CONDITIONS ADC Integral Nonlinearity ADCINL 13-bit, TA = +25C, VDD = 3.3V, VFS-ADC3 (Note 10) ADC Differential Nonlinearity ADCDNL VFS 1.2V ADC Sample-Sample Deviation ADC Offset MIN Factory calibrated ADC full scale set to VFS-ADC3 VOFFSET-ADC ADC[15:0] Input Resistance RIN-ADC ADC Sample Rate fSAMPLE ADC Temperature Conversion Time tTEMP Internal Temperature Measurement Error TINTERR 13-bit, VFS 1.2V -8 TYP MAX UNITS 6.55 V 3 LSB 0.5 LSB 2 LSB +1 +8 LSB 15 M (Note 11) 40 ksps With default ADC clock 41 s (Note 12) 2 C SAMPLE/HOLD Sample/Hold Input Range VSHP ADC-SHN[1:0] = GND Sample/Hold Capacitance CSH ADC-SHP[1:0] to ADC-SHN[1:0] Sample Input Leakage ISHLKG ADC-SHP[1:0] and ADC-SHN[1:0] Sample Time ts ADC-SHP[1:0] and ADC-SHN[1:0] connected to 50 voltage source Sample Conversion Complete th (Note 13) Sample Offset Sample Error Sample Discharge Strength VSH-OFF ERRSH 1 5 1.2 300 Measured at 10mV -10 VADC-SHP_ to VADC-SHN_ = 300mV, ts = 300ns, driven with 50 voltage source -4 V pF A ns -1.6 RDIS ADC-SHP[1:0] or ADC-SHN[1:0] to GND tME Mass erase 25 tPE Page erase 25 (Notes 14, 15) 75 320 s 7 mV +4 % 50 FLASH MEMORY Flash Erase Time (Note 14) Flash Programming Time per Word tPROG Flash Programming Temperature TFLASH Flash Endurance Data Retention www.maximintegrated.com -40 ms s +85 C nFLASH TA = +50C (Note 7) 20,000 Write Cycles tRET TA = +50C (Note 7) 100 Years Maxim Integrated 5 DS4830A Optical Microcontroller AC Electrical Characteristics (VDD = 2.85V to 3.63V, TA = -40C to +85C, unless otherwise noted.) (Note 1) PARAMETER I2C SYMBOL CONDITIONS MIN TYP MAX UNITS 400 kHz 100 kHz COMPATIBLE INTERFACE (See Figure 1) SCL/MSCL Clock Frequency SCL Bootloader Clock Frequency Bus Free Time Between a STOP and START Condition Hold Time (Repeated) START Condition fSCL Timeout not enabled fSCL:BOOT tBUF tHD:STA (Note 16) 1.3 s 0.6 s Low Period of SCL/MSCL Clock tLOW 1.3 s High Period of SCL/MSCL Clock tHIGH 0.6 s Setup Time for a (Repeated) START Condition tSU:STA 0.6 s Data Hold Time (Note 17) tHD:DAT Data Setup Time tSU:DAT Receive 0 Transmit 300 100 SCL/MSCL, SDA/MSDA Capacitive Loading CB (Note 18) Rise Time of Both SDA and SCL Signals tR (Note 18) Fall Time of Both SDA and SCL Signals tF (Note 18) Setup Time for STOP Condition tSU:STO Spike Pulse Width That Can Be Suppressed by Input Filter tSP SCL/MSCL and SDA/MSDA Input Capacitance SMBusTimeout ns ns 400 pF 20 + 0.1CB 300 ns 20 + 0.1CB 300 ns 0.6 (Note 19) s 50 ns CBIN 5 pF tSMBUS 30 ms JTAG INTERFACE (See Figure 2) JTAG Logic Reference TCK High Time TCK Low Time VREF VDD/2 V tTH 0.5 s tTL 0.5 s tTLQ 0.125 s TMS, TDI Input Setup to TCK High tDVTH 0.25 s TMS, TDI Input Hold after TCK High tTHDX 0.25 s TCK Low to TDO Output www.maximintegrated.com Maxim Integrated 6 DS4830A Optical Microcontroller AC Electrical Characteristics (continued) (VDD = 2.85V to 3.63V, TA = -40C to +85C, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 3-WIRE DIGITAL INTERFACE (See Figure 3) MSCL Clock Frequency fSCLOUT 1000 kHz t3WDC 50 % MSDIO Setup Time tDS 100 ns MSDIO Hold Time tDH 100 ns MSCL Duty Cycle MCS Pulse-Width Low tCSW 500 ns MCS Leading Time Before the First MSCL Edge tL 500 ns MCS Trailing Time After the Last MSCL Edge tT 500 ns 10 pF MSDIO, MSCL Load CB3W Total bus capacitance on one line SPI DIGITAL INTERFACE SPECIFICATION (See Figure 4 and Figure 5) SPI Master Operating Frequency 1/tMSPICK (Note 14) 5 MHz SPI Slave Operating Frequency 1/tSSPICK (Note 14) 2.5 MHz CL = 15pF, pullup = 560 25 ns SPI I/O Rise/Fall Time MSPICK Output Pulse-Width High/Low tSPI_RF tMCH, tMCL tMSPICK/2 - tSPI_RF ns MSPIDO Output Hold After MSPICK Sample Edge tMOH tMSPICK/2 - tSPI_RF ns MSPIDO Output Valid to MSPICK Sample Edge (MSPIDO Setup) tMOV tMSPICK/2 - tSPI_RF ns MSPIDI Input Valid to MSPICK Sample Edge (MSPIDI Setup) tMIS 2tSPI_RF ns MSPIDI Input to MSPICK Sample Edge Rise/Fall Hold tMIH 0 ns MSPICK Inactive to MSPIDO Inactive tMLH tMSPICK/2 - tSPI_RF ns SSPICK Input Pulse-Width High/ Low tSCH, tSCL SSPICS Active to First Shift Edge tSSE tSPI_RF ns SSPIDI Input to SSPICK Sample Edge Rise/Fall Setup tSIS tSPI_RF ns www.maximintegrated.com tSSPICK/2 ns Maxim Integrated 7 DS4830A Optical Microcontroller AC Electrical Characteristics (continued) (VDD = 2.85V to 3.63V, TA = -40C to +85C, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS SSPIDI Input from SSPICK Sample Edge Transition Hold tSIH SSPIDO Output Valid After SSPICK Shift Edge Transition tSOV SSPICS Inactive tSSH tSSPICK + tSPI_RF ns SSPICK Inactive to SSPICS Rising tSD tSPI_RF ns SSPIDO Output Disabled After SSPICS Edge Rise tSLH tSPI_RF ns 2tSPI_RF 2tSSPICK + 2tSPI_RF ns ns Note 1: Limits are 100% production test at TA = +25C. Limits over the operating temperature range and relevant supply voltage range are guaranteed by design and characterization. Note 2: All voltages referenced to GND. Currents entering the IC are specified positive and currents exiting the IC are negative. Note 3: Maximum current assuming 100% CPU duty cycle. Note 4: The value does not include current in GPIO, SCL, SDA, MSDIO, MSDI, MSCL, REFINA, and REFINB. Note 5: Using 2.5V internal reference. Note 6: There is one internal oscillator. The oscillator (peripheral clock) goes through a 2:1 divider to create the core clock. Note 7: Guaranteed by design. Note 8: Tested at worse-case positions. Note 9: Default or slower ADC clock settings. Note 10: Computed using end-point best fit and histogram method. Note 11: ADC conversions are delayed up to 1.6s if the fast comparator is sampling the selected ADC channel. This can cause a slight decrease in the ADC sampling rate. Note 12: Temperature readings averaged 64 times. Note 13: Time from valid sample to ADC data available (without any averaging). Note 14: Minimum and maximum timings depend upon fMOSC-CORE error. Note 15: Programming does not include overhead associated with the utility ROM interface. Note 16: fSCL must meet the minimum clock low time plus the rise/fall times. Note 17: This device internally provides a hold time of at least 75ns for the SDA signal (referred to the VIH:MIN of the SCL signal) to bridge the undefined region of the falling edge of SCL. Note 18: CB--total capacitance of one bus line in pF. Note 19: Filters on SDA and SCL suppress noise spikes at the input buffers and delay the sampling instant. www.maximintegrated.com Maxim Integrated 8 DS4830A Optical Microcontroller Timing Diagrams SDA tBUF tF tLOW tSP tHD:STA SCL tHD:STA tHIGH tR tHD:DAT STOP tSU:STA tSU:STO tSU:DAT START REPEATED START NOTE: TIMING IS REFERENCED TO VILMAX AND VIHMIN. Figure 1. I2C Timing Diagram tTL TCK VREF tTH TMS/TDI tDVTH tTHDX TDO tTLQ Figure 2. JTAG Timing Diagram www.maximintegrated.com Maxim Integrated 9 DS4830A Optical Microcontroller Timing Diagrams (continued) WRITE MODE MCS tL tCH MSCL 0 MSDIO tT tCL 1 A6 A5 2 3 4 5 6 7 8 9 A4 A3 A2 A1 A0 R/W D7 D6 tDS 10 11 D5 12 D4 13 D3 14 D2 15 D1 D0 tDH READ MODE MCS tL tCH MSCL tT tCL 0 1 2 3 4 5 6 7 A4 A3 A2 A1 A0 R/W 8 9 10 11 12 13 14 15 tDS MSDIO A6 A5 D7 D6 D5 D4 D3 D2 D1 D0 tDH Figure 3. 3-Wire Timing Diagram SHIFT SAMPLE SHIFT SAMPLE MSPICS (SAS = 0) MSPICK CKPOL/CKPHA MSPICK CKPOL/CKPHA 1/0 tMSPICK 1/0 0/1 0/1 tMCH 1/1 tMCL 1/1 0/0 0/0 tMOH tSPI_RF tMOV MSPIDO MSB MSB LSB MSB-1 tMIS MSPIDI tMLH tMIH MSB-1 LSB Figure 4. SPI Master Communications Timing Diagram www.maximintegrated.com Maxim Integrated 10 DS4830A Optical Microcontroller Timing Diagrams (continued) SHIFT SSPICS (SAS = 1) SSPICK CKPOL/CKPHA SSPICK CKPOL/CKPHA SAMPLE SHIFT SAMPLE tSSH tSSE 1/0 tSD tSSPICK 0/1 0/1 tSCH 1/1 tSCL 1/1 0/0 0/0 tSIS SSPIDI tSIH MSB MSB-1 MSB LSB tSPI_RF tSOV SSPIDO 1/0 MSB-1 tSLH LSB Figure 5. SPI Slave Communications Timing Diagram www.maximintegrated.com Maxim Integrated 11 DS4830A Optical Microcontroller Typical Operating Characteristics (TA = +25C, unless otherwise noted.) IDD CPU vs. VDD 7.3 IDDDAC vs. VDD toc01 6.05 7.25 6 5.95 IDD DAC (mA) IDD CPU (mA) 7.2 7.15 7.1 5.9 5.85 5.8 5.75 7.05 7 toc02 6.1 2.85 3 TA = +25oC 5.7 TA = +25oC 3.15 3.3 3.45 5.65 3.6 2.85 3 3.15 VDD (V) 3.3 3.45 3.6 VDD (V) IDD ADC vs. VDD IDD FASTCOMP vs. VDD toc03 2.85 toc04 2.48 2.825 2.45 2.42 IDD FASTCOMP(mA) IDD ADC(mA) 2.8 2.775 2.75 2.725 2.7 TA = +25oC 2.85 3 3.15 3.3 3.45 2.39 2.36 2.33 2.3 3.6 TA = +25oC 2.85 3 3.15 VDD (V) IDD FASTCOMP vs. VDD toc06 0 ADC INL (LSB) 2.45 2.42 IDD FASTCOMP(mA) 3.6 0.5 2.48 2.39 2.36 -0.5 -1 -1.5 -2 2.33 -2.5 TA = +25oC 2.85 3 3.15 VDD (V) www.maximintegrated.com 3.45 ADC INL vs. INPUT VOLTAGE toc04 2.3 3.3 VDD (V) 3.3 3.45 3.6 -3 TA = +25oC 0 0.2 0.4 0.6 0.8 1 1.2 INPUT VOLTAGE (V) Maxim Integrated 12 DS4830A Optical Microcontroller Typical Operating Characteristics (continued) (TA = +25C, unless otherwise noted.) DAC INL vs. DAC SETTING DAC DNL vs. DAC SETTING toc07 0.4 0.3 3 2 0.1 DAC INL(LSB) DAC DNL(LSB) 0.2 0 -0.1 -0.2 1 0 -1 -2 -0.3 No Load, VDD = 3.3V, TA = +25oC -0.4 -0.5 toc08 4 0 1023 -3 2046 3069 -4 4092 No Load, 3.3V, TA = +25oC 0 1023 FAST COMP DNL vs. FAST COMP SETTING 0.4 0.4 FAST COMP INL (LSB) FAST COMP DNL (LSB) toc10 0 0.2 0.1 0 -0.1 -0.2 -0.3 0 127 254 -0.2 -0.4 -0.6 -0.8 -1 -1.2 3.3V, TA = +25oC -0.4 -1.4 381 508 635 FAST COMP SETTING www.maximintegrated.com 4092 0.2 0.3 -0.5 3069 FAST COMP INL vs. FAST COMP SETTING toc09 0.5 2046 DAC SETTING DAC SETTING (COUNT) 762 889 1016 3.3V, TA = +25oC 0 127 254 381 508 635 762 FAST COMP SETTING 889 1016 Maxim Integrated 13 DS4830A Optical Microcontroller GP14 MSDIO SHEN MSCL 28 27 26 25 GP15 30 29 MSDI MCS VDD PWM8 TOP VIEW PWM9 Pin Configuration 24 23 22 21 REFINA 31 20 GP13 DACPW0 32 19 GP12 DACPW1 33 18 GP11 DACPW2 34 17 GP10 DACPW3 35 16 REG18 DS4830A DACPW4 36 15 GP9 14 GP8 DACPW5 37 DACPW6 38 REFINB 39 13 GP7 EP + 12 GP6 11 GP5 6 7 8 9 10 VDD GP3 GP4 SDA 5 GP2 SCL 4 GP1 3 GP0 2 REG274 1 RST DACPW7 40 TQFN (5mm x 5mm) Pin Description PIN NAME INPUT STRUCTURE(S) OUTPUT STRUCTURE POWER-ON STATE 1 RST Digital None High Impedance RST -- -- -- -- 2 SCL Digital Open Drain High Impedance I2C Slave Clock SCL SPI SSPICK -- -- -- 3 SDA Digital Open Drain High Impedance I2C Slave Data SDA SPI SSPIDI -- -- -- 4 GP0 ADC/Digital Input Push-Pull, Extra Strong 55A Pullup ADC-S0 ADCD0P PWMALT0 -- P2.0 5 REG274 VREG None 2.74V 6 GP1 ADC/Digital Input Push-Pull, Extra Strong 55A Pullup ADC-S1 ADCD0N PWMALT1 REFOUT P2.1 7 VDD Voltage Supply, ADC Input None VDD ADC-VDD -- -- -- -- 8 GP2 SH Input, ADC Input None High Impedance ADC-S2 ADCSHP0 ADCD1P -- -- 9 GP3 SH Input, ADC Input None High Impedance ADC-S3 ADCSHN0 ADCD1N -- -- www.maximintegrated.com SELECTABLE FUNCTIONS (FIRST COLUMN IS DEFAULT FUNCTION) Only function is for bypass capacitors for 2.74V internal regulator PORT -- Maxim Integrated 14 DS4830A Optical Microcontroller Pin Description (continued) PIN NAME INPUT STRUCTURE(S) OUTPUT STRUCTURE POWER-ON STATE SELECTABLE FUNCTIONS (FIRST COLUMN IS DEFAULT FUNCTION) 10 GP4 ADC/Digital Input Push-Pull 55A Pullup JTAG TCK ADC-S4 ADCD2P -- P6.0 11 GP5 ADC/Digital Input Push-Pull 55A Pullup JTAG TDI ADC-S5 ADCD2N -- P6.1 12 GP6 ADC/Digital Input Push-Pull 55A Pullup ADC-S6 ADCD3P PWM2 SPI SSPIDO P2.2 13 GP7 ADC/Digital Input Push-Pull 55A Pullup ADC-S7 ADCD3N PWM3 SPI SSPICS P2.3 14 GP8 ADC/Digital Input Push-Pull 55A Pullup ADC-S8 ADCD4P -- -- P2.4 15 GP9 ADC/Digital Input Push-Pull 55A Pullup ADC-S9 ADCD4N -- -- P2.5 16 REG18 VREG None 1.8V 17 GP10 ADC/Digital Input Push-Pull 55A Pullup JTAG TMS ADCS10 ADCD5P -- P6.2 18 GP11 ADC/Digital Input Push-Pull 55A Pullup JTAG TDO ADCS11 ADCD5N -- P6.3 19 GP12 SH Input, ADC/Digital Input Push-Pull 55A Pullup ADC-S12 ADCSHP1 ADCD6P -- P0.0 20 GP13 SH Input, ADC/Digital Input Push-Pull 55A Pullup ADC-S13 ADCSHN1 ADCD6N -- P0.1 21 GP14 ADC/Digital Input Push-Pull 55A Pullup ADC-S14 ADCD7P SHEN1 -- P0.2 22 GP15 ADC/Digital Input Push-Pull 55A Pullup ADC-S15 ADCD7N -- -- P0.3 23 SHEN Digital Push-Pull 55A Pullup SHEN0 -- -- -- P6.4 I2C SPI MSPIDO PWMALT4 P1.0 Pin for 1.8V regulator bypass capacitor PORT -- 24 MSDIO Digital Push-Pull 55A Pullup 3-Wire Data MSDIO MSDA 25 MSDI Digital Push-Pull, Strong 55A Pullup -- -- SPI MSPIDI PWMALT5 P1.3 26 MSCL Digital Push-Pull 55A Pullup 3-Wire Clock MSCL I2C MSCL SPI MSPICK PWMALT6 P1.1 27 MCS Digital Push-Pull, Extra Strong 55A Pullup 3-Wire Chip Select MCS -- SPI MSPICS PWMALT7 P1.2 28 VDD Voltage Supply None VDD ADC-VDD -- -- -- -- 55A Pullup PWM9 -- -- -- P0.7 29 PWM9 Digital Push-Pull, Extra Strong 30 PWM8 Digital Push-Pull, Extra Strong 55A Pullup PWM8 -- -- -- P0.6 31 REFINA Reference, ADC/Digital Input Push-Pull 55A Pullup ADCREFINA -- -- -- P2.6 www.maximintegrated.com Maxim Integrated 15 DS4830A Optical Microcontroller Pin Description (continued) PIN 32 33 34 35 36 37 INPUT STRUCTURE(S) NAME DACPW0 OUTPUT STRUCTURE POWER-ON STATE Push-Pull High Impedance DAC0, FS = REFINA or Internal Reference PWM0 -- -- P0.4 Push-Pull High Impedance DAC1, FS = REFINA or Internal Reference PWM1 -- -- P0.5 Digital Push-Pull High Impedance DAC2, FS = REFINA or Internal Reference PWM2 CLKIN -- P6.5 Digital Push-Pull, Strong High Impedance DAC3, FS = REFINA or Internal Reference PWM3 -- -- P1.5 Push-Pull High Impedance DAC4, FS = REFINB or Internal Reference PWM4 I2C MSDAALT -- P1.6 Digital Push-Pull High Impedance DAC5, FS = REFINB or Internal Reference PWM5 I2C MSCLALT -- P1.7 High Impedance DAC6, FS = REFINB or Internal Reference PWM6 -- -- P6.6 Digital DACPW1 Digital DACPW2 DACPW3 DACPW4 Digital DACPW5 SELECTABLE FUNCTIONS (FIRST COLUMN IS DEFAULT FUNCTION) PORT 38 DACPW6 Digital Push-Pull, Strong 39 REFINB Reference, ADC/ Digital Input Push-Pull 55A Pullup ADCREFINB -- -- -- P1.4 DAC7, FS = REFINB or Internal Reference PWM7 -- -- P2.7 -- -- -- -- -- 40 DACPW7 Digital Push-Pull High Impedance -- EP Exposed Pad (Connect to GND) -- GND Note: Bypass VDD, REG274, and REG18 each with 1F X5R and 10nF capacitors to ground. All input-only pins and open-drain outputs are high impedance after VDD exceeds VBO and prior to code execution. Except for pins having DAC functions, pins configured as GPIO have a weak internal pullup at power-up. See the Selectable Functions table for more information. www.maximintegrated.com Maxim Integrated 16 DS4830A Optical Microcontroller Selectable Functions FUNCTION NAME DESCRIPTION ADC-D[7:0][P/N] Differential Inputs to ADC. Also used for sample/hold inputs. ADC-REFIN[A/B] REFINA and REFINB Monitor Inputs to ADC ADC-S[15:0] Single-Ended Inputs to ADC ADC-SH[P/N][1:0] Sample/Hold Inputs 1 and 0 ADC-VDD VDD Monitor Input to ADC DAC[7:0] Voltage DAC Outputs MSCL, MCS, MSDIO MSCL, MSDA MSCL-ALT, MSDA-ALT MSPICK, MSPICS, MSPIDI, MSPIDO P0.n, P1.n, P2.n, P6.n PWM[9:0] PWM-ALT[9:0] RST Maxim Proprietary 3-Wire Interface: MSCL (3-Wire Master Clock), MCS (Chip Select), MSDIO (3Wire Data). Used to control the Maxim family of high-speed laser drivers. I2C Master Interface: MSCL (I2C Master Clock), MSDA (I2C Master Data) I2C Master Interface: MSCL-ALT (I2C Master Clock), MSDA (I2C Master Data) SPI Master Interface: MSPICK (SPI Master Clock), MSPICS (Chip Select), MSPIDI (Master Data In), MSPIDO (Master Data Out) General-Purpose Inputs/Outputs. Can also function as edge interrupts. PWM Outputs PWM Alternate Outputs Used by JTAG and as Active-Low Reset for Device SCL, SDA I2C Slave Interface: SCL (I2C Slave Clock), SDA (I2C Slave Data). These also function as a password-protected programming interface. SHEN[1:0] Sample/Hold Trigger Inputs SSPICK, SSPICS, SSPIDI, SSPIDO TCK, TDI, TDO, TMS REFOUT www.maximintegrated.com SPI Slave Interface: SSPICK (Clock), SSPICS (Chip Select), SSPIDI (Data In), SSPIDO (Data Out). In SPI slave mode, the I2C slave interface is disabled. JTAG Interface Pins. Also includes RST. ADC Internal Reference Output Maxim Integrated 17 DS4830A Optical Microcontroller Block Diagram DS4830A 31 x GPIO COMMUNICATION I2C 400kHz SLAVE SPI SLAVE I2C 400kHz MASTER SPI MASTER 3W MASTER 10 x PWMs16-BIT 8 x DACs 12-BIT VOLTAGE INTERNAL REF 16-BIT CPU AT 10MHz 8K x 8 ROM 64K x 8 FLASH I2C BOOTLOADER 4K x 8 SRAM 32 x 16 LEVEL STACK POR WATCHDOG 2 x 16-BIT TIMERS 2 x HARDWARE 16-BIT MULTIPLIER AND 48-BIT ACCUMULATOR GP PORT1 x8 FAST COMPARATOR DAC 10-BIT 16-CHANNEL 625ksps SEQUENCER 1.225V VREF GP PORT0 x8 HIGH/LOW THRESHOLD COMPARISON AMUX GP PORT2 x8 PROGRAMMABLE INTERRUPTS DAC 10-BIT 1.8V REGULATOR VDD, DAC INTERNAL REF ADC x2 2.74V REGULATOR 20MHz OSCILLATOR PROGRAMMABLE INTERRUPTS 24-CHANNEL SEQUENCER WITH AVERAGING ADC 40ksps 13-BIT SAMPLE AND HOLD GP PORT6 x7 CS AMUX 18 SINGLE-ENDED/ 8 DIFFERENTIAL INPUTS TEMPERATURE SENSOR www.maximintegrated.com Maxim Integrated 18 DS4830A Detailed Description The following is an introduction to the primary features of the DS4830A optical microcontroller. More detailed descriptions of the device features can be found in the DS4830A User's Guide. Core Architecture The device employs a low-power, low-cost, high-performance, 16-bit RISC microcontroller with on-chip flash memory. It is structured on an advanced, 16 accumulatorbased, 16-bit RISC architecture. Fetch and execution operations are completed in one cycle without pipelining, since the instruction contains both the op code and data. The highly efficient core is supported by 16 accumulators and a 32-level hardware stack, enabling fast subroutine calling and task switching. Data can be quickly and efficiently manipulated with three internal data pointers. Multiple data pointers allow more than one function to access data memory without having to save and restore data pointers each time. The data pointers can automatically increment or decrement following an operation, eliminating the need for software intervention. Module Information Top-level instruction decoding is extremely simple and based on transfers to and from registers. The registers are organized into functional modules, which are in turn divided into the system register and peripheral register groups. Peripherals and other features are accessed through peripheral registers. These registers reside in modules 0-5. The following provides information about the specific module that each peripheral resides in: Module 0: Timer 1, GPIO Ports 0, 1, and 2 Module 1: I2C Master, GPIO Port 6, Supply Voltage Monitor Module 2: I2C Slave Module 3: Timer 2, MAC-Related Registers, Software Interrupt and General-Purpose Registers Module 4: ADC, Sample/Hold, Internal Temperature, 3-Wire Master, SPI Slave, DAC Module 5: Quick Trips, SPI Master, PWM Instruction Set The instruction set is composed of fixed-length, 16-bit instructions that operate on registers and memory locations. The instruction set is highly orthogonal, allowing www.maximintegrated.com Optical Microcontroller arithmetic and logical operations to use any register along with the accumulator. Special-function registers control the peripherals and are subdivided into register modules. Memory Organization The device incorporates several memory areas: 32KWords of flash memory for application program and constant data storage 2KWords of SRAM 4KWords of utility ROM contain a debugger and program loader 32-level stack memory for storage of program return addresses and application use The memory is implemented with separate address spaces for program memory, data memory and register space which also allows ROM, application code, and data memory into a single contiguous memory map. The device allows data memory to be mapped into program space, permitting code execution from data memory. In addition program memory may be mapped into data space, permitting code constants to be accessed as data memory. Figure 6 shows the DS4830A's memory map when executing from program memory space. Refer to the DS4830A User's Guide for memory map information when executing from data or ROM space. The incorporation of flash memory allows field upgrade of the firmware. Flash memory can be password protected with a 16-word key, denying access to program memory by unauthorized individuals. Utility ROM The utility ROM is a 4KWord block of internal ROM memory that defaults to a starting address of 8000h. The utility ROM consists of subroutines that can be called from application software, which include the following: In-system programming (bootstrap loader) over JTAG or I2C-compatible interfaces Callable routines for in-application flash programming Following any reset, execution begins in the utility ROM. The ROM software determines whether the program execution should immediately jump to location 0000h, the start of application code, or to one of the special routines mentioned. Routines within the utility ROM are firmware-accessible and can be called as subroutines by the application software. More information on the utility ROM contents is contained in the DS4830A User's Guide. Maxim Integrated 19 DS4830A Optical Microcontroller SYSTEM REGISTERS 8h AP 9h A Bh PFX Ch IP Dh SP Eh DPC PROGRAM MEMORY SPACE 00h DATA MEMORY (WORD MODE) FFFFh FFFFh FFFFh 8FFFh 9FFFh 8FFFh 4K x 16 UTILITY ROM DP Fh DATA MEMORY (BYTE MODE) 0Fh 8000h 7FFFh 8K x 8 UTILITY ROM 8000h 4K x 16 UTILITY ROM 8000h PERIPHERAL REGISTERS 0h M0 1h M1 2h M2 3h M3 4h M4 32K x 16 USER PROGRAM FLASH MEMORY M5 5h 00h 1Fh 00h 1Fh 32 x 16 STACK 0FFFh 001Fh 0010h 0000h PASSWORD 0000h 4K x 8 SRAM DATA 07FFh 0000h 2K x 16 SRAM DATA Figure 6. Memory Map When Program Is Executing from Flash Memory Password Some applications require protection against unauthorized viewing of program code memory. For these applications, access to in-system programming, in-application programming, or in-circuit debugging is prohibited until a password has been supplied. The password is defined as the 16 words of physical program memory at addresses 0010h-001Fh. A single password lock (PWL) bit is implemented in the device. When the PWL is set to 1 (power-on reset default) and the contents of the memory at addresses 0010h-001Fh are any value other than all FFh or 00h, the password is required to access the utility ROM, including in-circuit debug and in-system programming routines that allow reading or writing of internal memory. When PWL is cleared to 0, these utilities are fully accessible without the password. The password is automatically set to all ones www.maximintegrated.com following a mass erase. Mass erase can be performed without password match. Detailed information regarding the password can be found in the DS4830A User's Guide. Stack Memory A 16-bit, 32-level internal stack provides storage for program return addresses. The stack is used automatically by the processor when the CALL, RET, and RETI instructions are executed and interrupts serviced. The stack can also be used explicitly to store and retrieve data by using the PUSH, POP, and POPI instructions. On reset, the stack pointer, SP, initializes to the top of the stack (1Fh). The CALL, PUSH, and interrupt-vectoring operations increment SP, then store a value at the location pointed to by SP. The RET, RETI, POP, and POPI operations retrieve the value at SP and then decrement SP. Maxim Integrated 20 DS4830A Optical Microcontroller Programming The microcontroller's flash memory can be programmed by one of two methods: in-system programming and inapplication programming. These provide great flexibility in system design as well as reduce the life-cycle cost of the embedded system. Programming can be password protected to prevent unauthorized access to code memory. In-System Programming An internal bootstrap loader allows the device to be programmed over the JTAG or I2C compatible interfaces. As a result, system software can be upgraded in-system, eliminating the need for a costly hardware retrofit when software updates are required. The programming source select (PSS) bits in the ICDF register determine which interface is used for boot loading operation. The device supports JTAG and I2C as an interface corresponding to 00 and 01 bits of PSS, respectively as shown in Figure 7. In-Application Programming The in-application programming feature allows the microcontroller to modify its own flash program memory. This allows on-the-fly software updates in mission-critical applications that cannot afford downtime. Alternatively, it allows the application to develop custom loader software that can operate under the control of the application software. The utility ROM contains firmware-accessible flash programming functions that erase and program flash memory. These functions are described in detail in the DS4830A User's Guide. Register Set Sets of registers control most device functions. These registers provide a working space for memory operations as well as configuring and addressing peripheral registers on the device. Registers are divided into two major types: system registers (special purpose registers, or SPRs) and peripheral registers (special function registers, or SFRs). The system registers includes the ALU, accumulator registers, data pointers, interrupt vectors and control, and stack pointer. The peripheral registers define additional functionality and the functionality is broken up into discrete modules. Both the system registers and the peripheral registers are described in detail in the DS4830A User's Guide. ANY DEVICE RESET OCCURS WAIT FOR 320 SYSTEM CYCLES (32s). RESET I2C. SET PWL BIT. SET ROD BIT. RESET DEVICE. BEGIN BOOT ROM CODE EXECUTION AT 8000h. IS JTAG_SPE BIT SET? NO YES BOOTLOADER SET USING JTAG PROGRAMMER, FOLLOWED BY RESET OF DEVICE. WAITS FOR EXIT LOADER COMMAND FROM HOST ROM CODE ENABLES SLAVE I2C INTERFACE: ADDRESS IS 36h. SET BY WRITING F0h TO I2C SLAVE 34h. IS I2C_SPE BIT SET? YES SET PSS[1:0] = 01 NO JUMP TO USER CODE (FLASH) AT 0000h. Figure 7. In-System Programming www.maximintegrated.com Maxim Integrated 21 DS4830A Optical Microcontroller System Timing The device generates its 10MHz instruction clock (MOSC) and 20MHz peripheral clock internally. On power-up, oscillator's output (which cannot be accessed externally) is disabled until VDD rises above VBO. Once this threshold is reached, the output is enabled after approximately 1ms (tSU:MOSC), clocking the device as shown in Figure 8. System Reset The device features several sources that can be used to reset the DS4830A. The DAC and PWM outputs are maintained during execution of all resets except POR. Power-On Reset An internal power-on reset (POR) circuit is used to enhance system reliability. This circuit forces the device to perform a POR whenever a rising voltage on VDD climbs above VBO. When this happens the following events occur: All registers and circuits enter their reset state. The POR flag (WDCN.7) is set to indicate the source of the reset. Code execution begins at location 8000h when the reset condition is released. Brownout Detect/Reset The device features a brownout detect/reset function. Whenever the power monitor detects a brown-out condition (when VDD < VBO), it immediately issues a reset and stays in that state as long as VDD remains below VBO. Once VDD voltage rises above VBO, the device waits for tSU:MOSC before returning to normal operation, also referred to as CPU state. If a brownout occurs during this tSU:MOSC, the device again goes back to the brownout state. Otherwise, it enters into CPU state. In CPU state, the brownout detector is also enabled. On power-up, the device always enters brownout state first and then follows the above sequence. The reset issued by brownout is same as POR. Any action performed after POR also happens on brownout reset. All the registers that are cleared on POR are also cleared on brownout reset. External Reset Asserting the RST pin low causes the device to enter the reset state. Execution resumes at location 8000h after RST is released. Watchdog Timer Reset The watchdog timer provides a mechanism to reset the processor in the case of undesirable code execution. The watchdog timer is a hardware timer designed to be periodically reset by the application software. If the software operates correctly, the timer is reset before it reaches its maximum count. However, if undesirable code execution prevents a reset of the watchdog timer, the timer reaches its maximum count and resets the processor. The watchdog timer is controlled through 2 bits in the WDCN register (WDCN[5:4] : WD[1:0]). Its timeout period can be set to one of the four programmable intervals ranging from 212 to 221 system clock (MOSC) periods (0.410ms to 0.210s). The watchdog interrupt occurs at the end of this timeout period, which is 512 MOSC clock periods, or approximately 50s, before the reset. The reset generated by the watchdog timer lasts for 4 system clock cycles, which is 0.4s. Software can determine if a reset is caused by a watchdog timeout by checking the watchdog timer reset flag (WTRF) in the WDCN register. Execution resumes at location 8000h following a watchdog timer reset. The watchdog reset has the same effect as the external reset as far as the reset values of all registers are concerned. tSU:MOSC = ~1ms CORE CLOCK VBO VDD Figure 8. System Timing www.maximintegrated.com Maxim Integrated 22 DS4830A Internal System Reset The host can issue an I2C command (BBh) to reset the communicating device. This reset has the same effect as the external reset as far as the reset values of all registers are concerned. Also, an internal system reset can occur when the in-system programming is done (ROD = 1). This reset has the same effect as the external reset as far as the reset values of all registers are concerned. Software Reset The device UROM provides option to soft reset through the application program. The application program can jump to UROM code, which generates the internal system reset. This reset has the same effect as the internal system reset. Further information regarding various resets can be found in the DS4830A User's Guide. Programmable Timer The device features two general-purpose programmable timers. Various timing loops can be implemented using the timers. The timer can be used in two modes: freerunning mode and compare mode. The functionality of the timers can be accessed through three SFRs for each of the general purpose timers. GTCN is the general control register, GTV is the timer value register and GTC is the timer compare register. The timer SFRs are accessed in Module 0 and 3. Detailed information regarding the timer block can be found in the DS4830A User's Guide. Hardware Multiplier The hardware multiplier (a multiply-accumulate, or MAC module) is a very powerful tool, especially for applications that require heavy calculations. This multiplier is capable of executing the multiply, multiply-negate, multiply-accumulate, multiply-subtract operation for signed or unsigned operands in a single machine cycle. The MAC module uses 10 SFRs, mapped as register 0h-05h, 07h-09h and 0Eh in Module M3. System Interrupts Multiple interrupt sources are available to respond to internal and external events. The microcontroller architecture uses a single interrupt vector (IV) and single interrupt-service routine (ISR) design. For maximum flexibility, interrupts can be enabled globally, individually, or by module. When an interrupt condition occurs, its individual flag is set, even if the interrupt source is disabled at the local, module, or global level. Interrupt flags must be cleared www.maximintegrated.com Optical Microcontroller within the firmware-interrupt routine to avoid repeated interrupts from the same source. Application software must ensure a delay between the write to the flag and the RETI instruction to allow time for the interrupt hardware to remove the internal interrupt condition. Asynchronous interrupt flags require a one-instruction delay and synchronous interrupt flags require a two-instruction delay. When an enabled interrupt is detected, execution jumps to a user-programmable interrupt vector location. The IV register defaults to 0000h on reset or power-up, so if it is not changed to a different address, application firmware must determine whether a jump to 0000h came from a RST or interrupt source. Once control has been transferred to the ISR, the interrupt identification register (IIR) can be used to determine which module was the source of the interrupt. In addition to IIR, MIIR registers are implemented to indicate which particular function under a peripheral module has caused the interrupt. The device contains six peripheral modules, M0 to M5. An MIIR register is implemented in modules M1, M4, and M5. The MIIRs are 16-bit read only registers and all of them default to all zero on system reset. Once the module that causes the interrupt is singled out, it can then be interrogated for the specific interrupt source and software can take appropriate action. Interrupts are evaluated by application code allowing the definition of a unique interrupt priority scheme for each application. Interrupt sources are available from the watchdog timer, the ADC (including sample/holds and internal temperature), fast comparators, the programmable timers, SVM, the I2C-compatible master and slave interface, 3-wire, master and slave SPI, software interrupts, as well as all GPIO pins. I/O Port The device allows for most inputs and outputs to function as general purpose input and/or output pins. There are four ports: P0, P1, P2, and P6. Note that there is no port pin corresponding to P6.7. The 7th bit of port 6 is nonfunctional in all SFRs. Each pin is multiplexed with at least one special function, such as interrupts, ADC, DAC, PWM, or JTAG pins etc. The GPIO pins have Schmitt trigger receivers and full CMOS output drivers, and can support alternate functions. The ports can be accessed through SFRs (PO[0,1,2,6], PI[0,1,2,6], PD[0,1,2,6], EIE[0,1,2,6], EIF[0,1,2,6], and EIES[0,1,2,6]) in Modules 0 and 1 and each pin can be individually configured. The pin is either high impedance or a weak pullup when defined as an input, dependent on the state of the corresponding bit in the output register. Maxim Integrated 23 DS4830A Optical Microcontroller In addition, each pin can function as an external interrupt with individual enable, flag and active edge selection, when programmed as input. sequence mode) or run a short burst of conversions and enter a shut down mode to conserve power (singlesequence mode). The GPIO pins also having DAC function are by default high impedance. The I/O port SFRs are accessed in Module 0 and 1. Detailed information regarding the GPIO block can be found in the DS4830A User's Guide. In voltage mode there are four full-scale values that can be programmed. These values can be trimmed by modifying the associated gain registers (ADCG1, ADCG2, ADCG3, and ADCG4). By default these are set to 1.2V, 0.6V, 2.4V, and 6.55V full scale. DAC Outputs The device provides eight 12-bit DAC outputs with multiple reference options. An internal 2.5V reference is provided. There are also two selectable external references. REFINA pin can be selected as the full-scale reference for DAC0 to DAC3. REFINB pin can be selected as the full-scale reference for DAC4 to DAC7. The external reference can be between 1.0V to 2.5V. The DAC outputs are voltage buffered. Each DAC can be individually disabled and put into a low power power-down mode using DACCFG. If a DAC output is used during the lifetime of the DS4830A, the DAC must always be enabled to guarantee meeting the INL and offset specifications. If a pin is used for a DAC, it should be used only for the DAC function. The pin's function should not be switched between DAC and PWM or switched between DAC and GPIO. The DAC SFRs are accessed in Module 4. Detailed information regarding the DAC block can be found in the DS4830A User's Guide. Analog-to-Digital Converter, Sample/Hold The analog-to-digital converter (ADC) controller is the digital interface block between the CPU and the ADC. It provides all the necessary controls to the ADC and the CPU interface. The ADC uses a set of SFRs for configuring the ADC in desired mode of operation. The device contains a 13-bit ADC with an input mux, as shown in Figure 9. The mux selects the ADC input from 16 single-ended or eight differential inputs. Additionally, the channels can be configured to convert internal temperature, VDD, internal reference or REFINA/B. Two channels can be programmed to be sample/hold inputs. The internal channel is used exclusively to measure the die temperature. The SFR registers control the ADC. The ADC clock (ADCCLK) is derived from the system clock with division ratio defined by the ADC control register. The ADC sampling rate is approximately 40ksps for the fastest ADC clock (Core Clk/8). The device provides eight different ADC clock configurations to set different ADC clock setting. Refer to the ADC section of the DS4830A User's Guide for different ADC clock settings. In applications where extending the acquisition time is desired, the sample can be acquired over a prolonged period determined by the ADC control register. Each ADC channel can have its own configuration, such as differential mode select, data alignment select, acquisition extension enable and ADC gain select, etc. The ADC also has 24 (0 to 23) 16-bit data buffers for conversion result storage. The ADC data available interrupt flag (ADDAI) can be configured to trigger an interrupt following a predetermined number of samples. Once set, ADDAI can be cleared by software or at the start of a conversion process. The ADC controller provides options to average the ADC results of individual channel. The device provides 1, 4, 8, and 16 samples averaging configurations for each channel independently. The ADC's internal reference can be output at pin GP1. ADCCFG ADC-S[15:0] ADC-D[7:0] ADC-SHP[1:0] 13-BIT ADC PGA www.maximintegrated.com ADC-SHN[1:0] ADC-REFIN[A/B] ADC-VDD ADGAIN ADC-VREF_2.5V ADC When used in voltage input mode, the voltage applied on the corresponding channel (differential or single-ended) is converted to a digital readout. The ADC can be set up to continuously poll selected input channels (continuous- MUX ADC-TINT ADCONV (START CONVERSATION) Figure 9. ADC Block Diagram Maxim Integrated 24 DS4830A Optical Microcontroller Sample/Hold capacitance on the input node and the sample capacitor before sampling begins. The negative input pins are used to reduce ground offsets and noise. Pin combinations GP2-GP3 and GP12-GP13 can be used for sample/hold conversions if enabled in the SHCN register. These two can be independently enabled or disabled by writing a 1 or 0 to their corresponding bit locations in SHCN register. A data buffer location is reserved for each channel. When a particular channel is enabled, a sample of the input voltage is taken when a signal is issued on the SHEN pin, converted and stored in the corresponding data buffer. The ADC controller provides options to average the sample/hold results of individual channel. The device provides 1, 2, 4, and 8 samples averaging configurations for each channel independently. The sample/hold inputs can be used for monitoring the burst mode receive power signal in APD biasing and OLT applications using current mirror, as shown Figure 10. The two sample/hold channels can sample simultaneously on the same SHEN signal or different SHEN signals depending on the SH_DUAL bit in the SHCN SFR. Temperature Measurement The device provides an internal temperature sensor for die temperature monitoring which can be enabled independently by setting the appropriate bit locations in the TEMPCN register. Whenever a temperature conversion is complete the INTDAI is set. This can be configured to cause an interrupt, and can be cleared by software. The temperature measurement resolution is 0.0625C. The sample/hold data available interrupt flag (SHnDAI) can be configured to trigger an interrupt following sample completion. Once set, SHnDAI can be cleared by software. Each sample/hold circuit consists of a sampling capacitor, charge injection nulling switches, and a buffer. Also included is a discharge circuit used to discharge parasitic 3.3V <76V DS4830A PWM APD BIAS RC BSS123 APD FEEDBACK TO ADC MIRIN RD DS1842 3.3V CLAMP CURRENT LIMIT GND MIR1 IMIROUT/10 MIR2 IMIROUT/5 VCC DS4830A VINP CIN RIN MIROUT CIN IBIAS RA 1M APD VOLTAGE MONITOR TO ADC CS ADC VINP CIN ROSA 4 x RIN APD S/H A VINN RAGC 100 RB 15k CS CIN TIA CS MCU CORE S/H B CS VINN BURST MODE RSSI TRIGGER SEN GND CONTROL LOGIC Figure 10. Burst Mode RSSI Monitoring www.maximintegrated.com Maxim Integrated 25 DS4830A Optical Microcontroller The ADC controller provides options to average the internal temperature results. The device provides 1, 8, 16, and 32 samples averaging configurations for the internal temperature. the corresponding PWM output and selects the PWM polarity. The user can set the duty cycle and the frequency of each PWM output individually by configuring the corresponding DCYCn register and the PWMCFGn register. The ADC related SFRs are accessed in Module 1 and Module 4. For further detailed information regarding ADC can be found in the ADC section of the DS4830A User's Guide. The device allows delta sigma dithering for each PWM channel. The PWM outputs can be configured to be output on an alternate location using the configuration register. PWMDLY is a 16-bit register for providing starting delay on different PWM channels, and can be used to create multiphase PWM operation. PWM Outputs The device provides 10 independently configurable PWM outputs. Each PWM output's resolution can be configured from 7-bit to 16-bit independently. The PWM outputs are configured using three SFRs: PWMCN, PWMDATA, and PWNSYNC. Using PWMCN and PWMDATA, individual PWM channels can be programmed for unique Duty Cycles (DCYCn), configurations (PWMCFGn) and delays (PWMDLYn) where n represents the PWM channel number. Different channels can be synchronized using the PWMSYNC register. Doing so effectively brings the channels in phase by restarting the channels that are to be synchronized. The PWM SFRs are accessed in Module 5. Detailed information regarding the PWM block can be found in the DS4830A User's Guide. The PWM clock can be obtained from the core clock, peripheral clock or an external clock depending on CLK_SEL bits programmed in individual PWMCFG registers. The PWMCFGn register also enables/disables DS4830A CLKIN 16-BIT PWM PWM9 16-BIT PWM PWM8 Figure 11 shows how the PWM outputs can be used to control a TEC. Refer to Application Note AN5424: Thermoelectric Cooler Control Using the DS4830 Optical Microcontroller for further detailed information. DS1088EX 133MHz CLOCK VCC QBH 16-BIT PWM QAH P PWM1 QBL PWM0 ADC REFERENCE VREF LA TEC CB N P VA RSENSE LB SIDE B 16-BIT PWM VB SIDE A CA RTH QAL N VOLTAGE MONITOR R ADC THERMAL FEEDBACK CURRENT MONITOR Figure 11. TEC Application www.maximintegrated.com Maxim Integrated 26 DS4830A Optical Microcontroller Fast Comparator/Quick Trips The device supports 10-bit quick trip comparison functionality. The quick trips may be used to continuously monitor user defined channels in a round robin sequence. The quick trip controller allows the user to control the list of channels to monitor in the round-robin sequence. The quick trip (analog) performs two comparisons on any selected channel. 1) Comparison with a high threshold value. 2) Comparison with a low threshold value. Any comparison above the high threshold value or below the low threshold value causes a bit to set in the corresponding register. This bit can be used to trigger an interrupt. The threshold values are stored in 32 internal register (16 for low threshold settings and 16 for high threshold settings). The quick trip controller provides user defined threshold values for the quick trips. Because the quick trips and the ADC use the same input pins, the controller ensures that no collision takes place. The quick-trip-related SFRs are accessed in Module 5. Refer to the quick trip section of the DS4830A User's Guide for more information. I2C-Compatible Interface Modules The device provides two independent I2C-compatible interfaces, one is a master and another is a slave. I2C-Compatible Master Interface The device features an internal I2C-compatible master interface for communication with a wide variety of external I2C devices. The I2C-compatible master bus is a bidirectional bus using two bus lines, the serial data line (MSDA) and the serial clock line (MSCL). For the I2C-compatible master, the device has ownership of the I2C bus and drives the clock and generates the START and STOP signals. This allows the device to send data to a slave or receive data from a slave. The device has a configuration bit in the I2CCN_M register that allows the user to configure I2C master MSDA and MSCL pins to two different set of pins. PIN I2CCN_M.I2CM_ALT = 0 I2CCN_M.I2CM_ALT = 1 MSDA P1.0 P1.6 MSCL P1.1 P1.7 www.maximintegrated.com Details can be found in the I2C master section of the DS4830A User's Guide. I2C-Compatible Slave Interface The device also features an internal I2C-compatible slave interface for communication with a host. Furthermore, the device can be in system programmed (bootloaded) through the I2C-compatible slave interface. The two interface signals used by the I2C slave interface are SCL and SDA. For the I2C-compatible slave interface, the device relies on an externally generated clock to drive SCL and responds to data and commands only when requested by the I2C master device. The I2C-compatible slave interface is open-drain and requires external pull up resistors. The device supports four slave addresses. Each slave address has dedicated 8-byte transmit page and all slave addresses share common 8-byte receive FIFO. SMBus Timeout Both the I2C-compatible slave interfaces can work in SMBus-compatible mode for communication with other SMBus devices. To achieve this, a 30ms timer has been implemented on the I2C-compatible slave interface to make the interface SMBus-compatible. The purpose of this timer is to issue a timeout interrupt and thus the firmware can reset the I2C-compatible slave interface when the SCL is held low for longer than 30ms. The timer only starts when none of the following conditions is true: 1) The I2C-compatible slave interface is in the idle state and there is no communication on the bus. 2) The I2C-compatible slave interface is not working in SMBus-compatible mode. 3) The SCL logic level is high. 4) The I2C-compatible slave interface is disabled. When a timeout occurs, the timeout bit is set and an interrupt is generated, if enabled. The I2C master related SFRs are accessed in Module 1. The I2C slave related SFRs are accessed in Module 2. Details can be found in the I2C master and slave section of the DS4830A User's Guide. Maxim Integrated 27 DS4830A Serial Peripheral Interface Module The device supports master and slave SPI interfaces. The SPI provides an independent serial communication channel to communicate synchronously with peripheral devices in a multiple master or multiple slave system. The interface allows access to a four-wire, full-duplex serial bus, and can be operated in either master mode or slave mode. Collision detection is provided when two or more masters attempt a data transfer at the same time. The maximum data rate of the SPI is 1/4 the system reference clock frequency for slave mode and 1/2 the system clock frequency for master mode. The SPI uses the following four interface signals: Master In-Slave Out. This signal is an output from a slave device, SSPIDO, and an input to the master device, MSPIDI. It is used to serially transfer data from the slave to the master. Data is transferred most significant bit (MSB) first. The slave device places this pin in an input state with a weak pullup when it is not selected. Master Out-Slave In. This signal is an output from a master device, MSPIDO, and an input to the slave devices, SSPIDI. It is used to serially transfer data from the master to the slave. Data is transferred MSB first. SPI Clock. This serial clock is an output from the master device, MSPICK, and an input to the slave devices, SSPICK. It is used to synchronize the transfer of data between the master and the slave on the data bus. Slave Select. The slave-select signal is an input to enable the SPI module in slave mode, SSPICS, by a master device. The SPI module supports configuration of an active SSPICS state through the slave-active select. Normally, this signal has no function in master mode and its port pin can be used as a general-purpose I/O. However, the SSEL can optionally be used as mode fault detection in master mode. SPI Master Interface The master mode is used when the device's SPI controls the data transmission rates and data format. The SPI is placed in master mode by setting the master mode bit (MSTM). Only an SPI master device can initiate a data www.maximintegrated.com Optical Microcontroller transfer. Writing a data character to the SPI data buffer (SPIB), when in master mode, starts a data transfer. The SPI master immediately shifts out the data serially on MSPIDO, MSB first, while providing the serial clock on the MSPICK output. New data is simultaneously gated in on MSPIDI into the least significant bit (LSB) of the shift register. At the end of a transfer, the received data is loaded into the data buffer for reading, and the SPI transfer complete flag (SPIC) is set. If SPIC is set, an interrupt request is generated to the interrupt handler, if enabled. SPI Slave Interface Slave mode is used when the SPI is controlled by another peripheral device. The SPI is in slave mode when an internal bit (MSTM) is cleared to logic 0. In slave mode, the SPI is dependent on the SPICK sourced from the master to control the data transfer. The SPICK input frequency should not be greater than the system clock frequency of the slave device divided by 4. The SPI master transfers data to a slave on the SSPIDI, MSB first, the selected slave device simultaneously transfers the contents of its shift register to the master on the SSPIDO, also MSB first. Data received from the master replaces data in the slave's shift register at the completion of a transfer. Just like in the master mode, received data is loaded into the read buffer and the SPIC is set at the end of the transfer. Setting the SPIC flag may cause an interrupt if enabled. The SPI master-related SFRs are accessed in Module 5. The SPI slave-related SFRs are accessed in Module 4. Details can be found in the SPI section of the DS4830A User's Guide. 3-Wire Interface Module The device controls 3-wire slave devices like the MAX3798 and MAX3799 over a proprietary 3-wire interface. The device acts as the 3-wire master, initiating communication with and generating the clock for the 3-wire slave. It is a 3-pin interface consisting of MSDIO (a bidirectional data line), an MSCL clock signal, and an MCS chip-select output (active high). The 3-wire master-related SFRs are accessed in Module 4. Detailed information regarding the 3-wire interface block can be found in the DS4830A User's Guide. Maxim Integrated 28 DS4830A Optical Microcontroller In-Circuit Debug Embedded debugging capability is available through the JTAG-compatible test access port (TAP). Embedded debug hardware and embedded ROM firmware provide in-circuit debugging capability to the user application, eliminating the need for an expensive in-circuit emulator. Figure 12 shows a block diagram of the in-circuit debugger. The in-circuit debug features include the following: Applications Information Power-Supply Decoupling Hardware debug engine To achieve the best results when using the DS4830A, decouple the VDD power supply with a 0.1F X5R capacitor. Use a high-quality, ceramic, surface-mount capacitor if possible. Surface-mount components minimize lead inductance, which improves performance, and ceramic capacitors tend to have adequate high-frequency response for decoupling applications. Set of registers able to set breakpoints on register, code, or data accesses (ICDA, ICDB, ICDC, ICDD, ICDF, ICDT0, and ICDT1) Decouple the REG274 and REG18 pins using 1F X5R and 10nF capacitors (one each/per output). Note: Do not use either of these pins for external circuitry. Set of debug service routines stored in the utility ROM The embedded hardware debug engine is an independent hardware block in the microcontroller. The debug engine can monitor internal activities and interact with selected internal registers while the CPU is executing user code. Collectively, the hardware and software features allow two basic modes of in-circuit debugging: Background mode allows the host to configure and set up the in-circuit debugger while the CPU continues to execute the application software at full speed. Debug mode can be invoked from background mode. Debug mode allows the debug engine to take control of the CPU, providing read/write access to internal registers and memory, and single-step trace operation. Additional Documentation Designers must have three documents to fully use all the features of this device. This data sheet contains pin descriptions, feature overviews, and electrical specifications. Errata sheets contain deviations from published specifications. User guides offer detailed information about device features and operation. The following documents can be downloaded from www.maximintegrated.com/DS4830A. The DS4830A data sheet, which contains electrical/ timing specifications, package information, and pin descriptions. The DS4830A revision-specific errata sheet, if applicable. The DS4830A User's Guide, which contains detailed information and programming guidelines for core features and peripherals. DS4830A Development and Technical Support DEBUG SERVICE ROUTINES (UTILITY ROM) Maxim Integrated and third party suppliers provide a variety of highly versatile, affordably priced development tools for this microcontroller, including the following: CPU DEBUG ENGINE TMS TCK TDI TDO TAP CONTROLLER Figure 12. In-Circuit Debugger www.maximintegrated.com CONTROL BREAKPOINT ADDRESS DATA Compilers (C and assembly) In-circuit debugger Integrated development environments (IDEs) Serial-to-JTAG converters for programming and debugging USB-to-JTAG converters for programming and debugging A partial list of development tool vendors can be found at www.maximintegrated.com/MAXQ_tools. Go to www.maximintegrated.com/support for additional technical support. Maxim Integrated 29 DS4830A Optical Microcontroller Typical Application Circuit VCC (+3.3V) VCCT 25 VSEL TOUTA MD DFB 25 25 SCL MSCL TOUTC SDA MSDIO VOUT CSEL VCCT VSEL MCS ALT MASTER I2C MODE_DEF2 (SDA) MODE_DEF1 (SCL) ROSA 13-BIT ADC R2 MAX3948 DFB BIAS MONITOR SCL 25 SLAVE I2 C TOUTA MD 25 DS4830A R1 MAX3948 TOUTC SDA VOUT CSEL VCCT VSEL RSSI MONITOR TOUTA MD R3 MAX3948 DFB SCL 25 25 TOUTC SDA VOUT CSEL VCCT VSEL TOUTA MD MAX3948 DFB SCL 25 www.maximintegrated.com TOUTC SDA VOUT CSEL Maxim Integrated 30 DS4830A Optical Microcontroller Ordering Information PART TEMP RANGE PIN-PACKAGE DS4830AT+ -40C to +85C 40 TQFN-EP* DS4830AT+T -40C to +85C 40 TQFN-EP* +Denotes a lead(Pb)-free/RoHS-compliant package. T = Tape and reel. *EP = Exposed pad. www.maximintegrated.com Maxim Integrated 31 DS4830A Optical Microcontroller Revision History REVISION NUMBER REVISION DATE PAGES CHANGED 0 12/13 Initial release 1 1/17 Updated DAC Outputs section and Package Information table DESCRIPTION -- 2, 24 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated's website at www.maximintegrated.com. Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance. Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc. (c) 2017 Maxim Integrated Products, Inc. 32 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Maxim Integrated: DS4830AT+T