XX-XE88LC05 Data Sheet XE88LC05 Ultra Low-Power Microcontroller with ADC and DACs for Sensor Conditioning General Description Key product Features The XE88LC05 is an ultra low-power microcontroller unit (MCU) associated with a versatile analog-to-digital converter (ADC) including a programmable offset and gain pre-amplifier (PGA) and digital-to-analog converters (DACs). * * * * * * * XE88LC05 is available with on chip Multiple-Time-Programmable (MTP) Flash program memory. Applications * * * * * * * Internet connected appliances Portable, battery operated instruments Piezoresistive bridge sensors 4-20 mA bus sensors 0.5 - 4.5 V sensors HVAC control Motor control * * * * Ultra low-power MCU (300 A at 1 MIPS) Low-voltage operation (2.4 - 5.5 V supply voltage) 22 kB (8 kW) MTP, 512 B RAM Voltage or current output DACs Buffered signal-DAC (up to 16 bits) Buffered bias-DAC (up to 10 mA drive) Low-power, high resolution ZoomingADC * up to 10 bits zoom * up to 16 bits ADC 4 x 2 or 7 x 1 PGA-ADC input multiplexer Analog matrix switching RC and crystal oscillators 5 reset, 16 interrupt, 8 event sources Ordering Information Nomenclature: (XX marks pre-production samples) ;(/&0( TQFP64 package program memory M: MTP temperature I: -40 to 85 C Cool Solutions XEMICS SA, Switzerland. Tel: +41 32 720 51 70 Fax: +41 32 720 57 70 e-mail: info@xemics.com web: www.xemics.com Low-Power Microcontroller XX-XE88LC01 OscIn OscOut RESET Vmult Vreg Vss_Vreg Vss Vbat DAS_AO DAS_AI_m DAS_AI_p DAS_Out Detailed Pin Description 63 PA(0) 1 PA(1) 2 PA(2) 3 PA(3) 4 PA(4) 5 PA(5) 6 PA(6) 7 PA(7) PC(0) 8 PC(1) 10 PC(2) 11 PC(3) 12 PC(4) PC(5) 13 PC(6) 15 PC(7) 16 18 61 59 57 55 53 device type 51 48 47 XEMICS XE88LC05MI N9K1444 9920 9 14 46 AC_R(0) 45 AC_R(1) 44 AC_A(0) 43 AC_A(1) 42 AC_A(2) 41 AC_A(3) 40 AC_A(4) 39 AC_A(5) 38 AC_A(6) 37 AC_A(7) 36 AC_R(2) 35 AC_R(3) production lot identification packaging date DAB_AI_p DAB_AO_p TEST DAB_AI_m DAB_R_m 33 30 DAB_AO_m 28 DAB_Out 26 DAB_R_p 24 PB(7) PB(6) PB(5) 22 PB(3) PB(4) 20 PB(2) PB(1) PB(0) 34 Pinout of the XE88LC05 in TQFP64 package Position Function name Pin Second function name 1 PA(0) testin Input 2 PA(1) testck Input 3 PA(2) Input Type 4 PA(3) Input 5 6 7 8 9 10 11 12 13 14 15 16 PA(4) PA(5) PA(6) PA(7) PC(0) PC(1) PC(2) PC(3) PC(4) PC(5) PC(6) PC(7) Input Input Input Input Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output 17 PB(0) testout Input/Output/Analog Description Input of Port A/ Data input for test and MTP programming/ Counter A input Input of Port A/ Data clock for test and MTP programming/ Counter B input Input of Port A/ Counter C input/ Counter capture input Input of Port A/ Counter D input/ Counter capture input Input of Port A Input of Port A Input of Port A Input of Port A Input-Output of Port C Input-Output of Port C Input-Output of Port C Input-Output of Port C Input-Output of Port C Input-Output of Port C Input-Output of Port C Input-Output of Port C Input-Output-Analog of Port B/ Data output for test and MTP programming/ PWM output Table 1.2: Pin-out of the XE88LC05 in TQFP64 XX/D010-060 Product Preliminary Specification Page 2 Low-Power Microcontroller XX-XE88LC01 Pin Second function name Position Function name 18 PB(1) 19 PB(2) 20 PB(3) SOU Input/Output/Analog 21 PB(4) SCL Input/Output/Analog 22 PB(5) SIN Input/Output/Analog 23 PB(6) Tx Input/Output/Analog 24 PB(7) Rx Input/Output/Analog 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47-50 51 52 53 54 55 56 57 58 59 60 61 DAB_R_p DAB_R_m DAB_Out DAB_AO_p DAB_AO_m DAB_AI_p DAB_AI_m 62 OscOut ptck Analog/Input 63 OscIn ck_cr Analog/Input 64 - TEST/Vhigh Type Input/Output/Analog Input/Output/Analog Vhigh AC_R(3) AC_R(2) AC_A(7) AC_A(6) AC_A(5) AC_A(4) AC_A(3) AC_A(2) AC_A(1) AC_A(0) AC_R(1) AC_R(0) DAS_Out DAS_AI_p DAS_AI_m DAS_AO Vbat Vss Vss_Reg Vreg Vmult RESET Analog Analog Analog Analog Analog Analog Analog Not connected Special Not connected Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Not connected Analog Analog Analog Analog Power Power Power Analog Not connected Analog Input - Description Input-Output-Analog of Port B/ PWM output Input-Output-Analog of Port B Input-Output-Analog of Port B, Output pin of USRT Input-Output-Analog of Port B/ Clock pin of USRT Input-Output-Analog of Port B/ Data input or input-output pin of USRT Input-Output-Analog of Port B/ Emission pin of UART Input-Output-Analog of Port B/ Reception pin of UART Positive reference of bias DAC Negative reference of bias DAC Output of bias DAC Highest potential output of bias DAC buffer Lowest potential output of bias DAC buffer Positive input of bias DAC buffer Negative input of bias DAC buffer Spare pins to be connected to negative power supply Test mode/High voltage for MTP programming Spare pins to be connected to negative power supply Highest potential node for 2nd reference of ADC Lowest potential node for 2nd reference of ADC ADC input node ADC input node ADC input node ADC input node ADC input node ADC input node ADC input node ADC input node Highest potential node for 1st reference of ADC Lowest potential node for 1st reference of ADC Spare pins to be connected to negative power supply Output of signal DAC Positive input of signal DAC buffer Negative input of signal DAC buffer Output of signal DAC buffer Positive power supply Negative power supply, connected to substrate Digital negative power supply, must be equal to Vss Regulated supply Spare pins to be connected to negative power supply Pad for optional voltage multiplier capacitor Reset pin (active high) Connection to Xtal/ Peripheral clock for test and MTP programming Connection to Xtal/ CoolRISC clock for test and MTP programming Do not connect, or VSS Table 1.2: Pin-out of the XE88LC05 in TQFP64 XX/D010-060 Product Preliminary Specification Page 3 Low-Power Microcontroller XX-XE88LC01 XE88LC05xI Electrical Characteristics Operation conditions min ROM version MTP version CPU running at 1 MIPS CPU running at 32 kHz on Xtal, RC off CPU halt, timer on Xtal, RC off CPU halt, timer on Xtal, RC ready CPU halt, Xtal off timer on RC at 100 kHz CPU halt, ADC 12 bits at 4 kHz CPU halt, ADC 12 bits at 4 kHz, Current requirement PGA gain 100 CPU at 1 MIPS, ADC 12 bits and DAC 10 bits at 4 kHz CPU at 1 MIPS, ADC 12 bits and DAC 10 bits at 4 kHz, PGA gain 10 CPU at 1 MIPS, ADC 12 bits and DAC 10 bits at 4 kHz, PGA gain 100 CPU at 1 MIPS, ADC 12 bits and DAC 10 bits at 4 kHz, PGA gain 1000 Voltage level detection Prog. voltage Erase time MTP Write/Erase cycles Data retention 2.4 2.4 Power supply typ 10.3 10 10 3 100 max Unit 5.5 5.5 V V 310 uA 1 10 uA 1 1 uA 1 1.7 uA 1 1.4 uA 1 200 uA 1,4 250 uA 1,4 660 uA 1,3,4 685 uA 1,3,4 710 uA 1,3,4 785 uA 1,3,4 15 uA 10.8 30 V s year Remarks 5 2 Current requirement of the XE88LC05 Note: Note: Note: Note: Note: 1) Power supply: 2.4 V - 5.5 V, at 27C; min voltage of XX version may be higher, max frequency of current XX version is 2 MHz 2) Temperature < 85C 3) Output not loaded. 4) Current requirement can be divided by a factor of 2 or 4 by reducing the speed accordingly. 5) More cycles possible during development, with restraint retention XX/D010-060 Product Preliminary Specification Page 4 Low-Power Microcontroller XX-XE88LC01 CPU The XE88LC05 CPU is a low power RISC core. It has 16 internal registers for efficient implementation of the C compiler. Its instruction set is made of 35 generic instructions, all coded on 22 bits, with 8 addressing modes. All instructions are executed in one clock cycle, including conditional jumps and 8x8 multiplication. A complete tool suite for development is available from XEMICS, including programmer, C-compiler, assembler, simulator, linker, all integrated in a modern and efficient graphical user interface. Memory organisation The CPU uses a Harvard architecture, so that memory is organised in two separated fields: program memory and data memory. As both memory are separated, the central processing unit can read/write data at the same time it loads an instruction. Peripherals and system control registers are mapped on data memory space. Program memory 8k instructions Data address bus Program address bus Program memory is made in one page (program page full size is 65'536 instructions). Data is made of several 256 bytes pages. RAM 512 Bytes CPU Peripherals CPU Instruction pipeline registers 22 bits wide Registers 8 bits wide Memory organization Program memory The program memory is implemented as Multiple Time Programmable (MTP) Flash memory. The power consumption of MTP is linear with the access frequency (no significant static current). Memory sizes: * Flash MTP: 8192 x 22 bits (= 22 kBytes) block size address MTP 8192 x 22 H0000 - H1FFF Program addresses XX/D010-060 Product Preliminary Specification Page 5 Low-Power Microcontroller XX-XE88LC01 Data memory The data memory is implemented as static Random-Access Memory (RAM). The size is 512 x 8 bits plus 8 low power registers that require very low current when addressed, programs using these registers instead of RAM will spare even more current. Note: The registers in Data memory are not related to the CPU registers. block size address LP RAM RAM 8x8 512 x 8 H0000 - H0007 H0080 - H027F RAM addresses Peripherals mapping block size address LP RAM System control Port A Port B Port C Port D MTP Event Interrupts control reserved UART Counters Zooming ADC Reserved DACs Other (VLD) RAM1 RAM2 RAM3 8x8 16x8 8x8 8x8 4x8 4x8 4x8 4x8 8x8 8x8 8x8 8x8 8x8 12x8 8x8 H0000-H0007 H0010-H001F H0020-H0027 H0028-H002F H0030-H0033 H0034-H0037 H0038-H003B H003C-H003F H0040-H0047 H0048-H004F H0050-H0057 H0058-H005F H0060-H0067 H0068-H0073 H0074-H007B 4x8 H007C-H007F 128x8 256x8 128x8 H0080 - H00FF H0100 - H01FF H0200 - H027F Page Page 0 Page 1 Page 2 Peripherals addresses Peripherals The XE88LC05 includes usual microcontroller peripherals and some other blocks more specific to low-voltage or mixed-signal operation. They are 3 parallel ports, one input port (A), one IO and analog port (B) with analog switching capabilities and one general purpose IO port (C). A watchdog is available, connected to a prescaler. Four 8-bit counters, with capture, PWM and chaining capabilities are available. The UART can handle transmission speeds as high as 38kbaud. Low-power low-voltage blocks include a voltage level detector, two oscillators (one internal 0.1-4 MHz RC oscillator and a 32 kHz crystal oscillator) and a specific regulation scheme that largely uncouples current requirement from external power supply (usual CMOS ASICs require much more current at 5.5 V than they need at 2.4 V. This is not the case for the XE88LC05). Analog blocks: acquisition path, bias DAC and signal DAC are defined below. All these blocks operate on 2.4 - 5.5 V power supply range. XX/D010-060 Product Preliminary Specification Page 6 Low-Power Microcontroller XX-XE88LC01 Zooming ADC Principle The fully differential acquisition chain is formed of a programmable gain (0.5 - 1000) and offset amplifier and a programmable speed and resolution ADC (example: 12 bits at 4 kHz, 16 bits at 1 kHz). It can handle inputs with very low full scale signal and large offsets. UHIHUHQFH VHOHFWLRQ $&B5 $&B5 $&B5 $&B5 $&B$ $&B$ $&B$ $&B$ $'& $&B$ $&B$ $&B$ JDLQ $&B$ JDLQ RIIVHW JDLQ PRGH RIIVHW RXWSXW FRGH LQSXW VHOHFWLRQ Acquisition channel block diagram Input selection is made from 1 of 4 differential pair or 1 of seven single signal versus AC_A(0). Reference is chosen from the 2 differential references. Acquisition path offset can be suppressed by inverting input polarity. The gain of each amplifier is programmed individually. Each amplifier is powered on and off on command to minimize the total current requirement. All blocks can be set to low frequency operation and lower their current requirement by a factor 2 or 4. The ADC can run continuously (end of conversion signalled by an interrupt, event or by pooling the ready bit), or it can be started on request. Input signal multiplexing There are 8 inputs named AC_A[0] to AC_A[7]. Inputs can be used either as four differential channels (Vin1=AC_A[1]-AC_A[0], ..., Vin4=AC_A[7]-AC_A[6]) or AC_A[0] can be used as a common reference, providing 7 signal paths (AC_A[1]-AC_A[0], ..., AC_A[7]-AC_A[0]), all referred to AC_A[0]. Default input is Vin1. On top of these settings, inputs can be crossed or not. All multiplexing combinations are summarised in the following table (see Table 1.3) : uni/bi-polar AMUX(4) sign AMUX(3) AMUX(2) 0 unused 1 unused 0 channel selection AMUX(1) AMUX(0) 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 selected differential input VINVIN+ A(0) A(2) A(4) A(6) A(1) A(3) A(5) A(7) A(1) A(3) A(5) A(7) A(0) A(2) A(4) A(6) Table 1.3: AMUX selection XX/D010-060 Product Preliminary Specification Page 7 Low-Power Microcontroller XX-XE88LC01 uni/bi-polar AMUX(4) sign AMUX(3) AMUX(2) channel selection AMUX(1) AMUX(0) 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 selected differential input VINVIN+ A(0) A(0) A(0) A(0) A(0) A(0) A(0) A(0) A(0) A(1) A(2) A(3) A(4) A(5) A(6) A(7) A(0) A(1) A(2) A(3) A(4) A(5) A(6) A(7) A(0) A(0) A(0) A(0) A(0) A(0) A(0) A(0) Table 1.3: AMUX selection Input reference multiplexing One must select one of two differential signal as reference signal (Vref1=AC_R[1]-AC_R[0], Vref2=AC_R[3]AC_R[2]). Default is Vref1. Amplifier chain The 3 stages transfer functions are: VD3 = GD3.VD2 - GDoff3.Vref VD2 = GD2.VD1 - GDoff2.Vref VD1 = GD1.Vin where: Vin=Selected input voltage Vref=Selected reference voltage VD1=Differential voltage at the output of first amplifier VD2=Differential voltage at the output of second amplifier VD3=Differential voltage at the output of third amplifier GD1=Differential gain of stage 1 GD2=Differential gain of stage 2 GD3=Differential gain of stage 3 GDoff2= Offset gain of stage 2 GDoff3=Offset gain of stage 3 and therefore the whole transfer function is: Vout of PGA = VD3 = GD3.GD2.GD1.Vin - (GDoff3 + GDoff2.GD3).Vref Note: Note: Note: As the offset compensation is realized together with the amplification on the same summing node, the only voltages that have to stay within the supplies are Vref and the VDi. GDi . VDi-1 and GDoffi . Vref can be larger without any saturation. All stages use a fully differential architecture and all gain and offset settings are realized with ratios of capacitors. As the ADC also provides a gain (2 nominal), the total chain transfer function is: Data _ out = 2 GD3 GD2 GD1 Vin - 2 (GDoff 3 + GDoff 2 GD3) Vref Each stage is called PGAi. Features of these stages are: XX/D010-060 Product Preliminary Specification Page 8 Low-Power Microcontroller XX-XE88LC01 * * * * Gain can be chosen between 1 and 10 (between 0 and 10 for PGA3) Offset can be compensated for in PGA2 (a little) and in PGA3 (to a large extent) Granularity of settings is rough for PGA1, medium for PGA2, fine for PGA3 Zero, one or two or three of the PGA stages can be used. A functional example of one of the stages is given on tag 1.1. Vref Vout Vin Figure 1.1: PGA stage principle implementation 1.1.1 PGA 1 symbol description min GD1 GD_preci GD_TC fs Zin1 Zin1p PGA1 Signal Gain Precision on gain settings Temperature dependency of gain settings input sampling frequency Input impedance Input impedance for gain 1 1 -5 -5 VN1 Input referred noise typ max unit Comments 10 +5 +5 512 % ppm/C kHz k k nV/ sqrt(Hz) GD1 = 1 or 10 150 1500 18 1 1 2 Table 1.4: PGA1 Performances Note: Note: 1) Measured with block connected to inputs through AMUX block. Normalized input sampling frequency for input impedance is 512 kHz. This figure has to be multiplied by 2 for fs = 256 kHz and 4 for fs = 128 kHz. 2) Input referred rms noise is 10 uV per input sample. This corresponds to 18 nV/sqrt(Hz) for fs = 512 kHz. 1.1.2 PGA2 sym description min GD2 GDoff2 GDoff2_step GD_preci GD_TC fs Zin2 PGA2 Signal Gain PGA2 Offset Gain GDoff2(code+1) - GDoff2(code) Precision on gain settings Temperature dependency of gain settings Input sampling frequency Input impedance 1 -1 0.18 -5 -5 VN2 Input referred noise typ 0.2 max unit Comments 10 1 0.22 +5 +5 512 FS % ppm/C kHz k nV/ sqrt(Hz) GD2 = 1, 2, 5 or 10 150 36 valid for GD2 and GDoff2 1 2 Table 1.5: PGA2 Performances Note: 1) Measured with block connected to inputs through AMUX block. Normalized input sampling frequency for input impedance is 512 kHz. This figure has to be multiplied by 2 for fs = 256 kHz and 4 for fs = 128 kHz. XX/D010-060 Product Preliminary Specification Page 9 Low-Power Microcontroller XX-XE88LC01 Note: 2) Input referred rms noise is 26uV per sample.This corresponds to 36 nV/sqrt(Hz) max for fs = 512 kHz. 1.1.3 PGA3 sym description min GD3 GDoff3 GD3_step GDoff3_step GD_preci GD_TC fs PGA3 Signal Gain PGA3 Offset Gain GD3(code+1) - GD3(code) GDoff2(code+1) - GDoff2(code) Precision on gain settings Temperature dependency of gain settings Input sampling frequency 0 -5 0.075 0.075 -5 -5 Zin3 Input impedance 150 VN3 Input referred noise typ 0.08 0.08 max unit 10 5 0.085 0.085 +5 +5 512 FS % ppm/C kHz 36 Comments valid for GD3 and GDoff3 k 1 nV/ sqrt(Hz) 2 Table 1.6: PGA3 Performances Note: Note: 1) Measured with block connected to inputs through AMUX block. Normalized input sampling frequency for input impedance is 512 kHz. This figure has to be multiplied by 2 for fs = 256 kHz and 4 for fs = 128 kHz. 2) Input referred rms noise is 26uV per sample. This corresponds to 36 nV/sqrt(Hz) max for fs = 512 kHz. ADC 1.1.4 Input-Output relation The ADC block is used to convert the differential input signal into a 16 bits 2's complement output format. The output code corresponds to the ratio: Output code = Vin . Vref smax + 1 smax smax being the number of samples used to generate one output sample per elementary conversion. smax is set by OSR on RegACCfg0. Vref can be selected up to the power supply rails and must be positive. The 2's complement output code corresponding is given in hexadecimal notation by 8000 (negative full scale) and 7FFF (positive full scale). Code outside the range are saturated to the closest full scale value. The output code is normalized into a 16 bits format. First non significant bit is forced to 1, further non signifant bits are forced to 0. data register MSB RegACOutLSB RegACOutMSB bit 5 sign LSB bit 4 bit 12 bit 3 bit 11 bit 2 bit 10 bit 1 bit 9 1 bit 8 0 bit 7 0 bit 6 Table 1.7: Output code exemple, for 13 bits resolution (OSR: h11, NELCONV: h01) 1.1.5 Operation mode The mode can be either "on request" or "continuously running". In the "on request" mode, after a request, an initialization sequence is performed, then an algorithm is applied and an output code is produced. The converter is idle until the next request. In the "continuously running" mode, an internal conversion request is generated each time a conversion is finished, so that the converter is never idle. The output code is updated at a fixed rate corresponding to 1/Tout, with Tout being the conversion time. XX/D010-060 Product Preliminary Specification Page 10 Low-Power Microcontroller XX-XE88LC01 1.1.6 Conversion sequence The whole conversion sequence is basically made of an initialisation, a set of Nelconv elementary incremental conversions and finally a termination phase(NumCONV is set by 2 bits on RegACCfg0). The result is a mean of the results of the elementary conversions. 1 2 input sample smax 1 2 1st elementary conversion START conversion index smax 1 2 2nd elementary conversion 1 elementary conversion 2 smax elementary conversion NumConv-1 END NumConv Figure 1.2: Conversion sequence. smax is the oversampling rate. Note: NumCONV elementary conversions are performed, each elementary conversion being made of smax input samples. NumCONV = 2NELCONV smax = 8*2OSR During the elementary conversions, the operation of the converter is the same as in a sigma delta modulator. During one conversion sequence, the elementary conversions are alternatively performed with direct and crossed PGA-ADC differential inputs, so that when two elementary conversions or more are performed, the offset of the converter is cancelled. Note: The sizing of the decimation filter puts some limits on the total number of conversions and it is not possible to combine the maximum number of elementary conversions with the maximum oversampling (see the Nelconv*smax specification). Some additional clock cycles (NINIT+NEND) clock cycles are required to initiate and terminate the conversion properly. 1.1.7 Conversion duration The conversion time is given by : TOUT = (2NELCONV *(8*2OSR +1) + (NINIT + NEND)) / fs 1.1.8 Resolution As far as it is not limited by thermal noise and internal registers width, the resolution is given by : Resolution (in bits) = 6 + 2*OSR + NELCONV 1.1.9 ADC performances sym description min VINR Resol NResol INL Input range Resolution Numerical resolution Integral non-linearity -0.5 12 typ max unit Comments 0.5 Vref bits bits LSB 1 4 1,3, LSB at 12bits 16 4 Table 1.8: ADC Performances XX/D010-060 Product Preliminary Specification Page 11 Low-Power Microcontroller XX-XE88LC01 sym description min max unit fs smax sampling frequency Oversampling Ratio Number of elementary conversions in incremental mode Number of periods for incremental conversion initialization Number of periods for incremental conversion termination 10 8 512 1024 kHz - 2 1 8 - 2 5 - 5 - NUMCONV Ninit Nend typ Comments Table 1.8: ADC Performances Note: Note: Note: Note: 1) Resolution specification also includes thermal noise and differential non-linearity (DNL) for a reference signal of 2.4 V. It is defined for default operating mode ( See "Default operation mode (not yet implemented)" on page 13.) 2) Only powers of 2 3) INL is defined as the deviation of the DC transfer curve from the best fit straight line. This specification holds over 100% of the full scale. 4) NResol is the maximal readable resolution of the digital filter. Input noise may be higher than NResol. Control part Starting a convention A conversion is started each time START or DEF is set. PGAs are reset after each writing operation to registers RegACCfg1 to RegACCfg5. When using the PGAs, one has to start the ADCs after a PGA common-mode stabilisation delay. This is done by writing bit START several cycles after PGA settings modification. Delay between PGA start and ADC start should be equivalent to smax number of cycles. End of a conversion The end of the conversion is marked by the return to zero of busy bit, and, if set, by the generation of ADC interrupt. Busy bit = 0 is not sufficient to denote the end of the conversion, as the ADC needs some clock cycles to set it to one at the conversion beginning. Only the transition from 1 to 0 denotes the end of conversion. For low power or low noise applications, one should prefer to use the interruption as the processor can go to HALT between conversion start and conversion end. Clocks generation Peripheral clock (psck) can be chosen among four prescaler clocks (bit FIN of RegACCfg2), see Table 1.10, derived from the XE8000 RC oscillator. The clock of the acquisition path (fs) is derived from the peripheral clock. fs = psck / 4 XX/D010-060 Product Preliminary Specification Page 12 Low-Power Microcontroller XX-XE88LC01 Acquisition of a sample no use default mode yes use PGA AND modifiy PGA no yes write in RegACCfg5 write in RegACCfg1-5 wait for PGA stable start ADC by writing RegACCfg0 wait for ADC ready read ADC results Figure 1.3: Acquisition flow Default operation mode (not yet implemented) The DEF bit (RegACCfg5) allows the use of the ADC in a default mode without any gain nor offset adjustment (see values in the right column of Table 1.10). This default mode is used in specifications to define resolution and INL. The only action to launch the operation of the peripheral is in this case to write a `x1xx xxxx' at address 111. VMUX and AMUX are written at the same time and are not reset to default value. BUSY is not affected. The only way to stop a running conversion before completion is to shut the ADC down writing `0000' in ENABLE (RegACCfg1). Registers Eight registers control this peripheral. Two registers are for the data output, six for peripheral general set-up. Registers are defined in Table 1.9 and Table 1.10. register data RegACOutLSB RegACOutMSB ADC_OUT_L ADC_OUT_H Table 1.9: Peripheral register memory map XX/D010-060 Product Preliminary Specification Page 13 Low-Power Microcontroller XX-XE88LC01 register RegACCfg0 RegACCfg1 RegACCfg2 RegACCfg3 RegACCfg4 RegACCfg5 data START NELCONV IB_AMP_ADC FIN PGA1_ GAIN reserved BUSY DEF OSR IB_AMP_PGA PGA2_GAIN CONT ENABLE PGA2_OFF reserved PGA3_GAIN PGA3_OFF AMUX VMUX Table 1.9: Peripheral register memory map Name Register rm description Default (reset and DEF mode) ADC_OUT(15:0) RegACOutLSB RegACOutMSB r data output 0000h AMUX(4:0) RegACCfg5 wr Selection of PGA inputs 00000 (reset only) BUSY RegACCfg5 CONT RegACCfg0 DEF RegACCfg5 ENABLE(3:0) RegACCfg1 FIN(1:0) RegACCfg2 IB_AMP_PGA(1:0) RegACCfg1 IB_AMP_ADC(1:0) RegACCfg1 NELCONV(1:0) RegACCfg0 OSR(2:0) RegACCfg0 wr PGA1_GAIN RegACCfg3 wr PGA2_GAIN(1:0) RegACCfg2 wr PGA2_OFF(3:0) RegACCfg2 wr PGA3_GAIN(6:0) RegACCfg3 wr PGA3_OFF(6:0) RegACCfg4 wr START RegACCfg0 wr0 `1' : conversion is in progress `0' : data is available `1' : continuous operation. wr `0' : one shot mode Default Operation bit wr0 `1': All registers but VMUX and AMUX are reset and default values are used `0': Normal operation bit3 : PGA3, bit2 : PGA2, bit1 : PGA1, bit 0 : ADC If a bit is `1', the block is powered. If not, the block is switched off and all internal wr digital signals are reset. Concerning the PGAs, ENABLE=0 means also that inputs and outputs are wired together and that the acquisition chain is not perturbed by the block. `00' : RC = psck = 4 fs `01' : RC / 2 = psck = 4 fs wr `10' : RC / 8 = psck = 4 fs `11' : RC / 32 = psck = 4 fs Rem: do not select an fs clock that is faster than 512 kHz. PGA amplifiers biasing current reduction factor `00' : current magnification factor = 0.25 wr `01' : current magnification factor = 0.5 `10' : current magnification factor = 0.75 `11' : current magnification factor = 1 ADC amplifiers biasing current reduction factor. wr Tuning identical to IB_AMP_PGA Number of elementary conversions wr `00' : 1 conversion, `01' : 2 conversions `10' : 4 conversions, `11' : 8 conversions r OverSampling Ratio. Defined as fs/fout. OSR = 8*2OSR(2:0). `000' : oversampling = 8, ..., `111' : oversampling = 1024 signal gain of first PGA stage (GD1) `1' : nominal gain is 10. `0' : nominal gain is 1 signal gain of second PGA stage (GD2) `11' : nominal gain is 10 `10' : nominal gain is 5 `01' : nominal gain is 2 `00' : nominal gain is 1 offset gain of second PGA stage (GDoff2) bit 3: offset sign (`0' : GDoff2 > 0, `1' : GDoff2 < 0) bits (2:0) : offset amplitude `01x1' : GDoff2 = 1.0 nominal, `0100' : GDoff2 = 0.8 nominal, `0011' : GDoff2 = 0.6 nominal, ..., `0000' : GDoff2 = 0.0 nominal, `1001'' : GDoff2 = -0.2 nominal, ..., `11x1' : GDoff2 = -1.0 nominal signal gain of third stage (GD3) GD3 = 0.08*PGA3_GAIN(6:0) Nominal values : 0 (`000 0000'), ..., 10 (`111 1000') offset gain of third stage (GDoff3) bit 6: offset sign (`0' : GDoff3 > 0, `1' : GDoff3 < 0) GDoff3 = 0.08*PGA3_OFF(5:0), maximum = 5.04 Nominal values : -5.04 (`111 1111'), 0 (`x00 0000'), +5.04 (`011 1111') writing a "1" in START bit restarts the ADC. It does not affect the PGAs. 0 0 N/A 0000 00 11 11 01 010 0 00 0000 000 1100 000 0000 0 Table 1.10: Peripheral register memory map, bits description XX/D010-060 Product Preliminary Specification Page 14 Low-Power Microcontroller XX-XE88LC01 Name Register rm TEST RegACCfg0 VMUX RegACCfg5 Default (reset and DEF mode) description reserved VREF selection multiplexer `0' : VREF0 is used, `1' : VREF1 is used wr 0 0 (reset only) Table 1.10: Peripheral register memory map, bits description DACs See XEMICS application note AN8000.03 for detailed information about the XE88LC05 DACs. Bias DAC The bias DAC is a low resolution (8 bits) DAC with a buffer perfectly adapted to sensor bridge bias. It can be used to bias a bridge in current (figure) or in voltage by choosing the pins connection. ;(/& XE88xx c o n t r o l D '$%B2XW '$%B$,P A '$%B$2S amp '$%B$2P '$%B$,S reference signal Current controlled bridge bias The bias DAC itself is built off a series of resistors which two extremes are available outside the chip, so that one can connect it to an external source when the output of the DAC should not be ratiometric to the power supply. XX/D010-060 Product Preliminary Specification Page 15 Low-Power Microcontroller XX-XE88LC01 Signal DAC The signal DAC is build around a programmable DAC and a buffer. It can generate fast (up to 64 kHz) or high resolution (resolution up to 16 bits) output. The output can be controlled in current or voltage. 4-20mA 9 UHJXODWRU XE88xx ;(/& 9EDW c o n t r o l D '$6B2XW A '$6B$,S '$6B$2 amp '$6B$,P 966 4-20mA loop including the circuit (and bridge) current consumption XX/D010-060 Product Preliminary Specification Page 16 Low-Power Microcontroller XX-XE88LC01 XE8000 Family Features The main characteristics of the XE8000 MCU family is * Ultra low power operation * Low voltage operation (1.2 V for the XE88LC04, XE88LC06 and XE88LC07, 2.4 V for the others) * High efficiency CPU * 1 instruction per clock cycle, for all instructions * 22 bits wide instructions * Integrated 8x8 -> 16 bits multiplier * All instructions on one page * 8 bits data bus * 8 addressing modes * MTP (multiple time programmable) memory available * Dual clock (X-tal and/or RC) * Each peripheral can be set on/off individually for minimal power consumption * UART * Watch dog * 4x8 bits timers with PWM ability * Advanced acquisition path * Fully differential analog signal path on signal and reference * 4x2 or 7x1 + 1 signal input * 2x2 reference input * 0.5 - 1000 programmable gain amplifier * Offset programmed over +- 10 full scale * 5 - 16 bits resolution ADC * Low speed modes with reduced bias current for minimal power consumption * Bias and signal DACs for resistive bridge sensing and analog output * Complete development tools using Windows95 or NT graphical interface * Assembler * ANSI-C compiler * Source level debugger * Current and memory usage monitoring (Profiler) * CPU Simulator * CPU Emulator XE8000HaCE * Programmer and starter kit (XE88LC01ProStart) * Hardware emulators (works with XE8000HaCE, in preparation) Family The XE8000 Family ultra low-power microcontroller is made of several members, all using the same microprocessor core and differing by the peripherals available. The XE88LC01 is a low power sensing microcontroller, based on the XE88LC03, with an advanced acquisition path including differential programmable gain amplifiers and a high resolution analog to digital converter. Its main applications are dataloggers and process control. The XE88LC02 is a low power sensing microcontroller, based on the XE88LC06 with the analog part of the XE88LC01, with an additional LCD driver. Its main applications are metering and dataloggers. TThe XE88LC03 is a low power, low voltage, general purpose microcontroller. Its main points are the very efficient CoolRISC core, the low voltage function and the real time clock. Its main applications are low voltage control and supervision. XX/D010-060 Product Preliminary Specification Page 17 Low-Power Microcontroller XX-XE88LC01 The XE88LC04 is a low power, low voltage, general purpose microcontroller, based on the XE88LC06, with an additional LCD driver. Its main points are the very efficient CoolRISC core, the low voltage function and the real time clock. Its main applications are low voltage control and supervision. The XE88LC05 is a low power sensing microcontroller, based on the XE88LC01, with analog outputs. Its main applications are piezoresistive sensors and 4 - 20 mA loops systems. The XE88LC06 is an improved XE88LC03, with 4 low power analog comparators. Its main applications are low voltage control and supervision. The XE88LC07 is a smaller and even lower power microcontroller, based on the XE88LC06, with less memory. XE88LC01 Supply voltage 2.4 - 5.5 V Max speed Operating temperature 2 MIPS -40 - 85 C XE88LC02 PWM Package TQFP44, die Availability yes XE88LC04 XE88LC05 1.2- 5.5 V for ROM 2.4 - 5.5 V 2.4 - 5.5 V 2.4 - 5.5 V 2.4 - 5.5 V for MTP 4 MIPS 2 MIPS 4 MIPS at 2.4 V 2 MIPS -40 - 85 C -40 - 85 C -40 - 85 C -40 - 85 C -40 - 125 C -40 - 125 C CoolRISC 816, CoolRISC 816, CoolRISC 816, CoolRISC 816, 22 bits 22 bits 22 bits 22 bits instructions instructions instructions instructions 8 bits data 8 bits data 8 bits data 8 bits data HW multiplier HW multiplier HW multiplier HW multiplier 8k Instruction 8k Instructions 8k Instructions 8k Instructions = 22 kB = 22 kB = 22 kB = 22 kB ROM or MTP ROM or MTP ROM or MTP ROM or MTP 768 + 8 Bytes 512 + 8 Bytes 768 + 8 Bytes 512 + 8 Bytes 8 input and 8 input and 8 input and 8 input and external interrupt external interrupt external interrupt external interrupt 8 input/output and 8 input/output and 8 input/output and 8 input/output and analog analog analog analog 8 input/output 4 to 8 input/output 4 to 8 input/output 8 input/output yes yes yes yes CoolRISC 816, 22 bits CPU instructions 8 bits data HW multiplier 8k Instructions Program memory = 22 kB ROM or MTP Data memory 512 + 8 Bytes 8 input and Port A external interrupt 8 input/output and Port B analog Port C 8 input/output Watchdog timer yes General purpose 4 x 8 bits 4 x 8 bits timers with PWM UART yes yes transition transition 2-3 wires serial detection detection interface + software + software Voltage level yes yes detector 32 kHz quartz, 32 kHz quartz, Oscillators internal RC internal RC LCD drivers 120 segments Port B and Port B and Analog mux 4x2 or 7x1+1 4x2 or 7x1+1 LP comparators 4 PGA gain 0.5 - 1000 gain 0.5 - 1000 5 - 16 bits 5 - 16 bits ADC resolution resolution DAC XE88LC03 4 x 8 bits 4 x 8 bits 4 x 8 bits yes transition detection + software yes transition detection + software yes transition detection + software yes yes yes 32 kHz quartz, internal RC 32 kHz quartz, internal RC 120 segments 32 kHz quartz, internal RC Port B Port B Port B and 4x2 or 7x1+1 4 PWM PWM PWM samples Q2/01 SO28, TQFP32, die yes samples Q2/01 gain 0.5 - 1000 5 - 16 bits resolution PWM 8 bit bias DAC, 4 - 16 bits signal DAC TQFP64, die yes Table 1.11: List of the XE8000 family members functions XX/D010-060 Product Preliminary Specification Page 18 Low-Power Microcontroller XX-XE88LC01 Contacting XEMICS You can contact XEMICS at XEMICS SA Tel: +41 32 720 5170 Fax: +41 32 720 5770 E-mail: info@xemics.com You will find more information about the XE88LC05 and other XEMICS products, as well as the addresses of our representatives and distributors for your region on www.xemics.com. Copyright XEMICS All rights are reserved. Reproduction whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.Printed in Switzerland. XX/D010-060 Product Preliminary Specification Page 19