Cool Solutions
XEMICS SA, Switzerland. Tel: +41 32 720 51 70 Fax: +41 32 720 57 70 e-mail: info@xemics.com web: www.xemics.com
XX-XE88LC05
Data Sheet
XE88LC05
Ultra Low-Power Microcontroller with
ADC and DACs for Sensor Conditioning
General Description
The XE88LC05 is an ultra low-power microcontroller unit
(MCU) associated with a versatile analo
g
-to-di
g
ital con-
verter (ADC) includin
g
a pro
g
rammable offset and
g
ain
pre-amplifier (PGA) and di
g
ital-to-analo
g
converters
(DACs).
XE88LC05 is available with on chip Multiple-Time-Pro-
g
rammable (MTP) Flash pro
g
ram memory.
Applications
• Internet connected appliances
• Portable, battery operated instruments
• Piezoresistive brid
g
e sensors
• 4-20 mA bus sensors
• 0.5 - 4.5 V sensors
• HVAC control
• Motor control
Key product Features
• Ultra low-power MCU (300 µA at 1 MIPS)
• Low-volta
g
e operation (2.4 - 5.5 V supply volta
g
e)
• 22 kB (8 kW) MTP, 512 B RAM
•Volta
g
e or current output DACs
• Buffered si
g
nal-DAC (up to 16 bits)
• Buffered bias-DA C (up to 10 mA drive)
• Low-po wer, hi
g
h resolution Zoomin
g
ADC
• up to 10 bits zoom
• up to 16 bits ADC
• 4 x 2 or 7 x 1 PGA-ADC input multiplexer
•Analo
g
matrix switchin
g
• RC and cryst al osc il lat ors
• 5 reset, 16 interrupt, 8 event sources
Orderin
g
Info rmatio n
Nomenclature: (XX marks pre-production samples)
;(/&0(
prog ram memory
M: MTP temperature
I: -40 to 85 °C
TQFP64 package
Low-Power Microcontroller
XX-XE88LC01
XX/D 010 -0 60 Produ ct Pr el im ina ry Speci fic ati on Pa
g
e 2
Detailed Pin Description
Pin Description
Position Function
name Second function
name Type
1 PA(0) testin Input Input of Port A/
Data input for test and MTP programming/
Counter A input
2 PA(1) testck Input Input of Port A/
Data clock for test and MTP programming/
Counter B input
3 PA(2) Input Input of Port A/
Counter C input/ Counter capture input
4 PA(3) Input Input of Port A/
Counter D input/ Counter capture input
5 PA(4) Input Input of Port A
6 PA(5) Input Input of Port A
7 PA(6) Input Input of Port A
8 PA(7) Input Input of Port A
9 PC(0) Input/Output Input-Output of Port C
10 PC(1) Input/Output Input-Output of Port C
11 PC(2) Input/Output Input-Output of Port C
12 PC(3) Input/Output Input-Output of Port C
13 PC(4) Input/Output Input-Output of Port C
14 PC(5) Input/Output Input-Output of Port C
15 PC(6) Input/Output Input-Output of Port C
16 PC(7) Input/Output Input-Output of Port C
17 PB(0) testout Input/Output/Analog Input-Output-Analog of Port B/
Data output for test and MTP programming/
PWM output
Table 1.2: Pin-out of the XE88LC05 in TQFP64
Pinout of the XE88LC05 in TQFP64 packa
g
e
PA(0)
PA(1)
PA(2)
PA(3)
PA(4)
PA(5)
PA(6)
PA(7)
PC(0)
PC(1)
PC(2)
PC(3)
PC(4)
PC(5)
PC(6)
PC(7)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16 18 20 22 24 26 28 30
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
63 61 59 57 55 53 51
PB(0)
PB(1)
PB(2)
PB(3)
PB(4)
PB(5)
PB(6)
PB(7)
DAB_Out
DAB_AO_p
DAB_AO_m
DAB_AI_p
DAB_AI_m
AC_R(0)
AC_R(1)
AC_A(0)
AC_A(1)
AC_A(2)
AC_A(3)
AC_A(4)
AC_A(5)
AC_A(6)
AC_A(7)
AC_R(2)
AC_R(3)
OscIn
OscOut
RESET
Vmult
TEST
Vreg
Vss_Vreg
Vss
Vbat
DAS_Out
DAS_AI_p
DAS_AI_m
DAS_AO
XEMICS
DAB_R_p
DAB_R_m
XE88LC05MI
N9K1444
9920
device type
production
packaging date
lot identification
Low-Power Microcontroller
XX-XE88LC01
XX/D 010 -0 60 Produ ct Pr el im ina ry Speci fic ati on Pa
g
e 3
18 PB(1) Input/Output/Analog Input-Output-Analog of Port B/
PWM output
19 PB(2) Input/Output/Analog Input-Output-Analog of Port B
20 PB(3) SOU Input/Output/Analog Input-Output-Analog of Port B,
Output pin of USRT
21 PB(4) SCL Input/Output/Analog Input-Output-Analog of Port B/
Clock pin of USRT
22 PB(5) SIN Input/Output/Analog Input-Output-Analog of Port B/
Data input or input-output pin of USRT
23 PB(6) Tx Input/Output/Analog Input-Output-Analog of Port B/
Emission pin of UART
24 PB(7) Rx Input/Output/Analog Input-Output-Analog of Port B/
Reception pin of UART
25 DAB_R_p Analog Positive refere nce of bias DAC
26 DAB_R_m Analog Negative ref ere nce of bias DAC
27 DAB_Out Analog Output of bias DAC
28 DAB_AO_p Analog Highest potential output of bias DAC buffer
29 DAB_AO_m Analog Lowest potential output of bias DAC buffer
30 DAB_AI_p Analog Positive input of bias DAC buffer
31 DAB_AI_m Analog Negative input of bias DAC buffer
32 Not connected Spare pins to be connected to negative power supply
33 TEST/Vhigh Vhigh Special Test mode/High voltage for MTP programming
34 Not connected Spare pins to be connected to negative power supply
35 AC_R(3) Analog Highest potential node for 2nd reference of ADC
36 AC_R(2) Analog Lowest potential node for 2nd reference of ADC
37 AC_A(7) Analog ADC input node
38 AC_A(6) Analog ADC input node
39 AC_A(5) Analog ADC input node
40 AC_A(4) Analog ADC input node
41 AC_A(3) Analog ADC input node
42 AC_A(2) Analog ADC input node
43 AC_A(1) Analog ADC input node
44 AC_A(0) Analog ADC input node
45 AC_R(1) Analog Highest potential node for 1st reference of ADC
46 AC_R(0) Analog Lowest potential node for 1st reference of ADC
47-50 Not connected Spare pins to be connected to negative power supply
51 DAS_Out Analog Output of signal DAC
52 DAS_AI_p Analog Positive input of signal DAC buffer
53 DAS_AI_m Analog Negative input of signal DAC buffer
54 DAS_AO Analog Output of signal DAC buffer
55 Vbat Power Positive power supply
56 Vss Power Negative power supply, connected to substrate
57 Vss_Reg Power Digital negative power supply, must be equal to Vss
58 Vreg Analog Regulated supply
59 Not connected Spare pins to be connected to negative power supply
60 Vmult Analog Pad for optional voltage multiplier capacitor
61 RESET Input Reset pin (active high)
62 OscOut ptck Analog/Input Connection to Xtal/
Periphe ral cl ock for test and MTP prog ram min g
63 OscIn ck_cr Analog/Input Connection to Xtal/
CoolRISC clock for test and MTP programming
64 - - Do not connect, or VSS
Pin Description
Position Function
name Second function
name Type
Table 1.2: Pin-out of the XE88LC05 in TQFP64
Low-Power Microcontroller
XX-XE88LC01
XX/D 010 -0 60 Produ ct Pr el im ina ry Speci fic ati on Pa
g
e 4
XE88LC05xI Electrical Characteristics
Note: 1) Power supply: 2.4 V - 5.5 V, at 27°C; min volta
g
e of XX versio n may be hi
g
her, max frequency
of current XX version is 2 MHz
Note: 2) Temperature < 85°C
Note: 3) Output not loaded.
Note: 4) Current requirement can be divided by a factor of 2 or 4 by reducin
g
the speed accordin
g
ly.
Note: 5) More cy cl es pos si ble durin
g
development, with restraint retention
Operation conditions min typ max Unit Remarks
Power supply ROM version 2.4 5.5 V
MTP version 2.4 5.5 V
Current requirement
CPU running
at 1 MIPS 310 uA 1
CPU running
at 32 kHz
on Xtal,
RC off
10 uA 1
CPU halt,
timer on Xtal,
RC off 1uA 1
CPU halt,
timer on Xtal,
RC ready 1.7 uA 1
CPU halt,
Xtal off
timer on RC
at 100 kHz
1.4 uA 1
CPU halt,
ADC 12 bits
at 4 kHz 200 uA 1,4
CPU halt,
ADC 12 bits
at 4 kHz,
PGA gain 100
250 uA 1,4
CPU at 1 MIPS,
ADC 12 bits and DAC
10 bits
at 4 kHz
660 uA 1,3,4
CPU at 1 MIPS,
ADC 12 bits and DAC
10 bits
at 4 kHz,
PGA gain 10
685 uA 1,3,4
CPU at 1 MIPS,
ADC 12 bits and DAC
10 bits
at 4 kHz,
PGA gain 100
710 uA 1,3,4
CPU at 1 MIPS,
ADC 12 bits and DAC
10 bits
at 4 kHz,
PGA gain 1000
785 uA 1,3,4
Voltage level
detection 15 uA
MTP
Prog. voltage 10.3 10.8 V
Erase time 3 30 s
Write/Erase cycles 10 100 5
Data retention 10 year 2
Current requirement of the XE88LC05
Low-Power Microcontroller
XX-XE88LC01
XX/D 010 -0 60 Produ ct Pr el im ina ry Speci fic ati on Pa
g
e 5
CPU
The XE88LC05 CPU is a low power RISC core. It has 16 internal re
isters for effici ent impleme ntation o f the C com-
piler. Its ins truction s et is made of 35
eneric ins tructions , all coded on 22 bits, wit h 8 addressin
modes. All instruc-
tions are executed in one clock cycle, includin
conditional jumps and 8x8 multiplication.
A complete tool suite for development is available from XEMICS, includin
pro
rammer, C-compiler, assembler,
simulator, linker, all inte
rated in a modern and efficient
raphical user interf ace.
Memor y organi sation
The CPU uses a Harvard architecture, so that memory is or
anised in two separated fields: pro
ram memory and
data memory. As both memory are separated, the central processin
unit can read/write data at the same time it
loads an instruction. Peripherals and system control re
isters are mapped on data memory space.
Pro
ram me mory is made in one pa
e (pro
ram pa
e full si ze is 65’5 36 instructions). Data is made of several 256
bytes pa
es.
Program memory
The pro
ram memory is implemented as Multiple Time Pro
rammable (M TP) Flash memory.
The power consumption of MTP is linear with the access frequency (no si
nificant static current) .
Memory sizes:
• Flash MTP: 8192 x 22 bits (= 22 kBytes)
block size address
MTP 8192 x 22 H0000 - H1FFF
Program addresses
Memory or
g
anization
CPU
Program
memory
Registers
Peripherals
RAM
Program address bus
Data address bus
22 bits wide 8 bits wide
CPU
registers
Instruction
pipeline
8k instructions
512 Bytes
Low-Power Microcontroller
XX-XE88LC01
XX/D 010 -0 60 Produ ct Pr el im ina ry Speci fic ati on Pa
g
e 6
Data memory
The data memory is implemented as static Random-Access Memory (RAM). The size is 512 x 8 bits plus 8 low pow-
er re
isters th at require v ery low cu rrent when ad dressed, p ro
rams usin
these re
isters instead of RAM will spare
even more current.
Note: The re
g
isters in Data memory are not related to the CPU re
g
isters.
Peripherals mapping
Peripherals
The XE88LC05 includ es usua l microco ntrolle r periph erals an d some o ther blo cks more specifi c to lo w-volta
e or
mixed-si
nal operat ion. They are 3 paralle l ports, one input port (A), one IO and anal o
port (B) with analo
switch-
in
capabilities and one
eneral purpose IO port (C). A watchdo
is available, connected to a prescaler. Four 8-bit
counter s, with ca pture, PWM and c hainin
capabi lities ar e avai lable. Th e UART can handle t ransmiss ion spe eds as
hi
h as 38kbaud.
Low-power low- volta
e bloc ks inc lude a volta
e level detec tor, t wo osci llator s (one i nternal 0.1 -4 MHz RC osc illat or
and a 32 kHz crystal oscillator) and a specific re
ulation scheme that lar
ely uncouples current requirement from
external po w er su ppl y (u su al CM OS ASIC s require much more current at 5 .5 V tha n the y ne ed at 2.4 V. Th is is no t
the case for the XE88LC05).
Analo
blocks : acquisition path, bias DAC and si
nal DAC are defined below. All these blocks operate on 2.4 - 5.5
V power supply ran
e.
block size address
LP RAM 8 x 8 H0000 - H0007
RAM 512 x 8 H0080 - H027F
RAM addresses
block size address Page
LP RAM 8x8 H 0 000 -H0007
Page 0
System control 16x8 H0010-H001F
Port A 8x8 H0020 -H0 027
Port B 8x8 H002 8- H002F
Port C 4x8 H0030-H0033
Port D 4x8 H0034-H0037
MTP 4x8 H0038-H003B
Event 4x8 H003C-H003F
Interrupts control 8x8 H0040-H0047
reserved 8x8 H0048-H004F
UART 8x8 H0050-H0057
Counters 8x8 H0058-H005F
Zooming ADC 8x8 H0060-H0067
Reserved 12x8 H0068-H0073
DACs 8x8 H0074-H007B
Other
(VLD) 4x8 H007C-H007F
RAM1 128x8 H00 80 - H00F F
RAM2 256x8 H0100 - H01FF Page 1
RAM3 128x8 H0200 - H027F Page 2
Peripherals addresses
Low-Power Microcontroller
XX-XE88LC01
XX/D 010 -0 60 Produ ct Pr el im ina ry Speci fic ati on Pa
g
e 7
Zooming ADC
Principle
The fully diff erential acquisition chain is formed of a pro
rammable
ain (0.5 - 1000) and offset amplifier and a pro-
rammable speed and resolution ADC (example: 12 bits at 4 kHz, 16 bits at 1 kHz). It can handle inputs with very
low full scale si
nal and lar
e offsets.
Input sele ction is ma de f rom 1 of 4 diffe rential pair or 1 of sev en sin
le si
nal versus AC_A(0). Refe rence is cho sen
from the 2 differential references. Acquisition path offset can be suppressed by invertin
input polarity.
The
ain of each amplifier is pro
rammed individually. Each amplifier is powered on and off on command to mini -
mize the total current requirement. All blocks can be set to low frequency operation and lower their current require-
men t by a factor 2 or 4.
The ADC can run continuously (end of conversion si
nalled by an interrupt, event or by poolin
the ready bit), or it
can be started on request.
Input signal multiplexing
There are 8 inputs named AC_A[0] to AC_A[7]. Inputs can be used either as four differential channels
(Vin1=AC_A[1]-AC _ A[0], …, Vi n4=A C_ A[7] -AC_A[6 ]) or AC_A[0] ca n b e us ed as a c om m on re fere nce, p r ovidi n
7
si
nal paths (AC_A[1]-AC_A[0], …, AC_A[7]-AC_A[0]), all referred to AC_A[0]. Default input is Vin1.
On top of these sett in
s, inp uts can be c rossed or not. All multi plexin
combi nations are s ummarised i n the follow in
table (see Table 1.3) :
uni/bi-polar sign channel selection selected differential input
AMUX(4) AMUX(3) AMUX(2) AMUX(1) AMUX(0) VIN- VIN+
0
0 unused
0 0 A(0) A(1)
0 1 A(2) A(3)
1 0 A(4) A(5)
1 1 A(6) A(7)
1 unused
0 0 A(1) A(0)
0 1 A(3) A(2)
1 0 A(5) A(4)
1 1 A(7) A(6)
Table 1.3: AMUX selection
Acquisition channel block dia
g
ram
JDLQ RIIVHW JDLQ RIIVHW JDLQ PRGH RXWSXW
FRGH
LQSXW VHOHFWLRQ
$'&
$&B$
$&B$
$&B$
$&B$
$&B$
$&B$
$&B$
$&B$
$&B5
$&B5
$&B5
$&B5
UHIHUHQFH VHOHFWLRQ
Low-Power Microcontroller
XX-XE88LC01
XX/D 010 -0 60 Produ ct Pr el im ina ry Speci fic ati on Pa
g
e 8
Input reference multiplexing
One must select one of two differential si
nal as reference si
nal (Vref1=AC_R[1]-AC_R[0], Vref2=AC_R[3]-
AC_R[2]). Default is Vref1.
Amplifier chain
The 3 sta
es transfer functions are: VD3 = GD3.VD2 - GDoff3.Vref
VD2 = GD2.VD1 - GDoff2.Vref
VD1 = GD1.Vin
where: Vin=Select ed input v olta
g
e
Vref=Selec ted refe renc e vol ta
g
e
VD1=Differential volta
g
e at the output of first amplifier
VD2=Differential volta
g
e at the output of second amplifier
VD3=Differential volta
g
e at the output of third amplifier
GD1=Differential
g
ain of sta
g
e 1
GD2=Differential
g
ain of sta
g
e 2
GD3=Differential
g
ain of sta
g
e 3
GDoff2= Offset
g
ain of sta
g
e 2
GDoff3=Offset
g
ain of sta
g
e 3
and therefore the whole transfer function is:
Vout of PGA = VD3 = GD3.GD2.GD1.Vin - (GDoff3 + GDoff2.GD3).Vref
Note: As th e offse t compen satio n is rea lized to
g
ether with the amplification on the same summin
g
node, the only volta
g
es that have to stay within the supplies are Vref and the VDi. GDi . VDi-1 and GDoffi .
Vref can be lar
g
er without any saturation.
Note: All sta
g
es use a fully differential architecture and all
g
ain and offset settin
g
s are realized with
ratios of capacitors.
Note: As the ADC also provides a
g
ain (2 nominal), the total chain transfer function is:
Each sta
e is called PGAi. Features of these sta
es are:
1
0
000A(0)A(0)
001A(0)A(1)
010A(0)A(2)
011A(0)A(3)
100A(0)A(4)
101A(0)A(5)
110A(0)A(6)
111A(0)A(7)
1
000A(0)A(0)
001A(1)A(0)
010A(2)A(0)
011A(3)A(0)
100A(4)A(0)
101A(5)A(0)
110A(6)A(0)
111A(7)A(0)
uni/bi-polar sign channel selection selected differential input
AMUX(4) AMUX(3) AMUX(2) AMUX(1) AMUX(0) VIN- VIN+
Table 1.3: AMUX selection
()
32321232_ GDGDoffGDoff
Vref
Vin
GDGDGDoutData ⋅+⋅−⋅⋅⋅⋅=
Low-Power Microcontroller
XX-XE88LC01
XX/D 010 -0 60 Produ ct Pr el im ina ry Speci fic ati on Pa
g
e 9
• Gain can be chosen between 1 and 10 (between 0 and 10 for PGA3)
• Offset can be compensated for in PGA2 (a little) and in PGA3 (to a lar
g
e extent)
• Granularity of settin
g
s is rou
g
h for PGA1, medium for PGA2, fine for PGA3
• Zero, one or two or three of the PGA sta
g
es can be used.
A functional example of one of the sta
es is
iven on ta
1.1.
1.1.1 PGA 1
Note: 1) Mea sured with bloc k conne cted to i nputs th rou
g
h AMUX b lock. No rmalized input s amplin
g
frequency for
input im pedance is 512 kHz. This fi
g
ure has to be multiplied by 2 for fs = 256 kHz an d 4 for fs = 12 8 kHz.
Note: 2) Input referred rms noise is 10 uV per input sample. This corresponds to 18 nV/sqrt(Hz) for fs = 512 kHz.
1.1.2 PGA2
Note: 1) Mea sured with bloc k conne cted to i nputs th rou
g
h AMUX b lock. No rmalized input s amplin
g
frequency for
input im pedance is 512 kHz. This fi
g
ure has to be multiplied by 2 for fs = 256 kHz an d 4 for fs = 12 8 kHz.
symbol description min typ max unit Comments
GD1 PGA1 Signal Gain 1 10 - GD1 = 1 or 10
GD_preci Precision on gain settings -5 +5 %
GD_TC Temperature dependency of gain settings -5 +5 ppm/°C
fs input sampling frequency 512 kHz
Zin1 Input impedance 150 kΩ1
Zin1p Input impedance for gain 1 1500 kΩ1
VN1 Input referred noise 18 nV/
sqrt(Hz) 2
Table 1.4: PGA1 Performances
sym description min typ max unit Comments
GD2 PGA2 Signal Gain 1 10 - GD2 = 1, 2, 5 or 10
GDoff2 PGA2 Offset Gain -1 1 FS
GDoff2_step GDoff2(code+1) – GDoff2(code) 0.18 0.2 0.22 -
GD_preci Precision on gain settings -5 +5 % valid for GD2 and GDoff2
GD_TC Temperature dependency of gain settings -5 +5 ppm/°C
fs Input sampling frequency 512 kHz
Zin2 Input impedance 150 kΩ1
VN2 Input referred noise 36 nV/
sqrt(Hz) 2
Table 1.5: PGA2 Performances
Fi
g
ure 1.1: PGA sta
g
e principle implementation
Vref Vin Vout
Low-Power Microcontroller
XX-XE88LC01
XX/D 010 -0 60 Produ ct Pr el im ina ry Speci fic ati on Pa
g
e 10
Note: 2) Input referred rms noise is 26uV per sample.This corresponds to 36 nV/sqrt(Hz) max for fs = 512 kHz.
1.1.3 PGA3
Note: 1) Mea sured with bloc k conne cted to i nputs th rou
g
h AMUX b lock. No rmalized input s amplin
g
frequency for
input im pedance is 512 kHz. This fi
g
ure has to be multiplied by 2 for fs = 256 kHz an d 4 for fs = 12 8 kHz.
Note: 2) Input referred rms noise is 26uV per sample. This corresponds to 36 nV/sqrt(Hz) max for fs = 512 kHz.
ADC
1.1.4 Input-Output relation
The ADC block is used to convert the differential input si
nal into a 1 6 bits 2’s co mplement out put format. T he output
code corresponds to the ratio:
smax b ein
the number of s ample s used to
enerat e one out put samp le per ele mentar y conve rsion . smax is set by
OSR on RegACCfg0.
Vref can be selected up to the power supply rails and must be positive. The 2’s complement output code correspond-
in
is
iven in hexadecimal notation by 8000 (ne
ative full scale) and 7FFF (positive full scale). Code outside the
ran
e are saturated to the closest full scale value. The output code is normalized into a 16 bits format. First non
si
nificant bit is forced to 1, further non si
nifant bits are forced to 0.
1.1.5 Operation mode
The mode can be either “on request” or “continuously runnin
”.
In the “on request” mode, after a request, an initialization sequence is performed, then an al
orithm is applied and
an output code is produced. The converter is idle until the next request.
In the “continuously runnin
“ mode, a n i ntern al co nv ers ion req ues t i s
enerat ed e ac h ti me a conversion is fin is hed ,
so that the converter is never idle. The output code is updated at a fixed rate corres pondin
to 1/Tout, with Tout
bein
the conversion time.
sym description min typ max unit Comments
GD3 PGA3 Signal Gain 0 10 -
GDoff3 PGA3 Offset Gain -5 5 FS
GD3_step GD3(code+1) - GD3(code) 0.075 0.08 0.0 85 -
GDoff3_step GDoff2(code+1) – GDoff2(code) 0.075 0.08 0.085 -
GD_preci Precision on gain settings -5 +5 % valid for GD3 and GDoff3
GD_TC Temperature dependency of gain settings -5 +5 ppm/°C
fs Input sampling frequency 512 kHz
Zin3 Input impedance 150 kΩ1
VN3 Input referred noise 36 nV/
sqrt(Hz) 2
Table 1.6: PGA3 Performances
register data
MSB LSB
RegACOutLSB bit 5 bit 4 bit 3 bit 2 bit 1 1 0 0
RegACOutMSB sign bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6
Table 1.7: Output code exemple, for 13 bits resolution (OSR: h11, NELCONV: h01)
Output code = Vin
Vref smax + 1
smax
.
Low-Power Microcontroller
XX-XE88LC01
XX/D 010 -0 60 Produ ct Pr el im ina ry Speci fic ati on Pa
g
e 11
1.1.6 Conversion sequence
The whole conver sion s equenc e is basic ally made of an initial isati on, a set o f Nelconv eleme ntary in creme ntal co n-
versions and finally a termination phase(NumCONV is se t by 2 bits on RegACCfg0). The r esu l t is a me an o f the
results of the elementary conversions.
Note: NumCONV elementary conversions are performed, each elementary conversion bein
g
made of smax input
samples.
NumCONV = 2NELCONV
smax = 8*2OSR
Durin
g
the elementary conversions, the operation of the converter is the same as in a si
g
ma del t a modu -
lator. Durin
g
one conv ersio n sequ ence, the el ement ary co nvers ions a re alte rnativ ely pe rformed wit h direc t
and crossed PGA-ADC differential inputs, so that when two elementary conversions or more are per-
formed, the offset of the converter is cancelled.
Note: The sizin
g
of the deci mation filter puts s ome l imits on the tota l num ber of c onvers ions and it is not poss ible
to combi ne the maximum number of elementary conversions with the maximum oversamplin
g
(see the Nel-
conv*smax spec ification).
Some additional clock cycles (NINIT+NEND) clock cycles are required to initiate and terminate the conversion prop-
erly.
1.1.7 Conversion duration
The conversion time is
iven by :
TOUT = (2NELCONV *(8*2OSR +1) + (NINIT + NEND)) / fs
1.1.8 Resolution
As far as it is not limited by thermal noise and internal re
isters width, the resolution is
iven by :
Resolution (in bits) = 6 + 2*OSR + NELCONV
1.1.9 ADC performances
sym description min typ max unit Comments
VINR Input range -0.5 0.5 Vref
Resol Resolution 12 bits 1
NResol Numerical resolution 16 bits 4
INL Integral non-linearity 4 LSB 1,3, LSB at 12bits
Table 1.8: ADC Performances
Fi
g
ure 1.2: Conversion sequence. smax is the oversamplin
g
rate.
START END
1st elementary
conversion 2nd elemen tar y
conversion elementary
conversion elementary
conversion
conversion
index 12N
umConv-1 NumConv
input 12 smax
12 smax 12 smax
sample
Low-Power Microcontroller
XX-XE88LC01
XX/D 010 -0 60 Produ ct Pr el im ina ry Speci fic ati on Pa
g
e 12
Note: 1) Resolution specification also includes thermal noise and differential non-linearity (DNL) for a reference
si
g
nal of 2.4 V. It is defined for default operatin
g
mode ( See “Default operation mode (not yet implement-
ed)” on pa
g
e13.)
Note: 2) Only powers of 2
Note: 3) INL is defined as the deviation of the DC transfer curve from the best fit strai
g
ht line. This specification
holds over 100% of the full scale.
Note: 4) NResol is th e maximal readable resolution of the di
g
ital filter. Input noise may be hi
g
her than NResol.
Control part
Startin
g
a convention
A conversion is started each time START or DEF is set. PGAs are reset after each writin
g
operation to re
g
isters
RegACCfg1 to RegACCfg5. When usin
g
the PGAs, one ha s to start the ADCs after a PGA common-mode stabili-
sation del ay. Thi s is do ne by wr itin
bit START several c ycles after PGA se ttin
g
s modification. Delay between PGA
start and ADC start should be equivalent to smax number of cycles .
End of a conversion
The end o f t he co nversi on is mark ed by the re turn to zero of bus y bit , and, if se t, by the
eneration of ADC interrupt.
Busy bit = 0 is not sufficient to denote the end of the conversion, as the ADC needs some clock cycles to set it to
one at the conversion be
innin
. Only the transiti on from 1 to 0 denotes the end of conversion.
For low powe r or low n ois e ap pli ca tio ns , one sho uld pref er to us e th e in terru pti on as the proc es so r can
o to HALT
between conversion start and conversion end.
Clocks
g
eneration
Peripheral clock (psck) can be chosen amon
four prescaler clocks (bit FIN of RegACCfg2), see Table 1.10, derived
from the XE8000 RC oscillator.
The clock of the acquisition path (fs) is derived from the peripheral clock.
fs = psck / 4
fs sampling frequency 10 512 kHz
smax Oversampling Ratio 8 1024 - 2
NUMCONV Number of elementary conversions in
incremental mode 18-2
Ninit Number of periods for incremental
conversion initialization 5-
Nend Number of periods for incremental
conversi on ter mina tion 5-
sym description min typ max unit Comments
Table 1.8: ADC Performances
Low-Power Microcontroller
XX-XE88LC01
XX/D 010 -0 60 Produ ct Pr el im ina ry Speci fic ati on Pa
g
e 13
Acquisition of a sample
Default operation mode (not yet implemented)
The DEF bit (RegACCfg5) allo ws the us e of the ADC in a default mode with out any
g
ain nor offs et adju stment (see
values in the ri
ht column of Table 1.10). This default mode is used in specifications to define resolution and INL.
The only action to lau nch th e op era t ion of the peri pheral is in this c as e to w rite a ‘ x1 xx xx x x’ at a ddre ss 11 1. VMUX
and AMUX are written at the same time and are not reset to default value. BUSY is not affected. The only way to
stop a runnin
conversion before completion is to shut the ADC down writin
‘0000’ in ENABLE (RegACCfg1).
Re
g
isters
Ei
ht re
isters con trol this peripheral. Two re
isters are for the data output, six for peripheral
eneral set-up. Re
-
isters are defined in Table 1.9 and Table 1.10.
register data
RegACOutLSB ADC_OUT_L
RegACOutMSB ADC_OUT_H
Table 1.9: Peripheral register memory map
Fi
g
ure 1.3: Acquisition flow
use default mode
write in
RegACCfg5
yes
no
use PGA
write in
RegACCfg1-5
yes
no
AND
modif iy P GA
wait for
PGA stable
start ADC by
writing RegACCfg0
wait for
ADC ready
read
ADC results
Low-Power Microcontroller
XX-XE88LC01
XX/D 010 -0 60 Produ ct Pr el im ina ry Speci fic ati on Pa
g
e 14
RegACCfg0 START NELCONV OSR CONT reserved
RegACCfg1 IB_AMP_ADC IB_AMP_PGA ENABLE
RegACCfg2 FIN PGA2_GAIN PGA2_OFF
RegACCfg3 PGA1_
GAIN PGA3_GAIN
RegACCfg4 reserved PGA3_OFF
RegACCfg5 BUSY DEF AMUX VMUX
Name Register rm description Default
(reset and DEF
mode)
ADC_OUT(15:0) RegACOutLSB
RegACOutMSB r data output 0000h
AMUX(4:0) RegACCfg5 wr Selection of PGA inputs 00000
(reset only)
BUSY RegACCfg5 r‘1’ : conversion is in progress
‘0’ : data is available 0
CONT RegACCfg0 wr ‘1’ : continuous operation.
‘0’ : one shot mode 0
DEF RegACCfg5 wr0 Def ault Opera t ion bit
‘1’: All registers but VMUX and AMUX are reset and default values are used
‘0’: Normal operation N/A
ENABLE(3:0) RegACCfg1 wr
bit3 : PGA3, bit2 : PGA2, bit1 : PGA1, bit 0 : ADC
If a bit is ‘1’, the block is powered. If not, the block is switched off and all internal
digital signals are reset.
Concerning the PGAs, ENABLE=0 means also that inputs and outputs are wired
together and that the acquisition chain is not perturbed by the block.
0000
FIN(1:0) RegACCfg2 wr
‘00’ : RC = psck = 4 fs
‘01’ : RC / 2 = psck = 4 fs
‘10’ : RC / 8 = psck = 4 fs
‘11’ : RC / 32 = psck = 4 fs
Rem: do not select an fs clock that is faster than 512 kHz.
00
IB_AMP_PGA(1:0) RegACCfg1 wr
PGA amplif iers biasi n g curr ent reduct ion f acto r
‘00’ : current magnification factor = 0.25
‘01’ : current magnification factor = 0.5
‘10’ : current magnification factor = 0.75
‘11’ : current magnification factor = 1
11
IB_AMP_ADC(1:0) RegACCfg1 wr ADC amplifiers biasing current reduction factor.
Tuning identical to IB_AMP_PGA 11
NELCONV(1:0) RegACCfg0 wr Number of elementary conversions
‘00’ : 1 conversion, ‘01’ : 2 conversions
‘10’ : 4 conversions, ‘11’ : 8 conversions 01
OSR(2:0) RegACCfg0 wr OverSampling Ratio. Defined as fs/fout. OSR = 8*2OSR(2:0).
‘000’ : oversampling = 8, ..., ‘111’ : oversampling = 1024 010
PGA1_GAIN RegACCfg3 wr signal gain of first PGA stage (GD1)
‘1’ : nominal gain is 10.
‘0’ : nominal gain is 1 0
PGA2_GAIN(1:0) RegACCfg2 wr
signal gain of second PG A stage (GD 2 )
‘11’ : nominal gain is 10
‘10’ : nominal gain is 5
‘01’ : nominal gain is 2
‘00’ : nominal gain is 1
00
PGA2_OFF(3:0) RegACCfg2 wr
offset gain of second PGA stage (GDoff2)
bit 3: offset sign (‘0’ : GDoff2 > 0, ‘1’ : GDoff2 < 0)
bits (2:0) : offset amplitude
‘01x1’ : GDoff2 = 1.0 nominal, ‘0100’ : GDoff2 = 0.8 nominal,
‘0011’ : GDoff2 = 0.6 nominal, ..., ‘0000’ : GDoff2 = 0.0 nominal,
‘1001’’ : GDoff2 = -0.2 nominal, ..., ‘11x1’ : GDoff2 = -1.0 nominal
0000
PGA3_GAIN(6:0) RegACCfg3 wr signal gain of third stage (GD3)
GD3 = 0.08*PGA3_GAIN(6:0)
Nominal values : 0 (‘000 0000’), ..., 10 (‘111 1000’) 000 1100
PGA3_OFF(6:0) RegACCfg4 wr
offset gain of third stage (GDoff3)
bit 6: offset sign (‘0’ : GDoff3 > 0, ‘1’ : GDoff3 < 0)
GDoff3 = 0.08*PGA3_OFF(5:0), maximum = 5.04
Nominal values : -5.04 (‘111 1111’), 0 (‘x00 0000’), +5.04 (‘011 1111’)
000 0000
START RegACCfg0 wr0 writing a “1” in START bit restarts the ADC. It does not affect the PGAs. 0
Table 1.10: Peripheral register memory map, bits description
register data
Table 1.9: Peripheral register memory map
Low-Power Microcontroller
XX-XE88LC01
XX/D 010 -0 60 Produ ct Pr el im ina ry Speci fic ati on Pa
g
e 15
DACs
See XEMICS application note AN8000.03 for detailed information about the XE88LC05 DACs.
Bias DAC
The bias DAC is a low resolution (8 bits) DAC with a buffer perfectly adapted t o sensor brid
e bias. It can be used
to bias a brid
e in current (fi
ure) or in volt a
e by choosin
the pins connection.
The bias DAC itself is built off a series of resistors which two extremes are available outside the chip, so that one
can connect it to an external source when the output of the DAC should not be ratiometric to the power supply.
TEST RegACCfg0 reserved 0
VMUX RegACCfg5 wr VREF selection multiplexer
‘0’ : VREF0 is used, ‘1’ : VREF1 is used 0 (reset only)
Name Register rm description Default
(reset and DEF
mode)
Table 1.10: Peripheral register memory map, bits description
Current controlled brid
g
e bias
signal
reference
XE88xx
D
A
c
o
n
t
r
o
l amp
'$%B2XW
'$%B$,S
'$%B$2S
'$%B$,P
'$%B$2P
;(/&
Low-Power Microcontroller
XX-XE88LC01
XX/D 010 -0 60 Produ ct Pr el im ina ry Speci fic ati on Pa
g
e 16
Signal DAC
The si
nal DAC is build around a pro
rammable DAC and a buffer. It can
enerate fast (up to 64 kHz) or hi
h res-
olution (resolution up to 16 bits) output. The output can be controlled in current or volta
e.
4-20mA loop includin
g
the circuit (and brid
g
e) current consumption
XE88xx
D
A
c
o
n
t
r
o
l
amp
4-20mA
'$6B2XW
'$6B$,P
'$6B$2
'$6B$,S
9EDW
966
9 UHJXODWRU
;(/&
Low-Power Microcontroller
XX-XE88LC01
XX/D 010 -0 60 Produ ct Pr el im ina ry Speci fic ati on Pa
g
e 17
XE8000 Family
Features
The main characteristics of the XE8000 MCU family is
• Ultra low power operation
• Low volta
g
e operation (1.2 V for the XE88LC04, XE88LC06 and XE88LC07, 2.4 V for the others)
•Hi
g
h efficiency CPU
• 1 instruction per clock cycle, for all instructions
• 22 bits wide ins truc tio ns
•Inte
g
rated 8x8 -> 16 bits multiplier
• All instructions on one pa
g
e
• 8 bits data bus
• 8 addressin
g
modes
• MTP (multiple time pro
g
rammable ) memory available
• Dual clock (X-tal and/or RC)
• Each peripheral can be set on/off individually for minimal power consumption
• UART
•Watch do
g
• 4x8 bits timers with PWM ability
• Advanced acquisition path
• Fully differential analo
g
si
g
nal path on si
g
nal and reference
• 4x2 or 7x1 + 1 si
g
nal input
• 2x2 reference input
• 0.5 - 1000 pro
g
rammable
g
ain ampli fier
•Offset pro
g
rammed over +- 10 full scale
• 5 - 16 bits resolution ADC
• Low speed modes with reduced bias current for minimal power consumption
• Bias and si
g
nal DACs for resistiv e brid
g
e sen s in
g
and analo
g
output
• Complete development tools usin
g
Windows95 or NT
g
raphical interface
• Assembler
• ANSI-C compiler
• Source lev el debu
gg
er
• Current and memory usa
g
e monitorin
g
(Profiler)
• CPU Simulator
• CPU Emulator XE8000HaCE
• Pro
g
rammer and starter kit (XE88LC01ProStart)
• Hardware emulators (works with XE8000HaCE, in preparation)
Family
The XE8000 Fa mily ultr a low-power mi crocontrolle r is made of s everal memb ers, all usin
the sa me micro process or
core and differin
by the peripherals ava ilable.
The XE88L C01 is a low power s ensin
microco ntroller, ba sed on the XE88 LC03, with a n advance d acquisi tion path
includin
differential pro
rammable
ain amplifiers and a hi
h resolution analo
to di
ital converter. Its main appli-
cations are datalo
ers and proc es s con trol .
The XE88LC02 is a low power sensin
microcontroller, based on the XE88LC06 with the analo
part of the
XE88LC01, with an additional LCD driver. Its main applications are meterin
and datalo
ers.
TThe XE88LC03 is a low power, low volta
e,
eneral purpose microcontroller. Its main points are the very efficient
CoolRISC core, the low volta
e function and the real time clock. Its main applications are low volta
e cont rol and
supervision.
Low-Power Microcontroller
XX-XE88LC01
XX/D 010 -0 60 Produ ct Pr el im ina ry Speci fic ati on Pa
g
e 18
The XE88LC04 is a low power , low volta
e,
eneral purpose microcontroller, based on the XE88LC06, with an ad-
ditional LCD driver. Its main points are the very efficient CoolRISC core, the low volta
e function and the real time
clock. Its main applications are low volta
e control and supervision.
The XE88LC05 is a low power sensin
microcontroller, based on the XE88LC01, with analo
outputs. Its main ap-
plications are piezoresistive sensors and 4 - 20 mA loops systems.
The XE88L C06 is an im proved XE88L C03, with 4 l ow power analo
comp arators. Its m ain appli catio ns are lo w volt-
a
e con trol and s upervision.
The XE88LC07 is a smaller and even lower power microcont roll er, based on the X E88LC06, with less me mory.
XE88LC01 XE88LC02 XE88LC03 XE88LC04 XE88LC05
Supply voltage 2.4 - 5.5 V 2.4 - 5.5 V 2.4 - 5.5 V
1.2- 5.5 V for
ROM
2.4 - 5.5 V for
MTP
2.4 - 5.5 V
Max speed 2 MIPS 4 MIPS 2 MIPS 4 MIPS at 2.4 V 2 MIPS
Operating
temperature -40 - 85 °C -40 - 85 °C
-40 - 125 °C -40 - 85 °C -40 - 85 °C
-40 - 125 °C -40 - 85 °C
CPU
CoolRISC 816,
22 bits
instructions
8 bits data
HW multiplier
CoolRI SC 816 ,
22 bits
instructions
8 bits data
HW multiplier
CoolRISC 816,
22 bits
instructions
8 bits data
HW multiplier
CoolRISC 816,
22 bits
instructions
8 bits data
HW multiplier
CoolRISC 816,
22 bits
instructions
8 bits data
HW multiplier
Program memory 8k Instructions
= 22 kB
ROM or MTP
8k Instruction
= 22 kB
ROM or MTP
8k Instructions
= 22 kB
ROM or MTP
8k Instructi ons
= 22 kB
ROM or MTP
8k Instructions
= 22 kB
ROM or MTP
Data memory 512 + 8 Bytes 768 + 8 Bytes 512 + 8 Bytes 768 + 8 Bytes 512 + 8 Bytes
Port A 8 input and
external interrupt 8 input and
external interrupt 8 input and
external interrupt 8 input and
external in ter ru pt 8 input and
external interrupt
Port B 8 input/output and
analog 8 input/output and
analog 8 input/output and
analog 8 input/output and
analog 8 input/output and
analog
Port C 8 input/output 8 input/output 4 to 8 input/output4 to 8 input/output 8 input/output
Watchdog t imer yes yes yes yes yes
General purpose
timers with PWM 4 x 8 bits 4 x 8 bits 4 x 8 bits 4 x 8 bits 4 x 8 bits
UART yes yes yes yes yes
2-3 wires serial
interface
transition
detection
+ software
transition
detection
+ software
transition
detection
+ software
transition
detection
+ software
transition
detection
+ software
Vol tage level
detector yes yes yes yes yes
Oscillators 32 kHz quartz,
internal RC 32 kHz quartz,
internal RC 32 kHz quartz,
internal RC 32 kHz quartz,
internal RC 32 kHz quartz,
int e r n al RC
LCD drivers 120 segments 120 segments
Analog mux Port B and
4x2 or 7x1+1 Port B and
4x2 or 7x1+1 Port B Port B Port B an d
4x2 or 7x1+1
LP compar ato rs 4 4
PGA gain 0.5 - 1000 gain 0.5 - 1000 gain 0.5 - 1000
ADC 5 - 16 bits
resolution 5 - 16 bits
resolution 5 - 16 bits
resolution
DAC PWM PWM PWM PWM
PWM
8 bit bias DAC,
4 - 16 bits signal
DAC
Package TQFP44, die SO28, TQFP32,
die TQFP64, die
Availability yes samples Q2/01 yes samples Q2/01 yes
Table 1.11: List of the XE8000 family members functions
Low-Power Microcontroller
XX-XE88LC01
XX/D 010 -0 60 Produ ct Pr el im ina ry Speci fic ati on Pa
g
e 19
Contacting XEMICS
You can contact XEMICS at
XEMICS SA
Tel: +41 32 720 5170
Fax: +41 32 720 5770
E-mail: info@xemics.com
You will find more information about the XE88LC05 and other XEMICS products, as well as the addresses of our
representatives and distributors for your re
ion on www.xemics.com.
Copyri
g
ht XEMICS
All ri
g
hts are reserved. Reproduction whole or in part is prohibited without the prior written consent of the copyri
g
ht
owner. Th e information pre sented in thi s document doe s not form part of any quo tation or cont ract, is belie ved to be
accurat e an d reliable and may be c ha n
g
ed wit hou t no tic e. N o lia bi lity w il l b e ac ce pted by the publish er fo r an y c on-
sequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or
intellectual property ri
g
hts.Printed in Switzerland.