Military QuickRAM 90,000 Usable PLD Gate QuickRAM Combining Performance, Density and Embedded RAM Military QuickRAM DEVICE HIGHLIGHTS FEATURES Device Highlights Features High Performance and High Density Total of 316 I/O pins Up to 90,000 Usable PLD Gates with 316 I/Os 300 MHz 16-bit Counters, 400 MHz Datapaths, 160+ MHz FIFOs 308 bi-directional input/output pins, PCI-compliant for 5.0 volt and 3.3 volt buses for -1/-2/-3/-4 speed grades 8 high-drive input/distributed network pins 0.35um four-layer metal non-volatile CMOS process for smallest die sizes Eight Low-Skew Distributed Networks High Speed Embedded SRAM Up to 22 dual-port RAM modules, organized in userconfigurable 1,152-bit blocks 5ns access times, each port independently accessible Fast and efficient for FIFO, RAM, and ROM functions Two array clock/control networks available to the logic cell flip-flop clock, set and reset inputs - each driven by an input-only pin Six global clock/control networks available to the logic cell F1, clock, set and reset inputs and the input and I/O register clock, reset and enable inputs as well as the output enable control - each driven by an input-only or I/O pin, or any logic cell output or I/O cell feedback Easy to Use / Fast Development Cycles High Performance 100% routable with 100% utilization and complete pin-out stability Input + logic cell + output total delays under 6 ns Variable-grain logic cells provide high performance and 100% utilization Data path speeds exceeding 400 MHz Comprehensive design tools include high quality Verilog/ VHDL synthesis Counter speeds over 300 MHz FIFO speeds over 160+ MHz Military Reliability Advanced I/O Capabilities Interfaces with both 3.3 volt and 5.0 volt devices Mil-STD-883 and Miil Temp Ceramic PCI compliant with 3.3V and 5.0V buses for -1/-2 speed grades Mil Temp Plastic - Guaranteed -55C to 125C Full JTAG boundary scan Registered I/O cells with individually controlled clocks and output enables Device Usable Gates Package 84CPGA 84PLCC 100CQFP 144CPGA QL4036 16,000208PQFP 16,128 RAM bits 25,000 208CQFP 208PQFP 208CQFP QL4090 36,000240PQFP 25,344 RAM bits 60,000 256CPGA 456PBGA M = Military Temperature (-15 to +125 degrees C) /888 = MIL STD 883 QL4016 11,520 RAM Bits 8,00016,000 Max I/O Qualification Level Supply Voltage 70 70 82 118 174 174 174 174 207 223 316 M, /883 M M, /883 M, /883 M M, /883 M M, /883 M M, /883 M 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3V 3.3V 3.3V 3.3V 3.3V TABLE 1: Selector Table Rev A 8-37 Military QuickRAM PRODUCT SUMMARY Product Summary The QuickRAM family of ESPs (Embedded Standard Products) offers FPGA logic in combination with Dual-Port SRAM modules. QuickRAM is a 90,000 usable PLD gate ESPs. QuickRAM ESPs are fabricated on a 0.35mm four-layer metal process using QuickLogic's patented ViaLink technology to provide a unique combination of high performance, high density, low cost, and extreme ease-of-use. able in plastic 84-PLCC, 208-PQFP, 240-PQFP and 456-PBGA packages and in ceramic 100, 208CQFP and 84, 144, 256-CPGA. Software support for the complete QuickRAM family is available through two basic packages. The turnkey QuickWorks package provides the most complete ESP software solution from design entry to logic synthesis, to place and route, to simulation. The QuickToolsTM for Workstations package provides a solution for designers who use Cadence, Exemplar, Mentor, Synopsys, Synplicity, Viewlogic, Veribest, or other third-party tools for design entry, synthesis, or simulation. QuickRAM contains up to 1,584 logic cells and 22 dual port RAM modules. Each RAM module has 1,152 RAM bits, for a total of up to 25,344 bits. RAM Modules are Dual Port (one read port, one write port) and can be configured into one of four modes: 64 (deep) x18 (wide), 128x9, 256x4, or 512x2. With a maximum of 316 I/Os, and is availPinout Diagram 84-Pin PLCC PINOUT DIAGRAM 84-PIN PLCC QuickRAM QL4016-1PL84M TABLE 2: 84-pin PLCC 8-38 38 Rev A Preliminary Military QuickRAM PINOUT DIAGRAM 100-PIN CQFP Pinout Diagram 100-Pin CQFP Pin #76 Pin #1 QuickRAM QL4016-1CF100M Pin #51 Pin #26 100 CQFP Pinout Table 100 TQFP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Function I/O I/O I/O I/O I/O I/O I/O I/O GND I/O GCLK / I ACLK / I VCC GCLK / I GCLK / I VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O 100 100 100 Function Function Function TQFP TQFP TQFP 26 TDI 51 I/O 76 TCK 27 I/O 52 I/O 77 STM 28 I/O 53 I/O 78 I/O 29 I/O 54 I/O 79 I/O 30 I/O 55 I/O 80 I/O 31 I/O 56 I/O 81 I/O 32 I/O 57 I/O 82 I/O 33 I/O 58 I/O 83 I/O 34 I/O 59 GND 84 I/O 35 GND 60 I/O 85 GND 36 I/O 61 GCLK / I 86 I/O 37 I/O 62 ACLK / I 87 I/O 38 GND 63 VCC 88 GND 39 I/O 64 GCLK / I 89 I/O 40 I/O 65 GCLK / I 90 I/O 41 I/O 66 VCC 91 I/O 42 VCCIO 67 I/O 92 VCCIO 43 I/O 68 I/O 93 I/O 44 I/O 69 I/O 94 I/O 45 I/O 70 I/O 95 I/O 46 I/O 71 I/O 96 I/O 47 I/O 72 I/O 97 I/O 48 I/O 73 I/O 98 I/O 49 TRSTB 74 I/O 99 I/O 50 TMS 75 I/O 100 TDO Rev A 8-39 Military QuickRAM PINOUT DIAGRAMS 208-Pin PQFP/CQFP Pin #157 Pin #1 QuickRAM QL4090-1PQ208M Pin #105 Pin #53 240-Pin PQFP Pin #157 Pin #1 QuickRAM QL4090-1PQ240M Pin #105 Pin #53 8-40 40 Rev A Preliminary Military QuickRAM PINOUT TABLE PQFP/CQFP 240/208 Pinout Table 240 208 PQFP PQFP Function 240 208 PQFP PQFP Function 240 208 PQFP PQFP Function 240 208 Function PQFP PQFP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 208 1 2 3 4 5 NC 6 7 8 9 10 11 12 13 14 NC 15 16 17 18 19 20 NC 21 22 23 24 25 26 27 28 29 30 31 32 NC 33 NC 34 35 36 NC 37 38 39 NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCC I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O GCLK / I ACLK / I VCC GCLK / I GCLK / I VCC I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O 51 52 53 54 55 56 57 58 59 60 NC NC 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 NC 84 85 86 87 88 89 90 91 92 93 94 43 44 45 46 47 48 NC 49 50 51 52 53 54 NC NC 55 56 NC 57 58 59 60 61 62 63 64 NC 65 66 67 NC 68 69 70 NC 71 NC 72 73 74 NC 75 76 77 78 79 80 GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TDI I/O I/O I/O I/O I/O I/O I/O GND I/O VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O VCC I/O I/O I/O GND I/O I/O 98 99 100 101 102 103 104 105 106 107 108 109 110 NC 111 NC NC 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 84 85 86 87 88 89 90 91 92 NC 93 94 95 96 97 98 99 100 NC 101 NC 102 NC NC 103 104 105 NC 106 107 108 109 NC 110 111 112 113 114 115 116 117 NC 118 119 120 121 NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O TRSTB TMS I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCC I/O GND I/O I/O I/O I/O I/O I/O I/O 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 NC 181 182 183 184 185 186 187 188 189 190 125 126 127 128 NC 129 130 131 132 133 134 135 136 NC 137 NC 138 139 140 141 142 NC 143 144 145 NC 146 147 148 149 150 151 152 153 154 155 156 157 158 NC 159 160 161 162 163 164 165 I/O I/O GND I/O I/O GCLK / I ACLK / I VCC GCLK / I GCLK / I VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O VCC I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O TCK STM I/O I/O I/O I/O I/O GND I/O VCC 48 49 50 40 41 42 I/O VCC I/O 95 96 97 81 82 83 I/O I/O VCCIO 142 143 144 122 123 124 I/O I/O I/O 191 192 193 166 NC 167 I/O I/O I/O Rev A 240 208 PQFP PQFP 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 168 169 NC 170 171 172 173 174 175 NC 176 177 178 179 NC 180 181 182 NC 183 184 185 186 187 188 NC 189 190 191 192 193 194 NC 195 196 197 198 NC 199 200 201 202 203 204 205 206 207 Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O VCCIO I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O VCC I/O I/O I/O I/O I/O TDO 8-41 Military QuickRAM PINOUT DIAGRAM 84-PIN CPGA Pinout Diagram 84-Pin CPGA QuickRAM QL4016-1CG84M 84-Pin CPGA Pinout Table 8-42 42 84 CPGA Function 84 CPGA Function 84 CPGA Function 84 CPGA Function A1 I/O B11 I/O F9 I/O K2 I/O A2 I/O C1 VCC F10 I/O K3 I/O A3 I/O C2 I/O F11 I/O K4 I/O A4 I/O C5 VCC G1 I/O K5 GCLK / I A5 I/O C6 ACLK / I G2 I/O K6 GCLK / I A6 I/O C7 GND G3 VCCIO K7 GCLK / I A7 I/O C10 I/O G9 GND K8 I/O A8 I/O C11 I/O G10 I/O K9 I/O A9 I/O D1 I/O G11 I/O K10 TCK A10 I/O D2 I/O H1 I/O K11 I/O A11 TDO D10 I/O H2 I/O L1 TMS B1 I/O D11 I/O H10 VCC L2 I/O B2 TDI E1 I/O H11 I/O L3 I/O B3 I/O E2 I/O J1 I/O L4 I/O B4 I/O E3 GND J2 TRSTB L5 I/O B5 GCLK / I E9 VCCIO J5 GND L6 I/O B6 GCLK / I E10 I/O J6 ACLK / I L7 I/O B7 GCLK / I E11 I/O J7 VCC L8 I/O B8 I/O F1 I/O J10 STM L9 I/O B9 I/O F2 I/O J11 I/O L10 I/O B10 I/O F3 I/O K1 I/O L11 I/O Rev A Preliminary Military QuickRAM PINOUT DIAGRAMS 144 & 256-PIN CPGAS Pinout Diagrams 144 & 256-Pin CPGAs QuickRAM QL4036-1CG144M 144-Pin CPGA 1 2 3 4 5 6 7 8 9 10 11121314151617181920 Y W V U T R P N M L K J H G F E D C B A QuickRAM QL4090-1CG256M 256-Pin CPGA Rev A 8-43 Military QuickRAM PINOUT TABLE 144-PIN CPGA Pinout Table 144-Pin CPGA 8-44 44 144 CPGA Function 144 CPGA Function 144 CPGA Function 144 CPGA Function A1 I/O C7 I/O H13 ACLK / I N10 I/O A2 I/O C8 GND H14 I/O N11 GND A3 I/O C9 I/O H15 GCLK / I N12 I/O A4 I/O C10 I/O J1 GCLK / I N13 I/O A5 I/O C11 I/O J2 VCC N14 I/O A6 I/O C12 TCK J3 VCC N15 I/O A7 I/O C13 I/O J13 I/O P1 I/O A8 I/O C14 I/O J14 I/O P2 I/O A9 I/O C15 I/O J15 GND P3 TDI A10 GND D1 I/O K1 GCLK / I P4 I/O A11 I/O D2 I/O K2 I/O P5 I/O A12 I/O D3 I/O K3 I/O P6 I/O A13 VCC D13 I/O K13 I/O P7 I/O A14 I/O D14 I/O K14 I/O P8 I/O A15 I/O D15 I/O K15 I/O P9 VCCIO B1 I/O E1 I/O L1 I/O P10 I/O B2 TDO E2 VCC L2 I/O P11 I/O B3 I/O E3 I/O L3 GND P12 I/O B4 I/O E13 GND L13 I/O P13 I/O B5 I/O E14 I/O L14 VCC P14 TRSTB B6 I/O E15 I/O L15 I/O P15 I/O B7 VCCIO F1 I/O M1 I/O R1 I/O B8 I/O F2 I/O M2 I/O R2 I/O B9 I/O F3 I/O M3 I/O R3 VCC B10 I/O F13 I/O M13 I/O R4 I/O B11 I/O F14 I/O M14 I/O R5 I/O B12 I/O F15 GCLK / I M15 I/O R6 GND B13 STM G1 GND N1 I/O R7 I/O B14 I/O G2 I/O N2 I/O R8 I/O B15 I/O G3 I/O N3 I/O R9 I/O C1 I/O G13 VCC N4 I/O R10 I/O C2 I/O G14 VCC N5 I/O R11 I/O C3 I/O G15 GCLK / I N6 I/O R12 I/O C4 I/O H1 GCLK / I N7 I/O R13 I/O C5 GND H2 I/O N8 GND R14 I/O C6 I/O H3 ACLK / I N9 I/O R15 TMS Rev A Preliminary Military QuickRAM PINOUT TABLE 256-PIN CPGA Pinout Table 256-Pin CPGA 256 CPGA Function 256 CPGA Function 256 CPGA 256 CPGA Function A1 VCC A2 I/O A3 Function 256 CPGA C4 I/O E19 C5 I/O E20 I/O L2 GCLK / I VCC L3 GND T17 I/O V20 I/O T18 I/O W1 I/O VCC C6 I/O F1 I/O L4 I/O T19 I/O W2 I/O A4 I/O C7 I/O A5 I/O C8 I/O F2 GND L17 F3 I/O L18 GCLK / I T20 I/O W3 I/O I/O U1 I/O W4 A6 I/O C9 I/O F4 I/O I/O L19 VCC U2 I/O W5 GND A7 I/O C10 I/O F17 I/O L20 ACLK / I U3 I/O W6 I/O A8 A9 I/O C11 VCC I/O C12 I/O F18 GND M1 VCC U4 I/O W7 I/O F19 I/O M2 I/O U5 I/O W8 A10 GND C13 I/O I/O F20 I/O M3 I/O U6 I/O W9 I/O A11 I/O C14 I/O G1 I/O M4 I/O U7 I/O W10 I/O GND Function 256 CPGA Function A12 I/O C15 I/O G2 I/O M17 I/O U8 I/O W11 A13 I/O C16 I/O G3 I/O M18 I/O U9 I/O W12 I/O A14 I/O C17 I/O G4 I/O M19 I/O U10 VCC W13 VCCIO A15 I/O C18 I/O G17 I/O M20 I/O U11 I/O W14 I/O A16 I/O C19 I/O G18 I/O N1 I/O U12 I/O W15 I/O A17 I/O C20 I/O G19 I/O N2 I/O U13 I/O W16 I/O A18 GND D1 VCC G20 I/O N3 I/O U14 I/O W17 I/O A19 I/O D2 I/O H1 I/O N4 I/O U15 I/O W18 I/O A20 TCK D3 I/O H2 I/O N17 I/O U16 I/O W19 TRSTB B1 I/O D4 I/O H3 I/O N18 I/O U17 I/O W20 I/O B2 I/O D5 I/O H4 I/O N19 I/O U18 I/O Y1 TDI B3 I/O D6 I/O H17 I/O N20 GND U19 I/O Y2 I/O B4 GND D7 I/O H18 I/O P1 I/O U20 I/O Y3 I/O B5 I/O D8 I/O H19 I/O P2 I/O V1 I/O Y4 VCC B6 I/O D9 I/O H20 I/O P3 VCC V2 I/O Y5 I/O B7 I/O D10 I/O J1 I/O P4 I/O V3 I/O Y6 I/O B8 VCCIO D11 I/O J2 I/O P17 GND V4 I/O Y7 I/O B9 I/O D12 I/O J3 GND P18 I/O V5 I/O Y8 I/O B10 VCC D13 I/O J4 I/O P19 I/O V6 I/O Y9 I/O B11 I/O D14 I/O J17 I/O P20 I/O V7 I/O Y10 I/O B12 GND D15 I/O J18 VCC R1 I/O V8 I/O Y11 I/O B13 I/O D16 I/O J19 GND R2 I/O V9 VCC Y12 I/O B14 I/O D17 STM J20 VCC R3 GND V10 GND Y13 I/O B15 I/O D18 I/O K1 ACLK / I R4 I/O V11 I/O Y14 I/O B16 VCC D19 I/O K2 VCC R17 I/O V12 I/O Y15 I/O B17 I/O D20 I/O K3 GND R18 VCC V13 I/O Y16 I/O B18 GND E1 I/O K4 GCLK / I R19 I/O V14 I/O Y17 VCC B19 I/O E2 I/O K17 I/O R20 I/O V15 GND Y18 I/O B20 I/O E3 I/O K18 I/O T1 I/O V16 I/O Y19 I/O C1 I/O E4 I/O K19 GCLK / I T2 I/O V17 GND Y20 I/O C2 I/O E17 I/O K20 GCLK / I T3 I/O V18 TMS C3 TDO E18 I/O L1 GCLK / I T4 VCC V19 I/O Rev A 8-45 Military QuickRAM PINOUT DIAGRAM 456-PIN PBGA Pinout Diagram 456-Pin PBGA QuickRAM QL4090-1PB456CM 456 Pin PBGA TOP PIN A1 CORNER Bottom 8-46 46 Rev A Preliminary Military QuickRAM PINOUT TABLE 456-PIN PBGA Pinout Table 456-Pin PBGA 456 Function 456 Function 456 Function 456 Function 456 Function B26 STM D25 I/O H4 I/O M14 GND/THERM C1 I/O D26 I/O H5 NC M15 GND/THERM C2 I/O E1 I/O H22 NC M16 GND/THERM C3 I/O E2 I/O H23 I/O M22 NC I/O C4 TDO E3 I/O H24 I/O M23 NC A6 I/O C5 I/O E4 I/O H25 I/O M24 I/O A7 I/O C6 I/O E5 GND H26 I/O M25 I/O A8 I/O C7 I/O E6 VCC J1 I/O M26 I/O A9 I/O C8 I/O E7 GND J2 I/O N1 GCLK/I A10 I/O C9 I/O E8 NC J3 I/O N2 I/O A11 I/O C10 I/O E9 GND J4 NC N3 I/O A12 VCCIO C11 I/O E10 I/O J5 GND N4 GCLK/I A13 I/O C12 I/O E11 GND J22 NC N5 VCC A14 I/O C13 I/O E12 GND J23 NC N11 GND/THERM A1 I/O A2 I/O A3 I/O A4 I/O A5 A15 I/O C14 I/O E13 VCC J24 I/O N12 GND/THERM A16 I/O C15 I/O E14 GND J25 I/O N13 GND/THERM A17 I/O C16 I/O E15 GND J26 I/O N14 GND/THERM A18 I/O C17 I/O E16 GND K1 I/O N15 GND/THERM A19 I/O C18 I/O E17 NC K2 I/O N16 GND/THERM A20 I/O C19 I/O E18 GND K3 I/O N22 GND A21 I/O C20 I/O E19 NC K4 I/O N23 I/O A22 I/O C21 I/O E20 GND K5 VCC N24 I/O A23 I/O C22 I/O E21 VCC K22 GND N25 I/O A24 I/O C23 I/O E22 GND K23 I/O N26 I/O A25 I/O C24 I/O E23 I/O K24 I/O P1 I/O A26 I/O C25 TCK E24 I/O K25 I/O P2 I/O B1 I/O C26 I/O E25 I/O K26 I/O P3 I/O B2 I/O D1 I/O E26 I/O L1 I/O P4 I/O B3 I/O D2 I/O F1 I/O L2 I/O P5 NC B4 I/O D3 I/O F2 I/O L3 I/O P11 GND/THERM B5 I/O D4 GND F3 I/O L4 I/O P12 GND/THERM B6 I/O D5 I/O F4 NC L5 NC P13 GND/THERM B7 I/O D6 NC F5 VCC L11 GND/THERM P14 GND/THERM B8 I/O D7 I/O F22 VCC L12 GND/THERM P15 GND/THERM B9 I/O D8 I/O F23 NC L13 GND/THERM P16 GND/THERM B10 I/O D9 GND F24 I/O L14 GND/THERM P22 NC B11 I/O D10 I/O F25 I/O L15 GND/THERM P23 GCLK / I B12 I/O D11 I/O F26 I/O L16 GND/THERM P24 GCLK / I B13 I/O D12 GND G1 I/O L22 NC P25 I/O B14 I/O D13 I/O G2 I/O L23 I/O P26 ACLK / I B15 I/O D14 I/O G3 I/O L24 I/O R1 I/O B16 I/O D15 GND G4 I/O L25 I/O R2 I/O B17 I/O D16 I/O G5 NC L26 I/O R3 I/O B18 I/O D17 I/O G22 GND M1 ACLK / I R4 NC B19 I/O D18 GND G23 I/O M2 GCLK/I R5 NC B20 I/O D19 I/O G24 I/O M3 I/O R11 GND/THERM B21 I/O D20 I/O G25 I/O M4 NC R12 GND/THERM B22 I/O D21 NC G26 I/O M5 GND R13 GND/THERM B23 I/O D22 I/O H1 I/O M11 GND/THERM R14 GND/THERM B24 I/O D23 GND H2 I/O M12 GND/THERM R15 GND/THERM B25 I/O D24 I/O H3 I/O M13 GND/THERM R16 GND/THERM (Cont'd on next page) Rev A 8-47 Military QuickRAM PBGA 456 Pinout Table (continued from previous page) 8-48 48 456 Function 456 Function 456 Function 456 Function R22 VCC Y1 I/O AC6 NC AE5 I/O R23 NC Y2 I/O AC7 I/O AE6 I/O R24 I/O Y3 I/O AC8 I/O AE7 I/O R25 I/O Y4 I/O AC9 NC AE8 I/O R26 GCLK / I Y5 I/O AC10 I/O AE9 I/O T1 I/O Y22 GND AC11 I/O AE10 I/O T2 I/O Y23 I/O AC12 NC AE11 I/O T3 I/O Y24 I/O AC13 I/O AE12 I/O T4 I/O Y25 I/O AC14 VCCIO AE13 I/O T5 VCC Y26 I/O AC15 NC AE14 I/O T11 GND/THERMAL AA1 I/O AC16 I/O AE15 I/O T12 GND/THERMAL AA2 I/O AC17 I/O AE16 I/O T13 GND/THERMAL AA3 NC AC18 NC AE17 I/O T14 GND/THERMAL AA4 NC AC19 I/O AE18 I/O T15 GND/THERMAL AA5 VCC AC20 I/O AE19 I/O T16 GND/THERMAL AA22 VCC AC21 I/O AE20 I/O T22 GND AA23 NC AC22 NC AE21 I/O T23 I/O AA24 I/O AC23 GND AE22 I/O T24 I/O AA25 I/O AC24 I/O AE23 NC T25 I/O AA26 I/O AC25 I/O AE24 TMS T26 I/O AB1 I/O AC26 I/O AE25 I/O U1 I/O AB2 I/O AD1 I/O AE26 I/O U2 I/O AB3 I/O AD2 NC AF1 I/O U3 I/O AB4 I/O AD3 I/O AF2 I/O U4 I/O AB5 GND AD4 I/O AF3 I/O U5 GND AB6 VCC AD5 I/O AF4 I/O U22 NC AB7 NC AD6 I/O AF5 I/O U23 I/O AB8 NC AD7 I/O AF6 I/O U24 I/O AB9 NC AD8 I/O AF7 I/O U25 I/O AB10 VCC AD9 I/O AF8 I/O U26 I/O AB11 GND AD10 I/O AF9 I/O V1 I/O AB12 NC AD11 I/O AF10 I/O V2 I/O AB13 I/O AD12 I/O AF11 I/O V3 I/O AB14 GND AD13 I/O AF12 I/O V4 NC AB15 VCC AD14 I/O AF13 I/O V5 NC AB16 I/O AD15 I/O AF14 I/O V22 GND AB17 NC AD16 I/O AF15 I/O V23 NC AB18 VCC AD17 I/O AF16 I/O V24 I/O AB19 GND AD18 I/O AF17 I/O V25 I/O AB20 NC AD19 I/O AF18 I/O V26 I/O AB21 VCC AD20 I/O AF19 I/O W1 I/O AB22 GND AD21 I/O AF20 I/O W2 I/O AB23 I/O AD22 I/O AF21 I/O W3 I/O AB24 I/O AD23 TRSTB AF22 I/O W4 I/O AB25 I/O AD24 I/O AF23 I/O I/O W5 NC AB26 I/O AD25 I/O AF24 W22 NC AC1 I/O AD26 I/O AF25 I/O W23 I/O AC2 I/O AE1 TDI AF26 I/O W24 I/O AC3 NC AE2 I/O W25 I/O AC4 GND AE3 I/O W26 I/O AC5 I/O AE4 I/O Rev A Preliminary Military QuickRAM Pin Descriptions PIN DESCRIPTIONS Pin TDI/RSI Function Test Data In for JTAG / RAM init. Serial Data In TRSTB/RRO Active low Reset for JTAG / RAM init. reset out TMS Test Mode Select for JTAG TCK Test Clock for JTAG TDO/RCO Test data out for JTAG / RAM init. clock out STM Special Test Mode I/ACLK Can be configured as either or both. I High-drive input and/or array network driver High-drive input and/or global network driver High-drive input I/O Input/Output pin Can be configured as an input and/or output. VCC Power supply pin Connect to 3.3V supply. VCCIO Input voltage tolerance pin GND Ground pin Connect to 5.0 volt supply if 5 volt input tolerance is required, otherwise connect to 3.3V supply. Connect to ground. GND/THERM Ground/Thermal pin I/GCLK Description Hold HIGH during normal operation. Connects to serial PROM data in for RAM initialization. Connect to VCC if unused. Hold LOW during normal operation. Connects to serial PROM reset for RAM initialization. Connect to GND if unused. Hold HIGH during normal operation. Connect to VCC if not used for JTAG. Hold HIGH or LOW during normal operation. Connect to VCC or ground if not used for JTAG. Connect to serial PROM clock for RAM initialization. Must be left unconnected if not used for JTAG or RAM initialization. Must be grounded during normal operation. Can be configured as either or both. Use for input signals with high fanout. Available on 456-PBGA only. Connect to ground plane on PCB if heat sinking desired. Otherwise may be left unconnected. Ordering Information QL 4090 - 1 PQ208 M QuickLogic device Operating Range M = Military M/883 = MIL STD 883 QuickRAM device part number 4016 4036 4090 Package Code PL84 = 84-pin PLCC CG84=84-pin CPGA CF100 = 100-pin CQFP CG144=144-pin CPGA PQ208 = 208-pin PQFP CF208 = 208-pin CQFP PQ240 = 240-pin PQFP CG256=256-pin CPGA CG456=456-pin PBGA Speed Grade 0 = quick 1 = fast 2 = faster Rev A 8-49 Military QuickRAM ABSOLUTE MAXIMUM RATINGS DC Input Current ...................... 20 mA ESD Pad Protection.................... 2000V Storage Temperature .......-65C to +150C Lead Temperature ...........................300C VCC Voltage ...........................-0.5 to 4.6V VCCIO Voltage .......................-0.5 to 7.0V Input Voltage.............. -0.5 to VCCIO+0.5V Latch-up Immunity ...................200 mA OPERATING RANGE Symbol VCC VCCIO TA TC K Parameter Min 3.0 3.0 -55 Supply Voltage I/O Input Tolerance Voltage Ambient Temperature Case Temperature -0 Speed Grade -1 Speed Grade -2 Speed Grade Delay Factor 0.42 0.42 0.42 Military Max 3.6 5.5 125 2.03 1.64 1.37 Unit V V C C DC CHARACTERISTICS Symbol VIH VIL VOH Parameter Input HIGH Voltage Input LOW Voltage Output HIGH Voltage Conditions VOL Output LOW Voltage II IOZ CI IOS I or I/O Input Leakage Current 3-State Output Leakage Current Input Capacitance [2] Output Short Circuit Current [3] ICC ICCIO D.C. Supply Current [4] D.C. Supply Current on VCCIO Min Max Unit 0.5VCC VCCIO+0.5 V -0.5 0.3VCC V IOH = -12 mA 2.4 V 0.9VCC V IOH = -500 A IOL = 8 mA [1] 0.45 V IOL = 1.5 mA 0.1VCC V VI = VCCIO or GND -10 10 A VI = VCCIO or GND -10 10 A 10 pF VO = GND -15 -180 mA VO = VCC 40 210 mA VI, VIO = VCCIO or GND 0.50 (typ) 5 mA 0 100 A Notes: [1] Military devices have 8 mA IOL specifications. [2] Capacitance is sample tested only. Clock pins are 12 pF maximum. [3] Only one output at a time. Duration should not exceed 30 seconds. [4] Maximum ICC is 5 mA for all military grade devices. For AC conditions, contact QuickLogic customer engineering. 8-50 50 Rev A Preliminary Military QuickRAM QL4016 QL4016 AC CHARACTERISTICS at VCC = 3.3V, TA = 25C (K = 1.00) (To calculate delays, multiply the appropriate K factor in the "Operating Range" section by the following numbers.) Logic Cells Symbol tPD tSU tH tCLK tCWHI tCWLO tSET tRESET tSW tRW Propagation Delays (ns) Fanout [6] 2 3 4 1.7 1.9 2.2 1.7 1.7 1.7 0.0 0.0 0.0 1.0 1.2 1.5 1.2 1.2 1.2 1.2 1.2 1.2 1.3 1.5 1.8 1.1 1.3 1.6 1.9 1.9 1.9 1.8 1.8 1.8 Parameter Combinatorial Delay [7] Setup Time [7] Hold Time Clock to Q Delay Clock High Time Clock Low Time Set Delay Reset Delay Set Width Reset Width 1 1.4 1.7 0.0 0.7 1.2 1.2 1.0 0.8 1.9 1.8 8 3.2 1.7 0.0 2.5 1.2 1.2 2.8 2.6 1.9 1.8 Input-Only/Clock Cells Symbol Propagation Delays (ns) Fanout [6] Parameter 1 2 3 4 8 12 24 TIN TINI TISU TIH TlCLK TlRST TlESU High Drive Input Delay High Drive Input, Inverting Delay Input Register Set-Up Time Input Register Hold Time Input Register Clock To Q Input Register Reset Delay Input Register Clock Enable Setup Time 1.5 1.6 3.1 0.0 0.7 0.6 2.3 1.6 1.7 3.1 0.0 0.8 0.7 2.3 1.8 1.9 3.1 0.0 1.0 0.9 2.3 1.9 2.0 3.1 0.0 1.1 1.0 2.3 2.4 2.5 3.1 0.0 1.6 1.5 2.3 2.9 3.0 3.1 0.0 2.1 2.0 2.3 4.4 4.5 3.1 0.0 3.6 3.5 2.3 TlEH Input Register Clock Enable Hold Time 0.0 0.0 0.0 0.0 0.0 0.0 0.0 Notes: [6] Stated timing for worst case Propagation Delay over process variation at VCC=3.3V and TA=25C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature settings as specified in the Operating Range. [7] These limits are derived from a representative selection of the slowest paths through the QuickRAM logic cell including typical net delays. Worst case delay values for specific paths should be determined from timing analysis of your particular design. Rev A 8-51 Military QuickRAM QL4016 Clock Cells Symbol tACK tGCKP tGCKB Propagation Delays (ns) Loads per Half Column [8] 2 3 4 8 10 1.2 1.3 1.3 1.5 1.6 0.7 0.7 0.7 0.7 0.7 0.8 0.9 0.9 1.1 1.2 Parameter 1 1.2 0.7 0.8 Array Clock Delay Global Clock Pin Delay Global Clock Buffer Delay 11 1.7 0.7 1.3 I/O Cell Input Delays Symbol tI/O TISU TIH TlOCLK TlORST TlESU TlEH Propagation Delays (ns) Fanout [6] Parameter Input Delay (bidirectional pad) Input Register Set-Up Time Input Register Hold Time Input Register Clock To Q Input Register Reset Delay Input Register clock Enable Set-Up Time Input Register Clock Enable Hold Time 1 2 3 4 8 10 1.3 3.1 0.0 0.7 0.6 2.3 0.0 1.6 3.1 0.0 1.0 0.9 2.3 0.0 1.8 3.1 0.0 1.2 1.1 2.3 0.0 2.1 3.1 0.0 1.5 1.4 2.3 0.0 3.1 3.1 0.0 2.5 2.4 2.3 0.0 3.6 3.1 0.0 3.0 2.9 2.3 0.0 I/O Cell Output Delays Symbol TOUTLH TOUTHL TPZH TPZL TPHZ TPLZ Propagation Delays (ns) Output Load Capacitance (pF) Parameter Output Delay Low to High Output Delay High to Low Output Delay Tri-state to High Output Delay Tri-state to Low Output Delay High to Tri-State [9] Output Delay Low to Tri-State [9] 30 50 75 100 150 2.1 2.2 1.2 1.6 2.0 1.2 2.5 2.6 1.7 2.0 3.1 3.2 2.2 2.6 3.6 3.7 2.8 3.1 4.7 4.8 3.9 4.2 Notes: [6] Stated timing for worst case Propagation Delay over process variation at VCC=3.3V and TA=25C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature settings as specified in the Operating Range. [8] The array distributed networks consist of 40 half columns and the global distributed networks consist of 44 half columns, each driven by an independent buffer. The number of half columns used does not affect clock buffer delay. The array clock has up to 8 loads per half column. The global clock has up to 11 loads per half column. [9] The following loads are used for tPXZ: tPHZ 1K 5 pF 1K tPLZ 5 pF 8-52 52 Rev A Preliminary Military QuickRAM QL4036 QL4036 AC CHARACTERISTICS at VCC = 3.3V, TA = 25C (K = 1.00) (To calculate delays, multiply the appropriate K factor in the "Operating Range" section by the following numbers.) Logic Cells Symbol tPD tSU tH tCLK tCWHI tCWLO tSET tRESET tSW tRW Propagation Delays (ns) Fanout [5] 2 3 4 1.7 1.9 2.2 1.7 1.7 1.7 0.0 0.0 0.0 1.0 1.2 1.5 1.2 1.2 1.2 1.2 1.2 1.2 1.3 1.5 1.8 1.1 1.3 1.6 1.9 1.9 1.9 1.8 1.8 1.8 Parameter Combinatorial Delay [6] Setup Time [6] Hold Time Clock to Q Delay Clock High Time Clock Low Time Set Delay Reset Delay Set Width Reset Width 1 1.4 1.7 0.0 0.7 1.2 1.2 1.0 0.8 1.9 1.8 8 3.2 1.7 0.0 2.5 1.2 1.2 2.8 2.6 1.9 1.8 Input-Only/Clock Cells Symbol Propagation Delays (ns) Fanout [5] Parameter 1 2 3 4 8 12 24 TIN TINI TISU TIH TlCLK TlRST TlESU High Drive Input Delay High Drive Input, Inverting Delay Input Register Set-Up Time Input Register Hold Time Input Register Clock To Q Input Register Reset Delay Input Register Clock Enable Setup Time 1.5 1.6 3.1 0.0 0.7 0.6 2.3 1.6 1.7 3.1 0.0 0.8 0.7 2.3 1.8 1.9 3.1 0.0 1.0 0.9 2.3 1.9 2.0 3.1 0.0 1.1 1.0 2.3 2.4 2.5 3.1 0.0 1.6 1.5 2.3 2.9 3.0 3.1 0.0 2.1 2.0 2.3 4.4 4.5 3.1 0.0 3.6 3.5 2.3 TlEH Input Register Clock Enable Hold Time 0.0 0.0 0.0 0.0 0.0 0.0 0.0 Notes: [5] Stated timing for worst case Propagation Delay over process variation at VCC=3.3V and TA=25C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature settings as specified in the Operating Range. [6] These limits are derived from a representative selection of the slowest paths through the pASIC 3 logic cell including typical net delays. Worst case delay values for specific paths should be determined fromtiming analysis of your particular design. Rev A 8-53 Military QuickRAM QL4036 Clock Cells Symbol tACK tGCKP tGCKB Parameter 1 1.2 0.7 0.8 Array Clock Delay Global Clock Pin Delay Global Clock Buffer Delay Propagation Delays (ns) Loads per Half Column [7] 2 3 4 8 10 1.2 1.3 1.3 1.5 1.6 0.7 0.7 0.7 0.7 0.7 0.8 0.9 0.9 1.1 1.2 12 1.7 0.7 1.3 15 1.8 0.7 1.4 I/O Cell Input Delays Symbol tI/O TISU TIH TlOCLK TlORST TlESU TlEH Propagation Delays (ns) Fanout [5] Parameter Input Delay (bidirectional pad) Input Register Set-Up Time Input Register Hold Time Input Register Clock To Q Input Register Reset Delay Input Register clock Enable Set-Up Time Input Register Clock Enable Hold Time 1 2 3 4 8 10 1.3 3.1 0.0 0.7 0.6 2.3 0.0 1.6 3.1 0.0 1.0 0.9 2.3 0.0 1.8 3.1 0.0 1.2 1.1 2.3 0.0 2.1 3.1 0.0 1.5 1.4 2.3 0.0 3.1 3.1 0.0 2.5 2.4 2.3 0.0 3.6 3.1 0.0 3.0 2.9 2.3 0.0 I/O Cell Output Delays Symbol TOUTLH TOUTHL TPZH TPZL TPHZ TPLZ Propagation Delays (ns) Output Load Capacitance (pF) Parameter Output Delay Low to High Output Delay High to Low Output Delay Tri-state to High Output Delay Tri-state to Low Output Delay High to Tri-State [8] Output Delay Low to Tri-State [8] 30 50 75 100 150 2.1 2.2 1.2 1.6 2.0 1.2 2.5 2.6 1.7 2.0 3.1 3.2 2.2 2.6 3.6 3.7 2.8 3.1 4.7 4.8 3.9 4.2 Notes: [5] Stated timing for worst case Propagation Delay over process variation at VCC=3.3V and TA=25C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature settings as specified in the Operating Range. [7] The array distributed networks consist of 56 half columns and the global distributed networks consist of 60 half columns, each driven by an independent buffer. The number of half columns used does not affect clock buffer delay. The array clock has up to 12 loads per half column. The global clock has up to 15 loads per half column. [8] The following loads are used for tPXZ: tPHZ 1K 5 pF 1K tPLZ 5 pF 8-54 54 Rev A Preliminary Military QuickRAM QL4090 QL4090 AC CHARACTERISTICS at VCC = 3.3V, TA = 25C (K = 1.00) (To calculate delays, multiply the appropriate K factor in the "Operating Range" section by the following numbers.) Logic Cells Symbol tPD tSU tH tCLK tCWHI tCWLO tSET tRESET tSW tRW Propagation Delays (ns) Fanout [5] 2 3 4 1.7 1.9 2.2 1.7 1.7 1.7 0.0 0.0 0.0 1.0 1.2 1.5 1.2 1.2 1.2 1.2 1.2 1.2 1.3 1.5 1.8 1.1 1.3 1.6 1.9 1.9 1.9 1.8 1.8 1.8 Parameter Combinatorial Delay [6] Setup Time [6] Hold Time Clock to Q Delay Clock High Time Clock Low Time Set Delay Reset Delay Set Width Reset Width 1 1.4 1.7 0.0 0.7 1.2 1.2 1.0 0.8 1.9 1.8 8 3.2 1.7 0.0 2.5 1.2 1.2 2.8 2.6 1.9 1.8 Input-Only/Clock Cells Symbol TIN TINI TISU TIH TlCLK TlRST TlESU TlEH Propagation Delays (ns) Fanout [5] Parameter High Drive Input Delay High Drive Input, Inverting Delay Input Register Set-Up Time Input Register Hold Time Input Register Clock To Q Input Register Reset Delay Input Register Clock Enable Setup Time Input Register Clock Enable Hold Time 1 2 3 4 8 12 24 1.5 1.6 3.1 0.0 0.7 0.6 2.3 0.0 1.6 1.7 3.1 0.0 0.8 0.7 2.3 0.0 1.8 1.9 3.1 0.0 1.0 0.9 2.3 0.0 1.9 2.0 3.1 0.0 1.1 1.0 2.3 0.0 2.4 2.5 3.1 0.0 1.6 1.5 2.3 0.0 2.9 3.0 3.1 0.0 2.1 2.0 2.3 0.0 4.4 4.5 3.1 0.0 3.6 3.5 2.3 0.0 Notes: [5] Stated timing for worst case Propagation Delay over process variation at VCC=3.3V and TA=25C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature settings as specified in the Operating Range. [6] These limits are derived from a representative selection of the slowest paths through the pASIC 3 logic cell including typical net delays. Worst case delay values for specific paths should be determined from timing analysis of your particular design. Rev A 8-55 Military QuickRAM QL4090 Clock Cells Symbol TACK TGCKP TGCKB Propagation Delays (ns) Loads per Half Column [7] Parameter 1 1.2 0.7 0.8 Array Clock Delay Global Clock Pin Delay Global Clock Buffer Delay 2 1.2 0.7 0.8 3 1.3 0.7 0.9 4 1.3 0.7 0.9 8 1.5 0.7 1.1 10 1.6 0.7 1.2 12 1.7 0.7 1.3 14 1.8 0.7 1.4 16 1.9 0.7 1.5 18 2 0.7 1.6 20 2.1 0.7 1.7 I/O Cell Input Delays Symbol tI/O TISU TIH TlOCLK TlORST TlESU TlEH Propagation Delays (ns) Fanout [5] Parameter Input Delay (bidirectional pad) Input Register Set-Up Time Input Register Hold Time Input Register Clock To Q Input Register Reset Delay Input Register clock Enable Set-Up Time Input Register Clock Enable Hold Time 1 2 3 4 8 10 1.3 3.1 0.0 0.7 0.6 2.3 0.0 1.6 3.1 0.0 1.0 0.9 2.3 0.0 1.8 3.1 0.0 1.2 1.1 2.3 0.0 2.1 3.1 0.0 1.5 1.4 2.3 0.0 3.1 3.1 0.0 2.5 2.4 2.3 0.0 3.6 3.1 0.0 3.0 2.9 2.3 0.0 I/O Cell Output Delays Symbol TOUTLH TOUTHL TPZH TPZL TPHZ TPLZ Propagation Delays (ns) Output Load Capacitance (pF) Parameter Output Delay Low to High Output Delay High to Low Output Delay Tri-state to High Output Delay Tri-state to Low Output Delay High to Tri-State [8] Output Delay Low to Tri-State [8] 30 50 75 100 150 2.1 2.2 1.2 1.6 2.0 1.2 2.5 2.6 1.7 2.0 3.1 3.2 2.2 2.6 3.6 3.7 2.8 3.1 4.7 4.8 3.9 4.2 Notes: [5] Stated timing for worst case Propagation Delay over process variation at VCC=3.3V and TA=25C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature settings as specified in the Operating Range. [7] The array distributed networks consist of 88 half columns and the global distributed networks consist of 92 half columns, each driven by an independent buffer. The number of half columns used does not affect clock buffer delay. The array clock has up to 18 loads per half column. The global clock has up to 20 loads per half column. [8] The following loads are used for tPXZ: tPHZ 1K 5 pF 1K tPLZ 5 pF 8-56 56 Rev A Preliminary Military QuickRAM RAM Cell Synchronous Write Timing Symbol TSWA THWA TSWD THWD TSWE THWE TWCRD Parameter WA Setup Time to WCLK WA Hold Time to WCLK WD Setup Time to WCLK WD Hold Time to WCLK WE Setup Time to WCLK WE Hold Time to WCLK WCLK to RD (WA=RA) [5] 1 1.0 0.0 1.0 0.0 1.0 0.0 5.0 Propagation Delays (ns) Fanout 2 3 4 1.0 1.0 1.0 0.0 0.0 0.0 1.0 1.0 1.0 0.0 0.0 0.0 1.0 1.0 1.0 0.0 0.0 0.0 5.3 5.6 5.9 8 1.0 0.0 1.0 0.0 1.0 0.0 7.1 RAM Cell Synchronous Read Timing Symbol TSRA THRA TSRE THRE TRCRD Parameter RA Setup Time to RCLK RA Hold Time to RCLK RE Setup Time to RCLK RE Hold Time to RCLK RCLK to RD [5] 1 1.0 0.0 1.0 0.0 4.0 Propagation Delays (ns) Fanout 2 3 4 1.0 1.0 1.0 0.0 0.0 0.0 1.0 1.0 1.0 0.0 0.0 0.0 4.3 4.6 4.9 8 1.0 0.0 1.0 0.0 6.1 RAM Cell Asynchronous Read Timing Symbol RPDRD Parameter RA to RD [5] 1 3.0 Propagation Delays (ns) Fanout 2 3 4 3.3 3.6 3.9 8 5.1 Notes: [5] Stated timing for worst case Propagation Delay over process variation at VCC=3.3V and TA=25C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature settings as specified in the Operating Range. Rev A 8-57 Military QuickRAM 8-58 58 Rev A Preliminary