67C401/13 67C402/23 First-In First-Out (FIFO) 64x4, 64x5 CMOS MEMORY 25/35 MHZ (Cascadable) cl Advanced Micro Devices FEATURES Zero standby power * High-speed 35-MHz shift-in/shift-out rates Very low active power consumption TTL-compatible inputs and outputs Readily expandable In word width and depth RAM-based architecture for short fall-through delay Full CMOS cell for maximum noise immunity Asynchronous operation Output Enable feature (67C4013/23) ORDERING INFORMATION 67 C 401 - 35 N OPERATING ty Cc PACKAGE TYPE CONDITIONS = Plastic DIP - PD 020 67 - Commercial J = Ceramic DIP - CD 020 (0C to 70C) NU = Plastic Leaded CMOS TECHNOLOGY Chip Carrier - PL 020 PERFORMANCE ram NUMBER 35 - 35 MHz Shift Rate Totem Pole Output 25 = 25 MHz Shift Rate 4013 64x4, Three-Stete Output 402 = -64x5, Totem Pole Output 4023 64x5, Three-State Output GENERAL DESCRIPTION The 67C40X/XX series devices are high-performance CMOS RAM-based First-in First-Out (FiFO} buffer memory products organized as 64 words by 4 or by 5 bits wide. These devices use Advanced Micro Devices latest CMOS process technology and meet the demands for high-speed, low-power operation. By utilizing an on-chip, dual-port RAM, a very short fall-through time is realized, thus improving overall system performance. By using both Read and Write pointers for addressing each memory location, the data can propagate to the outputs in much less time than in traditional register-based FIFOs. These FIFOs are easily integrated into many applications and perform particularly well for high-speed disc controllers, graphics, and communication network systems. The 550-,.watt standby power specification makes these devices ideal for ultra-low-power and battery- powered systems. BLOCK DIAGRAM INPUT SHIFT DATA IN READY IN INPUT =| conor |+| ften Loic MASTER RESET WRITE 64x4/5 READ | POINTER >) DUAL PORT {<t POINTER COUNTER RAM COUNTER OUTPUT OUTPUT CONTROL ENABLE REGISTER LOGIC {6704013/23 only) | DATA OUT SHIFT OUTPUT OUT READY Publication # Alay. 10098 8 issue Date: January 1989 Amendment 0 2-57CONNECTION DIAGRAMS 67C401/13 NC/OE Co INPUT READY G swt n [3] o Ef ot [5] o2 [e] D3 @ DATA IN GND a wT 0] vcc iis] SHIFT OUT ra] OUTPUT READY [3] 00 2] 01 ii] 02 fa] 03 OUTPUTS DIP ha] We tl Ror ia] 00 15]01 14] 02 Plastic Leaded Chip Carrier 670402/23 nc/OE [1 inpur neaby [2 stir In [3] vo [4 o1 [5] oz [6 os [7] oo DATA IN GND CG he] veo 7] sHieT ouT 1] ourPuT READY fa] 01 3] 02 | outpurs fia] o3 113 04 10] MASTER RESET DIP 2-58 67040113 67C402/23ABSOLUTE MAXIMUM RATINGS Supply voitage V6o .-.... cece eet cence reece eee nee ese en anes Leeann eee ere ee OREO Hea e EEE Eee tne eens -O5Vto7V IMPUt VOItAGE oo ccc ee cee ee ee ene EEE EEE ERED EEE E EE OER ee b FREER ERED e ee DEES ESSE GED Ee EES -15Vto7V Off-state output voltage 0.5 V to Veco 10.5 V Storage temperature .. 6.1 cece ee eee ene e eee nee b tenet eet nee eeneeeegenesuateriesens -65C to +150C Power dissipation 0.0... ccc cece cece eee e ee ten eee ee ee EEE eH ERE ORE EEE PEER Eee eb eEt bese e tener ye tenees TOW Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This js a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. OPERATING CONDITIONS Commercial: V,, = 5 V 210%, T, = 0C to +70C SYMBOL PARAMETER FIGURE ee mex UNIT Voc Supply voltage 45 5 | 45 5.5 Vv Ta Operating free-air temperature 0 70 | 0 70 | C fin Shift in rate 1 25 35 | MHz ton Shift in HIGH time 1 8 ns tsi" Shift in LOW time 1 8 ns tips Input data setup to SI (Shift In) 1 0 ns tioH Input data hold time from S} (Shift In) 1 20 16 ns trips Input data setup to IR (Input Ready) 3 5 2 ns tRIDH Input data hold time from !R (Input Ready) 3 20 15 ns fouT Shift out rate 4 25 35 | MHz tsoH" Shift out HIGH time 4 8 ns so. Shift out LOW time 4 8 ns tMRW Master Reset pulse 8 25 18 ns tuRS Master Reset to Si 8 10 7 ns * See AC test and high-speed application nate. DC CHARACTERISTICS v,,, = 5 V +10%, T, = 0C to +70C 67C40X/XX-25 67C40X/XX-35 SYMBOL PARAMETER TEST CONDITION MIN Max | MIN MAX UNIT vit" Low-level input voltage 0.8 0.8 Vv Vin" High-level input voltage 2 2 v lin Input current Voc = MAX GND<Vin <Voc -1 1 -1 1 BA loz Off-state output current Vcc = MAX GND<VouT <Vcoc -5 5 -5 5 vA lo = 20 pA 0.1 0.1 VoL Low-level output voltage Voc = MIN v lot =8mA 0.4 0.4 IOH = -20 pA Voc -0.1 Vcc -0.1 VOH High-level output voltage Voc = MIN Vv loH = -4mA 24 2.4 tos"* | Output short-circuit current | Voc = MAX [Vo =0V -90 ~20 -90 ~20 | mA Vin = Voc cc Standby supply current Voc = MAX {VIL = GND 100 100 uA . louT=9 | Vipq = MIN, Vit = MAX Operating supply current tin = fout = MAX 50 60 mA * These are absolute voltages with respect to GND and inctude all overshoots due to system and/or tester noise. ** Not more than one output should be shorted at a time, and duration of the short circuit should not exceed one second, 67C401/13 67C402/23 2-59SWITCHING CHARACTERISTICS over Operating Conditions 67C40X/XX-25 67C40X/XX-35 SYMBOL PARAMETER FIGURE MIN MAX | MIN MAX UNIT tL Shift In f to Input Ready LOW 1 21 18] as tiRH Shift Inj to Input Ready HIGH 28 20 | ns . Shift Out t to Output Ready LOW 19 18] ns torL * Shift Out | to Output Ready HIGH 4 20| ns ORH 4 tooH Output Data Hold (previous word) 5 5 ns tops Output Data Shift (next word) a4 20] ns tpt Data throughput 36 40 34] ns tMRORL Master Reset | to Output Ready LOW 35 28] ns tMRIRH Master Reset | to Input Ready HIGH 8 35 28 | ns tuiRO Master Reset | to Outputs LOW 25 22| ns tiPH Input Ready pulse HIGH ns topH Output Ready pulse HIGH ns torD Output Ready t to Data Valid 4 0 0] ns tpyz"" 15 12 PHZ ; Output Disable Delay ns tpLz A 16 12 tpz_ * 20 15 7 Output Enable Delay ns p7H 20 16 * See AC test and high-speed application note. ** Enable/Disable delays refer to 67C4013/23 only. CAPACITANCES* 67C4A0X/XX-25 67C40X/XX-35 SYMBOL PARAMETER TEST CONDITION MIN MAX | MIN MAX UNIT CIN Input capacitance Ta = 25C, f= 1 MHz 10 10 | pF Cout | Output capacitance Veco =45V 7 7| pF * Not tested in production av OUTPUT ENABLE Vy / Yr / ov ez. > ttoiz->| $1 AND 82 CLOSED WAVEFORM 1 siciosep \ 18 S20PEN ~K YT Z Vou +05 OL 'ezH>] + !piz { Vou WAVEFORM 2 sioPpen Vy, Vou -05 S2CLOSED 7) T 16 ov 81 AND Vy = 1.5 82 CLOSED Figure A. Enable and Disable Waveform 1 is fora data output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is fora data output with internal conditions such that the outputis high except when disabled by the output control. 2-60 670401/13 67C402/23STANDARD AC TEST LOAD 5v OUTPUT ) TEST POINT 3 Rz =p 30 pF Input Pulse Amplitude = 3 V Input Rise and Fall Time (10%-90%) = 2.5 ns Measurements made at 1.5 V All Diodes are 1N916 or 1N3064 RESISTOR VALUES 1oL RI R2 &8mA 600 9 1200 9 THREE-STATE TEST LOAD TEST POINT | nz = "| R1 oto $1 fo FUNCTIONAL DESCRIPTION Data Input The FIFO consists of a dual-port RAM and two ring counters for read and write. After power-up, the Master Reset should be pulsed LOW, which internally resets both the read and write counters. When the Input Ready (IR) is HIGH, the FIFO is ready to accept DATA from the Dy inputs. Data then present at the inputs is written into the first location of the RAM when Shift-In (SI!) is brought HIGH. A SI HIGH signal causes the IR to go LOW. When the Sl is brought LOW and the FIFO is not full, IR will go HIGH, indicating that more room is available. The write pointer now points to the next location in the RAM. If the memory is full, then the IR will remain LOW. Data Output Data is read from the Oy outputs. Just after the first shift-in, the first data word is available at the outputs, which is indicated by the Output Ready (OR) going HIGH. When the OR is HIGH, data may be shifted out by bringing the Shift-Out (SO) HIGH. A HIGH signal at SO causes the read pointer to point to the next location in the RAM, and also the OR to go LOW. Valid data is maintained while the SO is HIGH. When the SO is brought LOW, the OR goes HIGH, indicating the presence of new valid data. If the FIFO is emptied, OR stays LOW, and Ox remains as before, (ie., data does not change if the FIFO is empty). A dual-port RAM inside the chip provides the capability of simultaneous and asynchronous writes (Shift-Ins) and reads (Shift-Outs). AC TEST AND HIGH-SPEED APP. NOTES Since the FIFO is a very-high-speed device, care must be exer- cised in the design of the hardware and the timing utilized within the design. Device grounding and decoupling is crucial to cor- rect operation as the FIFO will respond to very small glitches due to long reflective lines, high capacitances and/or poor supply decoupling and grounding. Advanced Micro Devices recom- mends a monolithic ceramic capacitor of 0.1 .F directly between Voc and GND with very short tead length. In addition, care must be exercised in how the timing is set up and how the parameters are measured. For example, since an AND gate function is associated with both the Shift-In-Input Ready combination, as well as the Shift-Out-Output Ready combination, timing meas- urernents may be misteading; i.e., a rising edge of the Shift-In pulse is not recognized until Input Ready is HIGH. If input Ready is not HIGH due to (a) too high a frequency, or (6) FIFO being full or affected by Master Reset, the Shift-in activity will be ignored. This will affect the device from a functional standpoint, and will also cause the effective timing of Input Data Hold time (tipi) and the next activity of input Ready (t|RL) to be extended relative to Shift-in going HIGH. This same type of problem atso relates to tjRH, toRL. and toRH. For high-speed applications, proper grounding technique is essential. In order to diminish timing ambiguities between the Shift-in-Input-Ready or Shift- Out-Output-Ready pairs when operating at high frequencies, it is recommended that the tsjH and tsoH pulse widths be as short as possible within the specified limits. 67C401/13 67C402/23 2-61tN MAIN SHIFT IN A SIH tsiL \ iAH INPUT READY \ / lial neurone Xf ton UTTER ting Figure 1. Input Timing SHIFT IN \ DD INPUT READY > Q_ input pata XAYXHX)X+ STABLE DATA =A YANN AYA XXXII EIEN EAE HI Figure 2. The Mechanism of Shifting Data into the FIFO @ input Ready HIGH indicates space is available and a Shift-In pulse may be applied. @ Input Data is loaded into the first available memory location. Input Ready goes LOW indicating this memory location is full. Shift-tn going LOW aliows Input Ready to sense the status of the next memory location. The next memory tocation is empty as indicated by input Ready HIGH. It the FIFO is aiready full then the Input Ready remains LOW. Note: Shift-tn pulses applied while Input Ready is LOW will be ignored. SHIFT OUT x OQ wom / \ INPUT READY ? tery 1PM MAAR INPUT DATA A M Mi AUXERRE Figure 3. Data Is Shifted in Whenever Shift in and Input Ready are Both HIGH @ FIFO is initially full. @ Shift In is held HIGH Shift Out pulse is applied. An empty location is detected by the internal pointers on the failing edge of SO. @ As soon as Input Ready becomes HIGH the input Data is Joaded into this tocation. 2-62 67C401/13 67C402/23SHIFT OUT OUTPUT READY OUTPUT DATA Figure 4. Output Timing @ The diagram assumes that the FIFO contains at ieast three words: A-Data (first input word), B-Data (second input word}, and C-Data (third input word). @ Output data changes on the falling edge of SO atter a valid Shift-Out Sequence, i.e., OR and SO are both high together SHIFT OUT \oaoe OUTPUT READY \IARARRAAAA, ra OUTPUT DATA A-DATA TT B-DATA anf | MEY A OR Bm Figure 5. The Mechanism of Shifting Data Out of the FIFO @ Output Ready HIGH indicates thet data is available and a Shift-Out pulse may be applied @ Shift-Out goes HIGH causing 8-Data (second input word) to advance to the output register. Output data remains as valid A-Oata while Shift-Out is HIGH. @ Output Ready goes LOW. @ Shitt-out goes LOW causing Output Ready to go HIGH and new data (B) to appear at the data outputs. It the FIFO has only one word loaded (A-Data) then Output Ready stays LOW and the output data remains the same (A-Data). PT !opH > Figure 6. tpy and top}; Specification @ FIFO initially empty. @ Snhift-Out held HIGH. Shift-In pulse applied. A full location is detected by the internal pointers on the failing edge of Shift-In. @ As soon as Output Aeady becomes HIGH, the word is shifted out. 670401/13 67C402/23 2-63SHIFT OUT \ pecs assess OUTPUT L4OTEOMSATS ATES SOT sear LEILIILIDILITATG A: OUTPUT DATA x Aa-DATA x Figure 7. Data is Shitted Out Whenever Shift Out and Output Ready are Both HIGH @ The internal logic does not detect the presence of any words in the FIFO. @ New gata (A) arrives at the outputs. @ Output Ready goes HIGH indicating arrival of the new data. @ Since Shift Out is held HIGH, Output Ready goes immediately LOW. @ Assoon as Shift Out goes LOW the Output Data is subject to change. Output Ready will go HIGH or remain LOW depending on whether there are any additional words in the FIFO. MASTER RESET \ Vy tMRWw INPUT READY Pp fo UN tMRIRK OUTPUT READY + tMRORL>| twins >| SHIFT IN y DATA OUTPUTS TTT j+teno| FIFO is initially tult Figure 8. Master Reset Timing NORMALIZED I,,. vs FREQUENCY Taz 0 C,Voc=5.5 V, fin= fout 08V<V,,<2.0 OOVS Vy s5.5V fiw = four (az) 2-64 67C401/13 67C402/23