UC284XA UC384XA HIGH PERFORMANCE CURRENT MODE PWM CONTROLLER NOT FOR NEW DESIGN 1 FEATURES TRIMMED OSCILLATOR DISCHARGE CURRENT CURRENT MODE OPERATION TO 500kHz AUTOMATIC FEED FORWARD COMPENSATION LATCHING PWM FOR CYCLE-BY-CYCLE CURRENT LIMITING INTERNALLY TRIMMED REFERENCE WITH UNDERVOLTAGE LOCKOUT HIGH CURRENT TOTEM POLE OUTPUT UNDERVOLTAGE LOCKOUT WITH HYSTERESIS LOW START-UP CURRENT (< 0.5mA) DOUBLE PULSE SUPPRESSION Figure 1. Package DIP-8 Table 1. Order Codes Part Number e t le ) s t( SO-8 c u d UC2842AN; UC3842AN; UC2843AN; UC3843AN; UC2844AN; UC3844AN; UC2845AN; UC3845AN o r P DIP-8 Differences between members of this family are the under-voltage lockout thresholds and maximum duty cycle ranges. The UC3842A and UC3844A have UVLO thresholds of 16V (on) and 10V (off), ideally suited off-line applications The corresponding thresholds for the UC3843A and UC3845A are 8.5 V and 7.9V. The UC3842A and UC3843A can operate to duty cycles approaching 100%. A range of the zero to < 50 % is obtained by the UC3844A and UC3845A by the addition of an internal toggle flip flop which blanks the output off every other clock cycle. o s b O - u d o r P e Package UC2842AD1; UC3842AD1; UC2843AD1; UC3843AD1; UC2844AD1; UC3844AD1; UC2845AD1; UC3845AD1 2 DESCRIPTION The UC384xA family of control ICs provides the necessary features to implement off-line or DC to DC fixed frequency current mode control schemes with a minimal external parts count. Internally implemented circuits include a trimmed oscillator for precise DUTY CYCLE CONTROL under voltage lockout featuring start-up current less than 0.5mA, a precision reference trimmed for accuracy at the error amp input, logic to insure latched operation, a PWM comparator which also provides current limit control, and a totem pole output stage designed to source or sink high peak current. The output stage, suitable for driving N-Channel MOSFETs, is low in the off-state. ) s ( ct SO-8 Figure 2. Block Diagram (toggle flip flop used only in UC3844A and UC3845A) t e l o bs Vi 7 UVLO 34V GROUND S/R 5 O 8 5V REF INTERNAL BIAS 2.50V VREF GOOD LOGIC RT/CT VFB COMP CURRENT SENSE 4 2 1 3 6 OSC + - ERROR AMP. VREF 5V 50mA OUTPUT T 2R R S 1V R PWM LATCH CURRENT SENSE COMPARATOR D95IN331 May 2004 REV. 5 1/16 UC384XA - UC284XA Table 2. Absolute Maximum Ratings Symbol Parameter Vi Supply Voltage (low impedance source) Value Unit 30 V Vi Supply Voltage (Ii < 30mA) IO Output Current 1 A EO Output Energy (capacitive load) 5 J Self Limiting Analog Inputs (pins 2, 3) Error Amplifier Output Sink Current - 0.3 to 5.5 V 10 mA Ptot Power Dissipation at Tamb 25 C (DIP-8) 1.25 W Ptot Power Dissipation at Tamb 25 C (SO-8) 800 mW Tstg Storage Temperature Range - 65 to 150 C TJ Junction Operating Temperature - 40 to 150 C TL Lead Temperature (soldering 10s) 300 C * All voltages are with respect to pin 5, all currents are positive into the specified terminal. Figure 3. DIP-8/SO-8 Pin Connection (Top view) COMP 1 8 VREF VFB 2 7 Vi ISENSE 3 6 RT/CT 4 5 ) s ( ct N Pin 1 COMP 2 VFB bs 4 O 2/16 OUTPUT so GROUND Function This pin is the Error Amplifier output and is made available for loop compensation. r P e t e l o 3 u d o o r P b O - D95IN332 Table 3. Pin Description e t le c u d ) s t( This is the inverting input of the Error Amplifier. It is normally connected to the switching power supply output through a resistor divider. ISENSE A voltage proportional to inductor current is connected to this input. The PWM uses this information to terminate the output switch conduction. RT/CT The oscillator frequency and maximum Output duty cycle are programmed by connecting resistor RT to Vref and cpacitor CT to ground. Operation to 500kHz is possible. 5 GROUND This pin is the combined control circuitry and power ground. 6 OUTPUT This output directly drives the gate of a power MOSFET. Peak currents up to 1A are sourced and sunk by this pin. 7 VCC This pin is the positive supply of the control IC. 8 Vref This is the reference output. It provides charging current for capacitor CT through resistor RT. UC384XA - UC284XA Table 4. Thermal Data Symbol Parameter Rth j-amb Thermal Resistance Junction-ambient Max. DIP-8 SO-8 Unit 100 150 C/W Table 5. Electrical Characteristcs ( [note 1] Unless otherwise stated, these specifications apply for -25 < Tamb < 85C for UC284XA; 0 < Tamb < 70C for UC384XA; Vi = 15V (note 5); RT = 10K; CT = 3.3nF) Symbol Parameter UC284XA Test Condition UC384XA Min. Typ. Max. Min. Typ. Max. 4.95 4.90 Unit REFERENCE SECTION VREF Output Voltage Tj = 25C Io= 1mA 5.00 5.05 5.00 5.10 V VREF Line Regulation 12V Vi 25V 2 20 2 20 mV VREF Load Regulation 1 Io 20mA 3 25 3 25 mV VREF/T Temperature Stability eN (Note 2) 0.2 Total Output Variation Line, Load, Temperature Output Noise Voltage 10Hz f 10KHz Tj = 25C (note 2) Long Term Stability Tamb 4.9 -100 -180 -30 52 57 so e t le 0.2 1 5 - - - 1.6 - - 7.8 8.3 8.8 7.8 2.45 2.50 2.55 2.42 -0.1 -1 OSCILLATOR SECTION Frequency Tj = 25C fOSC/V Frequency Change with Volt. VREF/T Frequency Change with Temp. 47 VCC = 12V to 25V TA = Tlow to Thigh b O - VOSC Oscillator Voltage Swing (peak to peak) Idischg Discharge Current (VOSC =2V) TJ = 25C ) s ( ct ERROR AMP SECTION Input Voltage V2 Ib Input Bias Current VPIN1 = 2.5V BW PSRR Io Io - 2V Vo 4V 65 ) s t( V V 5 25 mV -100 -180 mA 47 52 57 KHz - 0.2 1 % 5 - % 1.6 - V 8.3 8.8 mA 2.50 2.58 V -0.1 -2 A o r P 90 65 90 dB Unity Gain Bandwidth TJ = 25C 0.7 1 0.7 1 MHz Power Supply Rejec. Ratio 12V Vi 25V 60 70 60 70 dB Output Sink Current VPIN2 = 2.7V VPIN1= 1.1V 2 12 2 12 mA Output Source Current VPIN2 = 2.3V VPIN1 = 5V -0.5 -1 -0.5 -1 mA VOUT High VPIN2 = 2.3V;RL = 15K to Ground 5 6.2 5 6.2 V VOUT Low VPIN2 = 2.7V;RL = 15K to Pin 8 t e l o bs O r P e - VFB = 5V u d o AVOL c u d 25 -30 mV/C 5.18 50 5 = 125C, 1000Hrs Output Short Circuit fOSC 4.82 50 (note 2) ISC 0.2 5.1 0.8 1.1 0.8 1.1 V CURRENT SENSE SECTION GV Gain (note 3 & 4) 2.85 3 3.15 2.85 3 3.15 V/V V3 Maximum Input Signal VPIN1 = 5V (note 3) 0.9 1 1.1 0.9 1 1.1 V Supply Voltage Rejection 12 Vi 25V (note 3) SVR Ib Input Bias Current Delay to Output 70 70 dB -2 -10 -2 -10 A 150 300 150 300 ns 3/16 UC384XA - UC284XA Table 5. Electrical Characteristcs (continued) ( [note 1] Unless otherwise stated, these specifications apply for -25 < Tamb < 85C for UC284XA; 0 < Tamb < 70C for UC384XA; Vi = 15V (note 5); RT = 10K; CT = 3.3nF) Symbol Parameter UC284XA Test Condition Min. UC384XA Typ. Max. ISINK = 20mA 0.1 ISINK = 200mA 1.6 Min. Unit Typ. Max. 0.4 0.1 0.4 V 2.2 1.6 2.2 V OUTPUT SECTION VOL Output Low Level VOH Output High Level VOLS UVLO Saturation VCC = 6V; I SINK = 1mA 0.7 1.2 0.7 1.2 V Rise Time Tj = 25C 50 150 50 150 ns 50 150 50 150 ns tr ISOURCE = 20mA 13 13.5 ISOURCE = 200mA 12 13.5 13 13.5 12 13.5 V V CL = 1nF (2) Fall Time tf Tj = 25C CL = 1nF (2) UNDER-VOLTAGE LOCKOUT SECTION Start Threshold Min Operating Voltage After Turn-on X842A/4A 15 16 17 14.5 16 17.5 7.8 8.4 9.0 7.8 8.4 9.0 V X842A/4A 9 10 11 8.5 c u d V X843A/5A 10 11.5 V X842A/3A 94 96 100 94 96 100 % X844A/5A so e t le 48 50 47 48 50 % 0 % Vi = 6.5V for UCX843A/ 45A 0.3 0.5 0.3 0.5 mA Vi = 14V for UCX842A/44A 0.3 0.5 0.3 0.5 mA 12 17 12 17 mA PWM SECTION Maximum Duty Cycle Minimum Duty Cycle TOTAL STANDBY CURRENT Ist Ii Start-up Current Viz ) s ( ct 47 b O - Operating Supply Current VPIN2 = VPIN3 = 0V Zener Voltage Ii = 25mA o r P e ) s t( du 30 36 o r P 0 30 36 V Notes: 1. Max package power dissipation limits must be respected; low duty cycle pulse techniques are used during test maintain Tj as close to Tamb as possible. 2. These parameters, although guaranteed, are not 100% tested in production. 3. Parameter measured at trip point of latch with VPIN2 = 0. 4. Gain defined as : A = VPIN1/VPIN3; 0 VPIN3 0.8V 5. Adjust Vi above the start threshold before setting at 15 V. t e l o s b O 4/16 UC384XA - UC284XA Figure 4. Open Loop Test Circuit. VREF 4.7K RT 2N2222 100K ERROR AMP. ADJUST 4.7K A VREF COMP VFB 1K ISENSE ISENSE ADJUST 5K RT/CT 1 Vi 0.1F 8 7 2 Vi 1W 1K 0.1F 3 6 4 5 OUTPUT OUTPUT GROUND CT GROUND D95IN343 ) s t( High peak currents associated with capacitive loads necessitate careful grounding techniques. Timing and bypass capacitors should be connected close to pin 5 in a single point ground. The transistor and 5 K potentiometer are used to sample the oscillator waveform and apply an adjustable ramp to pin 3. Figure 5. Oscillator Frequency vs Timing Resistance fo (Hz) D96IN362 Idischg (mA) 8.5 1M CT =4 1nF 2.2 100K 70 pF nF 10K 300 o r P e 1K 3K c u d 10K 30K (t s) t e l o D96IN363 bs Vi=15V VOSC=2V 7.5 7.0 -55 -25 0 25 50 75 100 TA(C) Figure 8. Error Amp Open-Loop Gain and Phase vs. Frequency. D95IN337 (dB) Vi=15V VO=2V to 4V RL=100K TA=25C 80 80 O D95IN335 o s b O - RT() Figure 6. Maximum Duty Cycle vs Timing Resistor fo (Hz) e t le o r P 8.0 nF 4.7 1K c u d Figure 7. Oscillator Discharge Current vs. Temperature. Gain 60 30 60 60 40 Phase 90 40 20 0 300 1K 3K 10K 30K RT() 20 120 0 150 -20 10 100 1K 10K 100K 1M 180 f(Hz) 5/16 UC384XA - UC284XA Figure 12. Output Saturation Voltage vs. Load Current. Figure 9. Current Sense Input Threshold vs. Error Amp Output Voltage. Vth (V) Vsat (V) D95IN338 D95IN341 Vi=15V Vi -1 1.0 TA=25C -2 0.8 Source Saturation (Load to Ground) TA=25C TA=-40C Vi=15V 80s Pulsed Load 120Hz Rate TA=125C 0.6 3 0.4 TA=-40C 2 TA=25C TA=-40C 0.2 1 0.0 0 0 2 4 6 VO(V) 0 Figure 10. Reference Voltage Change vs. Source Current.. 200 400 30 TA=25C so 10 0 20 40 60 (s) 80 100 Iref(mA) t c u b O - Figure 11. Reference Short Circuit Current vs. Temperature.. d o r P e ISC (mA) 100 Vi=15V RL0.1 t e l o 90 D95IN340 s b O 80 70 60 50 -55 6/16 -25 0 25 50 75 100 TA(C) 5 0 0 RT=10K CT=3.3nF VFB=0V ISense=0V TA=25C UCX842/44 15 TA=125C UCX843/45 P e let TA=-40C 0 ) s t( d o r 20 10 IO(mA) D95IN342 Vi=15V 20 600 uc Ii (mA) 50 40 GND Figure 13. Supply Current vs. Supply Voltage. D95IN339 60 Sink Saturation (Load to Vi) 10 20 30 Vi(V) UC384XA - UC284XA Figure 14. Output Waveform. Figure 15. Output Cross Conduction Figure 16. Oscillator and Output Waveforms. Vi 7 8 CT c u d 5V REG OUTPUT PWM 6 RT OUTPUT e t le OSCILLATOR ID CT 5 ) s ( ct GND o r P LARGE RT/SMALL CT CLOCK 4 ) s t( o s b O - CT OUTPUT SMALL RT/LARGE CT D95IN344 u d o Figure 17. Error Amp Configuration. r P e 2.5V t e l o s b O 1mA + Zi VFB 2 COMP 1 - Zf D95IN345 7/16 UC384XA - UC284XA Figure 18. Under Voltage Lockout. 7 Vi ON/OFF COMMAND TO REST OF IC ICC UC3842A UC3843A UC3844A UC3845A VON 16V 8.4V VOFF 10V 7.6V <17mA <0.5mA VCC VOFF VON D95IN346mod Figure 19. Current Sense Circuit. ERROR AMPL. IS 1 COMP R RS 2R R 3 CURRENT SENSE C e t le 5 GND D95IN347 Peak current (is) is determined by the formula 1V c u d ) s t( CURRENT SENSE COMPARATOR o r P o s b O - 1.0V I Smax -----------RS ) s ( ct A small RC filter may be required to suppress switch transients. u d o Figure 20. Slope Compensation Techniques. r P e t e l o s b O IS RSLOPE R1 RS VREG VREG 8 RT/CT RT/CT IS 4 CT ISENSE 8 RT RT RSLOPE R1 3 5 RS GND 4 CT ISENSE 3 5 GND D95IN348 8/16 UC384XA - UC284XA Figure 21. Isolated MOSFET Drive and Current Transformer Sensing. VCC Vin 7 ISOLATION BOUNDARY + 5.0Vref - VGS Waveforms + Q1 6 + 0 - S R Q 50% DC Ipk = - + 0 - V(pin 1) -1.4 3RS 25% DC ( NN ) S P + R 3 COMP/LATCH RS C NS NP c u d D95IN349 Figure 22. Latched Shutdown. 4 8 e t le OSC o s b O R ) s t( o r P BIAS R (s) t c u 2 od r P e t e l o O bs + 1mA + - EA 2R R 1 5 2N 3905 2N 3903 D95IN350 SCR must be selected for a holding current of less than 0.5mA at TA(min). The simple two transistor circuit can be used in place of the SCR as shown. All resistors are 10K. 9/16 UC384XA - UC284XA Figure 23. Error Amplifier Compensation From VO + 2.5V 1mA Ri 2R + - 2 Rd Cf EA R Rf 1 5 Error Amp compensation circuit for stabilizing any current-mode topology except for boost and flyback converters operating with continuous inductor current. From VO + 2.5V 1mA RP Ri - 2 CP 2R + Rd Cf EA R Rf c u d 1 5 D95IN351 o r P Error Amp compensation circuit for stabilizing current-mode boost and flyback topologies operating with continuous inductor current. e t le Figure 24. External Clock Synchronization. VREF o s b O 8 (t s) RT o r P e EXTERNAL SYNC INPUT t e l o s b O 10/16 c u d R BIAS R 4 + CT 0.01F 2 - OSC 2R + 47 ) s t( EA R 1 5 The diode clamp is required if the Sync amplitude is large enough to cause the bottom side of CT to go more than 300mV below ground D95IN352 UC384XA - UC284XA Figure 25. External Duty Cycle Clamp and Multi Unit Synchronization. VREF 8 RA R RB 8 5K 6 + 5 R + 7 2 S - NE555 2R + - 5K 1 OSC + Q 2 4 3 R 5K C BIAS 4 EA R 1 ) s t( 5 f= 1.44 Dmax = (RA + 2RB)C c u d TO ADDITIONAL UCX84XAs RB D95IN353 RA + 2RB e t le Figure 26. Soft-Start Circuit 8 (t s) R o r P e 4 t e l o s b O 2 1M c u d o s b O - o r P 5Vref + BIAS - R OSC + 1mA + - S 2R Q + EA 1V R R - 1 C 5 D95IN354 11/16 UC384XA - UC284XA Figure 27. Soft-Start and Error Amplifier Output Duty Cycle Clamp. VCC Vin 7 8 + 5Vref R - + BIAS 7 - R 4 1mA 2 R2 6 OSC + VClamp S 2R + - 5 Q R + EA 1V R Comp/Latch 1 c u d 5 R1 C VCLAMP = * R1 R1 + R 2 where 0 <VCLAMP <1V Ipk(max) = VCLAMP RS e t le ) s ( ct u d o r P e s b O 12/16 ) s t( RS BC109 t e l o Q1 o s b O - o r P D95IN355 UC384XA - UC284XA Figure 28. SO-8 Mechanical Data & Package Dimensions mm inch DIM. MIN. TYP. MAX. MIN. TYP. MAX. A 1.35 1.75 0.053 0.069 A1 0.10 0.25 0.004 0.010 A2 1.10 1.65 0.043 0.065 B 0.33 0.51 0.013 0.020 C 0.19 0.25 0.007 0.010 D (1) 4.80 5.00 0.189 0.197 E 3.80 4.00 0.15 0.157 e 1.27 0.050 H 5.80 6.20 0.228 0.244 h 0.25 0.50 0.010 0.020 L 0.40 1.27 0.016 0.050 k OUTLINE AND MECHANICAL DATA ddd 0 (min.), 8 (max.) c u d 0.10 0.004 Note: (1) Dimensions D does not include mold flash, protrusions or gate burrs. Mold flash, potrusions or gate burrs shall not exceed 0.15mm (.006inch) in total (both side). ) s ( ct ) s t( o r P SO-8 e t le o s b O - u d o r P e t e l o s b O 0016023 C 13/16 UC384XA - UC284XA Figure 29. DIP-8 Mechanical Data & Package Dimensions mm inch DIM. MIN. A TYP. MAX. MIN. 3.32 TYP. MAX. 0.131 a1 0.51 B 1.15 1.65 0.045 0.065 b 0.356 0.55 0.014 0.022 b1 0.204 0.304 0.008 0.012 0.020 D E 10.92 7.95 9.75 0.430 0.313 0.384 e 2.54 0.100 e3 7.62 0.300 e4 7.62 0.300 F 6.6 0.260 I 5.08 0.200 L 3.18 Z 3.81 0.125 1.52 r P e s b O 14/16 o r P DIP-8 e t le o s b O - 0.060 u d o c u d 0.150 ) s ( ct t e l o OUTLINE AND MECHANICAL DATA ) s t( UC384XA - UC284XA Table 6. Revision History Date Revision Description of Changes March 1999 4 First Issue in EDOCS May 2004 5 NOT FOR NEW DESIGN c u d e t le ) s ( ct ) s t( o r P o s b O - u d o r P e t e l o s b O 15/16 UC384XA - UC284XA c u d e t le ) s ( ct ) s t( o r P o s b O - u d o r P e t e l o Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. s b O The ST logo is a registered trademark of STMicroelectronics. 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