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UC284XA
UC384XA
May 2004
1 FEATURES
■TRIMMED OSCILLATOR DISCHARGE
CURRENT
■CURRENT MODE OPERATION TO 500kHz
AUTOMATIC FEED FORWARD
COMPENSATION
■LATCHING PWM FOR CYCLE-BY-CYCLE
CURRENT LIMITING
■INTERNALLY TRIMMED REFERENCE WITH
UNDERVOLTAGE LOCKOUT
■HIGH CURRENT TOTEM POLE OUTPUT
UNDERVOLTAGE LOCKOUT WITH
HYSTERESIS
■LOW START-UP CURRENT (< 0.5mA)
DOUBLE PULSE SUPPRESSION
2 DESCRIPTION
The UC384xA family of control ICs provides the
necessa ry feature s to impleme nt off-li ne or DC to
DC fixed frequency current mode control schemes
with a minimal external parts count. Internally im-
plemen ted cir cu its i nc lud e a trimmed o sc illa tor fo r
precise DUTY CYCLE CONTROL under voltage
lockout featuring start-up current less than 0.5mA,
a precisi on referenc e trimmed fo r accura cy at the
error amp input, log ic to insure l atched oper ation,
a PWM comparator which also provides current
limit control, and a totem pole output stage de-
signed to source or sink high peak current. The
output stage, suitable for driving N-Channel MOS-
FETs, is low in the off-state.
Differences between members of this family are
the under-voltage lockout thresholds and maxi-
mum duty cycle ranges. The UC3842A and
UC3844A h av e UVL O th res holds o f 16V (o n) a nd
10V (off), ideally suited off-line applications The
corresponding thresholds for the UC3843A and
UC3845A ar e 8.5 V and 7.9V. The UC3 842A a nd
UC3843A can operate to duty cycles approaching
100%. A range of the zero to < 50 % is obtained by
the UC3844A and UC3 845A by the addition of an
internal toggle flip flo p which bl anks the outp ut off
every other clock cycle.
NOT FOR NEW DESIGN
HIGH PERFORMANCE CURRENT MODE PWM CONTROLLER
Figure 2. Block Diagram (toggle flip flop used only in UC3844A and UC3845A)
UVLO
S/R 5V
REF
34V
INTERNAL
BIAS
VREF GOOD
LOGIC
2.50V
T
S
R
OSC
R1V
CURRENT
SENSE
COMPARATOR
2R
+
-PWM
LATCH
7
5
4
2
1
3
8
6
ERROR AMP.
Vi
GROUND
RT/CT
VFB
COMP
CURRENT
SENSE
VREF
5V 50mA
OUTPUT
D95IN331
REV. 5
Fi
gure 1.
P
ac
k
age
Table 1. Order Codes
Part Number Package
UC2842 AD 1; UC3842 AD 1;
UC2843 AD 1; UC3843 AD 1;
UC2844 AD 1; UC3844 AD 1;
UC2845 AD 1; UC3845 AD 1
SO-8
UC2842AN; UC3842AN;
UC2843AN; UC3843AN;
UC2844AN; UC3844AN;
UC2845AN; UC3845AN
DIP-8
SO-8
DIP-8
Obsolete Product(s) - Obsolete Product(s)
Obsolete Product(s) - Obsolete Product(s)
UC384XA - U C284XA
2/16
Table 2. Absolute Maximum Ratings
* All voltages are with respect to pin 5, all currents are positive into the spe cif ied terminal.
Figure 3. DIP-8/SO-8 Pin Connection (Top view)
Table 3. Pin Description
Symbol Parameter Value Unit
V
i
Supply Voltage (low impedance source) 30 V
V
i
Supply Voltage (Ii < 30mA) Self Limiting
I
O
Output Current ±1A
E
O
Output Energy (capacitive load) 5 µJ
Analog Inputs (pins 2, 3) – 0.3 to 5.5 V
Error Am plif ier Ou tp ut Sin k Cur ren t 10 mA
P
tot
Power Dis sip atio n at T
amb
≤ 25 °C (DIP-8) 1.25 W
P
tot
Power Dis sip atio n at T
amb
≤ 25 °C (SO-8) 800 mW
T
stg
Storage Temperature Range – 65 to 150 °C
T
J
Junction Operating Temperature – 40 to 150 °C
T
L
Lead Temperature (soldering 10s) 300 °C
N° Pin Function
1 COMP This pin is the Error Amplifier output and is made available for loop compensation.
2V
FB
This is the inverting input of the Error Amplifier. It is normally connected to the switching power
supply output through a resistor divider.
3I
SENSE
A voltage proportional to inductor current is connected to this input. The PWM uses this
information to terminate the output switch conduction.
4R
T
/C
T
The oscillator frequency and maximum Output duty cycle are programmed by connecting
resistor R
T
to V
ref
and cpacitor C
T
to ground. Operation to 500kHz is possible.
5 GROUND This pin is the combined control circuitry and power ground.
6 OUTPUT This output directly drives the gate of a power MOSFET. Peak currents up to 1A are sourced
and sunk by this pin.
7V
CC
This pin is the positive supply of the control IC.
8V
ref
This is the reference output. It provides charging current for capacitor C
T
through resistor R
T
.
COMP
VFB
ISENSE
RT/CTGROUND
OUTPUT
Vi
VREF
1
3
2
4
6
5
7
8
D95IN332
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UC384XA - UC284XA
Table 4. Thermal Data
Symbol Parameter DIP-8 SO-8 Unit
R
th j-amb
Thermal Resistance Junction-ambient Max. 100 150 °C/W
Table 5. Electrical Characteristcs
( [note 1] Unless otherwise stated, these specifications apply for -25 < T
amb
< 85°C for UC284XA;
0 < T
amb
< 70°C for UC384XA; V
i
= 15V (note 5); R
T
= 10K; C
T
= 3.3nF)
Symbol Parameter Test Condition UC284XA UC384XA Unit
Min. Typ. Max. Min. Typ. Max.
REFE RE NC E SE CT IO N
V
REF
Output Volta ge T
j
= 25°C I
o
= 1mA 4.95 5.00 5.05 4.90 5.00 5.10 V
∆V
REF
Line Regu lati on 12V ≤ V
i
≤ 25V 2 20 2 20 mV
∆V
REF
Load Regulation 1 ≤ I
o
≤ 20mA 3 25 3 25 mV
∆
V
REF
/
∆
T
Temperature Stability (Note 2) 0.2 0.2
mV/°C
Total Output Variation Line, Load, Temperature 4.9 5.1 4.82 5.18 V
e
N
Output No ise Voltage 10Hz ≤ f ≤ 10KHz
T
j
= 25°C (note 2) 50 50 µV
Long Term Stability Tamb = 125°C, 1000Hrs
(note 2) 525 525mV
ISC Output Sh ort Circu it -30 -100 -180 -30 -100 -180 mA
OSCILLATOR SECTION
f
OSC
Frequency T
j
= 25°C 47 52 57 47 52 57 KHz
∆
f
OSC
/
∆
V
Frequency Change with Volt.
V
CC
= 12V to 25V – 0.2 1 – 0.2 1 %
∆
V
REF
/
∆
T
Frequency Change with Temp.
T
A
= T
low
to T
high
–5––5–%
V
OSC
Oscillator Voltage Swing (peak to peak) – 1.6 – – 1.6 – V
I
dischg
Dis charge Cu rr ent (V
OSC
=2V)
T
J
= 25°C 7.8 8.3 8.8 7.8 8.3 8.8 mA
ERROR AMP SECTION
V
2
Input Voltage V
PIN1
= 2.5V 2.45 2.50 2.55 2.42 2.50 2.58 V
I
b
Input Bias Current V
FB
= 5V -0.1 -1 -0. 1 -2 µA
A
VOL
2V ≤ V
o
≤ 4V 65 90 65 90 dB
BW Unity Gain Bandwidth T
J
= 25°C 0.7 1 0.7 1 MHz
PSRR Power Supply Rejec. Ratio 12V ≤ V
i
≤ 25V 6070 6070 dB
I
o
Output Sin k Cur ren t V
PIN2
= 2.7V
V
PIN1
= 1.1V 212 212 mA
I
o
Output So urc e Cur ren t V
PIN2
= 2.3V V
PIN1
= 5V -0.5 -1 -0.5 -1 mA
V
OUT
High V
PIN2
= 2.3V;R
L
= 15KΩ to
Ground 5 6.2 5 6.2 V
V
OUT
Low V
PIN2
= 2.7V;R
L
= 15KΩ to
Pin 8 0.8 1.1 0.8 1.1 V
CURRENT SENSE SECTION
G
V
Gain (note 3 & 4) 2.85 3 3.15 2.85 3 3.15 V/V
V
3
Maximum Inp ut Sign al V
PIN1
= 5V (note 3) 0.9 1 1.1 0.9 1 1.1 V
SVR Supply Volta ge Reje ctio n 1 2 ≤ V
i
≤ 25V (note 3) 70 70 dB
I
b
Input Bias Current -2 -10 -2 -10 µA
Delay to Output 150 300 150 300 ns
Obsolete Product(s) - Obsolete Product(s)
UC384XA - U C284XA
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Notes: 1. Max packag e power dissipation limi ts must be respect ed; low duty cycle pu lse techniqu es are used during tes t maintain T
j
as close
to T
amb
as possible.
2. These parameters, alt hough guaranteed, are not 100% tested in pr oduction.
3. Parameter measured at tri p point of latch with V
PIN2
= 0.
4. Gain defined as : A = ∆V
PIN1
/∆V
PIN3
; 0 ≤ V
PIN3
≤ 0.8V
5. Adjust V
i
above the start threshold before setting at 15 V.
OUTPUT SECTION
V
OL
Output Low Level I
SINK
= 20mA 0.1 0.4 0.1 0.4 V
I
SINK
= 200mA 1.6 2.2 1.6 2.2 V
V
OH
Output Hig h Level I
SOURCE
= 20mA 13 13.5 13 13.5 V
I
SOURCE
= 200mA 12 13.5 12 13.5 V
V
OLS
UVLO Saturation V
CC
= 6V; I
SINK
= 1mA 0.7 1.2 0.7 1.2 V
t
r
Rise Time T
j
= 25°C
C
L
= 1nF
(2)
50 150 50 150 ns
t
f
Fall Tim e T
j
= 25°C
C
L
= 1nF
(2)
50 150 50 150 ns
UNDER-VOLTAGE LOCKOUT SECTION
Start Th res ho ld X842A /4A 15 16 17 14.5 16 17.5 V
X843A/5A 7.8 8.4 9.0 7.8 8.4 9.0 V
Min Operating Voltage
After Turn-on X842A/4A 9 10 11 8.5 10 11.5 V
PWM SECTION
Maximum Du ty Cy cle X842A/3A 94 96 10 0 94 96 10 0 %
X844A/5A 47 48 50 47 48 50 %
Minimum Duty Cycle 0 0 %
TOTAL STANDBY CURRENT
I
st
Start-up Current V
i
= 6.5V for UCX843A/
45A 0.3 0.5 0.3 0.5 mA
V
i
= 14V for UCX842A/44A 0.3 0.5 0.3 0.5 mA
I
i
Operating Supply Current V
PIN2
= V
PIN3
= 0V 12 17 12 17 mA
V
iz
Zener Voltage I
i
= 25mA 3036 3036 V
Table 5. Electrical Characteristcs (continued)
( [note 1] Unless otherwise stated, these specifications apply for -25 < T
amb
< 85°C for UC284XA;
0 < T
amb
< 70°C for UC384XA; V
i
= 15V (note 5); R
T
= 10K; C
T
= 3.3nF)
Symbol Parameter Test Condition UC284XA UC384XA Unit
Min. Typ. Max. Min. Typ. Max.
Obsolete Product(s) - Obsolete Product(s)
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UC384XA - UC284XA
Figure 4. Open Loop Test Circuit.
High peak currents associated with capacitive loads necessitate careful grounding techniques. Timing and
bypass ca pacitors s hould be c onnected close to pin 5 in a singl e point gr ound. The tr ansistor a nd 5 KΩ
potentiometer are used to sample the oscillator waveform and apply an adjustable ramp to pin 3.
R
T
A2N2222
4.7KΩ
1KΩ
ERROR AMP.
ADJUST
4.7KΩ5KΩ
I
SENSE
ADJUST
100KΩCOMP
V
FB
I
SENSE
R
T
/C
T
1
2
3
4
C
T
7
6
5
8
V
REF
V
i
OUTPUT
GROUND
0.1µF
0.1µF
V
REF
V
i
OUTPUT
GROUND
1W
1KΩ
D95IN343
Figure 5. Oscillator Frequency vs Timing
Resistance
Figure 6. Maximum Duty Cycle vs Timing
Resistor
Figure 7. Oscillator Discharge Current vs.
Temperature.
Figure 8. Error Amp Open-Loop Gain and
Phase vs. Frequenc y.
300 1K 3K 10K 30K R
T
(Ω)
1K
10K
100K
1M
f
o
(Hz)
D96IN362
CT=470pF
1nF
2.2nF
4.7nF
300 1K 3K 10K 30K R
T
(Ω)
0
20
40
60
f
o
(Hz)
D96IN363
80
-55 -25 0 25 50 75 100 TA(˚C)
7.0
7.5
8.0
8.5
Idischg
(mA)
D95IN335
Vi=15V
VOSC=2V
10 100 1K 10K 100K 1M f
(
Hz
)
-20
0
20
40
60
80
(dB)
180
150
120
90
60
30
φ
D95IN337
Vi=15V
VO=2V to 4V
RL=100K
TA=25˚C
Gain
Phase
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Figure 9. Current Sense Input Threshold vs.
Error Amp Output Voltage.
Figure 10. Reference Voltage Change vs.
Source Current..
Figure 11. Reference Short Circuit Current vs.
Temperature..
Figure 12. Output Saturation Voltage vs. Load
Current.
Figure 13. Supply Current vs. Supply Voltage.
0246V
O(V)
0.0
0.2
0.4
0.6
0.8
1.0
Vth
(V)
D95IN338
Vi=15V
TA=-40˚C
TA=125˚C
TA=25˚C
0 20406080100I
ref(mA)
D95IN339
0
10
20
30
40
50
60 Vi=15V
TA=-40˚C
TA=125˚C
T
A
=25˚C
-55 -25 0 25 50 75 100 TA(˚C)
D95IN340
50
60
70
80
90
100
ISC
(mA) Vi=15V
RL≤0.1Ω
0 200 400 600 IO(mA)
0
1
2
3
-2
-1
Vsat
(V)
D95IN341
Vi=15V
80µs Pulsed Load 120Hz Rate
TA=-40˚C
TA=25˚C
Vi
TA=-40˚C TA=25˚C
GND
Sink Saturation
(Load to Vi)
Source Saturation
(Load to Ground)
0 102030V
i(V)
0
5
10
15
20
Ii
(mA)
UCX843/45
UCX842/44
RT=10K
CT=3.3nF
VFB=0V
ISense=0V
TA=25˚C
D95IN342
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UC384XA - UC284XA
Figure 14. Output Waveform. Figure 15. Output Cross Conduction
Figure 16. Oscillator and Output Waveforms.
Figure 17. Error Amp Configuration.
5V REG
OSCILLATOR
PWM
CLOCK
8
4
5
6
RT
CT
GND
OUTPUT
7
Vi
ID
CT
OUTPUT
LARGE RT/SMALL CT
CT
OUTPUT
SMALL RT/LARGE CT
D95IN344
Zi
Zf
1mA
2
1
VFB
COMP
2.5V
D95IN345
+
-
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Figure 18. Under Voltage Lockout.
Figure 19. Current Sense Circuit.
Peak current (i
s
) is determined by the formula
A small RC filter may be required to suppress switch transients.
Figure 20. Slope Compensation Techniques.
UC3842A
UC3844A UC3843A
UC3845A
16V 8.4V
10V 7.6V
VON
VOFF
ViON/OFF COMMAND
TO REST OF IC
7
<0.5mA
<17mA
ICC
VCC
VOFF VON
D95IN346mod
ERROR
AMPL. 2R
R1V
CURRENT
SENSE
COMPARATOR
1
CURRENT
SENSE
COMP
CRS
R3
5
GND
IS
D95IN347
ISmax 1.0V
RS
------------
≈
RS
R1
ISRSLOPE CT
RT
VREG 8
RT/CT
ISENSE
4
35
GND RS
R1
IS
RSLOPE CT
RT
VREG 8
RT/CT
ISENSE
4
35
GND
D95IN348
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UC384XA - UC284XA
Figure 21. Isolated MOSFET Drive and Current Transformer Sensing.
Figure 22. Latched Shutdown.
7
6
COMP/LATCH
ISOLATION
BOUNDARY
D95IN349
5.0Vref
VCC
+
-
+
-
Q
S
R
+
-
3R
RSNS
C
Vin
Q1
NP
VGS Waveforms
+
0+
0
-- 50% DC 25% DC
Ipk = V(pin 1) -1.4
3RS
NS
NP
()
D95IN350
BIAS
+
-EA
R
+
OSC
2N
3905
2N
3903
1mA
R
R
2R
1
2
8
4
SCR must be selected for a holding current of less than 0.5mA at TA(min).
The sim
p
le two transistor circuit can be used in
p
lace of the SCR as shown. All resistors are 10K.
5
Obsolete Product(s) - Obsolete Product(s)
UC384XA - U C284XA
10/16
Figure 23. Error Amplifier Compensation
Figure 24. External Clock Synchronization.
D95IN351
+
-EA
Ri
+
1mA
RdR
2R
5
CfRf
1
2
From VO2.5V
+
-EA
RP
+
1mA
RdR
2R
5
CfRf
1
2
From VO2.5V
Error Amp compensation circuit for stabilizing any current-mode topology except
for boost and flyback converters operating with continuous inductor current.
CP
Ri
Error Amp compensation circuit for stabilizing current-mode boost and flyback
to
p
olo
g
ies o
p
eratin
g
with continuous inductor current.
D95IN352
+
-EA
+
R
2R
5
RT
1
2
EXTERNAL
SYNC INPUT
The diode clamp is required if the Sync amplitude is large enough to cause
the bottom side of CT to go more than 300mV below ground
R
BIAS
OSC
CT
0.01µF
47Ω
4
8
VREF
R
Obsolete Product(s) - Obsolete Product(s)
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UC384XA - UC284XA
Figure 25. External Duty Cycle Clamp and Multi Unit Synchronization.
Figure 26. Soft-Start Circuit
D95IN353
+
-
+
RA
1
7
f =
R
BIAS
OSC
C
6
VREF
RRB
+
-
+
-EA R
2R
R
S
Q
84
5
2
3
5K
5K
5K NE555
8
4
2
1
5
TO ADDITIONAL
UCX84XAs
1.44
(RA + 2RB)C Dmax = RB
RA + 2RB
D95IN354
+
R
BIAS
OSC
C
R
+
-
+
-EA R
2R
R
S
Q
8
4
2
1
5
1mA
1V
+
-
5Vref
1MΩ
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UC384XA - U C284XA
12/16
Figure 27. Soft-Start and Error Amplifier Output Duty Cycle Clamp.
D95IN355
+
R
BIAS
OSC
C
R
+
-
+
-EA R
2R
R
S
Q
8
4
2
1
5
1mA
1V
+
-
5Vref
R2
R1
VClamp
+
-
Comp/Latch
7
RS
VCC
Q1
Vin
7
6
5
BC109
VCLAMP = ·R1
R1 + R2where 0 <VCLAMP <1V Ipk(max) = VCLAMP
RS
Obsolete Product(s) - Obsolete Product(s)
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UC384XA - UC284XA
Figure 28. SO-8 Mechanical Data & Package Dimensions
OUTLI NE AND
M E CHAN ICAL DATA
DIM. mm inch
MIN. TYP. MAX. MIN. TYP. MAX.
A 1.35 1.75 0.053 0.069
A1 0.10 0.25 0.004 0.010
A2 1.10 1.65 0.043 0.065
B 0.33 0.51 0.013 0.020
C 0.19 0.25 0.007 0.010
D (1) 4.80 5.00 0.189 0.197
E 3.80 4.00 0.15 0.157
e 1.27 0.050
H 5.80 6.20 0.228 0.244
h 0.25 0.50 0.010 0.020
L 0.40 1.27 0.016 0.050
k 0˚ (min.), 8˚ (max.)
ddd 0.10 0.004
Note: (1) Dimensions D does not include mold flash, protru-
s i on s or gate burrs .
Mold fla sh, potr usio ns or ga te b urrs sh all no t ex ceed
0.15mm (.006inch) in total (both side).
SO-8
0016023 C
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Figure 29. DIP-8 Mechanical Data & Package Dimensions
OUTLINE AND
MECHANICAL DATA
DIM. mm inch
MIN. TYP. MAX. MIN. TYP. MAX.
A3.32 0.131
a1 0.51 0.020
B 1.15 1.65 0.045 0.065
b 0.356 0.55 0.014 0.022
b1 0.204 0.304 0.008 0.012
D 10.92 0.430
E 7.95 9.75 0.313 0.384
e2.54 0.100
e3 7.62 0.300
e4 7.62 0.300
F 6.6 0.260
I 5.08 0.200
L 3.18 3.81 0.125 0.150
Z 1.52 0.060
DIP-8
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UC384XA - UC284XA
Tab le 6. Revision History
Date Revision Descrip tio n of Ch anges
March 1999 4 First Issue in EDOCS
May 2004 5 NOT FOR NEW DESIGN
Obsolete Product(s) - Obsolete Product(s)
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility f or t he consequences
of use of such inf ormation nor for any infri ngement of patents or othe r rights of th ird parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previous ly supplied. ST Microelectronic s products are not
authorized for use as critical components in life suppor t devices or systems without express written approval of STMi croelectro nics.
The ST logo is a registered trademark of STMicroelectronics.
All other names ar e the property of their respective owners
© 2004 STMicroele ctronics - All rights reserved
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UC384XA - U C284XA
