Power-On
Reset
DAC
Register 14-/16-BitDAC Output
Buffer
InputControl
Logic
Power-Down
ControlLogic Resistor
Network
SYNC SCLK DIN
AVDD GND
VOUT
REF(+)
DAC8311
DAC8411
www.ti.com
SBAS439A –AUGUST 2008–REVISED AUGUST 2011
1.8V to 5.5V, 80μA, 14- and 16-Bit, Low-Power, Single-Channel,
DIGITAL-TO-ANALOG CONVERTERS in SC70 Package
Check for Samples: DAC8311,DAC8411
1FEATURES DESCRIPTION
The DAC8311 (14-bit) and DAC8411 (16-bit) are
234•Relative Accuracy: low-power, single-channel, voltage output
–1 LSB INL (DAC8311: 14-bit) digital-to-analog converters (DAC). They provide
–4 LSB INL (DAC8411: 16-bit) excellent linearity and minimize undesired
code-to-code transient voltages while offering an
•microPower Operation: 80μA at 1.8V easy upgrade path within a pin-compatible family. All
•Power-Down: 0.5μA at 5V, 0.1μA at 1.8V devices use a versatile, 3-wire serial interface that
•Wide Power Supply: +1.8V to +5.5V operates at clock rates of up to 50MHz and is
compatible with standard SPI™, QSPI™,
•Power-On Reset to Zero Scale MICROWIRE™, and digital signal processor (DSP)
•Straight Binary Data Format interfaces.
•Low Power Serial Interface with All devices use an external power supply as a
Schmitt-Triggered Inputs: Up to 50MHz reference voltage to set the output range. The
•On-Chip Output Buffer Amplifier, Rail-to-Rail devices incorporate a power-on reset (POR) circuit
Operation that ensures the DAC output powers up at 0V and
•SYNC Interrupt Facility remains there until a valid write to the device occurs.
The DAC8311 and DAC8411 contain a power-down
•Extended Temperature Range –40°C to +125°Cfeature, accessed over the serial interface, that
•Pin-Compatible Family in a Tiny, 6-Pin SC70 reduces current consumption of the device to 0.1μA
Package at 1.8V in power down mode. The low power
consumption of this part in normal operation makes it
APPLICATIONS ideally suited for portable, battery-operated
equipment. The power consumption is 0.55mW at 5V,
•Portable, Battery-Powered instruments reducing to 2.5μW in power-down mode.
•Process Control These devices are pin-compatible with the DAC5311,
•Digital Gain and Offset Adjustment DAC6311, and DAC7311, offering an easy upgrade
•Programmable Voltage and Current Sources path from 8-, 10-, and 12-bit resolution to 14- and
16-bit. All devices are available in a small, 6-pin,
SC70 package. This package offers a flexible,
pin-compatible, and functionally-compatible drop-in
RELATED solution within the family over an extended
DEVICES 16-BIT 14-BIT 12-BIT 10-BIT 8-BIT temperature range of –40°C to +125°C.
Pin and
Function DAC8411 DAC8311 DAC7311 DAC6311 DAC5311
Compatible
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2SPI, QSPI are trademarks of Motorola, Inc.
3MICROWIRE is a trademark of National Semiconductor Corporation.
4All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright ©2008–2011, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
DAC8311
DAC8411
SBAS439A –AUGUST 2008–REVISED AUGUST 2011
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGE/ORDERING INFORMATION(1)
MAXIMUM MAXIMUM
RELATIVE DIFFERENTIAL SPECIFIED
ACCURACY NONLINEARITY PACKAGE- PACKAGE TEMPERATURE PACKAGE
PRODUCT (LSB) (LSB) LEAD DESIGNATOR RANGE MARKING
DAC8411 ±8±2 SC70-6 DCK –40°C to 125°C D84
DAC8311 ±4±1 SC70-6 DCK –40°C to 125°C D83
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the
device product folder at www.ti.com.
ABSOLUTE MAXIMUM RATINGS(1)
PARAMETER VALUE UNIT
AVDD to GND –0.3 to +6 V
Digital input voltage to GND –0.3 to +AVDD +0.3 V
AVOUT to GND –0.3 to +AVDD +0.3 V
Operating temperature range –40 to +125 °C
Storage temperature range –65 to +150 °C
Junction temperature (TJmax) +150 °C
Power dissipation (TJmax –TA)/θJA
θJA thermal impedance 250 °C/W
(1) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute
maximum conditions for extended periods may affect device reliability.
2Copyright ©2008–2011, Texas Instruments Incorporated
DAC8311
DAC8411
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SBAS439A –AUGUST 2008–REVISED AUGUST 2011
ELECTRICAL CHARACTERISTICS
At AVDD = +1.8V to +5.5V, RL= 2kΩto GND, and CL= 200 pF to GND, unless otherwise noted.
DAC8411, DAC8311
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
STATIC PERFORMANCE(1)
Resolution 16 Bits
3.6V to 5V ±4±8
Measured by the line passing
Relative accuracy LSB
DAC8411 through codes 485 and 64714 1.8V to 3.6V ±4±12
Differential ±0.5 ±2 LSB
nonlinearity
Resolution 14 Bits
Measured by the line passing through codes 120 and
Relative accuracy ±1±4 LSB
DAC8311 16200
Differential ±0.125 ±1 LSB
nonlinearity
Offset error Measured by the line passing through two codes(2) ±0.05 ±4 mV
Offset error drift 3 μV/°C
Zero code error All zeros loaded to the DAC register 0.2 mV
Full-scale error All ones loaded to DAC register 0.04 0.2 % of FSR
Gain error 0.05 ±0.15 % of FSR
AVDD = +5V ±0.5 ppm of
Gain temperature coefficient FSR/°C
AVDD = +1.8V ±1.5
OUTPUT CHARACTERISTICS(3)
Output voltage range 0 AVDD V
RL= 2kΩ, CL= 200 pF, AVDD = 5V, 1/4 scale to 3/4 scale 6 10 μs
Output voltage settling time RL= 2MΩ, CL= 470pF 12 μs
Slew rate 0.7 V/μs
RL=∞470 pF
Capacitive load stability RL= 2kΩ1000 pF
Code change glitch impulse 1LSB change around major carry 0.5 nV-s
Digital feedthrough 0.5 nV-s
Power-on glitch impulse RL= 2kΩ, CL= 200pF, AVDD = 5V 17 mV
DC output impedance 0.5 Ω
AVDD = +5V 50 mA
Short-circuit current AVDD = +3V 20 mA
Power-up time Coming out of power-down mode 50 μs
AC PERFORMANCE
SNR 88 dB
TA= +25°C, BW = 20kHz, 16-bit level, AVDD = 5V,
THD –66 dB
fOUT = 1kHz, 1st 19 harmonics removed for SNR
SFDR 66 dB
calculation
SINAD 66 dB
TA= +25°C, at zero-scale input, fOUT = 1kHz, AVDD = 5V 17 nV/√Hz
DAC output noise density(4) TA= +25°C, at mid-code input, fOUT = 1kHz, AVDD = 5V 110 nV/√Hz
DAC output noise(5) TA= +25°C, at mid-code input, 0.1Hz to 10Hz, AVDD = 5V 3 μVpp
(1) Linearity calculated using a reduced code range of 485 to 64714 for 16-bit, and 120 to 16200 for 14-bit, output unloaded.
(2) Straight line passing through codes 485 and 64714 for 16-bit, and 120 and 16200 for 14-bit, output unloaded.
(3) Specified by design and characterization, not production tested.
(4) For more details, see Figure 31.
(5) For more details, see Figure 32.
Copyright ©2008–2011, Texas Instruments Incorporated 3
DAC8311
DAC8411
SBAS439A –AUGUST 2008–REVISED AUGUST 2011
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
At AVDD = +1.8V to +5.5V, RL= 2kΩto GND, and CL= 200 pF to GND, unless otherwise noted.
DAC8411, DAC8311
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
LOGIC INPUTS(6)
Input current ±1μA
AVDD = 2.7V to 5.5V 0.3AVDD V
VINL, input low voltage AVDD = 1.8V to 2.7V 0.1AVDD V
AVDD = 2.7V to 5.5V 0.7AVDD V
VINH, input high voltage AVDD = 1.8V to 2.7V 0.9AVDD V
Pin capacitance 1.5 3 pF
POWER REQUIREMENTS
AVDD 1.8 5.5 V
AVDD = 3.6V to 5.5V 110 160
VINH = AVDD and VINL =
Normal mode AVDD = 2.7V to 3.6V 95 150 μA
GND, at mid-scale code(7) AVDD = 1.8V to 2.7V 80 140
IDD AVDD = 3.6V to 5.5V 0.5 3.5
VINH = AVDD and VINL =
All power-down mode AVDD = 2.7V to 3.6V 0.4 3.0 μA
GND, at mid-scale code AVDD = 1.8V to 2.7V 0.1 2.0
AVDD = 3.6V to 5.5V 0.55 0.88
VINH = AVDD and VINL =
Normal mode AVDD = 2.7V to 3.6V 0.25 0.54 mW
GND, at mid-scale code AVDD = 1.8V to 2.7V 0.14 0.38
Power
dissipation AVDD = 3.6V to 5.5V 2.50 19.2
VINH = AVDD and VINL =
All power-down mode AVDD = 2.7V to 3.6V 1.08 10.8 μW
GND, at mid-scale code AVDD = 1.8V to 2.7V 0.72 8.1
TEMPERATURE RANGE
Specified performance –40 +125 °C
(6) Specified by design and characterization, not production tested.
(7) For more details, see Figure 12,Figure 53, and Figure 83.
4Copyright ©2008–2011, Texas Instruments Incorporated
1
2
3
6
5
4
SYNC
SCLK
DIN
VOUT
GND
AV /V
DD REF
DAC8311
DAC8411
www.ti.com
SBAS439A –AUGUST 2008–REVISED AUGUST 2011
PIN CONFIGURATION
DCK PACKAGE
SC70-6
(TOP VIEW)
Table 1. PIN DESCRIPTION
PIN NAME DESCRIPTION
Level-triggered control input (active low). This is the frame sychronization signal for the input data. When
SYNC goes low, it enables the input shift register and data are transferred in on the falling edges of the
following clocks. The DAC is updated following the 24th (DAC8411) or 16th (DAC8311) clock cycle,
1 SYNC unless SYNC is taken high before this edge, in which case the rising edge of SYNC acts as an interrupt
and the write sequence is ignored by the DAC8x11. Refer to the DAC8311 and DAC8411 SYNC Interrupt
sections for more details.
2 SCLK Serial Clock Input. Data can be transferred at rates up to 50MHz.
Serial Data Input. Data is clocked into the 24-bit (DAC8411) or 16-bit (DAC8311) input shift register on
3 DIN the falling edge of the serial clock input.
4 AVDD/VREF Power Supply Input, +1.8V to 5.5V.
5 GND Ground reference point for all circuitry on the part.
6 VOUT Analog output voltage from DAC. The output amplifier has rail-to-rail operation.
Copyright ©2008–2011, Texas Instruments Incorporated 5
SCLK 1
16
SYNC
DIN DB15 DB0 DB15
t10
t6
t3
t2
t1
t7
t9
t5
t4
t8
DAC8311
DAC8411
SBAS439A –AUGUST 2008–REVISED AUGUST 2011
www.ti.com
SERIAL WRITE OPERATION: 14-Bit (DAC8311)
TIMING REQUIREMENTS(1) (2)
All specifications at –40°C to +125°C, and AVDD = +1.8V to +5.5V, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
AVDD = 1.8V to 3.6V 50
t1(3) SCLK cycle time ns
AVDD = 3.6V to 5.5V 20
AVDD = 1.8V to 3.6V 25
t2SCLK high time ns
AVDD = 3.6V to 5.5V 10
AVDD = 1.8V to 3.6V 25
t3SCLK low time ns
AVDD = 3.6V to 5.5V 10
AVDD = 1.8V to 3.6V 0
t4SYNC to SCLK rising edge setup time ns
AVDD = 3.6V to 5.5V 0
AVDD = 1.8V to 3.6V 5
t5Data setup time ns
AVDD = 3.6V to 5.5V 5
AVDD = 1.8V to 3.6V 4.5
t6Data hold time ns
AVDD = 3.6V to 5.5V 4.5
AVDD = 1.8V to 3.6V 0
t7SCLK falling edge to SYNC rising edge ns
AVDD = 3.6V to 5.5V 0
AVDD = 1.8V to 3.6V 50
t8Minimum SYNC high time ns
AVDD = 3.6V to 5.5V 20
AVDD = 1.8V to 3.6V 100
t916th SCLK falling edge to SYNC falling edge ns
AVDD = 3.6V to 5.5V 100
AVDD = 1.8V to 3.6V 15
SYNC rising edge to 16th SCLK falling edge
t10 ns
(for successful SYNC interrupt) AVDD = 3.6V to 5.5V 15
(1) All input signals are specified with tR= tF= 3ns (10% to 90% of AVDD) and timed from a voltage level of (VIL + VIH)/2.
(2) See 14-Bit Serial Write Operation timing diagram.
(3) Maximum SCLK frequency is 50MHz at AVDD = 3.6V to 5.5V and 20MHz at AVDD = 1.8V to 3.6V.
6Copyright ©2008–2011, Texas Instruments Incorporated
SCLK 1
24
SYNC
DIN DB23 DB0 DB23
t10
t6
t3
t2
t1
t7
t9
t5
t4
t8
DAC8311
DAC8411
www.ti.com
SBAS439A –AUGUST 2008–REVISED AUGUST 2011
SERIAL WRITE OPERATION: 16-Bit (DAC8411)
TIMING REQUIREMENTS(1) (2)
All specifications at –40°C to +125°C, and AVDD = +1.8V to +5.5V, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
AVDD = 1.8V to 3.6V 50
t1(3) SCLK cycle time ns
AVDD = 3.6V to 5.5V 20
AVDD = 1.8V to 3.6V 25
t2SCLK high time ns
AVDD = 3.6V to 5.5V 10
AVDD = 1.8V to 3.6V 25
t3SCLK low time ns
AVDD = 3.6V to 5.5V 10
AVDD = 1.8V to 3.6V 0
t4SYNC to SCLK rising edge setup time ns
AVDD = 3.6V to 5.5V 0
AVDD = 1.8V to 3.6V 5
t5Data setup time ns
AVDD = 3.6V to 5.5V 5
AVDD = 1.8V to 3.6V 4.5
t6Data hold time ns
AVDD = 3.6V to 5.5V 4.5
AVDD = 1.8V to 3.6V 0
t7SCLK falling edge to SYNC rising edge ns
AVDD = 3.6V to 5.5V 0
AVDD = 1.8V to 3.6V 50
t8Minimum SYNC high time ns
AVDD = 3.6V to 5.5V 20
AVDD = 1.8V to 3.6V 100
t924th SCLK falling edge to SYNC falling edge ns
AVDD = 3.6V to 5.5V 100
AVDD = 1.8V to 3.6V 15
SYNC rising edge to 24th SCLK falling edge
t10 ns
(for successful SYNC interrupt) AVDD = 3.6V to 5.5V 15
(1) All input signals are specified with tR= tF= 3ns (10% to 90% of AVDD) and timed from a voltage level of (VIL + VIH)/2.
(2) See 16-Bit Serial Write Operation timing diagram.
(3) Maximum SCLK frequency is 50MHz at AVDD = 3.6V to 5.5V and 20MHz at AVDD = 1.8V to 3.6V.
Copyright ©2008–2011, Texas Instruments Incorporated 7
2
1
0
-1
-2
LE(LSB)
0 2048 4096 6144 8192
DigitalInputCode
10240 12288 14336 16384
0.2
0.1
0
-0.1
-0.2
DLE(LSB)
AVDD =5V
6
4
2
0
-2
-4
-6
LE(LSB)
0 8192 16384 24576 32768
DigitalInputCode
40960 49152 57344 65536
1.0
0.5
0
-0.5
-1.0
DLE(LSB)
AVDD =5V
2
1
0
-1
-2
LE(LSB)
0 2048 4096 6144 8192
DigitalInputCode
10240 12288 14336 16384
0.2
0.1
0
-0.1
-0.2
DLE(LSB)
AVDD =5V
6
4
2
0
-2
-4
-6
LE(LSB)
0 8192 16384 24576 32768
DigitalInputCode
40960 49152 57344 65536
1.0
0.5
0
-0.5
-1.0
DLE(LSB)
AVDD =5V
2
1
0
-1
-2
LE(LSB)
0 2048 4096 6144 8192
DigitalInputCode
10240 12288 14336 16384
0.2
0.1
0
-0.1
-0.2
DLE(LSB)
AVDD =5V
6
4
2
0
-2
-4
-6
LE(LSB)
0 8192 16384 24576 32768
DigitalInputCode
40960 49152 57344 65536
1.0
0.5
0
-0.5
-1.0
DLE(LSB)
AVDD =5V
DAC8311
DAC8411
SBAS439A –AUGUST 2008–REVISED AUGUST 2011
www.ti.com
TYPICAL CHARACTERISTICS: AVDD = +5V
At TA= +25°C, AVDD = +5V, and DAC loaded with mid-scale code, unless otherwise noted.
DAC8411 16-BIT LINEARITY ERROR AND DAC8311 14-BIT LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE (–40°C) DIFFERENTIAL LINEARITY ERROR vs CODE (–40°C)
Figure 1. Figure 2.
DAC8411 16-BIT LINEARITY ERROR AND DAC8311 14-BIT LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE (+25°C) DIFFERENTIAL LINEARITY ERROR vs CODE (+25°C)
Figure 3. Figure 4.
DAC8411 16-BIT LINEARITY ERROR AND DAC8311 14-BIT LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE (+125°C) DIFFERENTIAL LINEARITY ERROR vs CODE (+125°C)
Figure 5. Figure 6.
8Copyright ©2008–2011, Texas Instruments Incorporated
0.4
0.3
0.2
0.1
0
125-40 -25 -10 5 20 35 50 65 80 95 110
Zero-CodeError(mV)
Temperature( C)°
AV =5V
DD
5.5
5.0
4.5
4.0
3.5
3.0
2.5
1086420
AnalogOutputVoltage(V)
I (mA)
SOURCE
AV =5V
DD
DACLoadedwithFFFFh
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
125-40 -25 -10 5 20 35 50 65 80 95 110
OffsetError(mV)
Temperature( C)°
AV =5V
DD
0.6
0.4
0.2
0
1086420
AnalogOutputVoltage(V)
I (mA)
SINK
AV =5V
DD
DACLoadedwith0000h
120
100
80
60
655368192 16384 24576 32768 40960 49152 573440
Power-SupplyCurrent( A)m
DigitalInputCode
AV =5.5V
DD
DAC8311
DAC8411
www.ti.com
SBAS439A –AUGUST 2008–REVISED AUGUST 2011
TYPICAL CHARACTERISTICS: AVDD = +5V (continued)
At TA= +25°C, AVDD = +5V, and DAC loaded with mid-scale code, unless otherwise noted.
ZERO-CODE ERROR SOURCE CURRENT
vs TEMPERATURE AT POSITIVE RAIL
Figure 7. Figure 8.
OFFSET ERROR SINK CURRENT
vs TEMPERATURE AT NEGATIVE RAIL
Figure 9. Figure 10.
FULL-SCALE ERROR POWER-SUPPLY CURRENT
vs TEMPERATURE vs DIGITAL INPUT CODE
Figure 11. Figure 12.
Copyright ©2008–2011, Texas Instruments Incorporated 9
140
130
120
110
100
125-40 -25 -10 5 20 35 50 65 80 95 110
Power-SupplyCurrent( A)m
Temperature( C)°
AV =5V
DD
1.6
1.2
0.8
0.4
0
125-40 -25 -10 5 20 35 50 65 80 95 110
QuiescentCurrent( A)m
Temperature( C)°
AVDD =5V
2000
1500
1000
500
0
5.04.03.02.01.00 4.53.52.51.50.5
Power-SupplyCurrent( A)m
V (V)
LOGIC
SYNCInput(allotherdigitalinputs=GND)
Sweepfrom
0Vto5.5V
Sweepfrom
5.5Vto0V
Occurrences
I (mA)
DD
80
84
88
92
96
100
104
108
112
116
120
124
128
132
136
140
50
45
40
35
30
25
20
15
10
5
0
AV =5.5V
DD
-40
-50
-60
-70
-80
-90
-100
543210
THD(dB)
f (kHz)
OUT
AV =5V,f =225kSPS,
DD S
-1dBFSRDigitalInput,
MeasurementBandwidth=20kHz
THD
2ndHarmonic
3rdHarmonic
94
92
90
88
86
84
543210
SNR(dB)
f (kHz)
OUT
AV =5V,
DD
f =225kSPS,
S
-1dBFSRDigitalInput,
MeasurementBandwidth=20kHz
DAC8311
DAC8411
SBAS439A –AUGUST 2008–REVISED AUGUST 2011
www.ti.com
TYPICAL CHARACTERISTICS: AVDD = +5V (continued)
At TA= +25°C, AVDD = +5V, and DAC loaded with mid-scale code, unless otherwise noted.
POWER-SUPPLY CURRENT POWER-DOWN CURRENT
vs TEMPERATURE vs TEMPERATURE
Figure 13. Figure 14.
POWER-SUPPLY CURRENT POWER-SUPPLY CURRENT
vs LOGIC INPUT VOLTAGE HISTOGRAM
Figure 15. Figure 16.
TOTAL HARMONIC DISTORTION SIGNAL-TO-NOISE RATIO
vs OUTPUT FREQUENCY vs OUTPUT FREQUENCY
Figure 17. Figure 18.
10 Copyright ©2008–2011, Texas Instruments Incorporated
Time(500ns/div)
AV =5V
ClockFeedthroughImpulse~0.5nV-s
DD
V (500 V/div)m
OUT
0
20
-40
-60
-80
-100
-120
-140
205 10 150
Gain(dB)
Frequency(kHz)
AV =5V,
DD
fOUT S
=1kHz,f =225kSPS,
MeasurementBandwidth=20kHz
Time(5 s/div)m
V (100 V/div)m
OUT
Clock
Feedthrough
~0.5nV-s
GlitchImpulse
<0.5nV-s
AV =5V
FromCode:7FFFh
ToCode:8000h
DD
Time(5 s/div)m
V (100 V/div)m
OUT
Clock
Feedthrough
~0.5nV-s
GlitchImpulse
<0.5nV-s
AV =5V
FromCode:8000h
ToCode:7FFFh
DD
Time(5 s/div)m
V (100 V/div)m
OUT
Clock
Feedthrough
~0.5nV-s
GlitchImpulse
<0.5nV-s
AV =5V
FromCode:2000h
ToCode:2001h
DD
Time(5 s/div)m
V (100 V/div)m
OUT
Clock
Feedthrough
~0.5nV-s
GlitchImpulse
<0.5nV-s
AV =5V
FromCode:2001h
ToCode:2000h
DD
DAC8311
DAC8411
www.ti.com
SBAS439A –AUGUST 2008–REVISED AUGUST 2011
TYPICAL CHARACTERISTICS: AVDD = +5V (continued)
At TA= +25°C, AVDD = +5V, and DAC loaded with mid-scale code, unless otherwise noted.
CLOCK FEEDTHROUGH
POWER SPECTRAL DENSITY 5V, 2MHz, MIDSCALE
Figure 19. Figure 20.
GLITCH ENERGY GLITCH ENERGY
5V, 16-BIT, 1LSB STEP, RISING EDGE 5V, 16-BIT, 1LSB STEP, FALLING EDGE
Figure 21. Figure 22.
GLITCH ENERGY GLITCH ENERGY
5V, 14-BIT, 1LSB STEP, RISING EDGE 5V, 14-BIT, 1LSB STEP, FALLING EDGE
Figure 23. Figure 24.
Copyright ©2008–2011, Texas Instruments Incorporated 11
Time(2 s/div)m
AV =5V
FromCode:0000h
ToCode:FFFFh
DD
ZoomedRisingEdge
100 V/divm
RisingEdge
1V/div
TriggerPulse5V/div
Time(2 s/div)m
AV =5V
FromCode:FFFFh
ToCode:0000h
DD
TriggerPulse5V/div
FallingEdge
1V/div
ZoomedFallingEdge
100 V/divm
Time(2 s/div)m
AV =5V
FromCode:4000h
ToCode:C000h
DD
ZoomedRisingEdge
100 V/divm
Rising
Edge
1V/div
Trigger
Pulse
5V/div
Time(2 s/div)m
AV =5V
FromCode:C000h
ToCode:4000h
DD
Falling
Edge
1V/div
ZoomedFallingEdge
100 V/divm
Trigger
Pulse
5V/div
AV (2V/div)
DD
V (20mV/div)
OUT
Time(5ms/div)
AV =5V
DAC=ZeroScale
Load=200pF||10kW
DD
17mV
AV (2V/div)
DD
V (20mV/div)
OUT
Time(10ms/div)
AV =5V
DAC=ZeroScale
Load=200pF||10kW
DD
DAC8311
DAC8411
SBAS439A –AUGUST 2008–REVISED AUGUST 2011
www.ti.com
TYPICAL CHARACTERISTICS: AVDD = +5V (continued)
At TA= +25°C, AVDD = +5V, and DAC loaded with mid-scale code, unless otherwise noted.
FULL-SCALE SETTLING TIME FULL-SCALE SETTLING TIME
5V RISING EDGE 5V FALLING EDGE
Figure 25. Figure 26.
HALF-SCALE SETTLING TIME HALF-SCALE SETTLING TIME
5V RISING EDGE 5V FALLING EDGE
Figure 27. Figure 28.
POWER-ON RESET TO 0V
POWER-ON GLITCH POWER-OFF GLITCH
Figure 29. Figure 30.
12 Copyright ©2008–2011, Texas Instruments Incorporated
VNOISE (1 V/div)m
Time(2s/div)
3mVPP
AV =5V,
DD
DAC=Midscale,NoLoad
300
250
200
150
100
50
0
100k10 100 1k 10k
Noise(nV/ )ÖHz
Frequency(Hz)
AV =5V
DD
Midscale
FullScale ZeroScale
120
110
100
90
80
70
5.5002.725 3.650 4.5751.800
Power-SupplyCurrent( A)m
AV (V)
DD
AV =1.8Vto5.5V
DD
0.4
0.3
0.2
0.1
0
5.5002.725 3.650 4.5751.800
QuiescentCurrent( A)m
AV (V)
DD
AV =1.8Vto5.5V
DD
DAC8311
DAC8411
www.ti.com
SBAS439A –AUGUST 2008–REVISED AUGUST 2011
TYPICAL CHARACTERISTICS: AVDD = +5V (continued)
At TA= +25°C, AVDD = +5V, and DAC loaded with mid-scale code, unless otherwise noted.
DAC OUTPUT NOISE DENSITY DAC OUTPUT NOISE
vs FREQUENCY 0.1Hz TO 10Hz BANDWIDTH
Figure 31. Figure 32.
POWER-SUPPLY CURRENT POWER-DOWN CURRENT
vs POWER-SUPPLY VOLTAGE vs POWER-SUPPLY VOLTAGE
Figure 33. Figure 34.
Copyright ©2008–2011, Texas Instruments Incorporated 13
100
90
80
70
60
50
655368192 16384 24576 32768 40960 49152 573440
Power-SupplyCurrent( A)m
DigitalInputCode
AV =3.6V
DD
140
130
120
110
100
90
80
125-40 -25 -10 5 20 35 50 65 80 95 110
Power-SupplyCurrent( A)m
Temperature( C)°
AVDD =3.6V
1200
900
600
300
0
4.03.02.01.00 3.52.51.50.5
Power-SupplyCurrent( A)m
V (V)
LOGIC
SYNCInput(allotherdigitalinputs=GND)
Sweepfrom
0Vto3.6V
Sweepfrom
3.6Vto0V
1.2
0.8
0.4
0
125-40 -25 -10 5 20 35 50 65 80 95 110
QuiescentCurrent( A)m
Temperature( C)°
AVDD =3.6V
3.7
3.5
3.3
3.1
2.9
2.7
2.5
1086420
AnalogOutputVoltage(V)
I (mA)
SOURCE
AV =3.6V
DD
DACLoadedwithFFFFh
0.6
0.4
0.2
0
1086420
AnalogOutputVoltage(V)
I (mA)
SINK
AV =3.6V
DD
DACLoadedwith0000h
DAC8311
DAC8411
SBAS439A –AUGUST 2008–REVISED AUGUST 2011
www.ti.com
TYPICAL CHARACTERISTICS: AVDD = +3.6V
At TA= 25°C, and AVDD = +3.6V, unless otherwise noted.
POWER-SUPPLY CURRENT POWER-SUPPLY CURRENT
vs DIGITAL INPUT CODE vs TEMPERATURE
Figure 35. Figure 36.
POWER-SUPPLY CURRENT POWER-DOWN CURRENT
vs LOGIC INPUT VOLTAGE vs TEMPERATURE
Figure 37. Figure 38.
SOURCE CURRENT SINK CURRENT
AT POSITIVE RAIL AT NEGATIVE RAIL
Figure 39. Figure 40.
14 Copyright ©2008–2011, Texas Instruments Incorporated
Occurrences
I (mA)
DD
70
74
78
82
86
90
94
98
102
106
110
114
118
122
126
130
50
45
40
35
30
25
20
15
10
5
0
AV =3.6V
DD
DAC8311
DAC8411
www.ti.com
SBAS439A –AUGUST 2008–REVISED AUGUST 2011
TYPICAL CHARACTERISTICS: AVDD = +3.6V (continued)
At TA= 25°C, and AVDD = +3.6V, unless otherwise noted.
POWER-SUPPLY CURRENT
HISTOGRAM
Figure 41.
Copyright ©2008–2011, Texas Instruments Incorporated 15
2
1
0
-1
-2
LE(LSB)
0 2048 4096 6144 8192
DigitalInputCode
10240 12288 14336 16384
0.2
0.1
0
-0.1
-0.2
DLE(LSB)
AVDD =2.7V
6
4
2
0
-2
-4
-6
LE(LSB)
0 8192 16384 24576 32768
DigitalInputCode
40960 49152 57344 65536
1.0
0.5
0
-0.5
-1.0
DLE(LSB)
AVDD =2.7V
2
1
0
-1
-2
LE(LSB)
0 2048 4096 6144 8192
DigitalInputCode
10240 12288 14336 16384
0.2
0.1
0
-0.1
-0.2
DLE(LSB)
AVDD =2.7V
6
4
2
0
-2
-4
-6
LE(LSB)
0 8192 16384 24576 32768
DigitalInputCode
40960 49152 57344 65536
1.0
0.5
0
-0.5
-1.0
DLE(LSB)
AVDD =2.7V
2
1
0
-1
-2
LE(LSB)
0 2048 4096 6144 8192
DigitalInputCode
10240 12288 14336 16384
0.2
0.1
0
-0.1
-0.2
DLE(LSB)
AVDD =2.7V
6
4
2
0
-2
-4
-6
LE(LSB)
0 8192 16384 24576 32768
DigitalInputCode
40960 49152 57344 65536
1.0
0.5
0
-0.5
-1.0
DLE(LSB)
AVDD =2.7V
DAC8311
DAC8411
SBAS439A –AUGUST 2008–REVISED AUGUST 2011
www.ti.com
TYPICAL CHARACTERISTICS: AVDD = +2.7V
At TA= 25°C, and AVDD = +2.7V, unless otherwise noted.
DAC8411 16-BIT LINEARITY ERROR AND DAC8311 14-BIT LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE (–40°C) DIFFERENTIAL LINEARITY ERROR vs CODE (–40°C)
Figure 42. Figure 43.
DAC8411 16-BIT LINEARITY ERROR AND DAC8311 14-BIT LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE (+25°C) DIFFERENTIAL LINEARITY ERROR vs CODE (+25°C)
Figure 44. Figure 45.
DAC8411 16-BIT LINEARITY ERROR AND DAC8311 14-BIT LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE (+125°C) DIFFERENTIAL LINEARITY ERROR vs CODE (+125°C)
Figure 46. Figure 47.
16 Copyright ©2008–2011, Texas Instruments Incorporated