Power-On
Reset
DAC
Register 14-/16-BitDAC Output
Buffer
InputControl
Logic
Power-Down
ControlLogic Resistor
Network
SYNC SCLK DIN
AVDD GND
VOUT
REF(+)
DAC8311
DAC8411
www.ti.com
SBAS439A –AUGUST 2008–REVISED AUGUST 2011
1.8V to 5.5V, 80μA, 14- and 16-Bit, Low-Power, Single-Channel,
DIGITAL-TO-ANALOG CONVERTERS in SC70 Package
Check for Samples: DAC8311,DAC8411
1FEATURES DESCRIPTION
The DAC8311 (14-bit) and DAC8411 (16-bit) are
234•Relative Accuracy: low-power, single-channel, voltage output
–1 LSB INL (DAC8311: 14-bit) digital-to-analog converters (DAC). They provide
–4 LSB INL (DAC8411: 16-bit) excellent linearity and minimize undesired
code-to-code transient voltages while offering an
•microPower Operation: 80μA at 1.8V easy upgrade path within a pin-compatible family. All
•Power-Down: 0.5μA at 5V, 0.1μA at 1.8V devices use a versatile, 3-wire serial interface that
•Wide Power Supply: +1.8V to +5.5V operates at clock rates of up to 50MHz and is
compatible with standard SPI™, QSPI™,
•Power-On Reset to Zero Scale MICROWIRE™, and digital signal processor (DSP)
•Straight Binary Data Format interfaces.
•Low Power Serial Interface with All devices use an external power supply as a
Schmitt-Triggered Inputs: Up to 50MHz reference voltage to set the output range. The
•On-Chip Output Buffer Amplifier, Rail-to-Rail devices incorporate a power-on reset (POR) circuit
Operation that ensures the DAC output powers up at 0V and
•SYNC Interrupt Facility remains there until a valid write to the device occurs.
The DAC8311 and DAC8411 contain a power-down
•Extended Temperature Range –40°C to +125°Cfeature, accessed over the serial interface, that
•Pin-Compatible Family in a Tiny, 6-Pin SC70 reduces current consumption of the device to 0.1μA
Package at 1.8V in power down mode. The low power
consumption of this part in normal operation makes it
APPLICATIONS ideally suited for portable, battery-operated
equipment. The power consumption is 0.55mW at 5V,
•Portable, Battery-Powered instruments reducing to 2.5μW in power-down mode.
•Process Control These devices are pin-compatible with the DAC5311,
•Digital Gain and Offset Adjustment DAC6311, and DAC7311, offering an easy upgrade
•Programmable Voltage and Current Sources path from 8-, 10-, and 12-bit resolution to 14- and
16-bit. All devices are available in a small, 6-pin,
SC70 package. This package offers a flexible,
pin-compatible, and functionally-compatible drop-in
RELATED solution within the family over an extended
DEVICES 16-BIT 14-BIT 12-BIT 10-BIT 8-BIT temperature range of –40°C to +125°C.
Pin and
Function DAC8411 DAC8311 DAC7311 DAC6311 DAC5311
Compatible
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2SPI, QSPI are trademarks of Motorola, Inc.
3MICROWIRE is a trademark of National Semiconductor Corporation.
4All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright ©2008–2011, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
DAC8311
DAC8411
SBAS439A –AUGUST 2008–REVISED AUGUST 2011
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGE/ORDERING INFORMATION(1)
MAXIMUM MAXIMUM
RELATIVE DIFFERENTIAL SPECIFIED
ACCURACY NONLINEARITY PACKAGE- PACKAGE TEMPERATURE PACKAGE
PRODUCT (LSB) (LSB) LEAD DESIGNATOR RANGE MARKING
DAC8411 ±8±2 SC70-6 DCK –40°C to 125°C D84
DAC8311 ±4±1 SC70-6 DCK –40°C to 125°C D83
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the
device product folder at www.ti.com.
ABSOLUTE MAXIMUM RATINGS(1)
PARAMETER VALUE UNIT
AVDD to GND –0.3 to +6 V
Digital input voltage to GND –0.3 to +AVDD +0.3 V
AVOUT to GND –0.3 to +AVDD +0.3 V
Operating temperature range –40 to +125 °C
Storage temperature range –65 to +150 °C
Junction temperature (TJmax) +150 °C
Power dissipation (TJmax –TA)/θJA
θJA thermal impedance 250 °C/W
(1) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute
maximum conditions for extended periods may affect device reliability.
2Copyright ©2008–2011, Texas Instruments Incorporated
DAC8311
DAC8411
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SBAS439A –AUGUST 2008–REVISED AUGUST 2011
ELECTRICAL CHARACTERISTICS
At AVDD = +1.8V to +5.5V, RL= 2kΩto GND, and CL= 200 pF to GND, unless otherwise noted.
DAC8411, DAC8311
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
STATIC PERFORMANCE(1)
Resolution 16 Bits
3.6V to 5V ±4±8
Measured by the line passing
Relative accuracy LSB
DAC8411 through codes 485 and 64714 1.8V to 3.6V ±4±12
Differential ±0.5 ±2 LSB
nonlinearity
Resolution 14 Bits
Measured by the line passing through codes 120 and
Relative accuracy ±1±4 LSB
DAC8311 16200
Differential ±0.125 ±1 LSB
nonlinearity
Offset error Measured by the line passing through two codes(2) ±0.05 ±4 mV
Offset error drift 3 μV/°C
Zero code error All zeros loaded to the DAC register 0.2 mV
Full-scale error All ones loaded to DAC register 0.04 0.2 % of FSR
Gain error 0.05 ±0.15 % of FSR
AVDD = +5V ±0.5 ppm of
Gain temperature coefficient FSR/°C
AVDD = +1.8V ±1.5
OUTPUT CHARACTERISTICS(3)
Output voltage range 0 AVDD V
RL= 2kΩ, CL= 200 pF, AVDD = 5V, 1/4 scale to 3/4 scale 6 10 μs
Output voltage settling time RL= 2MΩ, CL= 470pF 12 μs
Slew rate 0.7 V/μs
RL=∞470 pF
Capacitive load stability RL= 2kΩ1000 pF
Code change glitch impulse 1LSB change around major carry 0.5 nV-s
Digital feedthrough 0.5 nV-s
Power-on glitch impulse RL= 2kΩ, CL= 200pF, AVDD = 5V 17 mV
DC output impedance 0.5 Ω
AVDD = +5V 50 mA
Short-circuit current AVDD = +3V 20 mA
Power-up time Coming out of power-down mode 50 μs
AC PERFORMANCE
SNR 88 dB
TA= +25°C, BW = 20kHz, 16-bit level, AVDD = 5V,
THD –66 dB
fOUT = 1kHz, 1st 19 harmonics removed for SNR
SFDR 66 dB
calculation
SINAD 66 dB
TA= +25°C, at zero-scale input, fOUT = 1kHz, AVDD = 5V 17 nV/√Hz
DAC output noise density(4) TA= +25°C, at mid-code input, fOUT = 1kHz, AVDD = 5V 110 nV/√Hz
DAC output noise(5) TA= +25°C, at mid-code input, 0.1Hz to 10Hz, AVDD = 5V 3 μVpp
(1) Linearity calculated using a reduced code range of 485 to 64714 for 16-bit, and 120 to 16200 for 14-bit, output unloaded.
(2) Straight line passing through codes 485 and 64714 for 16-bit, and 120 and 16200 for 14-bit, output unloaded.
(3) Specified by design and characterization, not production tested.
(4) For more details, see Figure 31.
(5) For more details, see Figure 32.
Copyright ©2008–2011, Texas Instruments Incorporated 3
DAC8311
DAC8411
SBAS439A –AUGUST 2008–REVISED AUGUST 2011
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
At AVDD = +1.8V to +5.5V, RL= 2kΩto GND, and CL= 200 pF to GND, unless otherwise noted.
DAC8411, DAC8311
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
LOGIC INPUTS(6)
Input current ±1μA
AVDD = 2.7V to 5.5V 0.3AVDD V
VINL, input low voltage AVDD = 1.8V to 2.7V 0.1AVDD V
AVDD = 2.7V to 5.5V 0.7AVDD V
VINH, input high voltage AVDD = 1.8V to 2.7V 0.9AVDD V
Pin capacitance 1.5 3 pF
POWER REQUIREMENTS
AVDD 1.8 5.5 V
AVDD = 3.6V to 5.5V 110 160
VINH = AVDD and VINL =
Normal mode AVDD = 2.7V to 3.6V 95 150 μA
GND, at mid-scale code(7) AVDD = 1.8V to 2.7V 80 140
IDD AVDD = 3.6V to 5.5V 0.5 3.5
VINH = AVDD and VINL =
All power-down mode AVDD = 2.7V to 3.6V 0.4 3.0 μA
GND, at mid-scale code AVDD = 1.8V to 2.7V 0.1 2.0
AVDD = 3.6V to 5.5V 0.55 0.88
VINH = AVDD and VINL =
Normal mode AVDD = 2.7V to 3.6V 0.25 0.54 mW
GND, at mid-scale code AVDD = 1.8V to 2.7V 0.14 0.38
Power
dissipation AVDD = 3.6V to 5.5V 2.50 19.2
VINH = AVDD and VINL =
All power-down mode AVDD = 2.7V to 3.6V 1.08 10.8 μW
GND, at mid-scale code AVDD = 1.8V to 2.7V 0.72 8.1
TEMPERATURE RANGE
Specified performance –40 +125 °C
(6) Specified by design and characterization, not production tested.
(7) For more details, see Figure 12,Figure 53, and Figure 83.
4Copyright ©2008–2011, Texas Instruments Incorporated
1
2
3
6
5
4
SYNC
SCLK
DIN
VOUT
GND
AV /V
DD REF
DAC8311
DAC8411
www.ti.com
SBAS439A –AUGUST 2008–REVISED AUGUST 2011
PIN CONFIGURATION
DCK PACKAGE
SC70-6
(TOP VIEW)
Table 1. PIN DESCRIPTION
PIN NAME DESCRIPTION
Level-triggered control input (active low). This is the frame sychronization signal for the input data. When
SYNC goes low, it enables the input shift register and data are transferred in on the falling edges of the
following clocks. The DAC is updated following the 24th (DAC8411) or 16th (DAC8311) clock cycle,
1 SYNC unless SYNC is taken high before this edge, in which case the rising edge of SYNC acts as an interrupt
and the write sequence is ignored by the DAC8x11. Refer to the DAC8311 and DAC8411 SYNC Interrupt
sections for more details.
2 SCLK Serial Clock Input. Data can be transferred at rates up to 50MHz.
Serial Data Input. Data is clocked into the 24-bit (DAC8411) or 16-bit (DAC8311) input shift register on
3 DIN the falling edge of the serial clock input.
4 AVDD/VREF Power Supply Input, +1.8V to 5.5V.
5 GND Ground reference point for all circuitry on the part.
6 VOUT Analog output voltage from DAC. The output amplifier has rail-to-rail operation.
Copyright ©2008–2011, Texas Instruments Incorporated 5
SCLK 1
16
SYNC
DIN DB15 DB0 DB15
t10
t6
t3
t2
t1
t7
t9
t5
t4
t8
DAC8311
DAC8411
SBAS439A –AUGUST 2008–REVISED AUGUST 2011
www.ti.com
SERIAL WRITE OPERATION: 14-Bit (DAC8311)
TIMING REQUIREMENTS(1) (2)
All specifications at –40°C to +125°C, and AVDD = +1.8V to +5.5V, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
AVDD = 1.8V to 3.6V 50
t1(3) SCLK cycle time ns
AVDD = 3.6V to 5.5V 20
AVDD = 1.8V to 3.6V 25
t2SCLK high time ns
AVDD = 3.6V to 5.5V 10
AVDD = 1.8V to 3.6V 25
t3SCLK low time ns
AVDD = 3.6V to 5.5V 10
AVDD = 1.8V to 3.6V 0
t4SYNC to SCLK rising edge setup time ns
AVDD = 3.6V to 5.5V 0
AVDD = 1.8V to 3.6V 5
t5Data setup time ns
AVDD = 3.6V to 5.5V 5
AVDD = 1.8V to 3.6V 4.5
t6Data hold time ns
AVDD = 3.6V to 5.5V 4.5
AVDD = 1.8V to 3.6V 0
t7SCLK falling edge to SYNC rising edge ns
AVDD = 3.6V to 5.5V 0
AVDD = 1.8V to 3.6V 50
t8Minimum SYNC high time ns
AVDD = 3.6V to 5.5V 20
AVDD = 1.8V to 3.6V 100
t916th SCLK falling edge to SYNC falling edge ns
AVDD = 3.6V to 5.5V 100
AVDD = 1.8V to 3.6V 15
SYNC rising edge to 16th SCLK falling edge
t10 ns
(for successful SYNC interrupt) AVDD = 3.6V to 5.5V 15
(1) All input signals are specified with tR= tF= 3ns (10% to 90% of AVDD) and timed from a voltage level of (VIL + VIH)/2.
(2) See 14-Bit Serial Write Operation timing diagram.
(3) Maximum SCLK frequency is 50MHz at AVDD = 3.6V to 5.5V and 20MHz at AVDD = 1.8V to 3.6V.
6Copyright ©2008–2011, Texas Instruments Incorporated
SCLK 1
24
SYNC
DIN DB23 DB0 DB23
t10
t6
t3
t2
t1
t7
t9
t5
t4
t8
DAC8311
DAC8411
www.ti.com
SBAS439A –AUGUST 2008–REVISED AUGUST 2011
SERIAL WRITE OPERATION: 16-Bit (DAC8411)
TIMING REQUIREMENTS(1) (2)
All specifications at –40°C to +125°C, and AVDD = +1.8V to +5.5V, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
AVDD = 1.8V to 3.6V 50
t1(3) SCLK cycle time ns
AVDD = 3.6V to 5.5V 20
AVDD = 1.8V to 3.6V 25
t2SCLK high time ns
AVDD = 3.6V to 5.5V 10
AVDD = 1.8V to 3.6V 25
t3SCLK low time ns
AVDD = 3.6V to 5.5V 10
AVDD = 1.8V to 3.6V 0
t4SYNC to SCLK rising edge setup time ns
AVDD = 3.6V to 5.5V 0
AVDD = 1.8V to 3.6V 5
t5Data setup time ns
AVDD = 3.6V to 5.5V 5
AVDD = 1.8V to 3.6V 4.5
t6Data hold time ns
AVDD = 3.6V to 5.5V 4.5
AVDD = 1.8V to 3.6V 0
t7SCLK falling edge to SYNC rising edge ns
AVDD = 3.6V to 5.5V 0
AVDD = 1.8V to 3.6V 50
t8Minimum SYNC high time ns
AVDD = 3.6V to 5.5V 20
AVDD = 1.8V to 3.6V 100
t924th SCLK falling edge to SYNC falling edge ns
AVDD = 3.6V to 5.5V 100
AVDD = 1.8V to 3.6V 15
SYNC rising edge to 24th SCLK falling edge
t10 ns
(for successful SYNC interrupt) AVDD = 3.6V to 5.5V 15
(1) All input signals are specified with tR= tF= 3ns (10% to 90% of AVDD) and timed from a voltage level of (VIL + VIH)/2.
(2) See 16-Bit Serial Write Operation timing diagram.
(3) Maximum SCLK frequency is 50MHz at AVDD = 3.6V to 5.5V and 20MHz at AVDD = 1.8V to 3.6V.
Copyright ©2008–2011, Texas Instruments Incorporated 7
2
1
0
-1
-2
LE(LSB)
0 2048 4096 6144 8192
DigitalInputCode
10240 12288 14336 16384
0.2
0.1
0
-0.1
-0.2
DLE(LSB)
AVDD =5V
6
4
2
0
-2
-4
-6
LE(LSB)
0 8192 16384 24576 32768
DigitalInputCode
40960 49152 57344 65536
1.0
0.5
0
-0.5
-1.0
DLE(LSB)
AVDD =5V
2
1
0
-1
-2
LE(LSB)
0 2048 4096 6144 8192
DigitalInputCode
10240 12288 14336 16384
0.2
0.1
0
-0.1
-0.2
DLE(LSB)
AVDD =5V
6
4
2
0
-2
-4
-6
LE(LSB)
0 8192 16384 24576 32768
DigitalInputCode
40960 49152 57344 65536
1.0
0.5
0
-0.5
-1.0
DLE(LSB)
AVDD =5V
2
1
0
-1
-2
LE(LSB)
0 2048 4096 6144 8192
DigitalInputCode
10240 12288 14336 16384
0.2
0.1
0
-0.1
-0.2
DLE(LSB)
AVDD =5V
6
4
2
0
-2
-4
-6
LE(LSB)
0 8192 16384 24576 32768
DigitalInputCode
40960 49152 57344 65536
1.0
0.5
0
-0.5
-1.0
DLE(LSB)
AVDD =5V
DAC8311
DAC8411
SBAS439A –AUGUST 2008–REVISED AUGUST 2011
www.ti.com
TYPICAL CHARACTERISTICS: AVDD = +5V
At TA= +25°C, AVDD = +5V, and DAC loaded with mid-scale code, unless otherwise noted.
DAC8411 16-BIT LINEARITY ERROR AND DAC8311 14-BIT LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE (–40°C) DIFFERENTIAL LINEARITY ERROR vs CODE (–40°C)
Figure 1. Figure 2.
DAC8411 16-BIT LINEARITY ERROR AND DAC8311 14-BIT LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE (+25°C) DIFFERENTIAL LINEARITY ERROR vs CODE (+25°C)
Figure 3. Figure 4.
DAC8411 16-BIT LINEARITY ERROR AND DAC8311 14-BIT LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE (+125°C) DIFFERENTIAL LINEARITY ERROR vs CODE (+125°C)
Figure 5. Figure 6.
8Copyright ©2008–2011, Texas Instruments Incorporated
0.4
0.3
0.2
0.1
0
125-40 -25 -10 5 20 35 50 65 80 95 110
Zero-CodeError(mV)
Temperature( C)°
AV =5V
DD
5.5
5.0
4.5
4.0
3.5
3.0
2.5
1086420
AnalogOutputVoltage(V)
I (mA)
SOURCE
AV =5V
DD
DACLoadedwithFFFFh
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
125-40 -25 -10 5 20 35 50 65 80 95 110
OffsetError(mV)
Temperature( C)°
AV =5V
DD
0.6
0.4
0.2
0
1086420
AnalogOutputVoltage(V)
I (mA)
SINK
AV =5V
DD
DACLoadedwith0000h
120
100
80
60
655368192 16384 24576 32768 40960 49152 573440
Power-SupplyCurrent( A)m
DigitalInputCode
AV =5.5V
DD
DAC8311
DAC8411
www.ti.com
SBAS439A –AUGUST 2008–REVISED AUGUST 2011
TYPICAL CHARACTERISTICS: AVDD = +5V (continued)
At TA= +25°C, AVDD = +5V, and DAC loaded with mid-scale code, unless otherwise noted.
ZERO-CODE ERROR SOURCE CURRENT
vs TEMPERATURE AT POSITIVE RAIL
Figure 7. Figure 8.
OFFSET ERROR SINK CURRENT
vs TEMPERATURE AT NEGATIVE RAIL
Figure 9. Figure 10.
FULL-SCALE ERROR POWER-SUPPLY CURRENT
vs TEMPERATURE vs DIGITAL INPUT CODE
Figure 11. Figure 12.
Copyright ©2008–2011, Texas Instruments Incorporated 9
140
130
120
110
100
125-40 -25 -10 5 20 35 50 65 80 95 110
Power-SupplyCurrent( A)m
Temperature( C)°
AV =5V
DD
1.6
1.2
0.8
0.4
0
125-40 -25 -10 5 20 35 50 65 80 95 110
QuiescentCurrent( A)m
Temperature( C)°
AVDD =5V
2000
1500
1000
500
0
5.04.03.02.01.00 4.53.52.51.50.5
Power-SupplyCurrent( A)m
V (V)
LOGIC
SYNCInput(allotherdigitalinputs=GND)
Sweepfrom
0Vto5.5V
Sweepfrom
5.5Vto0V
Occurrences
I (mA)
DD
80
84
88
92
96
100
104
108
112
116
120
124
128
132
136
140
50
45
40
35
30
25
20
15
10
5
0
AV =5.5V
DD
-40
-50
-60
-70
-80
-90
-100
543210
THD(dB)
f (kHz)
OUT
AV =5V,f =225kSPS,
DD S
-1dBFSRDigitalInput,
MeasurementBandwidth=20kHz
THD
2ndHarmonic
3rdHarmonic
94
92
90
88
86
84
543210
SNR(dB)
f (kHz)
OUT
AV =5V,
DD
f =225kSPS,
S
-1dBFSRDigitalInput,
MeasurementBandwidth=20kHz
DAC8311
DAC8411
SBAS439A –AUGUST 2008–REVISED AUGUST 2011
www.ti.com
TYPICAL CHARACTERISTICS: AVDD = +5V (continued)
At TA= +25°C, AVDD = +5V, and DAC loaded with mid-scale code, unless otherwise noted.
POWER-SUPPLY CURRENT POWER-DOWN CURRENT
vs TEMPERATURE vs TEMPERATURE
Figure 13. Figure 14.
POWER-SUPPLY CURRENT POWER-SUPPLY CURRENT
vs LOGIC INPUT VOLTAGE HISTOGRAM
Figure 15. Figure 16.
TOTAL HARMONIC DISTORTION SIGNAL-TO-NOISE RATIO
vs OUTPUT FREQUENCY vs OUTPUT FREQUENCY
Figure 17. Figure 18.
10 Copyright ©2008–2011, Texas Instruments Incorporated
Time(500ns/div)
AV =5V
ClockFeedthroughImpulse~0.5nV-s
DD
V (500 V/div)m
OUT
0
20
-40
-60
-80
-100
-120
-140
205 10 150
Gain(dB)
Frequency(kHz)
AV =5V,
DD
fOUT S
=1kHz,f =225kSPS,
MeasurementBandwidth=20kHz
Time(5 s/div)m
V (100 V/div)m
OUT
Clock
Feedthrough
~0.5nV-s
GlitchImpulse
<0.5nV-s
AV =5V
FromCode:7FFFh
ToCode:8000h
DD
Time(5 s/div)m
V (100 V/div)m
OUT
Clock
Feedthrough
~0.5nV-s
GlitchImpulse
<0.5nV-s
AV =5V
FromCode:8000h
ToCode:7FFFh
DD
Time(5 s/div)m
V (100 V/div)m
OUT
Clock
Feedthrough
~0.5nV-s
GlitchImpulse
<0.5nV-s
AV =5V
FromCode:2000h
ToCode:2001h
DD
Time(5 s/div)m
V (100 V/div)m
OUT
Clock
Feedthrough
~0.5nV-s
GlitchImpulse
<0.5nV-s
AV =5V
FromCode:2001h
ToCode:2000h
DD
DAC8311
DAC8411
www.ti.com
SBAS439A –AUGUST 2008–REVISED AUGUST 2011
TYPICAL CHARACTERISTICS: AVDD = +5V (continued)
At TA= +25°C, AVDD = +5V, and DAC loaded with mid-scale code, unless otherwise noted.
CLOCK FEEDTHROUGH
POWER SPECTRAL DENSITY 5V, 2MHz, MIDSCALE
Figure 19. Figure 20.
GLITCH ENERGY GLITCH ENERGY
5V, 16-BIT, 1LSB STEP, RISING EDGE 5V, 16-BIT, 1LSB STEP, FALLING EDGE
Figure 21. Figure 22.
GLITCH ENERGY GLITCH ENERGY
5V, 14-BIT, 1LSB STEP, RISING EDGE 5V, 14-BIT, 1LSB STEP, FALLING EDGE
Figure 23. Figure 24.
Copyright ©2008–2011, Texas Instruments Incorporated 11
Time(2 s/div)m
AV =5V
FromCode:0000h
ToCode:FFFFh
DD
ZoomedRisingEdge
100 V/divm
RisingEdge
1V/div
TriggerPulse5V/div
Time(2 s/div)m
AV =5V
FromCode:FFFFh
ToCode:0000h
DD
TriggerPulse5V/div
FallingEdge
1V/div
ZoomedFallingEdge
100 V/divm
Time(2 s/div)m
AV =5V
FromCode:4000h
ToCode:C000h
DD
ZoomedRisingEdge
100 V/divm
Rising
Edge
1V/div
Trigger
Pulse
5V/div
Time(2 s/div)m
AV =5V
FromCode:C000h
ToCode:4000h
DD
Falling
Edge
1V/div
ZoomedFallingEdge
100 V/divm
Trigger
Pulse
5V/div
AV (2V/div)
DD
V (20mV/div)
OUT
Time(5ms/div)
AV =5V
DAC=ZeroScale
Load=200pF||10kW
DD
17mV
AV (2V/div)
DD
V (20mV/div)
OUT
Time(10ms/div)
AV =5V
DAC=ZeroScale
Load=200pF||10kW
DD
DAC8311
DAC8411
SBAS439A –AUGUST 2008–REVISED AUGUST 2011
www.ti.com
TYPICAL CHARACTERISTICS: AVDD = +5V (continued)
At TA= +25°C, AVDD = +5V, and DAC loaded with mid-scale code, unless otherwise noted.
FULL-SCALE SETTLING TIME FULL-SCALE SETTLING TIME
5V RISING EDGE 5V FALLING EDGE
Figure 25. Figure 26.
HALF-SCALE SETTLING TIME HALF-SCALE SETTLING TIME
5V RISING EDGE 5V FALLING EDGE
Figure 27. Figure 28.
POWER-ON RESET TO 0V
POWER-ON GLITCH POWER-OFF GLITCH
Figure 29. Figure 30.
12 Copyright ©2008–2011, Texas Instruments Incorporated
VNOISE (1 V/div)m
Time(2s/div)
3mVPP
AV =5V,
DD
DAC=Midscale,NoLoad
300
250
200
150
100
50
0
100k10 100 1k 10k
Noise(nV/ )ÖHz
Frequency(Hz)
AV =5V
DD
Midscale
FullScale ZeroScale
120
110
100
90
80
70
5.5002.725 3.650 4.5751.800
Power-SupplyCurrent( A)m
AV (V)
DD
AV =1.8Vto5.5V
DD
0.4
0.3
0.2
0.1
0
5.5002.725 3.650 4.5751.800
QuiescentCurrent( A)m
AV (V)
DD
AV =1.8Vto5.5V
DD
DAC8311
DAC8411
www.ti.com
SBAS439A –AUGUST 2008–REVISED AUGUST 2011
TYPICAL CHARACTERISTICS: AVDD = +5V (continued)
At TA= +25°C, AVDD = +5V, and DAC loaded with mid-scale code, unless otherwise noted.
DAC OUTPUT NOISE DENSITY DAC OUTPUT NOISE
vs FREQUENCY 0.1Hz TO 10Hz BANDWIDTH
Figure 31. Figure 32.
POWER-SUPPLY CURRENT POWER-DOWN CURRENT
vs POWER-SUPPLY VOLTAGE vs POWER-SUPPLY VOLTAGE
Figure 33. Figure 34.
Copyright ©2008–2011, Texas Instruments Incorporated 13
100
90
80
70
60
50
655368192 16384 24576 32768 40960 49152 573440
Power-SupplyCurrent( A)m
DigitalInputCode
AV =3.6V
DD
140
130
120
110
100
90
80
125-40 -25 -10 5 20 35 50 65 80 95 110
Power-SupplyCurrent( A)m
Temperature( C)°
AVDD =3.6V
1200
900
600
300
0
4.03.02.01.00 3.52.51.50.5
Power-SupplyCurrent( A)m
V (V)
LOGIC
SYNCInput(allotherdigitalinputs=GND)
Sweepfrom
0Vto3.6V
Sweepfrom
3.6Vto0V
1.2
0.8
0.4
0
125-40 -25 -10 5 20 35 50 65 80 95 110
QuiescentCurrent( A)m
Temperature( C)°
AVDD =3.6V
3.7
3.5
3.3
3.1
2.9
2.7
2.5
1086420
AnalogOutputVoltage(V)
I (mA)
SOURCE
AV =3.6V
DD
DACLoadedwithFFFFh
0.6
0.4
0.2
0
1086420
AnalogOutputVoltage(V)
I (mA)
SINK
AV =3.6V
DD
DACLoadedwith0000h
DAC8311
DAC8411
SBAS439A –AUGUST 2008–REVISED AUGUST 2011
www.ti.com
TYPICAL CHARACTERISTICS: AVDD = +3.6V
At TA= 25°C, and AVDD = +3.6V, unless otherwise noted.
POWER-SUPPLY CURRENT POWER-SUPPLY CURRENT
vs DIGITAL INPUT CODE vs TEMPERATURE
Figure 35. Figure 36.
POWER-SUPPLY CURRENT POWER-DOWN CURRENT
vs LOGIC INPUT VOLTAGE vs TEMPERATURE
Figure 37. Figure 38.
SOURCE CURRENT SINK CURRENT
AT POSITIVE RAIL AT NEGATIVE RAIL
Figure 39. Figure 40.
14 Copyright ©2008–2011, Texas Instruments Incorporated
Occurrences
I (mA)
DD
70
74
78
82
86
90
94
98
102
106
110
114
118
122
126
130
50
45
40
35
30
25
20
15
10
5
0
AV =3.6V
DD
DAC8311
DAC8411
www.ti.com
SBAS439A –AUGUST 2008–REVISED AUGUST 2011
TYPICAL CHARACTERISTICS: AVDD = +3.6V (continued)
At TA= 25°C, and AVDD = +3.6V, unless otherwise noted.
POWER-SUPPLY CURRENT
HISTOGRAM
Figure 41.
Copyright ©2008–2011, Texas Instruments Incorporated 15
2
1
0
-1
-2
LE(LSB)
0 2048 4096 6144 8192
DigitalInputCode
10240 12288 14336 16384
0.2
0.1
0
-0.1
-0.2
DLE(LSB)
AVDD =2.7V
6
4
2
0
-2
-4
-6
LE(LSB)
0 8192 16384 24576 32768
DigitalInputCode
40960 49152 57344 65536
1.0
0.5
0
-0.5
-1.0
DLE(LSB)
AVDD =2.7V
2
1
0
-1
-2
LE(LSB)
0 2048 4096 6144 8192
DigitalInputCode
10240 12288 14336 16384
0.2
0.1
0
-0.1
-0.2
DLE(LSB)
AVDD =2.7V
6
4
2
0
-2
-4
-6
LE(LSB)
0 8192 16384 24576 32768
DigitalInputCode
40960 49152 57344 65536
1.0
0.5
0
-0.5
-1.0
DLE(LSB)
AVDD =2.7V
2
1
0
-1
-2
LE(LSB)
0 2048 4096 6144 8192
DigitalInputCode
10240 12288 14336 16384
0.2
0.1
0
-0.1
-0.2
DLE(LSB)
AVDD =2.7V
6
4
2
0
-2
-4
-6
LE(LSB)
0 8192 16384 24576 32768
DigitalInputCode
40960 49152 57344 65536
1.0
0.5
0
-0.5
-1.0
DLE(LSB)
AVDD =2.7V
DAC8311
DAC8411
SBAS439A –AUGUST 2008–REVISED AUGUST 2011
www.ti.com
TYPICAL CHARACTERISTICS: AVDD = +2.7V
At TA= 25°C, and AVDD = +2.7V, unless otherwise noted.
DAC8411 16-BIT LINEARITY ERROR AND DAC8311 14-BIT LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE (–40°C) DIFFERENTIAL LINEARITY ERROR vs CODE (–40°C)
Figure 42. Figure 43.
DAC8411 16-BIT LINEARITY ERROR AND DAC8311 14-BIT LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE (+25°C) DIFFERENTIAL LINEARITY ERROR vs CODE (+25°C)
Figure 44. Figure 45.
DAC8411 16-BIT LINEARITY ERROR AND DAC8311 14-BIT LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE (+125°C) DIFFERENTIAL LINEARITY ERROR vs CODE (+125°C)
Figure 46. Figure 47.
16 Copyright ©2008–2011, Texas Instruments Incorporated
0.4
0.3
0.2
0.1
0
125-40 -25 -10 5 20 35 50 65 80 95 110
Zero-CodeError(mV)
Temperature( C)°
AV =2.7V
DD
2.8
2.6
2.4
2.2
2.0
1086420
AnalogOutputVoltage(V)
I (mA)
SOURCE
AV =2.7V
DD
DACLoadedwithFFFFh
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
125-40 -25 -10 5 20 35 50 65 80 95 110
OffsetError(mV)
Temperature( C)°
AV =2.7V
DD
0.6
0.4
0.2
0
1086420
AnalogOutputVoltage(V)
I (mA)
SINK
AV =2.7V
DD
DACLoadedwith0000h
100
90
80
70
60
50
655368192 16384 24576 32768 40960 49152 573440
Power-SupplyCurrent( A)m
DigitalInputCode
AV =2.7V
DD
DAC8311
DAC8411
www.ti.com
SBAS439A –AUGUST 2008–REVISED AUGUST 2011
TYPICAL CHARACTERISTICS: AVDD = +2.7V (continued)
At TA= 25°C, and AVDD = +2.7V, unless otherwise noted.
ZERO-CODE ERROR SOURCE CURRENT
vs TEMPERATURE AT POSITIVE RAIL
Figure 48. Figure 49.
OFFSET ERROR SINK CURRENT
vs TEMPERATURE AT NEGATIVE RAIL
Figure 50. Figure 51.
FULL-SCALE ERROR POWER-SUPPLY CURRENT
vs TEMPERATURE vs DIGITAL INPUT CODE
Figure 52. Figure 53.
Copyright ©2008–2011, Texas Instruments Incorporated 17
120
110
100
90
80
70
125-40 -25 -10 5 20 35 50 65 80 95 110
Power-SupplyCurrent( A)m
Temperature( C)°
AVDD =2.7V
1.0
0.8
0.6
0.4
0.2
0
125-40 -25 -10 5 20 35 50 65 80 95 110
QuiescentCurrent( A)m
Temperature( C)°
AVDD =2.7V
800
600
400
200
0
3.02.01.00.5 1.5 2.50
Power-SupplyCurrent( A)m
V (V)
LOGIC
SYNCInput(allotherdigitalinputs=GND)
Sweepfrom
0Vto2.7V
Sweepfrom
2.7Vto0V
Occurrences
I (mA)
DD
60
64
68
72
76
80
84
88
92
96
100
104
50
45
40
35
30
25
20
15
10
5
0
AV =2.7V
DD
-20
-40
-60
-80
-100
543210
THD(dB)
f (kHz)
OUT
AV =2.7V,f =225kSPS,
DD S
-1dBFSRDigitalInput,
MeasurementBandwidth=20kHz THD
2ndHarmonic
3rdHarmonic
88
86
84
82
80
543210
SNR(dB)
f (kHz)
OUT
AV =2.7V,f =225kSPS,
DD S
-1dBFSRDigitalInput,
MeasurementBandwidth=20kHz
DAC8311
DAC8411
SBAS439A –AUGUST 2008–REVISED AUGUST 2011
www.ti.com
TYPICAL CHARACTERISTICS: AVDD = +2.7V (continued)
At TA= 25°C, and AVDD = +2.7V, unless otherwise noted.
POWER-SUPPLY CURRENT POWER-DOWN CURRENT
vs TEMPERATURE vs TEMPERATURE
Figure 54. Figure 55.
POWER-SUPPLY CURRENT POWER-SUPPLY CURRENT
vs LOGIC INPUT VOLTAGE HISTOGRAM
Figure 56. Figure 57.
TOTAL HARMONIC DISTORTION SIGNAL-TO-NOISE RATIO
vs OUTPUT FREQUENCY vs OUTPUT FREQUENCY
Figure 58. Figure 59.
18 Copyright ©2008–2011, Texas Instruments Incorporated
Time(5 s/div)m
AV =2.7V
ClockFeedthroughImpulse~0.4nV-s
DD
V (500 V/div)m
OUT
0
20
-40
-60
-80
-100
-120
-140
205 10 150
Gain(dB)
Frequency(kHz)
AV =2.7V,
DD
fOUT S
=1kHz,f =225kSPS,
MeasurementBandwidth=20kHz
Time(5 s/div)m
V (100 V/div)m
OUT
Clock
Feedthrough
~0.4nV-s
GlitchImpulse
<0.3nV-s
AV =2.7V
FromCode:7FFFh
ToCode:8000h
DD
Time(5 s/div)m
V (100 V/div)m
OUT
Clock
Feedthrough
~0.4nV-s
GlitchImpulse
<0.3nV-s
AV =2.7V
FromCode:8000h
ToCode:7FFFh
DD
Time(5 s/div)m
V (100 V/div)m
OUT
Clock
Feedthrough
~0.4nV-s
GlitchImpulse
<0.3nV-s
AV =2.7V
FromCode:2000h
ToCode:2001h
DD
Time(5 s/div)m
V (100 V/div)m
OUT
Clock
Feedthrough
~0.4nV-s
GlitchImpulse
<0.3nV-s
AV =2.7V
FromCode:2001h
ToCode:2000h
DD
DAC8311
DAC8411
www.ti.com
SBAS439A –AUGUST 2008–REVISED AUGUST 2011
TYPICAL CHARACTERISTICS: AVDD = +2.7V (continued)
At TA= 25°C, and AVDD = +2.7V, unless otherwise noted. CLOCK FEEDTHROUGH
POWER SPECTRAL DENSITY 2.7V, 20MHz, MIDSCALE
Figure 60. Figure 61.
GLITCH ENERGY GLITCH ENERGY
2.7V, 16-BIT, 1LSB STEP, RISING EDGE 2.7V, 16-BIT, 1LSB STEP, FALLING EDGE
Figure 62. Figure 63.
GLITCH ENERGY GLITCH ENERGY
2.7V, 14-BIT, 1LSB STEP, RISING EDGE 2.7V, 14-BIT, 1LSB STEP, FALLING EDGE
Figure 64. Figure 65.
Copyright ©2008–2011, Texas Instruments Incorporated 19
Time(2 s/div)m
AV =2.7V
FromCode:0000h
ToCode:FFFFh
DD
ZoomedRisingEdge
100 V/divm
RisingEdge
1V/div
Trigger
Pulse
2.7V/div
Time(2 s/div)m
AV =2.7V
FromCode:FFFFh
ToCode:0000h
DD
TriggerPulse2.7V/div
FallingEdge
1V/div
ZoomedFallingEdge
100 V/divm
Time(2 s/div)m
AV =2.7V
FromCode:4000h
ToCode:C000h
DD
ZoomedRisingEdge
100 V/divm
Rising
Edge
1V/div
Trigger
Pulse
2.7V/div
Time(2 s/div)m
AV =2.7V
FromCode:C000h
ToCode:4000h
DD
Falling
Edge
1V/div
ZoomedFallingEdge
100 V/divm
Trigger
Pulse
2.7V/div
AV (1V/div)
DD
V (20mV/div)
OUT
Time(5ms/div)
AV =2.7V
DAC=ZeroScale
Load=200pF||10kW
DD
17mV
AV (1V/div)
DD
V (20mV/div)
OUT
Time(10ms/div)
AV =2.7V
DAC=ZeroScale
Load=200pF||10kW
DD
DAC8311
DAC8411
SBAS439A –AUGUST 2008–REVISED AUGUST 2011
www.ti.com
TYPICAL CHARACTERISTICS: AVDD = +2.7V (continued)
At TA= 25°C, and AVDD = +2.7V, unless otherwise noted.
FULL-SCALE SETTLING TIME FULL-SCALE SETTLING TIME
2.7V RISING EDGE 2.7V FALLING EDGE
Figure 66. Figure 67.
HALF-SCALE SETTLING TIME HALF-SCALE SETTLING TIME
2.7V RISING EDGE 2.7V FALLING EDGE
Figure 68. Figure 69.
POWER-ON RESET TO 0V
POWER-ON GLITCH POWER-OFF GLITCH
Figure 70. Figure 71.
20 Copyright ©2008–2011, Texas Instruments Incorporated
2
1
0
-1
-2
LE(LSB)
0 2048 4096 6144 8192
DigitalInputCode
10240 12288 14336 16384
0.2
0.1
0
-0.1
-0.2
DLE(LSB)
AVDD =1.8V
6
4
2
0
-2
-4
-6
LE(LSB)
0 8192 16384 24576 32768
DigitalInputCode
40960 49152 57344 65536
1.0
0.5
0
-0.5
-1.0
DLE(LSB)
AVDD =1.8V
2
1
0
-1
-2
LE(LSB)
0 2048 4096 6144 8192
DigitalInputCode
10240 12288 14336 16384
0.2
0.1
0
-0.1
-0.2
DLE(LSB)
AVDD =1.8V
6
4
2
0
-2
-4
-6
LE(LSB)
0 8192 16384 24576 32768
DigitalInputCode
40960 49152 57344 65536
1.0
0.5
0
-0.5
-1.0
DLE(LSB)
AVDD =1.8V
2
1
0
-1
-2
LE(LSB)
0 2048 4096 6144 8192
DigitalInputCode
10240 12288 14336 16384
0.2
0.1
0
-0.1
-0.2
DLE(LSB)
AVDD =1.8V
6
4
2
0
-2
-4
-6
LE(LSB)
0 8192 16384 24576 32768
DigitalInputCode
40960 49152 57344 65536
1.0
0.5
0
-0.5
-1.0
DLE(LSB)
AVDD =1.8V
DAC8311
DAC8411
www.ti.com
SBAS439A –AUGUST 2008–REVISED AUGUST 2011
TYPICAL CHARACTERISTICS: AVDD = +1.8V
At TA= 25°C, and AVDD = +1.8V, unless otherwise noted.
DAC8411 16-BIT LINEARITY ERROR AND DAC8311 14-BIT LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE(–40°C) DIFFERENTIAL LINEARITY ERROR vs CODE (–40°C)
Figure 72. Figure 73.
DAC8411 16-BIT LINEARITY ERROR AND DAC8311 14-BIT LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE (+25°C) DIFFERENTIAL LINEARITY ERROR vs CODE (+25°C)
Figure 74. Figure 75.
DAC8411 16-BIT LINEARITY ERROR AND DAC8311 14-BIT LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE (+125°C) DIFFERENTIAL LINEARITY ERROR vs CODE (+125°C)
Figure 76. Figure 77.
Copyright ©2008–2011, Texas Instruments Incorporated 21
1.2
1.0
0.8
0.6
0.4
0.2
0
125-40 -25 -10 5 20 35 50 65 80 95 110
Zero-CodeError(mV)
Temperature( C)°
AV =1.8V
DD
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
86420
AnalogOutputVoltage(V)
I (mA)
SOURCE
AV =1.8V
DD
DACLoadedwithFFFFh
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
125-40 -25 -10 5 20 35 50 65 80 95 110
OffsetError(mV)
Temperature( C)°
AV =1.8V
DD
0.6
0.4
0.2
0
86420
AnalogOutputVoltage(V)
I (mA)
SINK
AV =1.8V
DD
DACLoadedwith0000h
100
90
80
70
60
50
655368192 16384 24576 32768 40960 49152 573440
Power-SupplyCurrent( A)m
DigitalInputCode
AV =1.8V
DD
DAC8311
DAC8411
SBAS439A –AUGUST 2008–REVISED AUGUST 2011
www.ti.com
TYPICAL CHARACTERISTICS: AVDD = +1.8V (continued)
At TA= 25°C, and AVDD = +1.8V, unless otherwise noted.
ZERO-CODE ERROR SOURCE CURRENT
vsTEMPERATURE AT POSITIVE RAIL
Figure 78. Figure 79.
OFFSET ERROR SINK CURRENT
vs TEMPERATURE AT NEGATIVE RAIL
Figure 80. Figure 81.
FULL-SCALE ERROR POWER-SUPPLY CURRENT
vs TEMPERATURE vs DIGITAL INPUT CODE
Figure 82. Figure 83.
22 Copyright ©2008–2011, Texas Instruments Incorporated
110
100
90
80
70
60
125-40 -25 -10 5 20 35 50 65 80 95 110
Power-SupplyCurrent( A)m
Temperature( C)°
AV =1.8V
DD
0.8
0.6
0.4
0.2
0
125-40 -25 -10 5 20 35 50 65 80 95 110
QuiescentCurrent( A)m
Temperature( C)°
AV =1.8V
DD
200
150
100
50
0
2.01.0 1.50.50
Power-SupplyCurrent( A)m
V (V)
LOGIC
SYNCInput(allotherdigitalinputs=GND)
Sweepfrom
0Vto1.8V
Sweepfrom
1.8Vto0V
Occurrences
I ( A)m
DD
60
64
68
72
76
80
84
88
92
96
100
104
108
112
116
120
50
45
40
35
30
25
20
15
10
5
0
AV =1.8V
DD
-20
-40
-60
-80
-100
-120
543210
THD(dB)
f (kHz)
OUT
AV =1.8V,f =225kSPS,
DD S
-1dBFSRDigitalInput,
MeasurementBandwidth=20kHz
THD
2ndHarmonic
3rdHarmonic
86
84
82
80
78
76
543210
SNR(dB)
f (kHz)
OUT
AVDD =1.8V,fS=225kSPS,
-1dBFSRDigitalInput,
MeasurementBandwidth=20kHz
DAC8311
DAC8411
www.ti.com
SBAS439A –AUGUST 2008–REVISED AUGUST 2011
TYPICAL CHARACTERISTICS: AVDD = +1.8V (continued)
At TA= 25°C, and AVDD = +1.8V, unless otherwise noted.
POWER-SUPPLY CURRENT POWER-DOWN CURRENT
vs TEMPERATURE vs TEMPERATURE
Figure 84. Figure 85.
POWER-SUPPLY CURRENT POWER-SUPPLY CURRENT
vs LOGIC INPUT VOLTAGE HISTOGRAM
Figure 86. Figure 87.
TOTAL HARMONIC DISTORTION SIGNAL-TO-NOISE RATIO
vs OUTPUT FREQUENCY vs OUTPUT FREQUENCY
Figure 88. Figure 89.
Copyright ©2008–2011, Texas Instruments Incorporated 23
Time(5 s/div)m
AV =1.8V
ClockFeedthroughImpulse~0.34nV-s
DD
V (500 V/div)m
OUT
0
20
-40
-60
-80
-100
-120
-140
205 10 150
Gain(dB)
Frequency(kHz)
AV =1.8V,
DD
fOUT S
=1kHz,f =225kSPS,
MeasurementBandwidth=20kHz
Time(5 s/div)m
V (100 V/div)m
OUT
Clock
Feedthrough
~0.3nV-s
GlitchImpulse
<0.2nV-s
AV =1.8V
FromCode:7FFFh
ToCode:8000h
DD
Time(5 s/div)m
V (100 V/div)m
OUT
Clock
Feedthrough
~0.3nV-s
GlitchImpulse
<0.2nV-s
AV =1.8V
FromCode:8000h
ToCode:7FFFh
DD
Time(5 s/div)m
V (100 V/div)m
OUT
Clock
Feedthrough
~0.3nV-s
GlitchImpulse
<0.2nV-s
AV =1.8V
FromCode:2000h
ToCode:2001h
DD
Time(5 s/div)m
V (100 V/div)m
OUT
Clock
Feedthrough
~0.3nV-s
GlitchImpulse
<0.2nV-s
AV =1.8V
FromCode:2001h
ToCode:2000h
DD
DAC8311
DAC8411
SBAS439A –AUGUST 2008–REVISED AUGUST 2011
www.ti.com
TYPICAL CHARACTERISTICS: AVDD = +1.8V (continued)
At TA= 25°C, and AVDD = +1.8V, unless otherwise noted. CLOCK FEEDTHROUGH
POWER SPECTRAL DENSITY 1.8V, 20MHz, MIDSCALE
Figure 90. Figure 91.
GLITCH ENERGY GLITCH ENERGY
1.8V, 16-BIT, 1LSB STEP, RISING EDGE 1.8V, 16-BIT, 1LSB STEP, FALLING EDGE
Figure 92. Figure 93.
GLITCH ENERGY GLITCH ENERGY
1.8V, 14-BIT, 1LSB STEP, RISING EDGE 1.8V, 14-BIT, 1LSB STEP, FALLING EDGE
Figure 94. Figure 95.
24 Copyright ©2008–2011, Texas Instruments Incorporated
Time(2 s/div)m
AV =1.8V
FromCode:0000h
ToCode:FFFFh
DD
ZoomedRisingEdge
100 V/divm
RisingEdge
1V/div
Trigger
Pulse
1.8V/div
Time(2 s/div)m
AV =1.8V
FromCode:FFFFh
ToCode:0000h
DD
TriggerPulse1.8V/div
FallingEdge
1V/div
ZoomedFallingEdge
100 V/divm
Time(2 s/div)m
AV =1.8V
FromCode:4000h
ToCode:C000h
DD
ZoomedRisingEdge
100 V/divm
Rising
Edge
1V/div
TriggerPulse1.8V/div
Time(2 s/div)m
AV =1.8V
FromCode:C000h
ToCode:4000h
DD
Falling
Edge
1V/div ZoomedFallingEdge
100 V/divm
Trigger
Pulse
1.8V/div
AV (1V/div)
DD
V (20mV/div)
OUT
Time(5ms/div)
AV =1.8V
DAC=ZeroScale
Load=200pF||10kW
DD
4mV
AV (1V/div)
DD
V (20mV/div)
OUT
Time(10ms/div)
AV =1.8V
DAC=ZeroScale
Load=200pF||10kW
DD
DAC8311
DAC8411
www.ti.com
SBAS439A –AUGUST 2008–REVISED AUGUST 2011
TYPICAL CHARACTERISTICS: AVDD = +1.8V (continued)
At TA= 25°C, and AVDD = +1.8V, unless otherwise noted.
FULL-SCALE SETTLING TIME FULL-SCALE SETTLING TIME
1.8V RISING EDGE 1.8V FALLING EDGE
Figure 96. Figure 97.
HALF-SCALE SETTLING TIME HALF-SCALE SETTLING TIME
1.8V RISING EDGE 1.8V FALLING EDGE
Figure 98. Figure 99.
POWER-ON RESET TO 0V
POWER-ON GLITCH POWER-OFF GLITCH
Figure 100. Figure 101.
Copyright ©2008–2011, Texas Instruments Incorporated 25
REF(+)
ResistorStringDACRegister
GND
Output
Amplifier
VOUT
AVDD
VOUT +AVDD D
2n
VREF
R
R
R
R
ToOutput
Amplifier
RDIVIDER
V
2
REF
DAC8311
DAC8411
SBAS439A –AUGUST 2008–REVISED AUGUST 2011
www.ti.com
THEORY OF OPERATION
DAC SECTION
The DAC8311 and DAC8411 are fabricated using TI's
proprietary HPA07 process technology. The
architecture consists of a string DAC followed by an
output buffer amplifier. Because there is no reference
input pin, the power supply (AVDD) acts as the
reference. Figure 102 shows a block diagram of the
DAC architecture.
Figure 102. DAC8x11 Architecture
The input coding to the DAC8311 and DAC8411 is
straight binary, so the ideal output voltage is given by:
Where:
n = resolution in bits; either 14 (DAC8311) or 16
(DAC8411).
D = decimal equivalent of the binary code that is Figure 103. Resistor String
loaded to the DAC register; it ranges from 0 to
16,383 for the 14-bit DAC8311, or 0 to 65,535 for
the 16-bit DAC8411. OUTPUT AMPLIFIER
RESISTOR STRING The output buffer amplifier is capable of generating
rail-to-rail voltages on its output which gives an output
The resistor string section is shown in Figure 103. It range of 0V to AVDD. It is capable of driving a load of
is simply a string of resistors, each of value R. The 2kΩin parallel with 1000pF to GND. The source and
code loaded into the DAC register determines at sink capabilities of the output amplifier can be seen in
which node on the string the voltage is tapped off to the Typical Characteristics section for each device.
be fed into the output amplifier by closing one of the The slew rate is 0.7V/μs with a half-scale settling time
switches connecting the string to the amplifier. It is of typically 6μs with the output unloaded.
tested monotonic because it is a string of resistors.
26 Copyright ©2008–2011, Texas Instruments Incorporated
InvalidWriteSequence:
HIGHbefore16thFallingEdgeSYNC
ValidWriteSequence:
OutputUpdateson16thFallingEdge
CLK
SYNC
DIN DB15 DB0 DB15 DB0
DAC8311
DAC8411
www.ti.com
SBAS439A –AUGUST 2008–REVISED AUGUST 2011
SERIAL INTERFACE (for 14-Bit DAC8311) At this point, the SYNC line may be kept low or
brought high. In either case, it must be brought high
The DAC8311 has a 3-wire serial interface (SYNC, for a minimum of 20ns before the next write
SCLK, and DIN) compatible with SPI, QSPI, and sequence so that a falling edge of SYNC can initiate
Microwire interface standards, as well as most DSPs. the next write sequence. As previously mentioned, it
See the 14-bit Serial Write Operation timing diagram must be brought high again before the next write
for an example of a typical write sequence. sequence.
DAC8311 Input Shift Register DAC8311 SYNC Interrupt
The input shift register is 16 bits wide, as shown in In a normal write sequence, the SYNC line is kept
Table 2. The first two bits (PD0 and PD1) are low for at least 16 falling edges of SCLK and the DAC
reserved control bits that set the desired mode of is updated on the 16th falling edge. However,
operation (normal mode or any one of three bringing SYNC high before the 16th falling edge acts
power-down modes) as indicated in Table 4.as an interrupt to the write sequence. The shift
register is reset and the write sequence is seen as
The write sequence begins by bringing the SYNC line invalid. Neither an update of the DAC register
low. Data from the DIN line are clocked into the 16-bit contents or a change in the operating mode occurs,
shift register on each falling edge of SCLK. The serial as shown in Figure 104.
clock frequency can be as high as 50MHz, making
the DAC8311 compatible with high-speed DSPs. On
the 16th falling edge of the serial clock, the last data
bit is clocked in and the programmed function is
executed.
Table 2. DAC8311 Data Input Register
DB15 DB14 DB0
PD1 PD0 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Figure 104. DAC8311 SYNC Interrupt Facility
Copyright ©2008–2011, Texas Instruments Incorporated 27
CLK
SYNC
DIN
ValidWriteSequence:
Output/ModeUpdates onthe18thor24thFallingEdge
18thFallingEdge 18th/24thFallingEdge
DB23
Invalid/InterruptedWriteSequence:
Output/ModeDoesNotUpdate onthe18thFallingEdge
DB6 DB5 DB0 DB23 DB6 DB5 DB0
18 2418 24
DAC8311
DAC8411
SBAS439A –AUGUST 2008–REVISED AUGUST 2011
www.ti.com
SERIAL INTERFACE (for 16-Bit DAC8411) At this point, the SYNC line may be kept low or
brought high. In either case, it must be brought high
for a minimum of 20ns before the next write
The DAC8411 has a 3-wire serial interface (SYNC, sequence so that a falling edge of SYNC can initiate
SCLK, and DIN) compatible with SPI, QSPI, and the next write sequence. As previously mentioned, it
Microwire interface standards, as well as most DSPs. must be brought high again before the next write
See the 16-bit Serial Write Operation timing diagram sequence.
for an example of a typical write sequence. The SYNC line may be brought high after the 18th bit
DAC8411 Input Shift Register is clocked in because the last six bits are don't care.
The input shift register is 24 bits wide, as shown in DAC8411 SYNC Interrupt
Table 3. The first two bits are reserved control bits
(PD0 and PD1) that set the desired mode of In a normal write sequence, the SYNC line is kept
operation (normal mode or any one of three low for 24 falling edges of SCLK and the DAC is
power-down modes) as indicated in Table 4. The last updated on the 18th falling edge, ignoring the last six
six bits are don't care.don't care bits. However, bringing SYNC high before
the 18th falling edge acts as an interrupt to the write
The write sequence begins by bringing the SYNC line sequence. The shift register is reset and the write
low. Data from the DIN line are clocked into the 24-bit sequence is seen as invalid. Neither an update of the
shift register on each falling edge of SCLK. The serial DAC register contents or a change in the operating
clock frequency can be as high as 50MHz, making mode occurs, as shown in Figure 105.
the DAC8411 compatible with high-speed DSPs. On
the 18th falling edge of the serial clock, the last data
bit is clocked in and the programmed function is
executed. The last six bits are don't care.
Table 3. DAC8411 Data Input Register
DB2 DB DB DB DB
3 7 6 5 0
PD1 PD0 D1 D1 D1 D1 D1 D1 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X X X
5 4 3 2 1 0
Figure 105. DAC8411 SYNC Interrupt Facility
28 Copyright ©2008–2011, Texas Instruments Incorporated
Resistor
StringDAC
Amplifier
Power-down
Circuitry
Resistor
Network
VOUT
DAC8311
DAC8411
www.ti.com
SBAS439A –AUGUST 2008–REVISED AUGUST 2011
POWER-ON RESET TO ZERO-SCALE advantage of this architecture is that the output
impedance of the part is known while the part is in
The DAC8x11 contains a power-on reset circuit that power-down mode. There are three different options.
controls the output voltage during power-up. On The output is connected internally to GND either
power-up, the DAC register is filled with zeros and through a 1kΩresistor or a 100kΩresistor, or is left
the output voltage is 0V. The DAC register remains open-circuited (High-Z). See Figure 106 for the output
that way until a valid write sequence is made to the stage.
DAC. This design is useful in applications where it is
important to know the state of the output of the DAC
while it is in the process of powering up.
The occuring power-on glitch impulse is only a few
mV (typically, 17mV; see Figure 29,Figure 70, or
Figure 100).
POWER-DOWN MODES
The DAC8x11 contains four separate modes of
operation. These modes are programmable by setting
two bits (PD1 and PD0) in the control register.
Table 4 shows how the state of the bits corresponds Figure 106. Output Stage During Power-Down
to the mode of operation of the device.
All linear circuitry is shut down when the power-down
Table 4. Modes of Operation for the DAC8x11 mode is activated. However, the contents of the DAC
PD1 PD0 OPERATING MODE register are unaffected when in power-down. The
0 0 Normal Operation time to exit power-down is typically 50μs for AVDD =
Power-Down Modes 5V and AVDD = 3V. See the Typical Characteristics
section for each device for more information.
0 1 Output 1kΩto GND
1 0 Output 100kΩto GND DAC NOISE PERFORMANCE
1 1 High-Z Typical noise performance for the DAC8x11 is shown
When both bits are set to 0, the device works in Figure 31 and Figure 32. Output noise spectral
normally with a standard power consumption of density at the VOUT pin versus frequency is depicted
typically 80μA at 1.8V. However, for the three in Figure 31 for full-scale, midscale, and zero-scale
power-down modes, the typical supply current falls to input codes. The typical noise density for midscale
0.5μA at 5V, 0.4μA at 3V, and 0.1μA at 1.8V. Not code is 110nV/√Hz at 1kHz and at 1MHz.
only does the supply current fall, but the output stage
is also internally switched from the output of the
amplifier to a resistor network of known values. The
Copyright ©2008–2011, Texas Instruments Incorporated 29
VO+ƪAVDD ǒD
2nǓ ǒR1)R2
R1Ǔ*AVDD ǒR2
R1Ǔƫ
VO+ǒ10 D
2nǓ*5V
REF5050
DAC8x11
+5V
110 Am
VOUT =0Vto5V
SYNC
SCLK
DIN
+5.5V
Three-Wire
Serial
Interface
1 Fm
DAC8x11
AVDD
VOUT
R
10kW
2
+5V
±5V
+5.5V
OPA211
10 Fm0.1 Fm
Three-Wire
Serial
Interface
-5.5V
R
10kW
1
DAC8311
DAC8411
SBAS439A –AUGUST 2008–REVISED AUGUST 2011
www.ti.com
APPLICATION INFORMATION
USING THE REF5050 AS A POWER SUPPLY BIPOLAR OPERATION USING THE DAC8x11
FOR THE DAC8x11 The DAC8x11 has been designed for single-supply
As a result of the extremely low supply current operation but a bipolar output range is also possible
required by the DAC8x11, an alternative option is to using the circuit in Figure 108. The circuit shown
use a REF5050 +5V precision voltage reference to gives an output voltage range of ±5V. Rail-to-rail
supply the required voltage to the part, as shown in operation at the amplifier output is achievable using
Figure 107. This option is especially useful if the an OPA211,OPA340,orOPA703 as the output
power supply is too noisy or if the system supply amplifier. For a full list of available operational
voltages are at some value other than 5V. The amplifiers from TI, see TI web site at www.ti.com
REF5050 outputs a steady supply voltage for the The output voltage for any input code can be
DAC8x11. If the REF5050 is used, the current calculated as follows:
needed to supply DAC8x11 is typically 110μA at 5V,
with no load on the output of the DAC. When the
DAC output is loaded, the REF5050 also needs to
supply the current to the load. The total current
required (with a 5kΩload on the DAC output) is: (1)
110μA + (5V/5kΩ) = 1.11mA Where:
The load regulation of the REF5050 is typically n = resolution in bits; either 14 (DAC8311) or 16
0.002%/mA, resulting in an error of 90μV for the (DAC8411).
1.11mA current drawn from it. This value corresponds D = the input code in decimal; either 0 to 16,383
to a 1.1LSB error at 16bit (DAC8411). (DAC8311) or 0 to 65,535 (DAC8411).
With AVDD = 5V, R1= R2= 10kΩ:
(2)
This is an output voltage range of ±5V with 0000h
(16-bit level) corresponding to a –5V output and
FFFFh (16-bit level) corresponding to a +5V output.
Figure 107. REF5050 as Power Supply to
DAC8x11
For other power-supply voltages, alternative
references such as the REF3030 (3V), REF3033
(3.3V), or REF3220 (2.048V) are recommended. For
a full list of available voltage references from TI, see Figure 108. Bipolar Operation with the DAC8x11
TI web site at www.ti.com.
30 Copyright ©2008–2011, Texas Instruments Incorporated
SYNC
SCLK
DIN
Microwire
CS
SK
SO
DAC8x11(1)
NOTE: (1) Additional pins omitted for clarity.
68HC11(1)
PC7
SCK
MOSI
SYNC
SCLK
DIN
DAC8x11(1)
NOTE:(1)Additionalpinsomittedforclarity.
80C51/80L51(1)
P3.3
TXD
RXD
DAC8x11(1)
SYNC
SCLK
DIN
NOTE:(1)Additionalpinsomittedforclarity.
DAC8311
DAC8411
www.ti.com
SBAS439A –AUGUST 2008–REVISED AUGUST 2011
MICROPROCESSOR INTERFACING
DAC8x11 to 8051 Interface
Figure 109 shows a serial interface between the
DAC8x11 and a typical 8051-type microcontroller.
The setup for the interface is as follows: TXD of the
8051 drives SCLK of the DAC8x11, while RXD drives
the serial data line of the part. The SYNC signal is Figure 110. DAC8x11 to Microwire Interface
derived from a bit programmable pin on the port. In
this case, port line P3.3 is used. When data are to be
transmitted to the DAC8x11, P3.3 is taken low. The DAC8x11 to 68HC11 Interface
8051 transmits data only in 8-bit bytes; thus, only
eight falling clock edges occur in the transmit cycle. Figure 111 shows a serial interface between the
To load data to the DAC, P3.3 remains low after the DAC8x11 and the 68HC11 microcontroller. SCK of
first eight bits are transmitted, and a second write the 68HC11 drives the SCLK of the DAC8x11, while
cycle is initiated to transmit the second byte of data. the MOSI output drives the serial data line of the
P3.3 is taken high following the completion of this DAC. The SYNC signal is derived from a port line
cycle. The 8051 outputs the serial data in a format (PC7), similar to what was done for the 8051.
which has the LSB first. The DAC8x11 requires its
data with the MSB as the first bit received. Therefore,
the 8051 transmit routine must take this requirement
into account, and mirror the data as needed.
Figure 111. DAC8x11 to 68HC11 Interface
The 68HC11 should be configured so that its CPOL
bit is a '0' and its CPHA bit is a '1'. This configuration
Figure 109. DAC8x11 to 80C51/80L51 Interfaces causes data appearing on the MOSI output to be
valid on the falling edge of SCK. When data are
DAC8x11 to Microwire Interface being transmitted to the DAC, the SYNC line is taken
low (PC7). Serial data from the 68HC11 are
Figure 110 shows an interface between the DAC8x11 transmitted in 8-bit bytes with only eight falling clock
and any Microwire-compatible device. Serial data are edges occurring in the transmit cycle. Data are
shifted out on the falling edge of the serial clock and transmitted MSB first. In order to load data to the
are clocked into the DAC8x11 on the rising edge of DAC8x11, PC7 is held low after the first eight bits are
the SK signal. transferred, and a second serial write operation is
performed to the DAC; PC7 is taken high at the end
of this procedure.
Copyright ©2008–2011, Texas Instruments Incorporated 31
DAC8311
DAC8411
SBAS439A –AUGUST 2008–REVISED AUGUST 2011
www.ti.com
LAYOUT
A precision analog component requires careful layout, The power applied to AVDD should be well-regulated
adequate bypassing, and clean, well-regulated power and low-noise. Switching power supplies and dc/dc
supplies. converters often have high-frequency glitches or
spikes riding on the output voltage. In addition, digital
The DAC8x11 offers single-supply operation; it will components can create similar high-frequency spikes
often be used in close proximity with digital logic, as the internal logic switches state. This noise can
microcontrollers, microprocessors, and digital signal easily couple into the DAC output voltage through
processors. The more digital logic present in the various paths between the power connections and
design and the higher the switching speed, the more analog output. This condition is particularly true for
difficult it will be to achieve good performance from the DAC8x11, as the power supply is also the
the converter. reference voltage for the DAC.
Because of the single ground pin of the DAC8x11, all As with the GND connection, AVDD should be
return currents, including digital and analog return connected to a +5V power supply plane or trace that
currents, must flow through the GND pin. Ideally, is separate from the connection for digital logic until
GND would be connected directly to an analog they are connected at the power entry point. In
ground plane. This plane would be separate from the addition, the 1μF to 10μF and 0.1μF bypass
ground connection for the digital components until capacitors are strongly recommended. In some
they were connected at the power entry point of the situations, additional bypassing may be required,
system. such as a 100μF electrolytic capacitor or even a Pi
filter made up of inductors and capacitors—all
designed to essentially low-pass filter the +5V supply,
removing the high-frequency noise.
32 Copyright ©2008–2011, Texas Instruments Incorporated
DAC8311
DAC8411
www.ti.com
SBAS439A –AUGUST 2008–REVISED AUGUST 2011
PARAMETER DEFINITIONS
With the increased complexity of many different Full-Scale Error
specifications listed in product data sheets, this
section summarizes selected specifications related to Full-scale error is defined as the deviation of the real
digital-to-analog converters. full-scale output voltage from the ideal output voltage
while the DAC register is loaded with the full-scale
STATIC PERFORMANCE code (0xFFFF). Ideally, the output should be VDD –1
LSB. The full-scale error is expressed in percent of
Static performance parameters are specifications full-scale range (%FSR).
such as differential nonlinearity (DNL) or integral
nonlinearity (INL). These are dc specifications and Offset Error
provide information on the accuracy of the DAC. They
are most important in applications where the signal Offset error is defined as the difference between
changes slowly and accuracy is required. actual output voltage and the ideal output voltage in
the linear region of the transfer function. This
Resolution difference is calculated by using a straight line
defined by two codes (for example, for 16-bit
Generally, the DAC resolution can be expressed in resolution, codes 485 and 64714). Since the offset
different forms. Specifications such as IEC 60748-4 error is defined by a straight line, it can have a
recognize the numerical, analog, and relative negative or positve value. Offset error is measured in
resolution. The numerical resolution is defined as the mV.
number of digits in the chosen numbering system
necessary to express the total number of steps of the Zero-Code Error
transfer characteristic, where a step represents both
a digital input code and the corresponding discrete Zero-code error is defined as the DAC output voltage,
analogue output value. The most commonly-used when all '0's are loaded into the DAC register.
definition of resolution provided in data sheets is the Zero-scale error is a measure of the difference
numerical resolution expressed in bits. between actual output voltage and ideal output
voltage (0V). It is expressed in mV. It is primarily
Least Significant Bit (LSB) caused by offsets in the output amplifier.
The least significant bit (LSB) is defined as the Gain Error
smallest value in a binary coded system. The value of
the LSB can be calculated by dividing the full-scale Gain error is defined as the deviation in the slope of
output voltage by 2n, where nis the resolution of the the real DAC transfer characteristic from the ideal
converter. transfer function. Gain error is expressed as a
percentage of full-scale range (%FSR).
Most Significant Bit (MSB) Full-Scale Error Drift
The most significant bit (MSB) is defined as the
largest value in a binary coded system. The value of Full-scale error drift is defined as the change in
the MSB can be calculated by dividing the full-scale full-scale error with a change in temperature.
output voltage by 2. Its value is one-half of full-scale. Full-scale error drift is expressed in units
of %FSR/°C.
Relative Accuracy or Integral Nonlinearity (INL) Offset Error Drift
Relative accuracy or integral nonlinearity (INL) is
defined as the maximum deviation between the real Offset error drift is defined as the change in offset
transfer function and a straight line passing through error with a change in temperature. Offset error drift
the endpoints of the ideal DAC transfer function. INL is expressed in μV/°C.
is measured in LSBs. Zero-Code Error Drift
Differential Nonlinearity (DNL) Zero-code error drift is defined as the change in
Differential nonlinearity (DNL) is defined as the zero-code error with a change in temperature.
maximum deviation of the real LSB step from the Zero-code error drift is expressed in μV/°C.
ideal 1LSB step. Ideally, any two adjacent digital
codes correspond to output analog voltages that are
exactly one LSB apart. If the DNL is within ±1LSB,
the DAC is said to be monotonic.
Copyright ©2008–2011, Texas Instruments Incorporated 33
SR=max
DV(t)
OUT
Dt
DAC8311
DAC8411
SBAS439A –AUGUST 2008–REVISED AUGUST 2011
www.ti.com
Gain Temperature Coefficient Digital Feedthrough
The gain temperature coefficient is defined as the Digital feedthrough is defined as impulse seen at the
change in gain error with changes in temperature. output of the DAC from the digital inputs of the DAC.
The gain temperature coefficient is expressed in ppm It is measured when the DAC output is not updated. It
of FSR/°C. is specified in nV-s, and measured with a full-scale
code change on the data bus; that is, from all '0's to
Power-Supply Rejection Ratio (PSRR) all '1's and vice versa.
Power-supply rejection ratio (PSRR) is defined as the Channel-to-Channel DC Crosstalk
ratio of change in output voltage to a change in
supply voltage for a full-scale output of the DAC. The Channel-to-channel dc crosstalk is defined as the dc
PSRR of a device indicates how the output of the change in the output level of one DAC channel in
DAC is affected by changes in the supply voltage. response to a change in the output of another DAC
PSRR is measured in decibels (dB). channel. It is measured with a full-scale output
change on one DAC channel while monitoring
Monotonicity another DAC channel remains at midscale. It is
expressed in LSB.
Monotonicity is defined as a slope whose sign does
not change. If a DAC is monotonic, the output Channel-to-Channel AC Crosstalk
changes in the same direction or remains at least
constant for each step increase (or decrease) in the AC crosstalk in a multi-channel DAC is defined as the
input code. amount of ac interference experienced on the output
of a channel at a frequency (f) (and its harmonics),
when the output of an adjacent channel changes its
DYNAMIC PERFORMANCE value at the rate of frequency (f). It is measured with
Dynamic performance parameters are specifications one channel output oscillating with a sine wave of
such as settling time or slew rate, which are important 1kHz frequency, while monitoring the amplitude of
in applications where the signal rapidly changes 1kHz harmonics on an adjacent DAC channel output
and/or high frequency signals are present. (kept at zero scale). It is expressed in dB.
Slew Rate Signal-to-Noise Ratio (SNR)
The output slew rate (SR) of an amplifier or other Signal-to-noise ratio (SNR) is defined as the ratio of
electronic circuit is defined as the maximum rate of the root mean-squared (RMS) value of the output
change of the output voltage for all possible input signal divided by the RMS values of the sum of all
signals. other spectral components below one-half the output
frequency, not including harmonics or dc. SNR is
measured in dB.
(3) Total Harmonic Distortion (THD)
Where ΔVOUT(t) is the output produced by the
amplifier as a function of time t.Total harmonic distortion + noise is defined as the
ratio of the RMS values of the harmonics and noise
Output Voltage Settling Time to the value of the fundamental frequency. It is
expressed in a percentage of the fundamental
Settling time is the total time (including slew time) for frequency amplitude at sampling rate fS.
the DAC output to settle within an error band around
its final value after a change in input. Settling times Spurious-Free Dynamic Range (SFDR)
are specified to within ±0.003% (or whatever value is
specified) of full-scale range (FSR). Spurious-free dynamic range (SFDR) is the usable
dynamic range of a DAC before spurious noise
Code Change/Digital-to-Analog Glitch Energy interferes or distorts the fundamental signal. SFDR is
the measure of the difference in amplitude between
Digital-to-analog glitch impulse is the impulse injected the fundamental and the largest harmonically or
into the analog output when the input code in the non-harmonically related spur from dc to the full
DAC register changes state. It is normally specified Nyquist bandwidth (half the DAC sampling rate, or
as the area of the glitch in nanovolts-second (nV-s), fS/2). A spur is any frequency bin on a spectrum
and is measured when the digital input code is analyzer, or from a Fourier transform, of the analog
changed by 1LSB at the major carry transition. output of the DAC. SFDR is specified in decibels
relative to the carrier (dBc).
34 Copyright ©2008–2011, Texas Instruments Incorporated
DAC8311
DAC8411
www.ti.com
SBAS439A –AUGUST 2008–REVISED AUGUST 2011
Signal-to-Noise plus Distortion (SINAD) DAC Output Noise
SINAD includes all the harmonic and outstanding DAC output noise is defined as any voltage deviation
spurious components in the definition of output noise of DAC output from the desired value (within a
power in addition to quantizing any internal random particular frequency band). It is measured with a DAC
noise power. SINAD is expressed in dB at a specified channel kept at midscale while filtering the output
input frequency and sampling rate, fS. voltage within a band of 0.1Hz to 10Hz and
measuring its amplitude peaks. It is expressed in
DAC Output Noise Density terms of peak-to-peak voltage (Vpp).
Output noise density is defined as Full-Scale Range (FSR)
internally-generated random noise. Random noise is
characterized as a spectral density (nV/√Hz). It is Full-scale range (FSR) is the difference between the
measured by loading the DAC to midscale and maximum and minimum analog output values that the
measuring noise at the output. DAC is specified to provide; typically, the maximum
and minimum values are also specified. For an n-bit
DAC, these values are usually given as the values
matching with code 0 and 2n–1.
Copyright ©2008–2011, Texas Instruments Incorporated 35
DAC8311
DAC8411
SBAS439A –AUGUST 2008–REVISED AUGUST 2011
www.ti.com
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (August, 2008) to Revision A Page
•Changed specifications and test conditions for input low voltage parameter ....................................................................... 4
•Changed specifications and test conditions for input high voltage parameter ..................................................................... 4
36 Copyright ©2008–2011, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com 13-Jul-2011
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
DAC8311IDCKR ACTIVE SC70 DCK 6 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
DAC8311IDCKRG4 ACTIVE SC70 DCK 6 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
DAC8311IDCKT ACTIVE SC70 DCK 6 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
DAC8311IDCKTG4 ACTIVE SC70 DCK 6 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
DAC8411IDCKR ACTIVE SC70 DCK 6 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
DAC8411IDCKRG4 ACTIVE SC70 DCK 6 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
DAC8411IDCKT ACTIVE SC70 DCK 6 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
DAC8411IDCKTG4 ACTIVE SC70 DCK 6 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
PACKAGE OPTION ADDENDUM
www.ti.com 13-Jul-2011
Addendum-Page 2
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
DAC8311IDCKR SC70 DCK 6 3000 177.8 9.7 2.3 2.52 1.2 4.0 8.0 Q3
DAC8311IDCKT SC70 DCK 6 250 177.8 9.7 2.3 2.52 1.2 4.0 8.0 Q3
DAC8411IDCKR SC70 DCK 6 3000 177.8 9.7 2.3 2.52 1.2 4.0 8.0 Q3
DAC8411IDCKT SC70 DCK 6 250 177.8 9.7 2.3 2.52 1.2 4.0 8.0 Q3
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Jul-2011
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
DAC8311IDCKR SC70 DCK 6 3000 184.0 184.0 50.0
DAC8311IDCKT SC70 DCK 6 250 184.0 184.0 50.0
DAC8411IDCKR SC70 DCK 6 3000 184.0 184.0 50.0
DAC8411IDCKT SC70 DCK 6 250 184.0 184.0 50.0
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Jul-2011
Pack Materials-Page 2
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