Products and specifications discussed herein are subject to change by Micron without notice.
32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Features
PDF: 09005aef82832fa2/Source: 09005aef82832f5f Micron Technology, Inc., reserves the right to change products or specifica tions without notice.
32mb_burst_cr1_0_p24z_1.fm - Rev. E 9/08 EN 1©2007 Micron Technology, Inc. All rights reserved.
Async/Page/Burst
CellularRAM®1.0 Memory
MT45W2MW16BGB
Features
• Single device supports asynchronous, page, and
burst operations
• Random access time: 70ns
•V
CC, VCCQ voltages
–1.7–1.95V VCC
–1.7–3.6V VCCQ
• Page mode read access
–16-word page size
–Interpage read access: 70ns
–Intrapage read access: 20ns
• Burst mode write access : continuous burst
• Burst mode read access
–4, 8, or 16 words or continuous burst
–MAX clock rate: 104 MHz (tCLK = 9.62ns)
–Burst initial latency: 38.5ns (4 clocks) at 104 MHz
–tACLK: 7ns at 104 MHz
•Low power consumption
–Asynchronous read: <20mA
–Intrapage read: <15mA
–Intrapage read initial access, burst read:
(38.5ns [4 clocks] at 104 MHz) <40mA
–Continuous burst read: <25mA
–Standby: <110µA
–Deep power-down: <10µA (TYP at 25°C)
• Low-power features
–Temperature-compensated refresh (TCR)
–On-chip temperature sensor
–Partial-array refresh (PAR)
–Deep power-down (DPD) mode
Options Designator
•Configuration
–2 Meg x 16 MT45W2MW16B
•Package
–54-ball VFBGA (“green”) GB
•Access time
–70ns -70
•Frequency
–80 MHz 8
–104 MHz 1
Figure 1: 54-Ball VFBGA Ball Assignment
Notes:1. –30°C exceeds the CellularRAM W o rk group
1.0 specification of –25°C.
2. Contact factory for availability.
Part Number Example:
MT45W2MW16BGB-701WT
Options (continued) Designator
• Standby power
–Standard None
•Low power L
• Operating temperature range
–Wireless (–30°C to +85°C) WT1
–Industrial (–40°C to +85°C) IT2
A
B
C
D
E
F
G
H
J
1 2 3 4 5 6
Top view
(Ball down)
LB#
DQ8
DQ9
V
SS
Q
V
CC
Q
DQ14
DQ15
A18
WAIT
OE#
UB#
DQ10
DQ11
DQ12
DQ13
A19
A8
CLK
A0
A3
A5
A17
NC
A14
A12
A9
ADV#
A2
CE#
DQ1
DQ3
DQ4
DQ5
WE#
A11
NC
A1
A4
A6
A7
A16
A15
A13
A10
NC
CRE
DQ0
DQ2
VCC
VSS
DQ6
DQ7
A20
NC
PDF: 09005aef82832fa2/Source: 09005aef82832f5f Micron Technology, Inc., reserves the right to change products or specifica tions without notice.
32mb_burst_c1_0_p24zTOC.fm - Rev. E 9/08 EN 2©2006 Micron Technology, Inc. All rights reserved.
32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Table of Contents
Table of Contents
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Ball Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Part Numbering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Valid Part Number Combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Device Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Power-Up Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Bus Operating Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Asynchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Page Mode READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Burst Mode Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Mixed-Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
WAIT Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
LB#/UB# Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Low-Power Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Standby Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Temperature-Compensated Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Partial-Array Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Deep Power-Down Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Access Using CRE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Software Access to the Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Bus Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Burst Length (BCR[2:0]) Default = Continuous Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Burst Wrap (BCR[3]) Default = Burst No Wrap (Within Burst Length) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Output Impedance (BCR[5]) Default =Outputs Use Full Drive Strength. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
WAIT Configuration (BCR[8]) Default =WAIT Transitions One Clock Before Data Valid/Invalid . . . . . . . . .28
WAIT Polarity (BCR[10]) Default = WAIT Active HIGH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Latency Counter (BCR[13:11]) Default = Three-Clock Latency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Operating Mode (BCR[15]) Default = Asynchronous Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Refresh Configuration Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Partial-Array Refresh (RCR[2:0]) Default = FullArray Refresh. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Deep Power-Down (RCR[4]) Default = DPD Disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Page Mode Operation (RCR[7]) Default =Disabled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Maximum and Typical Standby Currents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Timing Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Timing Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
PDF: 09005aef82832fa2/Source: 09005aef82832f5f Micron Technology, Inc., reserves the right to change products or specifica tions without notice.
32mb_burst_c1_0_p24zLOF.fm - Rev. E 9/08 EN 3©2007 Micron Technology, Inc. All rights reserved.
32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
List of Figures
List of Figures
Figure 1: 54-Ball VFBGA Ball Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Figure 2: Fun ctional Block D iag ram – 2 Meg x 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3: Part Number Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Figure 4: Power-Up Initialization Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Figure 5: READ Operation (ADV = LOW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Figure 6: WRITE Operation (ADV = LOW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Figure 7: Page Mode READ Operation (ADV = LOW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Figure 8: Burst Mode READ (4-Word Burst) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Figure 9: Burst Mode WRITE (4-Word Burst) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Figure 10: Wired-OR WAIT Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Figure 11: Refresh Collision During READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Figure 12: Refresh Collision During WRITE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Figure 13: Asynchronous Mode Configuration Re gister WRITE Followed by READ ARRAY Operation . . . . . .20
Figure 14: Synchronous Mode Configuration Register WRITE Followed by READ ARRAY Operation . . . . . . .21
Figure 15: Asynchronous Mode Configuration Register READ Followed by READ ARRAY Operation . . . . . . .22
Figure 16: Synchronous Mode Configuration Register READ Followed by READ ARRAY Operation . . . . . . . .23
Figure 17: Load Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Figure 18: Read Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Figure 19: Bus Configuration Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Figure 20: WAIT Configuration (BCR[8] = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Figure 21: WAIT Configuration (BCR[8] = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Figure 22: WAIT Configuration During Burst Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Figure 23: Latency Counter (Variable Latency, No Refresh Collision) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Figure 24: Refresh Configuration Register Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Figure 25: Ty pic al Refres h Curre nt vs. Te mperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Figure 26: AC Input/Output Reference Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Figure 27: Output Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Figure 28: Initialization Period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Figure 29: Asynchrono us READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Figure 30: Asynchrono us READ Using ADV# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Figure 31: Page Mode READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Figure 32: S ingle-Access B u rs t REA D Ope r at ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Figure 33: 4-Word Burst READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Figure 34: READ Burst Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Figure 35: Output Delay in Continuous Burst READ with BCR[8] = 0 for End-of-Row Condition . . . . . . . . . . .46
Figure 36: CE#-Controlled Asynchronous WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Figure 37: LB#/UB#-Controlled Asynchronous WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Figure 38: WE#-Controlled Asynchronous WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Figure 39: Asynchronous WRITE Using ADV# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Figure 40: Burst WRITE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Figure 41: Output Delay in Continuous Burst WRITE with BCR[8] = 0 for End-of-Row Condition . . . . . . . . . .52
Figure 42: Burst WRITE Followed by Burst READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Figure 43: Asynchronous WRITE Followed by Burst READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Figure 44: Asynchronous WRITE Followed by Burst READ with ADV# LOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Figure 45: Burst REA D Fo ll owed by Asynchronous WRITE (WE#-Controlled) . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Figure 46: Burst REA D Fo ll owed by Asynchronous WRITE Using ADV# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Figure 47: Asynchronous WRITE Followed by Asynchronous READ with ADV# LOW . . . . . . . . . . . . . . . . . . . . .58
Figure 48: Asynchronous WRITE Followed by Asynchronous READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Figure 49: 54-Ball VFBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
PDF: 09005aef82832fa2/Source: 09005aef82832f5f Micron Technology, Inc., reserves the right to change products or specifica tions without notice.
32mb_burst_c1_0_p24zLOT.fm - Rev. E 9/08 EN 4©2007 Micron Technology, Inc. All rights reserved.
32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
List of Tables
List of Tables
Table 1: VFBGA Ball Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Table 2: Bus Operations: Asynchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 3: Bus Operations: Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Table 4: Sequence and Burst Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Table 5: Latency Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Table 6: 32Mb Address Patterns for PAR (RCR[4] = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Table 7: Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Table 8: Electrical Characteristics and Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Table 9: Partial-Array Refresh Spec if ic ati o ns and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Table 10: Deep Power-Down Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Table 11: Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Table 12: Asynchronous READ Cycle Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Table 13: Burst READ Cycle Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Table 14: Asynchronous WRITE Cycle Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Table 15: Burst WRITE Cycle Tim ing Req uirem e n ts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Table 16: Initialization Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
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32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
General Description
General Description
Micron® CellularRAM® is a high-speed, CMOS PSRAM memory device developed for
low-power, portable applications. The MT45W2MW16BGB is a 32Mb DRAM core
device organized as 2 M eg x 16 bits. This device incl udes an industry-standard
burst mode Flash interface that dramatically increases READ/WRITE bandwidth
compared with other low-power SRAM or pseudo-SRAM (PSRAM) offerings.
For seamless operation on a burst Flash bus, CellularRAM products incorporate a trans-
parent self refresh mechanism. The hidden refresh requires no additional support from
the system memory controller and has no significant impact on device READ/WRITE
performance.
Two user-accessible control register s define device operation. The bus confi g urat ion
register (BCR) defines how the CellularRAM device interacts with the system memory
bus and is nearly identical to its counterpart on burst mode Flash devices. The refresh
configuration register (RCR) is used to control how refresh is performed on the DRAM
array. These registers are automatically loaded with default settings during power-up
and can be updated anytime during normal operati o n.
Special attention has been focused on standby current consumption during self refresh.
CellularRAM products include three system-acce ssible mechanisms to minimize
standby current. Partial-array refresh (PAR) limits refresh to only that part of the DRAM
array that contains essential data. Temperature-compensated refresh (TCR) uses an on-
chip sensor to adjust the refresh rate to match the device temperature. The refresh rate
decreases at lower temper atures to minimize current consumption during standby.
Deep power-down (DPD) halts the REFRESH operation altogether and is used when no
vital informat ion is stored in the de vic e. Th es e thre e refre sh mec hani s ms a re acc es s ed
through the RCR.
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32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Functional Block Diagram
Functional Block Diagram
Figure 2: Functional Block Diagram – 2 Meg x 16
Note: Functional block diagrams illustrate simplified device operation. See ball description table,
bus operations tables, and timing diagrams for detailed information.
A[20:0]
CE#
WE#
OE#
CLK
ADV#
CRE
WAIT
LB#
UB#
DQ[7:0]
DQ[15:8]
Input/
output
MUX
and
buffers
2,048K x 16
DRAM
memory
array
Refresh configuration
register (RCR)
Bus configuration
register (BCR)
Address decode
logic
Control
logic
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32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Ball Descriptions
Ball Descriptions
Note: The CLK and ADV# inputs can be tied to VSS if the device is always operatin g in asynchro-
nous or page mode. WAIT will be asser t ed, but should be ignored during asyn chronous
and page mode operations.
Table 1: VFBGA Ball Descriptions
VFBGA
Assignment Symbol Type Description
H6, G2, H1, D3,
E4, F4, F3, G4,
G3, H5, H4, H3,
H2, D4, C4, C3,
B4, B3, A5, A4,
A3
A[20:0] Input Address inputs : Inputs for ad dr e ss e s during READ and WRITE operations.
Addresses are internally latched during READ and WRITE cycles. The address lines
are also used to define the value to be loaded into the BCR or the RCR.
J3 ADV# Input Address valid: Indicates that a valid address is present on the address inputs.
Addresses ca n be latched on the rising edge of ADV# during asynchronous READ
and WRITE operat ions. ADV# can be held LOW du ring asynchronous READ and
WRITE operations.
B5 CE# Input Chip enable: Activates the device when LOW. When CE# is HIGH, the device is
disabled and goes into standby or deep power-down mode.
J2 CLK Input Clock: Synchronizes the memory to the system operating frequency during
synchronous o perations. When configured for synchronous operation, the address
is latched on the first rising CLK edge when ADV# is active. CLK must be static
LOW or HIGH during asynchronous access READ and WRITE operations and during
PAGE READ ACCESS operations.
A6 CRE Input Configuration register enable: When CRE is HIGH, WRITE o perations load the R CR
or BCR, and READ operations either access the RCR or the BCR.
A1 LB# Input Lower byte enable: DQ[7:0].
A2 OE# Input Output enable: Enables the output buffers when LOW. When OE# is HIGH, the
output buffers are disabled.
B2 UB# Input Uppe r byte enable: DQ[15:8].
G5 WE# Input WRITE enable: Determines whether a given cycle is a WRITE cycle. If WE# is LOW,
the cycle is a WRITE to either a configuration register or the memory array.
G1, F1, F2, E2,
D2, C2, C1, B1,
G6, F6, F5, E5,
D5, C6, C5, B6
DQ[15:0] Input/
Output Data inputs/outputs.
J1 WAIT Output Wait: Provides data-valid feedback during burst READ and WRITE operations. The
signal is gated by CE#. WAIT is used to arbitrate collisions between REFRESH and
READ/WRITE operations. WAIT is asserted when a burst crosses a row boundary.
WAIT is also used to mask the delay associated with open ing a new internal page.
WAIT is asserted and should be ignored duri ng asyn ch ronous and page mode
operations. WAIT is High-Z when CE# is HIGH.
E3, J4, J5, J6 NC – Not interna lly connected.
D6 VCC Supply Device power supply (1.7–1.95V): Power supply for device core operation.
E1 VCCQ Supply I/O power supply (1.7–3.6V): Power supply for input/output buffers.
E6 VSS Supply VSS must be connected to ground.
D1 VSSQ Supply VSSQ must be connected to ground.
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32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Bus Operations
Bus Operations
Notes: 1. CLK must be static (HIGH or LOW) during asynchronous READ and asynchronous WRITE
modes and to achieve standby power during stan dby and DPD modes. CLK must be static
(HIGH or LOW) during burst suspend.
2. The WAIT polarity is configured through the bus configuration register (BCR[10]).
3. When LB# and UB# are in select mode (LOW), DQ[15:0] are affected. When only LB# is in
select mode, DQ[7:0] are affected . When on ly UB# is in the select mode, DQ[15:8] are
affected.
4. The device will consume active power in this mode whenever addresses are changed.
5. When the device is in standby mode, address inputs and data inputs/outputs are internally
isolated from any external influence.
6. VIN = VCCQ or 0V; all devic e balls must be stati c (unswitched) to achieve standby current.
7. DPD is maintained until RCR is reconfigured.
8. CRE-controlled reading of the configuration register is supported for this device, though it
is not an official CellularRAM 1.0 feature.
Table 2: Bus Operations: Asynchronous Mode
Mode Power CLK1ADV# CE# OE# WE# CRE LB#/
UB# WAIT2DQ[15:0]3Notes
READ Active L L L L H L L Low-Z Data-out 4
WRITE Active L L L X L L L Low-Z Data-in 4
Standby Standby L X H X X L X High-Z High-Z 5, 6
No operation Idle L X L X X L X Low-Z X 4, 6
Configuration
register WRITE Active LLLHLHXLow-ZHigh-Z
Configuration
register READ Active L L L H H H X Low-Z Config. reg.
out 8
DPD Deep
power-down L X H X X X X High-Z High-Z 7
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32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Bus Operations
Notes: 1. CLK must be static (HIGH or LOW) during asynchronous READ and asynchronous WRITE
modes and to achieve standby power during stan dby and DPD modes. CLK must be static
(HIGH or LOW) during burst suspend.
2. The WAIT polarity is configured through the bus configuration register (BCR[10]).
3. When LB# and UB# are in select mode (LOW), DQ[15:0] are affected. When only LB# is in
select mode, DQ[7:0] are affected . When on ly UB# is in the select mode, DQ[15:8] are
affected.
4. The device will consume active power in this mode whenever addresses are changed.
5. When the device is in standby mode, address inputs and data inputs/outputs are internally
isolated from any external influence.
6. VIN = VCCQ or 0V; all devic e balls must be stati c (unswitched) to achieve standby current.
7. DPD is maintained until RCR is reconfigured.
8. Burst mode operation i s initialized through the bus configuration register (BCR[15]).
9. This device supports CRE-controlled configuration register READs. This feature is not an
official CellularRAM 1.0 feature.
Table 3: Bus Operations: Burst Mode
Mode Power CLK1ADV# CE# OE# WE# CRE LB#/
UB# WAIT2DQ[15:0]3Notes
Asynchronous
READ Active L L L L H L L Low-Z Data-out 4
Asynchronous
WRITE Active L L L X L L L Low-Z Data-in 4
Standby Standby L X H X X L X High-Z High-Z 5, 6
No operation Idle L X L X X L X Low-Z X 4, 6
Initial burst
READ Active L L X H L L Low-Z X 4, 8
Initial burst
WRITE Active L L H L L X Low-Z X 4, 8
Burst continue Active H L X X X L Low-Z Data-in or
data-out 4, 8
Burst suspend Active X X L H X L X Low-Z High-Z 4, 8
Configuration
register WRITE Active L L H L H X Low-Z High-Z 8
Configuration
register READ Active L L H H H X Low-Z Config. reg.
out Z 8, 9
DPD Deep
power-down L X H X X X X High-Z High-Z 7
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32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Part Numbering Information
Part Numbering Information
Micron CellularRAM devices ar e available in several configurations and densities.
Figure 3: Part Number Chart
Note: –30°C exceeds the CellularRAM Workgroup 1.0 specification of –25°C.
Valid Part Number Combinations
After building the part number from the part num bering chart, vi sit the Micron We b site
at www.micron.com/psram to verify that the part number is offered and valid. If the
device required is not on this list, contact the factory.
Device Marking
Due to the size of the package, the Micron-standard part number is not printed on the
top of the device. Instead, an abbreviated devi ce mark c ons is ti ng of a five-digit alphanu-
meric code is used. The abbre v iate d device mark s are cros s-referenced to the Micron
part numbers at the FBGA Part Marking Decoder site, http://www.micron.com/
decoder. To view the location of the abbreviated mark on the device, refer to customer
service note, CSN-11, “Product Mark/Label,” at www.micron.com/csn.
MT 45 W 2M W 16 B GB -70 8 WT ES
Micron Technology
Product family
45 = PSRAM/CellularRAM memory
Operating core voltage
W = 1.7V–1.95V
Address locations
M = Megabits
Operating voltage
W = 1.7–3.6V
Bus configuration
16 = x16
READ/WRITE operation mode
B = Asynchronous/page/burst
Package codes
GB = 54-ball VFBGA “green” (6 x 9 grid, 0.75mm pitch, 6.0mm x 8.0mm x 1.0mm)
Production status
Blank = Production
ES = Engineering sample
MS = Mechanical sample
Operating temperature
WT = –30°C to +85°C (see note 1)
IT = –40°C to +85°C
Standby power options
Blank = Standard
Low power = L
Frequency
8 = 80 MHz
1 = 104 MHz
Access/cycle time
70 = 70ns
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32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Functional Description
Functional Description
In general, the MT45W2MW16BGB devices are high-density alternatives to SRAM and
PSRAM products, popular in low-power, portable applications.
The MT45W2MW16BGB contains a 33,554,432-bit DRAM core organized as 2,097,152
addresses by 16 bits. This device implements the same high-speed bus interface found
on burst mode Flash products.
The CellularRAM bus interface supports both asynchronous and burst mode transfers.
Page mode accesses are also included as a bandwidth-enhancin g extension to the asyn-
chronous READ protocol.
Power-Up Initialization
CellularRAM products include an on-chip voltage sensor used to launch the power-up
initialization process. Initialization will configure the BCR and the RCR with their
default settings (see Fi gure 19 on page 26 and Figure 24 on page 31). VCC and VCCQ must
be applied simultaneously. When they reach a stable level at or above 1.7V, the device
will require 150µs to complete its self-initi al ization process. During th e ini tialization
period, CE# should remain HIGH. When initialization is complete, the device is ready for
normal operation.
Figure 4: Power-Up Initialization Timing
Bus Operating Modes
The MT45W2MW16BGB CellularRAM products incorporate a burst mode interface
found on Flash products targeting low-power, wireless applications. This bus interface
supports asynchronous, page mode , an d burs t mod e READ and WRITE transfers. The
specific interface supported is def ine d b y the value loaded into the bus configuration
register. Page mode is controll ed by the refresh configuration register (RCR[7]).
Asynchronous Mode
CellularRAM products power up in the asynchronous operating mode. This mode uses
the industry-standard SRAM control bus (CE#, OE#, WE#, and LB#/UB#). READ opera-
tions are initiated by bringing CE#, OE#, and LB#/UB# LOW while keeping WE# HIGH
(see Figure 5 on page 12). Valid data will be driven out of the I/Os after the specified
access time has elaps ed . WRITE operations occur when CE#, WE#, and LB#/UB# are
driven LOW (see Figure 6 on page 12). During asynchronous WRITE operations, the OE#
level is a “Don't Care,” and WE# will override OE#. The data to be written is latched on
the rising edge of CE#, WE#, or LB#/UB#, whichever occurs first. Asynchronous opera-
tions (page mode disabled) either can use the ADV input to latch the address, or ADV
can be driven LOW during the entire READ/WRITE operation.
During asynchronous operation, the CLK input must be held static LOW or HIGH. WAIT
will be driven whil e the device is enabled, and its state should be ignored. WE# LOW
time must be limited to tCEM.
Vcc
VccQ Device initialization
Vcc = 1.7V Device ready for
normal operation
tPU >150μs
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32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Bus Operating Modes
Figure 5: READ Operation (ADV = LOW)
Note: ADV must remain LOW for page mode operation.
Figure 6: WRITE Operation (ADV = LOW)
Valid address
Data
CE#
Don’t Care
Valid data
OE#
WE#
LB#/UB#
tRC = READ cycle time
Address
Valid address
Data
CE#
Don’t Care
Valid data
OE#
WE#
LB#/UB#
tWC = WRITE cycle time
Address
<tCEM
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32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Bus Operating Modes
Page Mode READ Operation
Page mode is a performance-enhancing extension to the legacy asynchronous READ
operation. In page-m od e-capable products, an ini tial asynchronous READ ac ce ss is
performed, and then adjacent addresses can be read quickly by simply changing the
low-order address. Addresses A[3:0] are used to determine the members of the 16-
address CellularRAM page. Any change in address es A[4] or higher will initiate a new tAA
access time. Figure 7 on page 13 shows the timing for a page mode access.
Page mode takes advantage of the fact that adjacent addresses can be read in a shorter
period of time than random addresses. WRITE operations do not include comparable
page mode functionality.
During asynchronous page mode operation, the CLK input must be held static LOW or
HIGH. CE# must be driven HIGH upon completion of a page mode access. WAIT will be
driven while the device is enabled , and its state should be ignored. Page mode is enabled
by setting RCR[7] to HIGH. ADV must be driven LOW during all page mode READ
accesses.
The CE# LOW time is limited by refresh considerations. C E# mus t not stay LOW longer
than tCEM.
Figure 7: Page Mode READ Operation (ADV = LOW)
Burst Mode Operation
Burst mode operations enable high-speed synchronous READ and WRITE operations.
Burst operations consis t of a multiclock sequ ence that must be performed in an ordered
fashion. After CE# goes LOW, the address to access is latched on the next rising edge of
CLK that ADV# is LOW. During this first clock rising edge, WE# indicates whether the
operation is going to be a READ (WE# = HIGH, Figure8 on page 14) or WRITE
(WE# = LOW, Figure 9 on page 15).
The size of a burst can be specified in the BCR either as fixed-length or continuous.
Fixed-length bursts consist of 4, 8, or 16 words. Continuous bursts have the ability to
start at a specified address and burst through the entire memory. The latency count
stored in the BCR defines the number of clock cycles that elapse before the initia l data
value is transferred between the processor and CellularRAM device.
Data
CE#
Don’t Care
OE#
WE#
LB#/UB#
Address Address[0] Address
[1] Address
[2] Address
[3]
D[1] D[2] D[3]
tAA tAPA
<tCEM
tAPA tAPA
D[0]
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32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Bus Operating Modes
The WAIT output will be asserted as soon as CE# goes LOW and will be de-asserted to
indicate when data is to be transferred into (or out of) the memory. WAIT will again be
asserted if the burst crosses the boundary between 128-word rows. After the Cellu-
larRAM device has restored the previous row’s data and accessed the next row, WAIT
will be deasserted and the burst can continue (see Figure 35 on page 46).
The processor can access other device s wi thout inc urring the ti mi ng penalty of the
initial latency for a new burst by suspending burst mode. Bursts are suspended by stop-
ping CLK. CLK can be stopped HIGH or LOW. If another device will use the data bus
while the burst is suspended, OE# should be taken HIGH to disable the CellularRAM
outputs; otherwise, OE# can remain LOW. Note that the WAIT output will continue to be
active, and, as a result, no other devices should directly share the WAIT connection to
the controller. To continue the burst sequence, OE# is taken LOW, and then CLK is
restarted after valid data is available on the bus.
The CE# LOW time is limited by refresh considerations. C E# mus t not stay LOW longer
than tCEM unless row boundaries are crossed at least every tCEM. If a burst suspension
will cause CE# to remain LOW for longer than tCEM, CE# should be taken HIGH and the
burst restarted with a new CE# LOW/ADV# LOW cycle.
Figure 8: Burst Mode READ (4-Word Burst)
Note: Nondefault BCR settings: latency code 2 (3 clocks); WAIT active LOW; WAIT asserted during
delay.
A[20:0]
D[0]
ADV#
CE#
OE#
D[1] D[2] D[3]
WE#
WAIT
DQ[15:0]
LB#/UB#
Latency code 2 (3 clocks)
CLK
UndefinedDon’t Care
READ burst identified
(WE# = HIGH)
Valid
address
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32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Bus Operating Modes
Figure 9: Burst Mode WRITE (4-Word Burst)
Note: Nondefault BCR settings: latency code 2 (3 clocks); WAIT active LOW; WAIT asserted during
delay.
A[20:0]
D[0]
ADV#
CE#
OE#
D[1] D[2] D[3]
WE#
WAIT
DQ[15:0]
LB#/UB#
Valid
address
Latency code 2 (3 clocks)
CLK
Don’t Care
WRITE burst identified
(WE# = LOW)
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32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Bus Operating Modes
Mixed-Mode Operation
The device can support a combination of synchronous READ and asynchronous WRITE
operations when the BCR is configured for synchronous operation. The asynchronous
WRITE operation requires that the clock (CLK) be held static LOW or HIGH during the
entire sequence. The ADV# signal can be used to latch the target address, or it can
remain LOW during the entire WRITE operation. CE# must return HIGH when transi-
tioning between mixed-mode operations. Note that the tCKA period is the same as a
READ or WRITE cycle. This time is required to ensure adequate refresh. Mixed-mode
operation facilitates a seamless i nterface to legacy burst mode F lash memory controllers
(see Figure 43 on page 54).
WAIT Operation
The WAIT output on a CellularRAM device is typically connected to a shared, system-
level WAIT signal (see Figure 10). The shared WAIT signal is used by the processor to
coordinate transactions with multiple memories on the synchronous bus.
Figure 10: Wired-OR WAIT Configuration
After a READ or WRITE operation has been initiated, WAIT goes active to indicate that
the CellularRAM device requires additional time before data can be transferred. For
READ operations, WAIT will remain active until valid data is output from the device. For
WRITE operations, WAIT will indicate to the memory controller when data will be
accepted into the CellularRAM device. When WAIT transitions to an inactive state, the
data burst will progress on successive clock edges.
During a burst cycle, CE# must remain asserted until the first data is valid. Bringi ng CE#
HIGH during this initial latency may cause data corruption.
The WAIT output also performs an arbitration role when a READ or WRITE operation is
launched while an on-chip refresh is in progress. If a collision occurs, WAIT is asserted
for additional cloc k cycles until the refresh has completed (see Figure11 on page17 and
Figure12 on page18). When the REFRESH operation has completed, the READ or WRITE
operation will continue normally.
WAIT is also asserted when a continuous READ or WRITE burst crosses a r ow boundary.
The WAIT assertion allows time for the new row to be accessed and permits any pending
REFRESH operations to be performed.
LB#/UB# Operation
The LB# enable and UB# enable signals support byte-wide data transfers. During READ
operations, the enabled byte(s) are driven onto the DQ. The DQ associated with a
disabled byt e are put int o a High-Z state during a READ operation. During WRITE oper-
CellularRAM
External
pull-up/
pull-down
resistor
Processor
READY
Other
device
WAIT
Other
device
WAIT
WAIT
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32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Bus Operating Modes
ations, any disabled bytes will not be transferred to the RAM array, and the internal
value will remain unchanged. During an asynchronous WRITE cycle, the data to be
written is latched on the rising edge of CE#, WE#, LB#, or UB#, whichever occurs first.
When both the LB# and UB# are disabled (HIGH) during an operation, the device will
disable the data bus from receiving or transmitting data. Although the device will seem
to be deselected, it remains in an active mode as long as CE# remains LOW.
Figure 11: Refresh Collision During READ Operation
Note: Nondefault BCR settings: latency code 2 (3 clocks); WAIT active LOW; WAIT asserted during
delay.
A[20:0]
ADV#
CE#
OE#
WE#
WAIT
DQ[15:0]
CLK VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VOH
VOL
VOH
VOL
D[2]D[1] D[3]
Valid
address
Additional WAIT states inserted to allow refresh completion
LB#/UB#
Undefined Don’t Care
D[0]
High-Z
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32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Bus Operating Modes
Figure 12: Refresh Collision During WRITE Operation
Note: Nondefault BCR settings: latency code 2 (3 clocks); WAIT active LOW; WAIT asserted
during delay.
A[20:0]
ADV#
CE#
OE#
WE#
WAIT
DQ[15:0]
CLK
D[1]D[0] D[3]D[2]
Valid
address
Additional WAIT states inserted to allow refresh completion
LB#/UB#
Don’t Care
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VOH
VOL
VOH
VOL High-Z
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32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Low-Power Operation
Low-Power Operation
Standby Mode Operation
During standby, the device current consumption is reduced to the level necessary to
perform the DRAM REFRESH operation. Standby operation occurs when CE# is HIGH.
The device will enter a reduced power state upon completion of a READ or WRITE oper-
ation or when the address and control inputs remain static for an extended period of
time. This mode will continue until a change occurs to the address or control inputs.
Temperature-Compensated Refresh
Temperature-compensated refresh (TCR) allows for adequate refresh at different
temperatures. This CellularRAM device includes an on-chip temperature sensor that
continually adjusts the refresh rate according to th e ope rating temperature.
Partial-Array Refresh
Partial-array refresh (PAR) restricts REFRESH operation to a portion of the total memory
array. This feature enables the device to reduce standby current by refreshing only that
part of the memory array required by the host system. The refresh options are full array,
one-half array, one-quarter array, one-eighth array, or none of the array. The mapping
of these partitions either can start at the beginning or the end of the address map (see
Table 6 on page 32). READ and WRITE operations to address ranges receiving refresh
will not be affected. Data stored in addresses not receivi n g refresh will become
corrupted. When reenabling additional portions of the array, the new portions are avail-
able immediately upon writing to the RCR.
Deep Power-Down Operation
Deep power-down (DPD) operation disables all refresh-related activity. This mode is
used if the system does not require the storag e provided by the Cel lularRAM devic e. Any
stored data will b ecome corrupted when DPD i s enabled. When refresh ac tivity has been
reenabled by rewriting the RCR, the CellularRAM de vice will require 150µs to perform an
initialization procedure before normal operations can resume. During this 150µs period,
the current consumption will be higher than the specified standby levels, but consi der-
ably lower than the active current specific at ion.
DPD cannot be enabled or disabled by writing to the RCR using the software access
sequence; the RCR shoul d be acc e ss e d usi ng C RE ins te a d .
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32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Configuration Registers
Configuration Registers
Two user-accessible configuration registers define the device operation. The bus config-
uration register (BCR) defines how the CellularRAM interact s with the system memory bus
and is nearly identical to its counterpart on burst mode Flash devices. The refresh configu-
ration register (RCR) is used to control how refresh is performed on the DRAM array.
These registers are automatically loaded with default settings during power-up and can
be updated any time t he de vices are operating in a standby state.
Access Using CRE
The configuration registers are loaded using either a synchronous or an asynchronous
WRITE operation when the configuration register enable (CRE) input is HIGH (see
Figure 13, and Figure 14 on page 21). W hen CRE is LOW, a READ or WRITE operation
will access the memory array. The register values are placed on address pins A[19:0]. In
an asynchronous WRITE, the values are latched into the configuration register on the
rising edge of ADV#, CE#, or WE#, whichever occurs first; LB# and UB# are “Don’t Care.”
The BCR is accessed when A[19] is HIGH; the RCR is accessed when A[19] is LOW. For
READs, address inputs other than A19 are “Don't Care,” and register bits 15:0 are output
on DQ[15:0].
Figure 13: Asynchronous Mode Configuration Register WRITE Followed by READ ARRAY Operation
Note:
Note: A[19] = LOW to load RCR, HIGH to load BCR.
A[20:0]
(except A19)
CLK
OPCODE Address
Address
Valid data
A191
ADV#
CE#
OE#
WE#
LB#/UB#
DQ[15:0]
Initiate control register access
CRE
tAVS tAVH
tAVH
tAVS
tVP
tVPH
tCPH
tWP
tCW
Don’t Care
Select control register
Write address bus value
to control register
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32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Configuration Registers
Figure 14: Synchronous Mode Configuration Register WRITE Followed by READ ARRAY Operation
Notes: 1. Nondefault BCR settings for CR WRITE in synchronous mode followed by READ ARRAY
operation: latency code 2 (3 clocks); WAIT active LOW; WAIT asserted during delay.
2. A[19] = LOW to load RCR, HIGH to load BCR.
3. CE# must remain LOW to complete a burst-of-one WRITE. WAIT must be monitored—addi-
tional WAIT cycles caused by refresh collisions require a corresponding number of addi-
tional CE# LOW cycle s .
CLK
A[20:0]
(except A19)
A192
CRE
ADV#
CE#3
OE#
WE#
LB#/UB#
WAIT
DQ[15:0]
tSP
tSP
tSP
tHD
tHD
tHD
tCSP
tSP
tHD
High-Z
OPCODE Address
High-Z
tCEW
Latch control register value
Latch control register address
Valid
data
Address
Don’t Care
tCBPH
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32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Configuration Registers
Figure 15: Asynchronous Mode Configuration Register READ Followed by READ ARRAY Operation
Note: A[19] = LOW to read RCR, HIGH to read BCR.
A[20:0]
(except A19) Address
Address
Valid data
Valid CR
A[19]1
ADV#
CE#
OE#
WE#
LB#/UB#
DQ[15:0]
Initiate register access
CRE
tAVH
tAVS
tAA
tVP
tVPH
tCBPH
tCO
tOLZ
tBA
tLZ
tOE
tLZ
UndefinedDon’t Care
Select register
tAAVD
tAVS
tAA
tHZ
tOHZ
tBHZ
tAVH
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32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Configuration Registers
Figure 16: Synchronous Mode Configuration Register READ Followed by READ ARRAY Operation
Notes: 1. Nondefault BCR settings for synchronous mode register READ followed by READ ARRAY
operation: latency code 2 (3 clocks); WAIT active LOW; WAIT asserted during delay.
2. A[19] = LOW to read RCR, HIGH to read BCR.
3. CE# must remain LOW to complete a burst-of-one READ. WAIT must be monitored—addi-
tional WAIT cycles caused by refresh collisions require a corresponding number of addi-
tional CE# LOW cycle s .
CLK
A[20:0]
(except A19)
A[19]2
CRE
ADV#
CE#
OE#
WE#
LB#/UB#
WAIT
DQ[15:0]
tSP
tSP
tSP
tHD
tHD
tHD
tHZ
tCSP
tKOH
UndefinedDon’t Care
tSP
tHD
Address
tCEW
Latch control register value
tOLZ
Latch control register address
tCBPH3
tBOE
Valid
data
Address
tACLK
tOHZ
High-Z
High-Z
tABA
Valid
CR
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32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Configuration Registers
Software Access to the Configuration Register
Software access of the configuration registers uses a sequence of asynchronous READ
and asynchronous WRITE operations. The contents of the configuration registers can be
read or modified using the software sequence.
The configuration registers are loaded using a four-step sequence consisti ng of two
asynchronous READ operations followed by two asynchronous WRITE operations (see
Figure 17). The READ sequence is virtually identical except that an asynchronous READ
is performed during the fourth operation (see Figure 18 on page 25) .
The address used during all READ and WRITE operations is the highest address of the
CellularRAM device being accessed (1FFFFFh for 32Mb); the content at this address is
not changed by using this sequence.
The data value presented during the third operation (WRITE) in the sequence defines
whether the BCR or the RCR is to be accessed. If the data is 0000h, the sequence will
access the RCR; if the data is 0001h, the sequence will access the BCR. During the fourth
operation, DQ[15:0] transfer data into or out of bits 15–0 of the configuration registers.
The use of the software sequence does not affect the ability to perform the standard
(CRE-controlled) method of loading the configuration registers. However, the software
nature of this access mechanism eliminates the need for the control register enable
(CRE) pin. If the software mechanism is used, the CRE pin can simply b e tied to V SS. The
port line often used for CRE control purposes is no longer required.
Software access of the RCR should not be used to enter or exit DPD.
Figure 17: Load Configuration Register
Note: It is possible that the data stored at the highest memory location will be altered if the data
at the falling edge of WE# is not 0000h or 0001h.
Address
(MAX) Address
(MAX) Address
(MAX)
XXXXh XXXXh
RCR: 0000h
BCR: 0001h
CR value
in
Address
CE#
OE#
WE#
LB#/UB#
Data
Don't Care
READ READ WRITE WRITE
Address
(MAX)
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32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Configuration Registers
Figure 18: Read Configuration Register
Note: It is possible that the data stored at the highest memory location will be altered if the data
at the falling edge of WE# is not 0000h or 0001h.
Address
(MAX) Address
(MAX) Address
(MAX)
XXXXh XXXXh CR value
out
Address
CE#
OE#
WE#
LB#/UB#
Data
Don't Care
READ READ WRITE READ
RCR: 0000h
BCR: 0001h
Address
(MAX)
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32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Configuration Registers
Bus Configuration Register
The BCR defines how the CellularRAM device interacts with the system memory bus.
Page mode operation is enabled by a bit contained in the RCR. Figure 19 describes the
control bits in the BCR. At power-up, the BCR is set to 9D4Fh.
The BCR is accessed using CRE and A[1 9] HIGH or through the configuration register
software sequence with DQ = 0001h on the third cycle.
Figure 19: Bus Configuration Register Definition
Note: All burst WRITEs are continuous.
Must be set to "0"
A13
13 12 11 0
Latency
Counter
321
WAIT
Polarity
45
WAIT
Configuration (WC)
Clock
Configuration (CC)
678
Output
Impedance
Burst
Wrap (BW)*
14
A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
0
1
Operating Mode
Synchronous burst access mode
Asynchronous access mode (default)
BCR[12] BCR[11]
Latency Counter
BCR[13]
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Code 0–reserved
Code 1–reserved
Code 2
Code 3 (default)
Code 4–reserved
Code 5–reserved
Code 6–reserved
Code 7–reserved
0
1
WAIT Polarity
Active LOW
Active HIGH (default)
BCR[10]
0
1
WAIT Configuration
Asserted during delay
Asserted one data cycle before delay (default)
0
1
Output Impedance
Full drive (default)
1/4 drive
BCR[5]
Burst Wrap (Note 1)
Burst wraps within the burst length
Burst no wrap (default)
BCR[3]
BCR[1] BCR[0] Burst Length (Note 1) BCR[2]
15
Burst
Length (BL)*
Reserved
Reserved
910
Reserved
Operating
Mode
Reserved
20
A14A15
A[18:16]
0
1
Register Select
Select RCR
Select BCR
Must be set to "0"
19 18–16
Register
Select
Reserved
A19A20
Reserved
Must be set to "0" Must be set to "0" Must be set to "0" Must be set to "0"
BCR[8]
0
1
Clock Configuration
Not supported
Rising edge (default)
BCR[6]
BCR[15]
BCR[19]
0
1
0
0
0
1
0
1
1
1
1
0
1
1
4 words
8 words
16 words
Continuous burst (default)
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32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Configuration Registers
Burst Length (BCR[2:0]) Default = Continuous Burst
Burst lengths define the number of words the device outputs during a burst READ oper-
ation. The device supports a burst length of 4, 8, or 16 words. The device can also be set
in continuous burst mode where data is output sequentially without regard to address
boundaries; the internal address wraps to 000000h if the device is read past the last
address. WRITE bursts are always performed using continuous burst mode.
Burst Wrap (BCR[3]) Default = Burst No Wrap (Within Burst Length)
The burst wrap option d etermines whether a 4-, 8-, or 16-word burst READ wraps within
the burst length or steps through sequential addresses. If the wrap option is not enabled,
the device outputs data from sequential addresses without regard to burst boundaries;
the internal address wraps to 000000h if the device is read past the last address.
Table 4: Sequence and Burst Length
Burst Wrap Starting
Address
4-Word
Burst
Length 8-Word
Burst Length 16-Word Burst Length Continuous Burst
BCR[3] Wrap (Decimal) Linear Linear Linear Linear
0 Yes 0 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7-8-9-10-11-12-13-14-15 0-1-2-3-4-5-6-…
1 1-2-3-0 1-2-3-4-5-6-7-0 1-2-3-4-5-6-7-8-9-10-11-12-13-14-15-0 1-2-3-4-5-6-7-…
2 2-3-0-1 2-3-4-5-6-7-0-1 2-3-4-5-6-7-8-9-10-11-12-13-14-15-0-1 2-3-4-5-6-7-8-…
3 3-0-1-2 3-4-5-6-7-0-1-2 3-4-5-6-7-8-9-10-11-12-13-14-15-0-1-2 3-4-5-6-7-8-9-…
4 4-5-6-7-0-1-2-3 4-5-6-7-8-9-10-11-12-13-14-15-0-1-2-3 4-5-6-7-8-9-10-…
5 5-6-7-0-1-2-3-4 5-6-7-8-9-10-11-12-13-14-15-0-1-2-3-4 5-6-7-8-9-10-11-…
6 6-7-0-1-2-3-4-5 6-7-8-9-10-11-12-13-14-15-0-1-2-3-4-5 6-7-8-9-10-11-12-…
7 7-0-1-2-3-4-5-6 7-8-9-10-11-12-13-14-15-0-1-2-3-4-5-6 7-8-9-10-11-12-13-…
... ... ...
14 14-15-0-1-2-3-4-5-6-7-8-9-10-11-12-13 14-15-16-17-18-19-20-
...
15 15-0-1-2-3-4-5-6-7-8-9-10-11-12-13-14 15-16-17-18-19-20-21-
...
1 No 0 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7-8-9-10-11-12-13-14-15 0-1-2-3-4-5-6-…
1 1-2-3-4 1-2-3-4-5-6-7-8 1-2-3-4-5-6-7-8-9-10-11-12-13-14-15-16 1-2-3-4-5-6-7-…
2 2-3-4-5 2-3-4-5-6-7-8-9 2-3-4-5-6-7-8-9-10-11-12-13-14-15-16-
17 2-3-4-5-6-7-8-…
3 3-4-5-6 3-4-5-6-7-8-9-10 3-4-5-6-7-8-9-10-11-12-13-14-15-16-17-
18 3-4-5-6-7-8-9-…
4 4-5-6-7-8-9-10-11 4-5-6-7-8-9-10-11-12-13-14-15-16-17-
18-19 4-5-6-7-8-9-10-…
5 5-6-7-8-9-10-11-12 5-6-7-8-9-10-11-12-13-...-15-16-17-18-
19-20 5-6-7-8-9-10-11-…
6 6-7-8-9-10-11-12-
13 6-7-8-9-10-11-12-13-14-...-16-17-18-19-
20-21 6-7-8-9-10-11-12-…
7 7-8-9-10-11-12-13-
14 7-8-9-10-11-12-13-14-...-17-18-19-20-
21-22 7-8-9-10-11-12-13-…
... ... ...
14 14-15-16-17-18-19-...-23-24-25-26-27-
28-29 14-15-16-17-18-19-20-
…
15 15-16-17-18-19-20-...-24-25-26-27-28-
29-30 15-16-17-18-19-20-21-
…
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32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Configuration Registers
Output Impedance (BCR[5]) Default = Outpu ts Use Full Drive Strength
The output driver strength can be altered to adjust for different data bus loading
scenarios. The reduced-strength option should be more than adequate in stacked chip
(Flash + CellularRAM) e nvironments when there is a dedicated memory bus. The reduced-
drive-strength option is included to minimize noise generated on the data bus during
READ operations. Normal output impedance should be selected when using a discrete
CellularRAM device in a more heavily loaded data bus environment. Partial drive is
approximately one-quarter full drive strength. Outputs are configured at full drive
strength during testing.
WAIT Configuration (BCR[8]) Default = WAIT Transitions One Clock Before Data Valid/Invalid
The WAIT configuration bit is used to determine when WAIT transitions between the
asserted and the deasserted state with respect to valid data presented on the data bus.
The memory controller will use the WAIT signal to coordinate data transfer during
synchronous READ and WRITE operations. When BCR[8] = 0, data will be valid or invalid
on the clock edge immediately after WAIT transitions to the deasserted or asserted state,
respectively (see Fi gure s 20 and 22). When BCR[8] = 1, the WAIT signal transitions one
clock period prior to the data bus going valid or invalid (see Figure 21 and Figure 22 on
page 29).
Figure 20: WAIT Configuration (BCR[8] = 0)
Note: Data valid/invalid immediately after WAIT transitions (BCR[8] = 0). See Figure 22 on
page 29.
Figure 21: WAIT Configuration (BCR[8] = 1)
Note: Valid/invalid data delayed for one clock after WAIT transitio ns (BCR[8] = 1). See Figure 22
on page 29.
WAIT
DQ[15:0]
CLK
Data[0] Data[1]
Data immediately valid (or invalid)
High-Z
WAIT
D[15:0]
CLK
Data[0]
Data valid (or invalid) after one clock delay
High-Z
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32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Configuration Registers
Figure 22: WAIT Configuration During Burst Operation
Note: Nondefault BCR setting for WAIT during BURST operation: WAIT active LOW.
WAIT Polarity (BCR[10]) Default = WAIT Active HIGH
The WAIT polarity bit indicates whether an asserted WAIT output should be HIGH or
LOW. This bit will determine whether the WAIT signal requires a pull-up or pull-down
resistor to maintain the deasserted state.
Latency Counter (BCR[13:11]) Default = Three-Clock Latency
The latency counter bits determine how many clocks occur between the beginning of a
READ or WRITE operation and the first data value transferred. Only latency code 2 (3
clocks) or latency code 3 (4 clocks) is allowed (see Table 5 and Figure 23 on page 30).
Operating Mode (BCR[15]) Default = Asynchronous Operation
The operating mode bit either selects synchronous burst operation or the default asyn-
chronous mode of operation.
Table 5: Latency Configuration
Latency Configuration Code
Max Input CLK Frequency
104 MHz 80 MHz
2 (3 clocks) 66 (15ns) 53 (18.75ns)
3 (4 clocks) – default 104 (9.62ns) 80 (12.50ns)
WAIT
WAIT
DQ[15:0]
CLK
D[0] D[1]
BCR[8] = 0
Data valid in current cycle
BCR[8] = 1
Data valid in next cycle
Don’t Care
D[2] D[3] D[4]
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32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Configuration Registers
Figure 23: Latency Counter (Variable Latency, No Refresh Collision)
A[20:0]
ADV#
DQ[15:0]
CLK
Code 2
Valid
output Valid
output Valid
output
Valid
output
Valid
output
Valid
output Valid
output
Valid
output
Valid
output
Code 3 (Default)
DQ[15:0]
Don’t Care Undefined
VIH
VIL
VIH
VIL
VIH
VIL
VOH
VOL
VOH
VOL
Valid
address
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32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Configuration Registers
Refresh Configuration Register
The refresh configuration register (RCR) defines how the CellularRAM device performs
its transparent self refresh. Altering the refresh parameters can dramatically reduce
current consumption during standby mode. Page mod e c ontrol is also embedded into
the RCR. Figure 24 describes the control bits used in the RCR. At power-up, the RCR is
set to 0010h.
The RCR is accessed using CRE and A[19] LOW or through the configuration register
software access sequence with DQ = 0000h on the third cycle (see “Configuration Regis-
ters” on page 20.)
Partial-Array Refresh (RCR[2:0]) Default = Full Array Refresh
The PAR bits restrict refresh operation to a portion of the total memory array. This
feature enables the device to reduce standby current by refreshing only that part of the
memory array required by the host system. The refresh options are full array, one-half
array, one-quarter array, one-eighth array, or none of the array. The mapping of these
partitions can start either at the beginni ng or the e nd of the addre ss map (se e Table 6 on
page 32).
Figure 24: Refresh Configuration Register Mapping
PAR
A4 A3 A2 A1 A0 Address Bus
45 1
2
30
Reserved Reserved
6
A5
0
1
Deep Power-Down
DPD enable
DPD disable (default)
RCR[4]
Ignored
A6
All must be set to “0”
A[18:8]
18–8
19
20
Register
Select
Reserved
A20 A19
0
1
Register Select
Select RCR
Select BCR
RCR[19]
RCR[1]
0
0
1
1
RCR[0]
0
1
0
1
Refresh Coverage
Full array (default)
Bottom 1/2 array
Bottom 1/4 array
Bottom 1/8 array
RCR[2]
0
0
0
0
00
1
01
1
10
1
11
1
None of array
Top 1/2 array
Top 1/4 array
Top 1/8 array
DPD
Must be set to “0”
A7
7
Page
0
1
Page Mode Enable/Disable
Page mode disabled (default)
Page mode enable
RCR[7]
Must be set to “0” Setting is ignored
(default 00b)
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32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN 32 ©2007 Micron Technology, Inc. All rights reserved.
32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Electrical Characteristics
Deep Power-Down (RCR[4]) Default = DPD Disabled
The deep power-down bit enables and disables all refresh-related activity. This mode is
used if the system does not require the storag e provided by the Cel lularRAM devic e. Any
stored data will b ecome corrupted when DPD i s enabled. When refresh ac tivity has been
reenabled, the CellularRAM device will require 150µs to perform an initialization proce-
dure before normal operations can resume.
Deep power-down is enabled when RCR[4] = 0 an d remains enabled until RCR[4] is set to
“1.” DPD should not be enabled or disabled with the software access seque n ce; instead,
use CRE to access the RCR.
Page Mode Operation (RCR[7]) Default = Disabled
The page mode operation bit determines whether page mode is enabled for asynchro-
nous READ operations. In the power-up default state, page mode is disabled.
Electrical Characteristics
Stresses greater than those listed may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at these or any other condi-
tions above those indicated in the operational sections of this specifi cation is not
implied. Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
Note: –30°C exceeds the CellularRAM Workgroup 1.0 specification of –25°C.
Table 6: 32Mb Address Patterns for PAR (RCR[4] = 1)
RCR[2] RCR[1] RCR[0] Active Section Address Space Size Density
0 0 0 Full die 000000h–1FFFFFh 2 Meg x 16 32Mb
0 0 1 One-half of die 000000h–0FFFFFh 1 Meg x 16 16Mb
0 1 0 One-quarter of die 000000h–07FFFFh 512K x 16 8Mb
0 1 1 One-eighth of die 000000h–03FFFFh 256K x 16 4Mb
1 0 0 None of die 0 0 Meg x 16 0Mb
1 0 1 One-half of die 100000h–1FFFFFh 1 Meg x 16 16Mb
1 1 0 One-quarter of die 180000h–1FFFFFh 512K x 16 8Mb
1 1 1 One-eighth of die 1C0000h–1FFFFFh 256K x 16 4Mb
Table 7: Absolute Maximum Ratings
Parameter Rating
Voltage to any ball except VCC; VCCQ relative
to VSS –0.5V to (4.0V or VCCQ + 0.3V, whichever is
less)
Voltage on VCC supply relative to VSS –0.2V to +2.45V
Voltage on VCCQ supply relative to VSS –0.2V to +4.0V
Storage temperature (plastic) –55ºC to +150ºC
Operating temperature (case)
Wirelessnote:
Industrial –30ºC to +85ºC
–40ºC to +85ºC
Soldering temperature and time
10 seconds (solder ball only) +260ºC
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32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN 33 ©2007 Micron Technology, Inc. All rights reserved.
32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Electrical Characteristics
Notes: 1. –30°C exceeds the CellularRAM Workgroup 1.0 specification of –25°C.
2. Input signals may overshoot to VCCQ + 1.0V for periods less than 2ns during transitions.
3. VIH (MIN) value is not aligned with CellularRAM Workgroup 1.0 specification of VCCQ - 0.4V.
4. Input signals may undershoot to VSS - 1.0V for periods less than 2ns during transitions.
5. BCR[5] = 0b.
6. This parameter is specified with the outputs disabled to avoid external loading effects.
The user must add the current required to drive output capacit ance expected in the actual
system.
7. ISB (MAX) values measured with PAR set to FULL ARRAY. To achi eve low stand by current, al l
inputs must be driven either to VCCQ or VSS. ISB might be slightly higher for up to 500ms
after power-up, after changes to the PAR array partition, or when entering standby mode.
Table 8: Electrical Characteristics and Operating Conditions
Wireless temperature1 (–30ºC < TC < +85ºC); industrial temperature (–40ºC < TC < +85ºC)
Description Conditions Symbol Min Max Units Notes
Supply voltage VCC 1.7 1.95 V
I/O supply voltage VCCQ1.73.6V
Input high volt ag e VIH 1.4 VCCQ + 0.2 V 2, 3
Input low voltage VIL –0.2 0.4 V 4
Output high voltage IOH = –0.2mA VOH 0.8 VCCQ– V5
Output low voltage IOL = +0.2mA VOL – 0.2 VCCQV 5
Input leakage current VIN = 0 to VCCQILI –1µA
Output leakage current OE# = VIH or
chip disabl ed ILO –1µA
Operating Current
Asynchronous random READ/
WRITE VIN = VCCQ or 0V
chip enabled;
IOUT = 0
ICC1–70 – 20mA6
–
Asynchronous page READ ICC1P –70 – 15 mA 6
–
Initial access, burst READ/WRITE ICC2 104 MHz – 40 mA 6
80 MHz 35
Continuous burst READ ICC3R 104 MHz – 25 mA 6
80 MHz 18
Continuous burst WRITE ICC3W 104 MHz – 40 mA 6
80 MHz 35
Standby current VIN = VCCQ or 0V
CE# = VCCQISB Standard – 110 µA 7
–
–
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32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN 34 ©2007 Micron Technology, Inc. All rights reserved.
32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Electrical Characteristics
Maximum and Typical Standby Currents
The following table and figure refer to the maximum and typical standby currents for the
MT45W2MW16BGB device. The typical values shown in Figure 25 are me asured with
the default on-chip temperature sensor control enabled.
Note: IPAR (MAX) values measure d at 85 °C . IPAR might be slightly higher for up to 500ms after
changes to the PAR array partition or when entering standby mode. To achi eve low
standby current, all inputs must be driven eithe r to VCCQ or VSS.
Figure 25: Typical Refresh Current vs. Temperature
Table 9: Partial-Array Refresh Specifications and Conditions
Description Conditions Symbol Array Partition Max Unit
Partial-array refresh
standby current VIN = VCCQ or 0V;
CE# = VCCQIPAR Standard power
(no designation) Full 110 µA
1/2 105
1/4 95
1/8 95
070
0
20
30
40
50
–45 –35 –25 –15 –05 05 15 25 35 45 55 65 75 85
Temperature (°C)
ISB (μA)
10
60
70
95
PAR full
PAR 1/2
PAR 1/4
PAR 0
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32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN 35 ©2007 Micron Technology, Inc. All rights reserved.
32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Electrical Characteristics
Note: These parameters are verified in device characterization and are not 100% tested.
Figure 26: AC Input/Output Reference Waveform
Notes: 1. AC test inputs are driven at VCCQ for a logic 1 and VSSQ for a logic 0. Input rise and fall
times (10% to 90%) < 1.6ns.
2. Input timing begins at VCCQ/2.
3. Output timing ends at VCCQ/2.
Figure 27: Output Load Circuit
Note: All tests are performed with the outputs configured for full drive strength (BCR[5] = 0b).
Table 10: Deep Power-Down Specifications
Description Conditions Symbol Typ Units
Deep power-down VIN = VCCQ or 0V; +25°C IZZ 10 µA
Table 11: Capacitance
Description Conditions Symbol Min Max Units Notes
Input capacitance TC = +25ºC; f = 1 MHz;
VIN = 0V CIN 2.0 6.5 pF Note:
Input/output capacitance (DQ) CIO 3.0 6.5 pF Note:
Output
Test points
Input
1
VSS
Q
VCCQ/2
3
VCC
Q
VCCQ/2
2
DUT VccQ/2
30pF
Test point
50W
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32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN 36 ©2007 Micron Technology, Inc. All rights reserved.
32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Timing Requirements
Timing Requirements
Notes: 1. All tests are performed with the outputs configured for full drive strength (BCR[5] = 0b).
2. Low-Z to High-Z timings are tested with the circuit shown in Figure 27 on page 35. The
High-Z timings measure a 100mV transition either from VOH or VOL toward VCCQ/2.
3. High-Z to Low-Z timings are tested with the circuit shown in Figure 27 on page 35. The Low-
Z timings measure a 100mV transition away from the High-Z (VCCQ/2) level either toward
VOH or VOL.
4. Page mode enabled only.
Table 12: Asynchronous READ Cycle Timing Requirements
Parameter1Symbol
70ns
Units NotesMin Max
Address access time tAA – 70 ns
ADV# access time tAADV – 70 ns
Page access time tAPA – 20 ns
Address hold from ADV# HIGH tAVH 5 – ns
Address setup to ADV# HIGH tAVS 5 – ns
LB#/UB# access time tBA – 70 ns
LB#/UB# disable to DQ High-Z output tBHZ – 8 ns 2
LB#/UB# enable to Low-Z output tBLZ10–ns3
Maximum CE# pu lse width tCEM – 8 µs 4
CE# LOW to WAIT valid tCEW 1 7.5 ns
Chip select access time tCO – 70 ns
CE# LOW to ADV# HIGH tCVS 10 – ns
Chip disable to DQ and WAIT High-Z output tHZ – 8 ns 2
Chip enable to Low-Z output tLZ 10 – ns 3
Output enable to valid output tOE – 20 ns
Output hold from address change tOH 5 – ns
Output disable to DQ High-Z output tOHZ – 8 ns 2
Output enable to Low-Z output tOLZ 3 – ns 3
Page cycle time tPC 20 – ns
READ cycle time tRC 70 – ns
ADV# pulse wid t h L OW tVP 10 – ns
ADV# pulse width HIGH tVPH 10 – ns
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32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN 37 ©2007 Micron Technology, Inc. All rights reserved.
32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Timing Requirements
Notes: 1. All tests are performed with the outputs configured for full drive strength (BCR[5] = 0b).
2. When co nfigured for synchr onous mode (BCR[15] = 0), a refresh opportunity must be pro-
vided every tCEM. A refresh opportunity is satisfied by either of the following two condi-
tions: clocked CE# HIGH or CE# HIGH for greater than 15ns.
3. Low-Z to High-Z timings are tested with the circuit shown in Figure 27 on page 35. The
High-Z timings measure a 100mV transition either from VOH or VOL toward VCCQ/2.
4. High-Z to Low-Z timings are tested with the circuit shown in Figure 27 on page 35. The Low-
Z timings measure a 100mV transition away from the High-Z (VCCQ/2) level either toward
VOH or VOL.
Table 13: Burst READ Cycle Timing Requirements
Parameter1Symbol
104 MHz 80 MHz
Units NotesMin Max Min Max
Burst to READ access time tABA – 35.9 – 46.5 ns
CLK to output delay tACLK – 7 – 9 ns
Burst OE# LOW to output delay tBOE – 20 – 20 ns
CE# HIGH between subsequent burst and
mixed-mode operations
tCBPH5–5–ns2
Maximum CE# pu lse width tCEM – 8 – 8 µs
CE# LOW to WAIT valid tCEW 1 7.5 1 7.5 ns
CLK period tCLK 9.62 – 12.5 – ns
CE# setup time to active CLK edge tCSP 3 – 4.5 – ns
Hold time from active CLK edge tHD 2–2–ns
Chip disable to DQ and WAIT High-Z output tHZ – 8 – 8 ns 3
CLK rise or fall time tKHKL –1.6–1.8ns
CLK to WAIT valid tKHTL – 7 – 9 ns
Output HOLD from CLK tKOH 2–2–ns
CLK HIGH or LOW time tKP 3–4–ns
Output disable to DQ High-Z output tOHZ – 8 – 8 ns 3
Output enable to Low-Z output tOLZ 3 – 3 – ns 4
Setup time to active CLK edge tSP 3–3–ns
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32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN 38 ©2007 Micron Technology, Inc. All rights reserved.
32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Timing Requirements
Notes: 1. High-Z to Low-Z timings are tested with the circuit shown in Figure 27 on page 35. The Lo w-
Z timings measure a 100mV transition away from the High-Z (VCCQ/2) level either toward
VOH or VOL.
2. Low-Z to High-Z timings are tested with the circuit shown in Figure 27 on page 35. The
High-Z timings measure a 100mV transition either from VOH or VOL toward VCCQ/2.
3. WE# LOW time must be lim ite d to tCEM (8µs).
Table 14: Asynchronous WRITE Cycle Timing Requirements
Parameter Symbol
70ns
Units NotesMin Max
Address and ADV# LOW setup time tAS 0 – ns
Address hold from ADV# going HIGH tAVH 5 – ns
Address setup to ADV# going HIGH tAVS 5 – ns
Address valid to end of WRITE tAW 70 – ns
LB#/UB# select to end of WRITE tBW 70 – ns
CE# LOW to WAIT valid tCEW 1 7.5 ns
Asynchronous address-to-burst transition time tCKA 70 – ns
CE# HIGH between subsequent asynchronous operations tCPH 5 – ns
CE# LOW to ADV# HIGH tCVS 10 – ns
Chip enable to end of WRITE tCW 70 – ns
Data hold from WRITE time tDH 0 – ns
Data WRITE setup time tDW 23 – ns
Chip disable to WAIT High-Z output tHZ – 8 ns
Chip enable to Low-Z output tLZ 10 – ns 2
End WRITE to Low-Z output tOW 5 – ns 1
ADV# pulse wid t h tVP 10 – ns
ADV# pulse width HIGH tVPH 10 – ns
ADV# setup to end of WRITE tVS 70 – ns
WRITE cycle time tWC 70 – ns
WRITE to DQ High-Z output tWHZ – 8 ns 2
WRITE pulse width tWP 46 – ns 3
WRITE pulse width HIGH tWPH 10 – ns
WRITE recovery time tWR 0 – ns
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32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN 39 ©2007 Micron Technology, Inc. All rights reserved.
32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Timing Requirements
Note: When configured for synchronous mode (BCR[15] = 0), a refresh opportunity must be pro-
vided every tCEM. A refresh opportunity is satisfied by either of the fo ll owi ng two condi-
tions: clocked CE# HIGH or CE# HIGH for greater than 15ns.
Figure 28: Initialization Period
Table 15: Burst WRITE Cycle Timing Requirements
Parameter Symbol
104 MHz 80 MHz
Units NotesMin Max Min Max
CE# HIGH between subsequent burst and
mixed-mode operations
tCBPH5–5–ns 1
Maximum CE# pu lse width tCEM – 8 – 8 µs 1
CE# LOW to WAIT valid tCEW 1 7.5 1 7.5 ns
Clock period tCLK 9.62 – 12.5 – ns
CE# setup to CLK active edge tCSP 3 – 4.5 – ns
Hold time from active CLK edge tHD2–2–ns
Chip disable to WAIT High-Z output tHZ – 8 – 8 ns
CLK rise or fall time tKHKL – 1.6 – 1.8 ns
Clock to WAIT valid tKHTL – 7 – 9 ns
CLK HIGH or LOW time tKP3–4–ns
Setup time to active CLK edge tSP3–3–ns
Table 16: Initialization Timing Parameters
Parameter Symbol
-70
UnitsMin Max
Initialization period
(required before normal operations)
tPU 150 – µs
tPU
Vcc, VccQ = 1.7V
Vcc (MIN)
Device ready for
normal operation
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32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN 40 ©2007 Micron Technology, Inc. All rights reserved.
32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Timing Diagrams
Timing Diagrams
Figure 29: Asynchronous READ
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VOH
VOL
VOH
VOL
A[20:0]
ADV#
CE#
LB#/UB#
OE#
WE#
WAIT
DQ[15:0]
Valid address
tAA
tHZ
tBA
High-Z High-Z
tRC
tCO
tBHZ
tOHZ
tOE
tCEW tHZ
Valid output
High-Z
Undefined
Don’t Care
tBLZ
tLZ
tOLZ
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32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN 41 ©2007 Micron Technology, Inc. All rights reserved.
32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Timing Diagrams
Figure 30: Asynchronous READ Using ADV#
A[20:0]
ADV#
CE#
LB#/UB#
OE#
WE#
WAIT
DQ[15:0]
Valid address
tVPH
tAADV
tAA
tVP
tHZ
tBA
High-Z High-Z
tCVS
tCO
tBLZ
tBHZ
tOHZ
tLZ
tOE
tOLZ
Valid output
tAVH
tAVS
High-Z
Undefined
Don’t Care
tCEW tHZ
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VOH
VOL
VOH
VOL
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32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Timing Diagrams
Figure 31: Page Mode READ
A[3:0]
ADV#
CE#
LB#/UB#
OE#
WE#
WAIT
DQ[15:0]
Valid address
tAA
tHZ
tBA
High-Z High-Z
tCO
tCEM
tBLZ
tBHZ
tOHZ
tLZ
tOE
tOLZ
tCEW tHZ
High-Z
Undefined
Don’t Care
A[20:4] Valid address
Valid
address
Valid
address
Valid
address
tRC
Valid
output
tAPA
tPC
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VOH
VOL
VOH
VOL
tOH
Valid
output Valid
output Valid
output
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32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN 43 ©2007 Micron Technology, Inc. All rights reserved.
32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Timing Diagrams
Figure 32: Single-Access Burst READ Operation
Note: Nondefault BCR settings for single-access burst READ operation: latency code 2 (3 clocks );
WAIT active LOW; WAIT asserted during delay.
A[20:0]
VIH
VIL
ADV#
VIH
VIL
CE#
VIH
VIL
OE#
VIH
VIL
WE#
VIH
VIL
WAIT
DQ[15:0]
VOH
VOL
CLK
VIH
VIL
VOH
VOL
tSP
tCLK
tACLK
tCEW
tHD
tABA
Valid output
Valid address
High-Z
tKOH
tOHZ
tSP tHD
LB#/UB#
VIH
VIL
tCSP
tSP
tCEM
tOLZ
tHD
tHZ
tKP tKP tKHKL
tHD
tSP
Undefined
Don’t Care
READ burst identified
(WE# = HIGH)
tKHTL
tBOE
High-Z High-Z
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32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Timing Diagrams
Figure 33: 4-Word Burst READ Operation
Note: Nondefault BCR settings for 4-word burst READ operation: l atency c ode 2 ( 3 cl oc ks); WAI T
active LOW; WAIT asserted during delay.
A[20:0] VIH
VIL
ADV# VIH
VIL
CE# VIH
VIL
OE# VIH
VIL
WE# VIH
VIL
WAIT
DQ[15:0]
VOH
VOL
CLK VIH
VIL
VOH
VOL
tSP
tCLK
tKHKL
tHD
Valid address
High-Z
tKOH
tHZ
tHD
tSP tHD
LB#/UB# VIH
VIL
tOLZ
tCBPH
tCSP
tSP
tCEM
tSP tHD
tOHZ
tKP tKP
Undefined
Don’t Care
READ burst identified
(WE# = HIGH)
tCEW
tACLK
tKHTL
Valid outputValid output Valid outputValid output
tBOE
High-Z
tABA
High-Z
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32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Timing Diagrams
Figure 34: READ Burst Suspend
Note: Nondefault BCR settings for READ burst suspend: laten cy code 2 (3 clocks); WAIT active
LOW; WAIT asserted during delay.
A[20:0] VIH
VIL
ADV# VIH
VIL
CE# VIH
VIL
OE# VIH
VIL
WE# VIH
VIL
WAIT
DQ[15:0]
VOH
VOL
CLK VIH
VIL
VOH
VOL
tSP tHD
tOLZ
tACLK
LB#/UB# VIH
VIL
tCLK
tSP
tHD
tCSP
tSP
tCEM
tSP tHD
tKOH
Valid
output
Valid
address
tCBPH
tHZ
tOHZ
Valid
output Valid
output Valid
output Valid
output
tBOE
tOHZ
tBOE
Valid
address
High-Z
Don’t Care Undefined
High-Z
Valid
output
tOLZ
High-Z
PDF: 09005aef82832fa2/Source: 09005aef82832f5f Micron Technology, Inc., reserves the right to change products or specifica tions without notice.
32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN 46 ©2007 Micron Technology, Inc. All rights reserved.
32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Timing Diagrams
Figure 35: Output Delay in Continuous Burst READ with BCR[8] = 0 for End-of-Row Condition
Notes: 1. Nondefault BCR settings for continuous burst READ showing an output delay, BCR[8] = 0 for
end-of-row condition: latency code 2 (3 cloc ks); WAIT active LOW; WAIT asserted during
delay.
2. WAIT will be asserted a maximum of LC cycles (BCR[8] = 0; WAIT asserted during delay).
LC = latency code (BCR[13:11]).
3. CE# must not remain LOW longer than tCEM.
tACLK tKOH
A[20:0] VIH
VIL
ADV# VIH
VIL
CE# VIH
VIL
OE# VIH
VIL
WE# VIH
VIL
WAIT
DQ[15:0]
VOH
VOL
CLK VIH
VIL
VOH
VOL
tKHTL tKHTL
tCLK
LB#/UB# VIH
VIL
Valid output Valid output Valid output Valid output
Note 2
Note 3
Don’t Care
PDF: 09005aef82832fa2/Source: 09005aef82832f5f Micron Technology, Inc., reserves the right to change products or specifica tions without notice.
32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN 47 ©2007 Micron Technology, Inc. All rights reserved.
32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Timing Diagrams
Figure 36: CE#-Controlled Asynchronous WRITE
A[20:0]
ADV#
CE#
LB#/UB#
OE#
WE#
WAIT
DQ[15:0]
in
Valid address
High-Z High-Z
tWC
tCEW tHZ
Valid input
tAW
Don’t Care
tCW
tDW
DQ[15:0]
out
tWHZ
tBW
tLZ
tDH
tAS
tWP
tWPH
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VOH
VOL
VOH
VOL
High-Z
tCPH
tWR
PDF: 09005aef82832fa2/Source: 09005aef82832f5f Micron Technology, Inc., reserves the right to change products or specifica tions without notice.
32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN 48 ©2007 Micron Technology, Inc. All rights reserved.
32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Timing Diagrams
Figure 37: LB#/UB#-Controlled Asynchronous WRITE
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VOH
VOL
A[20:0]
ADV#
CE#
LB#/UB#
OE#
WE#
WAIT
DQ[15:0]
in
VIH
VIL
Valid address
High-Z
tWC
tCEW tHZ
Valid input
tAW
Don’t Care
tCW
tDW
DQ[15:0]
out
VOH
VOL
tWHZ
tBW
tLZ
tDH
tAS
tWP
tWPH
High-Z
High-Z
tWR
PDF: 09005aef82832fa2/Source: 09005aef82832f5f Micron Technology, Inc., reserves the right to change products or specifica tions without notice.
32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN 49 ©2007 Micron Technology, Inc. All rights reserved.
32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Timing Diagrams
Figure 38: WE#-Controlled Asynchronous WRITE
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VOH
VOL
A[20:0]
ADV#
CE#
LB#/UB#
OE#
WE#
WAIT
DQ[15:0]
in
VIH
VIL
Valid address
tWC
tCEW tHZ
Valid input
tAW
Don’t Care
tWR
tDW
DQ[15:0]
out
VOH
VOL
tWHZ
tBW
tCW
tLZ
tWP
tDH
tOW
tAS
tWPH
High-Z
High-Z
High-Z
PDF: 09005aef82832fa2/Source: 09005aef82832f5f Micron Technology, Inc., reserves the right to change products or specifica tions without notice.
32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN 50 ©2007 Micron Technology, Inc. All rights reserved.
32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Timing Diagrams
Figure 39: Asynchronous WRITE Using ADV#
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VOH
VOL
A[20:0]
ADV#
CE#
LB#/UB#
OE#
WE#
WAIT
DQ[15:0]
in
VIH
VIL
Valid address
High-Z High-Z
tCEW tHZ
Valid input
tVS
Don’t Care
tCW
tDW
DQ[15:0]
out
VOH
VOL
tWHZ
tBW
tLZ
tWP
tDH
tOW
tAS
tWPH
tAS
tVPH
tAVH
tAVS
tVP
tAW
High-Z
PDF: 09005aef82832fa2/Source: 09005aef82832f5f Micron Technology, Inc., reserves the right to change products or specifica tions without notice.
32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN 51 ©2007 Micron Technology, Inc. All rights reserved.
32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Timing Diagrams
Figure 40: Burst WRITE Operation
Note: Nondefault BCR settings for burst WRITE operation: latency code 2 (3 clocks); WAIT active
LOW; WAIT asserted.
A[20:0] VIH
VIL
ADV# VIH
VIL
CE# VIH
VIL
OE# VIH
VIL
WE# VIH
VIL
WAIT
DQ[15:0]
VOH
VOL
CLK VIH
VIL
VIH
VIL
tCLK tKP
tSP tHD
tCSP
tCEM
D[3]D[2]D[1]D[0]
Valid address
tHD
tSP
tHD
tSP
tHD
tSP
High-Z High-Z
LB#/UB# VIH
VIL
tSP tHD
tHD
Don’t Care
WRITE burst identified
(WE# = LOW)
tCBPH
tKHTL tHZ
tCEW
tKP tKHKL
PDF: 09005aef82832fa2/Source: 09005aef82832f5f Micron Technology, Inc., reserves the right to change products or specifica tions without notice.
32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN 52 ©2007 Micron Technology, Inc. All rights reserved.
32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Timing Diagrams
Figure 41: Output Delay in Continuous Burst WRITE with BCR[8] = 0 for End-of-Row Condition
Notes: 1. Nondefault BCR settings for continuous burst WRITE, BCR[ 8] = 0; WAIT active LOW; WAIT
asserted during delay. Do not cross row bo undaries with fixe d latency.
2. CE# must not remain LOW longer than tCEM.
3. WAIT asserts anywhere from LC to 2LC cycles. LC = latency code (BCR[13:11]).
4. Taking CE# HIGH or ADV# LOW on the start-of-row cycle will abort the burst and not write
the start-of-row data. Devices from different CellularRAM vendors can assert WAIT so that
the start-of-row data is input just before (as shown) or just after WAIT asserts. This differ-
ence in behavior will not be noticed by controllers that monitor WAIT or that use WAIT to
abort on the start-of-row input cycle.
A[20:0] VIH
VIL
ADV# VIH
VIL
CE# VIH
VIL
OE#
VIH
VIL
WE#
VIH
VIL
WAIT
DQ[15:0]
VOH
VOL
CLK VIH
VIL
VIH
VIL
tKHTL tKHTL
tCLK
tSP tHD
Valid input Valid input
Start of row
(A[6:0] = 00h)
(Note 4)
End of row
(A[6:0] = 7Fh)
Note 3
Note 4
Valid input Valid input
Don’t Care
VIH
VIL
LB#/UB#
PDF: 09005aef82832fa2/Source: 09005aef82832f5f Micron Technology, Inc., reserves the right to change products or specifica tions without notice.
32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN 53 ©2007 Micron Technology, Inc. All rights reserved.
32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Timing Diagrams
Figure 42: Burst WRITE Followed by Burst READ
Notes: 1. Nondefault BCR settings for burst WRITE followed by burst READ: latency code 2 (3 clocks);
WAIT active LOW; WAIT assert ed during delay.
2. When co nfigured for synchr onous mode (BCR[15] = 0), a refresh opportunity must be pro-
vided every tCEM. A refresh opportunity is satisfied by either of the following two condi-
tions: clocked CE# HIGH or CE# HIGH for greater than 15ns. Note that the CellularRAM
Workgroup 1.0 specification requires CE# to be clocked HIGH to terminate the burst.
A[20:0] VIH
VIL
ADV# VIH
VIL
CE# VIH
VIL
OE# VIH
VIL
WE# VIH
VIL
WAIT
DQ[15:0]
in/out
VOH
VOL
CLK VIH
VIL
VIH
VIL
tCLK
tSP
tSP tHD
tCSP
D[3]D[2]D[1]
D[0]
Valid
address
tHD
tSP
tHD
tSP
tHD
Valid
address
tABA
tCSP
tCSP
tOHZ
tKOH
Valid
output
Valid
output Valid
output
Valid
output
High-Z
High-Z VOH
VOL
LB#/UB# VIH
VIL
tHD
tSP tHD
tSP
tHD
tSP
tHD
High-Z
Undefined
Don’t Care
tBOE
tCBPH
2
High-Z
tSP
tHD
tACLK
PDF: 09005aef82832fa2/Source: 09005aef82832f5f Micron Technology, Inc., reserves the right to change products or specifica tions without notice.
32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN 54 ©2007 Micron Technology, Inc. All rights reserved.
32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Timing Diagrams
Figure 43: Asynchronous WRITE Followed by Burst READ
Notes: 1. Nondefault BCR settings for asynchronous WRITE followed by burst READ: latency code 2 (3
clocks); WAIT active LOW; WAIT asserted during delay.
2. When co nfigured for synchr onous mode (BCR[15] = 0), a refresh opportunity must be pro-
vided every tCEM. A refresh opportunity is satisfied by either of the following two condi-
tions: clocked CE# HIGH or CE# HIGH for greater than 15ns. Note that the CellularRAM
Workgroup 1.0 specification requires CE# to be clocked HIGH to terminate the burst.
tCLK
tSP tHD
tSP tHD
Valid
address
tOHZ
tKOH
tACLK
High-Z
High-Z
tAVS tAVH tAW tWR
tVP tVS
tCKA
A[20:0] VIH
VIL
ADV# VIH
VIL
OE# VIH
VIL
WE# VIH
VIL
WAIT
DQ[15:0]
in/out
VOH
VOL
CLK VIH
VIL
VIH
VIL
VOH
VOL
CE# VIH
VIL
LB#/UB# VIH
VIL
tCW
tWPH
tAS
tAS
tWP
tWC
tDH tDW
Data Data
High-Z
tCVS tSP
tCEW
tSP tHD
tCSP
tWC
tWC
tBW
tWHZ
Valid
output Valid
output Valid
output
Valid
output
Don’t Care Undefined
tABA
tBOE
tCBPH2
tVPH
Valid
address
Valid
address
PDF: 09005aef82832fa2/Source: 09005aef82832f5f Micron Technology, Inc., reserves the right to change products or specifica tions without notice.
32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN 55 ©2007 Micron Technology, Inc. All rights reserved.
32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Timing Diagrams
Figure 44: Asynchronous WRITE Followed by Burst READ with ADV# LOW
Notes: 1. Nondefault BCR settings for asynchronous WRITE followed by burst READ: latency code 2 (3
clocks); WAIT active LOW; WAIT asserted during delay.
2. When co nfigured for synchr onous mode (BCR[15] = 0), a refresh opportunity must be pro-
vided every tCEM. A refresh opportunity is satisfied by either of these conditions: clocked
CE# HIGH or CE# HIGH for greater than 15ns. Note that the CellularRAM Workgroup 1.0
specification requires CE# to be clocked HIGH to terminate the burst.
tCLK
tSP tHD
tSP tHD
Valid
address
tOHZ
tKOH
tACLK
High-Z
High-Z
tAVS tAVH tAW tWR
tVP tVS
tCKA
A[20:0] VIH
VIL
ADV# VIH
VIL
OE# VIH
VIL
WE# VIH
VIL
WAIT
DQ[15:0]
in/out
VOH
VOL
CLK VIH
VIL
VIH
VIL
VOH
VOL
CE# VIH
VIL
LB#/UB# VIH
VIL
tCW
tWPH
tAS
tAS
tWP
tWC
tDH tDW
Data Data
High-Z
tCVS tSP
tCEW
tSP tHD
tCSP
tWC
tWC
tBW
tWHZ
Valid
output Valid
output Valid
output
Valid
output
Don’t Care Undefined
tABA
tBOE
tCBPH2
tVPH
Valid
address
Valid
address
PDF: 09005aef82832fa2/Source: 09005aef82832f5f Micron Technology, Inc., reserves the right to change products or specifica tions without notice.
32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN 56 ©2007 Micron Technology, Inc. All rights reserved.
32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Timing Diagrams
Figure 45: Burst READ Followed by Asynchronous WRITE (WE#-Controlled)
Note: When configured for synchronous mode (BCR[15] = 0), a refresh opportunity must be pro-
vided every tCEM. A refresh opportunity is satisfied by either of the fo ll owi ng two condi-
tions: clocked CE# HIGH or CE# HIGH for greater than 15ns. Note that CellularRAM
Workgroup specification 1.0 requires CE# to be clocked HIGH to terminate the burs t.
A[20:0]
VIH
VIL
ADV#
VIH
VIL
CE#
VIH
VIL
OE#
VIH
VIL
WE#
VIH
VIL
WAIT
DQ[15:0]
VOH
VOL
CLK
VIH
VIL
VOH
VOL
tSP
tCLK
tACLK
tCEW
tHD
tABA
tAW
tCW
tWR
Valid output
Valid address
High-Z
tKOH tDW
tOHZ
tSP tHD
LB#/UB#
VIH
VIL
tCSP
High-Z
tOLZ
tHD tWP tWPH
tAS
tDH
tHZ
tBW
tSP
tHZ
tHD
tSP
Undefined
Don’t Care
READ burst identified
(WE# = HIGH)
tWC
tKHTL
Valid address
Valid input
High-Z
tCEW
tCBPH
1
tBOE
PDF: 09005aef82832fa2/Source: 09005aef82832f5f Micron Technology, Inc., reserves the right to change products or specifica tions without notice.
32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN 57 ©2007 Micron Technology, Inc. All rights reserved.
32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Timing Diagrams
Figure 46: Burst READ Followed by Asynchronous WRITE Using ADV#
Note: When configured for synchronous mode (BCR[15] = 0), a refresh opportunity must be pro-
vided every tCEM. A refresh opportunity is satisfied by either of the fo ll owi ng two condi-
tions: clocked CE# HIGH or CE# HIGH for greater than 15ns. Note that CellularRAM
Workgroup specification 1.0 requires CE# to be clocked HIGH to terminate the burs t.
A[20:0]
V
IH
V
IL
ADV#
V
IH
V
IL
CE#
V
IH
V
IL
OE#
V
IH
V
IL
WE#
V
IH
V
IL
WAIT
DQ[15:0]
V
OH
V
OL
CLK
V
IH
V
IL
V
OH
V
OL
tSP
tCLK
tCEW
tHD
tVPH tVS
tAVS tAVH
tAW
tCW
Valid output
Valid address
High-Z
tKOH tDW
tOHZ
tSP tHD tVP
LB#/UB#
V
IH
V
IL
tCSP
High-Z
tOLZ
tHD tWP tWPH
tAS
tDH
tBW
tSP
tHZ
tHD
tSP
Undefined
Don’t Care
READ burst identified
(WE# = HIGH)
Valid address
Valid input
High-Z
tCEW tHZ
tCBPH1
tACLK
tBOE
tAS
tKHTL
tABA
PDF: 09005aef82832fa2/Source: 09005aef82832f5f Micron Technology, Inc., reserves the right to change products or specifica tions without notice.
32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN 58 ©2007 Micron Technology, Inc. All rights reserved.
32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Timing Diagrams
Figure 47: Asynchronous WRITE Followed by Asynchronous READ with ADV# LOW
Note: When configured for synchronous mode (BCR[15] = 0), CE# must remain HIGH for at least
5ns (tCPH) to schedule the appropriate internal refresh operation. Otherwise, tCPH is only
required after CE#-controlled WRITEs.
Valid address Valid address
A[20:0] VIH
VIL
ADV#
VIH
VIL
OE#
WE#
WAIT
DQ[15:0]
in/out
VOH
VOL
VIH
VIL
VOH
VOL
CE#
LB#/UB# VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
tCW
tWPH
tWP
tWC
tDH tDW
tHZ
Data
tHZ
High-Z
Valid address
tAA
tBHZ
tCPH1tCO
Valid output
High-Z
tOE
tOLZ
tLZ
tBLZ
tOHZ
tHZ
tAW tWR
tBW
Don’t Care Undefined
Data
PDF: 09005aef82832fa2/Source: 09005aef82832f5f Micron Technology, Inc., reserves the right to change products or specifica tions without notice.
32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN 59 ©2007 Micron Technology, Inc. All rights reserved.
32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Timing Diagrams
Figure 48: Asynchronous WRITE Followed by Asynchronous READ
Note: When configured for synchronous mode (BCR[15] = 0), CE# must remain HIGH for at least
5ns (tCPH) to schedule the appropriate internal refresh operation. Otherwise, tCPH is only
required after CE#-controlled WRITEs.
Valid address Valid address
tAVS tAVH
tVPH tVP tVS
A[20:0] VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
ADV#
OE#
WE#
WAIT
DQ[15:0]
in/out
VOH
VOL
VIH
VIL
VOH
VOL
CE#
LB#/UB#
tVP
tAVH
tCW
tWPH
tAS tWP
tWC
tDH tDW
Data DataHigh-Z
Valid address
tAA
tBHZ
tAADV
tCPH1tCO
Valid outputHigh-Z
tCVS
tOLZ
tLZ
tAS
tBLZ
tOHZ
tHZ
tAW tWR
tBW
Undefined
Don’t Care
tOE
tAVS
tCVS
®
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900
prodmktg@micron.com www.micron.com Cu stomer Comment Line: 800-932-4992
Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc. CellularRAM is a trademark of Micron
Technology, Inc., inside the U.S. and a trademark of Qimonda AG outside the U.S. All other trademarks are the property of
their respective owners. This data sheet contains minimum and maximum limits specified over the complete power supply
and temperature range for production devices. Although considered fi na l, t hes e specifications are subject to change, as fur-
ther product development and data characterization sometimes occur.
32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Package Dimensions
PDF: 09005aef82832fa2/Source: 09005aef82832f5f Micron Technology, Inc., reserves the right to change products or specifica tions without notice.
32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN 60 ©2007 Micron Technology, Inc. All rights reserved.
Package Dimensions
Figure 49: 54-Ball VFBGA
Notes: 1. All dimensions are in millimeters.
2. Package width and length do not include mold protrusion; allowable mold protrusion is
0.25mm per side.
3. The MT45W2MW16 BGB uses “green” packaging.
Ball A1 ID
0.70 ±0.05
Seating
plane
0.10 A
A
1.00 MAX
Ball A6
Ball A1
Ball A1 ID
0.75
TYP
0.75 TYP
1.875
3.75
6.00 ±0.10
3.00 ±0.05
Dimensions apply
to solder balls
post-reflow.
Pre-reflow ball
diameter is 0.35
on a 0.30 SMD
ball pad.
54X Ø0.37
Solder ball material:
96.5% Sn, 3% Ag, 0.5% Cu
Mold compound: epoxy novolac
Substrate material: plastic laminate
6.00
3.00
4.00 ±0.05
8.00 ±0.10
PDF: 09005aef82832fa2/Source: 09005aef82832f5f Micron Technology, Inc., reserves the right to change products or specifica tions without notice.
32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN 61 ©2007 Micron Technology, Inc. All rights reserved.
32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Revision History
Revision History
Rev. E, Production . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .09/08
• “Options” on page 1: Added “Low Power: L” to table.
• Table 2, “Bus Operations: Asynchronous Mode,” on page8: Changed note 1 from
“CLK must be low...” to “CLK must be static HIGH or LOW...”
• Table 3, “Bus Operations: Burst Mode,” on page9: Changed note 1 from “CLK must
be low...” to “CLK must be static HIGH or LOW...”
• Figure 26: “AC Input/Output Reference Waveform,” on page 35: Changed “VCC” to
“VCCQ” in two instances in the diagram ; re vis ed note 2 to read, “Input timing begins
at VCCQ/2.”
• Figure 32: “Single-Access Burst READ Operation,” on page 43: Changed symbol for
LB#/UB# from tCSP to tSP.
• Figure 33: “4-Word Burst READ Operation,” on page 44: Changed symbol for LB#/
UB# from tCSP to tSP.
• Figure 34: “READ Burst Suspend,” on page 45: Changed symbol for LB#/UB# from
tCSP to tSP.
Rev. D, Production . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .02/08
• Table 15, “Burst WRITE Cycle Timing Requirements,” on page 39: Corrected tCEM
parameter label from minimum to maximum.
Rev. C, Production . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .07/07
• Renumbered the notes in Table 12 on page 36.
• Replaced “‘” with “2” in the “Notes” column in Table 12 on page 36.
Rev. B, Production . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .05/07
• Changed revision status to Production.
• Removed “Contact factory” note from the “Options” section on page 1.
• Changed burst initial latency from “39ns” to “38.5ns” in the “Features” section on
page 1.
• Removed “...(contact factory)” from Figure 3 on page 10.
• Moved the “WAIT Polarity (BCR[10]) Default = WAIT Active HIGH” section to page 29.
• Changed A6 and A5 to “Ignored” and added the following text in Figure 24 on page 31:
“Setting is ignored (default 00b).”
Rev. A, Preliminary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .02/07
•Initial release.
