32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Features Async/Page/Burst CellularRAM(R) 1.0 Memory MT45W2MW16BGB Features Figure 1: * Single device supports asynchronous, page, and burst operations * Random access time: 70ns * VCC, VCCQ voltages - 1.7-1.95V VCC - 1.7-3.6V VCCQ * Page mode read access - 16-word page size - Interpage read access: 70ns - Intrapage read access: 20ns * Burst mode write access: continuous burst * Burst mode read access - 4, 8, or 16 words or continuous burst - MAX clock rate: 104 MHz (tCLK = 9.62ns) - Burst initial latency: 38.5ns (4 clocks) at 104 MHz - tACLK: 7ns at 104 MHz * Low power consumption - Asynchronous read: <20mA - Intrapage read: <15mA - Intrapage read initial access, burst read: (38.5ns [4 clocks] at 104 MHz) <40mA - Continuous burst read: <25mA - Standby: <110A - Deep power-down: <10A (TYP at 25C) * Low-power features - Temperature-compensated refresh (TCR) - On-chip temperature sensor - Partial-array refresh (PAR) - Deep power-down (DPD) mode Options PDF: 09005aef82832fa2/Source: 09005aef82832f5f 32mb_burst_cr1_0_p24z_1.fm - Rev. E 9/08 EN 1 2 3 4 5 6 A LB# OE# A0 A1 A2 CRE B DQ8 UB# A3 A4 CE# DQ0 C DQ9 DQ10 A5 A6 DQ1 DQ2 D VSSQ DQ11 A17 A7 DQ3 VCC E VCCQ DQ12 NC A16 DQ4 VSS F DQ14 DQ13 A14 A15 DQ5 DQ6 G DQ15 A19 A12 A13 WE# DQ7 H A18 A8 A9 A10 A11 A20 J WAIT CLK ADV# NC NC NC Top view (Ball down) Options (continued) Designator * Standby power - Standard * Low power * Operating temperature range - Wireless (-30C to +85C) - Industrial (-40C to +85C) Designator * Configuration - 2 Meg x 16 * Package - 54-ball VFBGA ("green") * Access time - 70ns * Frequency - 80 MHz - 104 MHz 54-Ball VFBGA Ball Assignment MT45W2MW16B None L WT1 IT2 Notes: 1. -30C exceeds the CellularRAM Workgroup 1.0 specification of -25C. 2. Contact factory for availability. GB -70 Part Number Example: 8 1 MT45W2MW16BGB-701WT 1 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice. 32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Table of Contents Table of Contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Ball Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Part Numbering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Valid Part Number Combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Device Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Power-Up Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Bus Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Asynchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Page Mode READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Burst Mode Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Mixed-Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 WAIT Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 LB#/UB# Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Low-Power Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Standby Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Temperature-Compensated Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Partial-Array Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Deep Power-Down Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Access Using CRE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Software Access to the Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Bus Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Burst Length (BCR[2:0]) Default = Continuous Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Burst Wrap (BCR[3]) Default = Burst No Wrap (Within Burst Length) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Output Impedance (BCR[5]) Default = Outputs Use Full Drive Strength . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 WAIT Configuration (BCR[8]) Default = WAIT Transitions One Clock Before Data Valid/Invalid . . . . . . . . .28 WAIT Polarity (BCR[10]) Default = WAIT Active HIGH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Latency Counter (BCR[13:11]) Default = Three-Clock Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Operating Mode (BCR[15]) Default = Asynchronous Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Refresh Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Partial-Array Refresh (RCR[2:0]) Default = Full Array Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Deep Power-Down (RCR[4]) Default = DPD Disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Page Mode Operation (RCR[7]) Default = Disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Maximum and Typical Standby Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Timing Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Timing Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 PDF: 09005aef82832fa2/Source: 09005aef82832f5f 32mb_burst_c1_0_p24zTOC.fm - Rev. E 9/08 EN 2 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory List of Figures List of Figures Figure 1: Figure 2: Figure 3: Figure 4: Figure 5: Figure 6: Figure 7: Figure 8: Figure 9: Figure 10: Figure 11: Figure 12: Figure 13: Figure 14: Figure 15: Figure 16: Figure 17: Figure 18: Figure 19: Figure 20: Figure 21: Figure 22: Figure 23: Figure 24: Figure 25: Figure 26: Figure 27: Figure 28: Figure 29: Figure 30: Figure 31: Figure 32: Figure 33: Figure 34: Figure 35: Figure 36: Figure 37: Figure 38: Figure 39: Figure 40: Figure 41: Figure 42: Figure 43: Figure 44: Figure 45: Figure 46: Figure 47: Figure 48: Figure 49: 54-Ball VFBGA Ball Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Functional Block Diagram - 2 Meg x 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Part Number Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Power-Up Initialization Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 READ Operation (ADV = LOW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 WRITE Operation (ADV = LOW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Page Mode READ Operation (ADV = LOW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Burst Mode READ (4-Word Burst) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Burst Mode WRITE (4-Word Burst) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Wired-OR WAIT Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Refresh Collision During READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Refresh Collision During WRITE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Asynchronous Mode Configuration Register WRITE Followed by READ ARRAY Operation . . . . . .20 Synchronous Mode Configuration Register WRITE Followed by READ ARRAY Operation . . . . . . .21 Asynchronous Mode Configuration Register READ Followed by READ ARRAY Operation . . . . . . .22 Synchronous Mode Configuration Register READ Followed by READ ARRAY Operation . . . . . . . .23 Load Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Read Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Bus Configuration Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 WAIT Configuration (BCR[8] = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 WAIT Configuration (BCR[8] = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 WAIT Configuration During Burst Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Latency Counter (Variable Latency, No Refresh Collision) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Refresh Configuration Register Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Typical Refresh Current vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 AC Input/Output Reference Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Output Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Initialization Period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 Asynchronous READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Asynchronous READ Using ADV# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 Page Mode READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 Single-Access Burst READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 4-Word Burst READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 READ Burst Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 Output Delay in Continuous Burst READ with BCR[8] = 0 for End-of-Row Condition . . . . . . . . . . .46 CE#-Controlled Asynchronous WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 LB#/UB#-Controlled Asynchronous WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 WE#-Controlled Asynchronous WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Asynchronous WRITE Using ADV# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 Burst WRITE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 Output Delay in Continuous Burst WRITE with BCR[8] = 0 for End-of-Row Condition . . . . . . . . . .52 Burst WRITE Followed by Burst READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 Asynchronous WRITE Followed by Burst READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 Asynchronous WRITE Followed by Burst READ with ADV# LOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 Burst READ Followed by Asynchronous WRITE (WE#-Controlled) . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 Burst READ Followed by Asynchronous WRITE Using ADV# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 Asynchronous WRITE Followed by Asynchronous READ with ADV# LOW . . . . . . . . . . . . . . . . . . . . .58 Asynchronous WRITE Followed by Asynchronous READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 54-Ball VFBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 PDF: 09005aef82832fa2/Source: 09005aef82832f5f 32mb_burst_c1_0_p24zLOF.fm - Rev. E 9/08 EN 3 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory List of Tables List of Tables Table 1: Table 2: Table 3: Table 4: Table 5: Table 6: Table 7: Table 8: Table 9: Table 10: Table 11: Table 12: Table 13: Table 14: Table 15: Table 16: VFBGA Ball Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Bus Operations: Asynchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Bus Operations: Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Sequence and Burst Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Latency Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 32Mb Address Patterns for PAR (RCR[4] = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Electrical Characteristics and Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Partial-Array Refresh Specifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Deep Power-Down Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Asynchronous READ Cycle Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Burst READ Cycle Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 Asynchronous WRITE Cycle Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 Burst WRITE Cycle Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 Initialization Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 PDF: 09005aef82832fa2/Source: 09005aef82832f5f 32mb_burst_c1_0_p24zLOT.fm - Rev. E 9/08 EN 4 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory General Description General Description Micron(R) CellularRAM(R) is a high-speed, CMOS PSRAM memory device developed for low-power, portable applications. The MT45W2MW16BGB is a 32Mb DRAM core device organized as 2 Meg x 16 bits. This device includes an industry-standard burst mode Flash interface that dramatically increases READ/WRITE bandwidth compared with other low-power SRAM or pseudo-SRAM (PSRAM) offerings. For seamless operation on a burst Flash bus, CellularRAM products incorporate a transparent self refresh mechanism. The hidden refresh requires no additional support from the system memory controller and has no significant impact on device READ/WRITE performance. Two user-accessible control registers define device operation. The bus configuration register (BCR) defines how the CellularRAM device interacts with the system memory bus and is nearly identical to its counterpart on burst mode Flash devices. The refresh configuration register (RCR) is used to control how refresh is performed on the DRAM array. These registers are automatically loaded with default settings during power-up and can be updated anytime during normal operation. Special attention has been focused on standby current consumption during self refresh. CellularRAM products include three system-accessible mechanisms to minimize standby current. Partial-array refresh (PAR) limits refresh to only that part of the DRAM array that contains essential data. Temperature-compensated refresh (TCR) uses an onchip sensor to adjust the refresh rate to match the device temperature. The refresh rate decreases at lower temperatures to minimize current consumption during standby. Deep power-down (DPD) halts the REFRESH operation altogether and is used when no vital information is stored in the device. These three refresh mechanisms are accessed through the RCR. PDF: 09005aef82832fa2/Source: 09005aef82832f5f 32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN 5 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Functional Block Diagram Functional Block Diagram Figure 2: Functional Block Diagram - 2 Meg x 16 A[20:0] Address decode logic 2,048K x 16 DRAM memory array Input/ output MUX and buffers DQ[7:0] DQ[15:8] Refresh configuration register (RCR) Bus configuration register (BCR) CE# WE# OE# CLK ADV# CRE WAIT LB# UB# Control logic Note: PDF: 09005aef82832fa2/Source: 09005aef82832f5f 32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN Functional block diagrams illustrate simplified device operation. See ball description table, bus operations tables, and timing diagrams for detailed information. 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Ball Descriptions Ball Descriptions Table 1: VFBGA Ball Descriptions VFBGA Assignment Symbol Type Description H6, G2, H1, D3, E4, F4, F3, G4, G3, H5, H4, H3, H2, D4, C4, C3, B4, B3, A5, A4, A3 J3 A[20:0] Input Address inputs: Inputs for addresses during READ and WRITE operations. Addresses are internally latched during READ and WRITE cycles. The address lines are also used to define the value to be loaded into the BCR or the RCR. ADV# Input B5 CE# Input J2 CLK Input A6 CRE Input A1 A2 LB# OE# Input Input B2 G5 UB# WE# Input Input G1, F1, F2, E2, D2, C2, C1, B1, G6, F6, F5, E5, D5, C6, C5, B6 J1 DQ[15:0] Input/ Output Address valid: Indicates that a valid address is present on the address inputs. Addresses can be latched on the rising edge of ADV# during asynchronous READ and WRITE operations. ADV# can be held LOW during asynchronous READ and WRITE operations. Chip enable: Activates the device when LOW. When CE# is HIGH, the device is disabled and goes into standby or deep power-down mode. Clock: Synchronizes the memory to the system operating frequency during synchronous operations. When configured for synchronous operation, the address is latched on the first rising CLK edge when ADV# is active. CLK must be static LOW or HIGH during asynchronous access READ and WRITE operations and during PAGE READ ACCESS operations. Configuration register enable: When CRE is HIGH, WRITE operations load the RCR or BCR, and READ operations either access the RCR or the BCR. Lower byte enable: DQ[7:0]. Output enable: Enables the output buffers when LOW. When OE# is HIGH, the output buffers are disabled. Upper byte enable: DQ[15:8]. WRITE enable: Determines whether a given cycle is a WRITE cycle. If WE# is LOW, the cycle is a WRITE to either a configuration register or the memory array. Data inputs/outputs. WAIT Output E3, J4, J5, J6 D6 E1 E6 D1 NC VCC VCCQ VSS VSSQ - Supply Supply Supply Supply Note: PDF: 09005aef82832fa2/Source: 09005aef82832f5f 32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN Wait: Provides data-valid feedback during burst READ and WRITE operations. The signal is gated by CE#. WAIT is used to arbitrate collisions between REFRESH and READ/WRITE operations. WAIT is asserted when a burst crosses a row boundary. WAIT is also used to mask the delay associated with opening a new internal page. WAIT is asserted and should be ignored during asynchronous and page mode operations. WAIT is High-Z when CE# is HIGH. Not internally connected. Device power supply (1.7-1.95V): Power supply for device core operation. I/O power supply (1.7-3.6V): Power supply for input/output buffers. VSS must be connected to ground. VSSQ must be connected to ground. The CLK and ADV# inputs can be tied to VSS if the device is always operating in asynchronous or page mode. WAIT will be asserted, but should be ignored during asynchronous and page mode operations. 7 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Bus Operations Bus Operations Table 2: Bus Operations: Asynchronous Mode Mode Power CLK1 ADV# CE# OE# WE# CRE LB#/ UB# WAIT2 DQ[15:0]3 Notes READ WRITE Standby No operation Configuration register WRITE Configuration register READ DPD Active Active Standby Idle Active L L L L L L L X X L L L H L L L X X X H H L X X L L L L L H L L X X X Low-Z Low-Z High-Z Low-Z Low-Z Data-out Data-in High-Z X High-Z 4 4 5, 6 4, 6 Active L L L H H H X Low-Z Deep power-down L X H X X X X Notes: PDF: 09005aef82832fa2/Source: 09005aef82832f5f 32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN Config. reg. out High-Z High-Z 8 7 1. CLK must be static (HIGH or LOW) during asynchronous READ and asynchronous WRITE modes and to achieve standby power during standby and DPD modes. CLK must be static (HIGH or LOW) during burst suspend. 2. The WAIT polarity is configured through the bus configuration register (BCR[10]). 3. When LB# and UB# are in select mode (LOW), DQ[15:0] are affected. When only LB# is in select mode, DQ[7:0] are affected. When only UB# is in the select mode, DQ[15:8] are affected. 4. The device will consume active power in this mode whenever addresses are changed. 5. When the device is in standby mode, address inputs and data inputs/outputs are internally isolated from any external influence. 6. VIN = VCCQ or 0V; all device balls must be static (unswitched) to achieve standby current. 7. DPD is maintained until RCR is reconfigured. 8. CRE-controlled reading of the configuration register is supported for this device, though it is not an official CellularRAM 1.0 feature. 8 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Bus Operations Table 3: Bus Operations: Burst Mode Mode Power CLK1 ADV# CE# OE# WE# CRE LB#/ UB# WAIT2 DQ[15:0]3 Notes Asynchronous READ Asynchronous WRITE Standby No operation Initial burst READ Initial burst WRITE Burst continue Active L L L L H L L Low-Z Data-out 4 Active L L L X L L L Low-Z Data-in 4 Standby Idle Active L L X X L H L L X X X X X H L L L X X L High-Z Low-Z Low-Z High-Z X X 5, 6 4, 6 4, 8 Active L L H L L X Low-Z X 4, 8 Active H L X X X L Low-Z 4, 8 X L L L H H X L L H X X Low-Z Low-Z Data-in or data-out High-Z High-Z L L H H H X X H X X X X Low-Z Config. reg. out Z High-Z High-Z Burst suspend Configuration register WRITE Configuration register READ DPD Active Active X Active Deep power-down Notes: PDF: 09005aef82832fa2/Source: 09005aef82832f5f 32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN L 4, 8 8 8, 9 7 1. CLK must be static (HIGH or LOW) during asynchronous READ and asynchronous WRITE modes and to achieve standby power during standby and DPD modes. CLK must be static (HIGH or LOW) during burst suspend. 2. The WAIT polarity is configured through the bus configuration register (BCR[10]). 3. When LB# and UB# are in select mode (LOW), DQ[15:0] are affected. When only LB# is in select mode, DQ[7:0] are affected. When only UB# is in the select mode, DQ[15:8] are affected. 4. The device will consume active power in this mode whenever addresses are changed. 5. When the device is in standby mode, address inputs and data inputs/outputs are internally isolated from any external influence. 6. VIN = VCCQ or 0V; all device balls must be static (unswitched) to achieve standby current. 7. DPD is maintained until RCR is reconfigured. 8. Burst mode operation is initialized through the bus configuration register (BCR[15]). 9. This device supports CRE-controlled configuration register READs. This feature is not an official CellularRAM 1.0 feature. 9 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Part Numbering Information Part Numbering Information Micron CellularRAM devices are available in several configurations and densities. Figure 3: Part Number Chart MT 45 W 2M W 16 B GB -70 8 WT ES Production status Micron Technology Blank = Production Product family ES = Engineering sample 45 = PSRAM/CellularRAM memory MS = Mechanical sample Operating core voltage Operating temperature W = 1.7V-1.95V WT = -30C to +85C (see note 1) IT = -40C to +85C Address locations Standby power options M = Megabits Blank = Standard Operating voltage Low power = L W = 1.7-3.6V Frequency Bus configuration 8 = 80 MHz 16 = x16 1 = 104 MHz READ/WRITE operation mode Access/cycle time B = Asynchronous/page/burst 70 = 70ns Package codes GB = 54-ball VFBGA "green" (6 x 9 grid, 0.75mm pitch, 6.0mm x 8.0mm x 1.0mm) Note: -30C exceeds the CellularRAM Workgroup 1.0 specification of -25C. Valid Part Number Combinations After building the part number from the part numbering chart, visit the Micron Web site at www.micron.com/psram to verify that the part number is offered and valid. If the device required is not on this list, contact the factory. Device Marking Due to the size of the package, the Micron-standard part number is not printed on the top of the device. Instead, an abbreviated device mark consisting of a five-digit alphanumeric code is used. The abbreviated device marks are cross-referenced to the Micron part numbers at the FBGA Part Marking Decoder site, http://www.micron.com/ decoder. To view the location of the abbreviated mark on the device, refer to customer service note, CSN-11, "Product Mark/Label," at www.micron.com/csn. PDF: 09005aef82832fa2/Source: 09005aef82832f5f 32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN 10 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Functional Description Functional Description In general, the MT45W2MW16BGB devices are high-density alternatives to SRAM and PSRAM products, popular in low-power, portable applications. The MT45W2MW16BGB contains a 33,554,432-bit DRAM core organized as 2,097,152 addresses by 16 bits. This device implements the same high-speed bus interface found on burst mode Flash products. The CellularRAM bus interface supports both asynchronous and burst mode transfers. Page mode accesses are also included as a bandwidth-enhancing extension to the asynchronous READ protocol. Power-Up Initialization CellularRAM products include an on-chip voltage sensor used to launch the power-up initialization process. Initialization will configure the BCR and the RCR with their default settings (see Figure 19 on page 26 and Figure 24 on page 31). VCC and VCCQ must be applied simultaneously. When they reach a stable level at or above 1.7V, the device will require 150s to complete its self-initialization process. During the initialization period, CE# should remain HIGH. When initialization is complete, the device is ready for normal operation. Figure 4: Power-Up Initialization Timing Vcc = 1.7V Vcc VccQ tPU > 150s Device ready for Device initialization normal operation Bus Operating Modes The MT45W2MW16BGB CellularRAM products incorporate a burst mode interface found on Flash products targeting low-power, wireless applications. This bus interface supports asynchronous, page mode, and burst mode READ and WRITE transfers. The specific interface supported is defined by the value loaded into the bus configuration register. Page mode is controlled by the refresh configuration register (RCR[7]). Asynchronous Mode CellularRAM products power up in the asynchronous operating mode. This mode uses the industry-standard SRAM control bus (CE#, OE#, WE#, and LB#/UB#). READ operations are initiated by bringing CE#, OE#, and LB#/UB# LOW while keeping WE# HIGH (see Figure 5 on page 12). Valid data will be driven out of the I/Os after the specified access time has elapsed. WRITE operations occur when CE#, WE#, and LB#/UB# are driven LOW (see Figure 6 on page 12). During asynchronous WRITE operations, the OE# level is a "Don't Care," and WE# will override OE#. The data to be written is latched on the rising edge of CE#, WE#, or LB#/UB#, whichever occurs first. Asynchronous operations (page mode disabled) either can use the ADV input to latch the address, or ADV can be driven LOW during the entire READ/WRITE operation. During asynchronous operation, the CLK input must be held static LOW or HIGH. WAIT will be driven while the device is enabled, and its state should be ignored. WE# LOW time must be limited to tCEM. PDF: 09005aef82832fa2/Source: 09005aef82832f5f 32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN 11 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Bus Operating Modes Figure 5: READ Operation (ADV = LOW) CE# OE# WE# Address Valid address Valid data Data LB#/UB# tRC = READ cycle time Don't Care Note: Figure 6: ADV must remain LOW for page mode operation. WRITE Operation (ADV = LOW) CE# OE# <tCEM WE# Address Data Valid address Valid data LB#/UB# tWC = WRITE cycle time Don't Care PDF: 09005aef82832fa2/Source: 09005aef82832f5f 32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN 12 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Bus Operating Modes Page Mode READ Operation Page mode is a performance-enhancing extension to the legacy asynchronous READ operation. In page-mode-capable products, an initial asynchronous READ access is performed, and then adjacent addresses can be read quickly by simply changing the low-order address. Addresses A[3:0] are used to determine the members of the 16address CellularRAM page. Any change in addresses A[4] or higher will initiate a new tAA access time. Figure 7 on page 13 shows the timing for a page mode access. Page mode takes advantage of the fact that adjacent addresses can be read in a shorter period of time than random addresses. WRITE operations do not include comparable page mode functionality. During asynchronous page mode operation, the CLK input must be held static LOW or HIGH. CE# must be driven HIGH upon completion of a page mode access. WAIT will be driven while the device is enabled, and its state should be ignored. Page mode is enabled by setting RCR[7] to HIGH. ADV must be driven LOW during all page mode READ accesses. The CE# LOW time is limited by refresh considerations. CE# must not stay LOW longer than tCEM. Figure 7: Page Mode READ Operation (ADV = LOW) <tCEM CE# OE# WE# Address Address[0] tAA Data Address [1] Address [2] tAPA tAPA Address [3] tAPA D[0] D[1] D[2] D[3] LB#/UB# Don't Care Burst Mode Operation Burst mode operations enable high-speed synchronous READ and WRITE operations. Burst operations consist of a multiclock sequence that must be performed in an ordered fashion. After CE# goes LOW, the address to access is latched on the next rising edge of CLK that ADV# is LOW. During this first clock rising edge, WE# indicates whether the operation is going to be a READ (WE# = HIGH, Figure 8 on page 14) or WRITE (WE# = LOW, Figure 9 on page 15). The size of a burst can be specified in the BCR either as fixed-length or continuous. Fixed-length bursts consist of 4, 8, or 16 words. Continuous bursts have the ability to start at a specified address and burst through the entire memory. The latency count stored in the BCR defines the number of clock cycles that elapse before the initial data value is transferred between the processor and CellularRAM device. PDF: 09005aef82832fa2/Source: 09005aef82832f5f 32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN 13 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Bus Operating Modes The WAIT output will be asserted as soon as CE# goes LOW and will be de-asserted to indicate when data is to be transferred into (or out of) the memory. WAIT will again be asserted if the burst crosses the boundary between 128-word rows. After the CellularRAM device has restored the previous row's data and accessed the next row, WAIT will be deasserted and the burst can continue (see Figure 35 on page 46). The processor can access other devices without incurring the timing penalty of the initial latency for a new burst by suspending burst mode. Bursts are suspended by stopping CLK. CLK can be stopped HIGH or LOW. If another device will use the data bus while the burst is suspended, OE# should be taken HIGH to disable the CellularRAM outputs; otherwise, OE# can remain LOW. Note that the WAIT output will continue to be active, and, as a result, no other devices should directly share the WAIT connection to the controller. To continue the burst sequence, OE# is taken LOW, and then CLK is restarted after valid data is available on the bus. The CE# LOW time is limited by refresh considerations. CE# must not stay LOW longer than tCEM unless row boundaries are crossed at least every tCEM. If a burst suspension will cause CE# to remain LOW for longer than tCEM, CE# should be taken HIGH and the burst restarted with a new CE# LOW/ADV# LOW cycle. Figure 8: Burst Mode READ (4-Word Burst) CLK Valid address A[20:0] ADV# Latency code 2 (3 clocks) CE# OE# WE# WAIT DQ[15:0] D[0] D[1] D[2] D[3] LB#/UB# Don't Care READ burst identified (WE# = HIGH) Note: PDF: 09005aef82832fa2/Source: 09005aef82832f5f 32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN Undefined Nondefault BCR settings: latency code 2 (3 clocks); WAIT active LOW; WAIT asserted during delay. 14 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Bus Operating Modes Figure 9: Burst Mode WRITE (4-Word Burst) CLK A[20:0] Valid address ADV# Latency code 2 (3 clocks) CE# OE# WE# WAIT DQ[15:0] D[0] D[1] D[2] D[3] LB#/UB# WRITE burst identified (WE# = LOW) Note: PDF: 09005aef82832fa2/Source: 09005aef82832f5f 32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN Don't Care Nondefault BCR settings: latency code 2 (3 clocks); WAIT active LOW; WAIT asserted during delay. 15 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Bus Operating Modes Mixed-Mode Operation The device can support a combination of synchronous READ and asynchronous WRITE operations when the BCR is configured for synchronous operation. The asynchronous WRITE operation requires that the clock (CLK) be held static LOW or HIGH during the entire sequence. The ADV# signal can be used to latch the target address, or it can remain LOW during the entire WRITE operation. CE# must return HIGH when transitioning between mixed-mode operations. Note that the tCKA period is the same as a READ or WRITE cycle. This time is required to ensure adequate refresh. Mixed-mode operation facilitates a seamless interface to legacy burst mode Flash memory controllers (see Figure 43 on page 54). WAIT Operation The WAIT output on a CellularRAM device is typically connected to a shared, systemlevel WAIT signal (see Figure 10). The shared WAIT signal is used by the processor to coordinate transactions with multiple memories on the synchronous bus. Figure 10: Wired-OR WAIT Configuration CellularRAM WAIT External pull-up/ pull-down resistor READY Processor WAIT WAIT Other device Other device After a READ or WRITE operation has been initiated, WAIT goes active to indicate that the CellularRAM device requires additional time before data can be transferred. For READ operations, WAIT will remain active until valid data is output from the device. For WRITE operations, WAIT will indicate to the memory controller when data will be accepted into the CellularRAM device. When WAIT transitions to an inactive state, the data burst will progress on successive clock edges. During a burst cycle, CE# must remain asserted until the first data is valid. Bringing CE# HIGH during this initial latency may cause data corruption. The WAIT output also performs an arbitration role when a READ or WRITE operation is launched while an on-chip refresh is in progress. If a collision occurs, WAIT is asserted for additional clock cycles until the refresh has completed (see Figure 11 on page 17 and Figure 12 on page 18). When the REFRESH operation has completed, the READ or WRITE operation will continue normally. WAIT is also asserted when a continuous READ or WRITE burst crosses a row boundary. The WAIT assertion allows time for the new row to be accessed and permits any pending REFRESH operations to be performed. LB#/UB# Operation The LB# enable and UB# enable signals support byte-wide data transfers. During READ operations, the enabled byte(s) are driven onto the DQ. The DQ associated with a disabled byte are put into a High-Z state during a READ operation. During WRITE oper- PDF: 09005aef82832fa2/Source: 09005aef82832f5f 32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN 16 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Bus Operating Modes ations, any disabled bytes will not be transferred to the RAM array, and the internal value will remain unchanged. During an asynchronous WRITE cycle, the data to be written is latched on the rising edge of CE#, WE#, LB#, or UB#, whichever occurs first. When both the LB# and UB# are disabled (HIGH) during an operation, the device will disable the data bus from receiving or transmitting data. Although the device will seem to be deselected, it remains in an active mode as long as CE# remains LOW. Figure 11: CLK A[20:0] ADV# CE# OE# WE# LB#/UB# WAIT DQ[15:0] Refresh Collision During READ Operation VIH VIL VIH VIL Valid address VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VOH VOL High-Z VOH D[0] VOL Additional WAIT states inserted to allow refresh completion Note: PDF: 09005aef82832fa2/Source: 09005aef82832f5f 32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN D[1] D[2] D[3] Undefined Don't Care Nondefault BCR settings: latency code 2 (3 clocks); WAIT active LOW; WAIT asserted during delay. 17 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Bus Operating Modes Figure 12: CLK A[20:0] ADV# CE# OE# WE# LB#/UB# WAIT DQ[15:0] Refresh Collision During WRITE Operation VIH VIL VIH VIL Valid address VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VOH VOL High-Z VOH D[0] VOL Additional WAIT states inserted to allow refresh completion Note: PDF: 09005aef82832fa2/Source: 09005aef82832f5f 32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN D[1] D[2] D[3] Don't Care Nondefault BCR settings: latency code 2 (3 clocks); WAIT active LOW; WAIT asserted during delay. 18 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Low-Power Operation Low-Power Operation Standby Mode Operation During standby, the device current consumption is reduced to the level necessary to perform the DRAM REFRESH operation. Standby operation occurs when CE# is HIGH. The device will enter a reduced power state upon completion of a READ or WRITE operation or when the address and control inputs remain static for an extended period of time. This mode will continue until a change occurs to the address or control inputs. Temperature-Compensated Refresh Temperature-compensated refresh (TCR) allows for adequate refresh at different temperatures. This CellularRAM device includes an on-chip temperature sensor that continually adjusts the refresh rate according to the operating temperature. Partial-Array Refresh Partial-array refresh (PAR) restricts REFRESH operation to a portion of the total memory array. This feature enables the device to reduce standby current by refreshing only that part of the memory array required by the host system. The refresh options are full array, one-half array, one-quarter array, one-eighth array, or none of the array. The mapping of these partitions either can start at the beginning or the end of the address map (see Table 6 on page 32). READ and WRITE operations to address ranges receiving refresh will not be affected. Data stored in addresses not receiving refresh will become corrupted. When reenabling additional portions of the array, the new portions are available immediately upon writing to the RCR. Deep Power-Down Operation Deep power-down (DPD) operation disables all refresh-related activity. This mode is used if the system does not require the storage provided by the CellularRAM device. Any stored data will become corrupted when DPD is enabled. When refresh activity has been reenabled by rewriting the RCR, the CellularRAM device will require 150s to perform an initialization procedure before normal operations can resume. During this 150s period, the current consumption will be higher than the specified standby levels, but considerably lower than the active current specification. DPD cannot be enabled or disabled by writing to the RCR using the software access sequence; the RCR should be accessed using CRE instead. PDF: 09005aef82832fa2/Source: 09005aef82832f5f 32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN 19 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Configuration Registers Configuration Registers Two user-accessible configuration registers define the device operation. The bus configuration register (BCR) defines how the CellularRAM interacts with the system memory bus and is nearly identical to its counterpart on burst mode Flash devices. The refresh configuration register (RCR) is used to control how refresh is performed on the DRAM array. These registers are automatically loaded with default settings during power-up and can be updated any time the devices are operating in a standby state. Access Using CRE The configuration registers are loaded using either a synchronous or an asynchronous WRITE operation when the configuration register enable (CRE) input is HIGH (see Figure 13, and Figure 14 on page 21). When CRE is LOW, a READ or WRITE operation will access the memory array. The register values are placed on address pins A[19:0]. In an asynchronous WRITE, the values are latched into the configuration register on the rising edge of ADV#, CE#, or WE#, whichever occurs first; LB# and UB# are "Don't Care." The BCR is accessed when A[19] is HIGH; the RCR is accessed when A[19] is LOW. For READs, address inputs other than A19 are "Don't Care," and register bits 15:0 are output on DQ[15:0]. Figure 13: Asynchronous Mode Configuration Register WRITE Followed by READ ARRAY Operation Note: CLK A[20:0] (except A19) OPCODE tAVS Address tAVH Select control register A191 Address tAVS CRE tAVH tVPH ADV# tVP tCPH Initiate control register access CE# tCW OE# tWP Write address bus value to control register WE# LB#/UB# DQ[15:0] Valid data Don't Care Note: PDF: 09005aef82832fa2/Source: 09005aef82832f5f 32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN A[19] = LOW to load RCR, HIGH to load BCR. 20 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Configuration Registers Figure 14: Synchronous Mode Configuration Register WRITE Followed by READ ARRAY Operation CLK Latch control register value A[20:0] (except A19) Address OPCODE tHD tSP Latch control register address A192 Address tSP CRE tHD tSP ADV# tHD tCBPH tCSP 3 CE# OE# tSP WE# tHD LB#/UB# tCEW WAIT High-Z High-Z Valid data DQ[15:0] Don't Care Notes: PDF: 09005aef82832fa2/Source: 09005aef82832f5f 32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN 1. Nondefault BCR settings for CR WRITE in synchronous mode followed by READ ARRAY operation: latency code 2 (3 clocks); WAIT active LOW; WAIT asserted during delay. 2. A[19] = LOW to load RCR, HIGH to load BCR. 3. CE# must remain LOW to complete a burst-of-one WRITE. WAIT must be monitored--additional WAIT cycles caused by refresh collisions require a corresponding number of additional CE# LOW cycles. 21 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Configuration Registers Figure 15: Asynchronous Mode Configuration Register READ Followed by READ ARRAY Operation A[20:0] (except A19) Address tAVH tAVS Select register A[19]1 Address tAA tAVH tAVS CRE tAA tVPH ADV# tVP tAAVD tCBPH Initiate register access CE# tHZ tCO OE# tOHZ tOE tBA WE# tOLZ tLZ tBHZ LB#/UB# tLZ DQ[15:0] Valid CR Valid data Don't Care Note: PDF: 09005aef82832fa2/Source: 09005aef82832f5f 32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN Undefined A[19] = LOW to read RCR, HIGH to read BCR. 22 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Configuration Registers Figure 16: Synchronous Mode Configuration Register READ Followed by READ ARRAY Operation CLK Latch control register value A[20:0] (except A19) Address tSP Latch control register address A[19]2 Address tHD tSP CRE tHD tSP ADV# tHD tABA tCBPH3 tCSP CE# tHZ OE# tOHZ WE# tBOE tSP LB#/UB# tHD tCEW WAIT tOLZ tACLK High-Z High-Z Valid CR DQ[15:0] Valid data tKOH Don't Care Notes: PDF: 09005aef82832fa2/Source: 09005aef82832f5f 32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN Undefined 1. Nondefault BCR settings for synchronous mode register READ followed by READ ARRAY operation: latency code 2 (3 clocks); WAIT active LOW; WAIT asserted during delay. 2. A[19] = LOW to read RCR, HIGH to read BCR. 3. CE# must remain LOW to complete a burst-of-one READ. WAIT must be monitored--additional WAIT cycles caused by refresh collisions require a corresponding number of additional CE# LOW cycles. 23 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Configuration Registers Software Access to the Configuration Register Software access of the configuration registers uses a sequence of asynchronous READ and asynchronous WRITE operations. The contents of the configuration registers can be read or modified using the software sequence. The configuration registers are loaded using a four-step sequence consisting of two asynchronous READ operations followed by two asynchronous WRITE operations (see Figure 17). The READ sequence is virtually identical except that an asynchronous READ is performed during the fourth operation (see Figure 18 on page 25). The address used during all READ and WRITE operations is the highest address of the CellularRAM device being accessed (1FFFFFh for 32Mb); the content at this address is not changed by using this sequence. The data value presented during the third operation (WRITE) in the sequence defines whether the BCR or the RCR is to be accessed. If the data is 0000h, the sequence will access the RCR; if the data is 0001h, the sequence will access the BCR. During the fourth operation, DQ[15:0] transfer data into or out of bits 15-0 of the configuration registers. The use of the software sequence does not affect the ability to perform the standard (CRE-controlled) method of loading the configuration registers. However, the software nature of this access mechanism eliminates the need for the control register enable (CRE) pin. If the software mechanism is used, the CRE pin can simply be tied to VSS. The port line often used for CRE control purposes is no longer required. Software access of the RCR should not be used to enter or exit DPD. Figure 17: Load Configuration Register Address READ READ WRITE WRITE Address (MAX) Address (MAX) Address (MAX) Address (MAX) XXXXh XXXXh CE# OE# WE# LB#/UB# Data CR value in RCR: 0000h BCR: 0001h Note: PDF: 09005aef82832fa2/Source: 09005aef82832f5f 32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN Don't Care It is possible that the data stored at the highest memory location will be altered if the data at the falling edge of WE# is not 0000h or 0001h. 24 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Configuration Registers Figure 18: Read Configuration Register Address READ READ WRITE READ Address (MAX) Address (MAX) Address (MAX) Address (MAX) XXXXh XXXXh CE# OE# WE# LB#/UB# Data CR value out RCR: 0000h BCR: 0001h Note: PDF: 09005aef82832fa2/Source: 09005aef82832f5f 32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN Don't Care It is possible that the data stored at the highest memory location will be altered if the data at the falling edge of WE# is not 0000h or 0001h. 25 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Configuration Registers Bus Configuration Register The BCR defines how the CellularRAM device interacts with the system memory bus. Page mode operation is enabled by a bit contained in the RCR. Figure 19 describes the control bits in the BCR. At power-up, the BCR is set to 9D4Fh. The BCR is accessed using CRE and A[19] HIGH or through the configuration register software sequence with DQ = 0001h on the third cycle. Figure 19: Bus Configuration Register Definition A20 A19 A[18:16] 20 19 Reserved Must be set to "0" 18-16 A15 15 A14 A13 A12 A11 A10 14 Reserved Operating Reserved Mode Register Select 13 12 11 Latency Counter 10 WAIT Polarity Must be set to "0" Must be set to "0" A8 A9 9 A7 8 7 WAIT Configuration (WC) Reserved Must be set to "0" A5 A6 6 A4 5 4 Clock Output Reserved Configuration (CC) Impedance Reserved Must be set to "0" A3 A2 A1 A0 3 2 1 0 Burst Burst Wrap (BW)* Length (BL)* Must be set to "0" BCR[13] BCR[12] BCR[11] Latency Counter 0 0 0 Code 0-reserved 0 0 1 Code 1-reserved 0 1 0 Code 2 0 1 1 Code 3 (default) 1 0 0 Code 4-reserved 1 0 1 Code 5-reserved 1 1 0 Code 6-reserved 1 1 1 Code 7-reserved Burst Wrap (Note 1) BCR[3] 0 Burst wraps within the burst length 1 Burst no wrap (default) BCR[10] WAIT Polarity BCR[8] BCR[15] 0 Active LOW 1 Active HIGH (default) BCR[5] Output Impedance 0 Full drive (default) 1 1/4 drive WAIT Configuration BCR[6] 0 Asserted during delay 1 Asserted one data cycle before delay (default) Clock Configuration 0 Not supported 1 Rising edge (default) Operating Mode 0 Synchronous burst access mode 1 Asynchronous access mode (default) BCR[2] BCR[1] BCR[0] Burst Length (Note 1) BCR[19] Register Select 0 Select RCR 1 Select BCR Note: PDF: 09005aef82832fa2/Source: 09005aef82832f5f 32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN 0 0 1 4 words 0 1 0 8 words 0 1 1 16 words 1 1 1 Continuous burst (default) All burst WRITEs are continuous. 26 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Configuration Registers Table 4: Sequence and Burst Length Burst Wrap 4-Word Burst Length 8-Word Burst Length 16-Word Burst Length Continuous Burst Linear Linear Linear Linear 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 0-1-2-3-4-5-6-7-8-9-10-11-12-13-14-15 1-2-3-4-5-6-7-8-9-10-11-12-13-14-15-0 2-3-4-5-6-7-8-9-10-11-12-13-14-15-0-1 3-4-5-6-7-8-9-10-11-12-13-14-15-0-1-2 4-5-6-7-8-9-10-11-12-13-14-15-0-1-2-3 5-6-7-8-9-10-11-12-13-14-15-0-1-2-3-4 6-7-8-9-10-11-12-13-14-15-0-1-2-3-4-5 7-8-9-10-11-12-13-14-15-0-1-2-3-4-5-6 ... 14-15-0-1-2-3-4-5-6-7-8-9-10-11-12-13 0 1 2 0-1-2-3 1-2-3-4 2-3-4-5 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-8 2-3-4-5-6-7-8-9 3 3-4-5-6 3-4-5-6-7-8-9-10 Starting Address BCR[3] Wrap (Decimal) 0 Yes 0 1 2 3 4 5 6 7 ... 14 15 1 No 4 4-5-6-7-8-9-10-11 5 5-6-7-8-9-10-11-12 6 6-7-8-9-10-11-1213 7-8-9-10-11-12-1314 7 ... 14 15 0-1-2-3-4-5-6-... 1-2-3-4-5-6-7-... 2-3-4-5-6-7-8-... 3-4-5-6-7-8-9-... 4-5-6-7-8-9-10-... 5-6-7-8-9-10-11-... 6-7-8-9-10-11-12-... 7-8-9-10-11-12-13-... ... 14-15-16-17-18-19-20... 15-0-1-2-3-4-5-6-7-8-9-10-11-12-13-14 15-16-17-18-19-20-21... 0-1-2-3-4-5-6-7-8-9-10-11-12-13-14-15 0-1-2-3-4-5-6-... 1-2-3-4-5-6-7-8-9-10-11-12-13-14-15-16 1-2-3-4-5-6-7-... 2-3-4-5-6-7-8-9-10-11-12-13-14-15-162-3-4-5-6-7-8-... 17 3-4-5-6-7-8-9-10-11-12-13-14-15-16-173-4-5-6-7-8-9-... 18 4-5-6-7-8-9-10-11-12-13-14-15-16-174-5-6-7-8-9-10-... 18-19 5-6-7-8-9-10-11-12-13-...-15-16-17-185-6-7-8-9-10-11-... 19-20 6-7-8-9-10-11-12-13-14-...-16-17-18-196-7-8-9-10-11-12-... 20-21 7-8-9-10-11-12-13-14-...-17-18-19-207-8-9-10-11-12-13-... 21-22 ... ... 14-15-16-17-18-19-...-23-24-25-26-27- 14-15-16-17-18-19-2028-29 ... 15-16-17-18-19-20-...-24-25-26-27-28- 15-16-17-18-19-20-2129-30 ... Burst Length (BCR[2:0]) Default = Continuous Burst Burst lengths define the number of words the device outputs during a burst READ operation. The device supports a burst length of 4, 8, or 16 words. The device can also be set in continuous burst mode where data is output sequentially without regard to address boundaries; the internal address wraps to 000000h if the device is read past the last address. WRITE bursts are always performed using continuous burst mode. Burst Wrap (BCR[3]) Default = Burst No Wrap (Within Burst Length) The burst wrap option determines whether a 4-, 8-, or 16-word burst READ wraps within the burst length or steps through sequential addresses. If the wrap option is not enabled, the device outputs data from sequential addresses without regard to burst boundaries; the internal address wraps to 000000h if the device is read past the last address. PDF: 09005aef82832fa2/Source: 09005aef82832f5f 32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN 27 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Configuration Registers Output Impedance (BCR[5]) Default = Outputs Use Full Drive Strength The output driver strength can be altered to adjust for different data bus loading scenarios. The reduced-strength option should be more than adequate in stacked chip (Flash + CellularRAM) environments when there is a dedicated memory bus. The reduceddrive-strength option is included to minimize noise generated on the data bus during READ operations. Normal output impedance should be selected when using a discrete CellularRAM device in a more heavily loaded data bus environment. Partial drive is approximately one-quarter full drive strength. Outputs are configured at full drive strength during testing. WAIT Configuration (BCR[8]) Default = WAIT Transitions One Clock Before Data Valid/Invalid The WAIT configuration bit is used to determine when WAIT transitions between the asserted and the deasserted state with respect to valid data presented on the data bus. The memory controller will use the WAIT signal to coordinate data transfer during synchronous READ and WRITE operations. When BCR[8] = 0, data will be valid or invalid on the clock edge immediately after WAIT transitions to the deasserted or asserted state, respectively (see Figures 20 and 22). When BCR[8] = 1, the WAIT signal transitions one clock period prior to the data bus going valid or invalid (see Figure 21 and Figure 22 on page 29). Figure 20: WAIT Configuration (BCR[8] = 0) CLK WAIT DQ[15:0] High-Z Data[0] Data[1] Data immediately valid (or invalid) Note: Figure 21: Data valid/invalid immediately after WAIT transitions (BCR[8] = 0). See Figure 22 on page 29. WAIT Configuration (BCR[8] = 1) CLK WAIT D[15:0] High-Z Data[0] Data valid (or invalid) after one clock delay Note: PDF: 09005aef82832fa2/Source: 09005aef82832f5f 32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN Valid/invalid data delayed for one clock after WAIT transitions (BCR[8] = 1). See Figure 22 on page 29. 28 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Configuration Registers Figure 22: WAIT Configuration During Burst Operation CLK BCR[8] = 0 Data valid in current cycle WAIT BCR[8] = 1 Data valid in next cycle WAIT DQ[15:0] D[0] D[1] D[3] D[2] D[4] Don't Care Note: Nondefault BCR setting for WAIT during BURST operation: WAIT active LOW. WAIT Polarity (BCR[10]) Default = WAIT Active HIGH The WAIT polarity bit indicates whether an asserted WAIT output should be HIGH or LOW. This bit will determine whether the WAIT signal requires a pull-up or pull-down resistor to maintain the deasserted state. Latency Counter (BCR[13:11]) Default = Three-Clock Latency The latency counter bits determine how many clocks occur between the beginning of a READ or WRITE operation and the first data value transferred. Only latency code 2 (3 clocks) or latency code 3 (4 clocks) is allowed (see Table 5 and Figure 23 on page 30). Operating Mode (BCR[15]) Default = Asynchronous Operation The operating mode bit either selects synchronous burst operation or the default asynchronous mode of operation. Table 5: Latency Configuration Max Input CLK Frequency Latency Configuration Code 2 (3 clocks) 3 (4 clocks) - default PDF: 09005aef82832fa2/Source: 09005aef82832f5f 32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN 29 104 MHz 80 MHz 66 (15ns) 104 (9.62ns) 53 (18.75ns) 80 (12.50ns) Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Configuration Registers Figure 23: CLK A[20:0] ADV# Latency Counter (Variable Latency, No Refresh Collision) VIH VIL VIH VIL Valid address VIH VIL Code 2 DQ[15:0] VOH Valid output VOL Code 3 DQ[15:0] Valid output Valid output Valid output Valid output Valid output Valid output Valid output Valid output (Default) VOH VOL Don't Care PDF: 09005aef82832fa2/Source: 09005aef82832f5f 32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN 30 Undefined Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Configuration Registers Refresh Configuration Register The refresh configuration register (RCR) defines how the CellularRAM device performs its transparent self refresh. Altering the refresh parameters can dramatically reduce current consumption during standby mode. Page mode control is also embedded into the RCR. Figure 24 describes the control bits used in the RCR. At power-up, the RCR is set to 0010h. The RCR is accessed using CRE and A[19] LOW or through the configuration register software access sequence with DQ = 0000h on the third cycle (see "Configuration Registers" on page 20.) Partial-Array Refresh (RCR[2:0]) Default = Full Array Refresh The PAR bits restrict refresh operation to a portion of the total memory array. This feature enables the device to reduce standby current by refreshing only that part of the memory array required by the host system. The refresh options are full array, one-half array, one-quarter array, one-eighth array, or none of the array. The mapping of these partitions can start either at the beginning or the end of the address map (see Table 6 on page 32). Figure 24: Refresh Configuration Register Mapping A20 20 Reserved Must be set to "0" RCR[19] A19 19 Register Select A[18:8] A6 A7 18-8 7 Reserved Page All must be set to "0" A4 A5 5 6 Ignored A3 3 4 DPD 2 Reserved Select RCR 1 Select BCR RCR[7] A0 1 0 Address Bus PAR Must be set to "0" Setting is ignored (default 00b) Refresh Coverage RCR[2] RCR[1] RCR[0] 0 0 0 0 0 1 Bottom 1/2 array 0 1 0 Bottom 1/4 array 0 1 1 Bottom 1/8 array 1 0 0 None of array Top 1/2 array Register Select 0 A1 A2 Full array (default) Page Mode Enable/Disable 1 0 1 0 Page mode disabled (default) 1 1 0 Top 1/4 array 1 Page mode enable 1 1 1 Top 1/8 array RCR[4] PDF: 09005aef82832fa2/Source: 09005aef82832f5f 32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN 31 Deep Power-Down 0 DPD enable 1 DPD disable (default) Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Electrical Characteristics Table 6: 32Mb Address Patterns for PAR (RCR[4] = 1) RCR[2] RCR[1] RCR[0] Active Section Address Space Size Density 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Full die One-half of die One-quarter of die One-eighth of die None of die One-half of die One-quarter of die One-eighth of die 000000h-1FFFFFh 000000h-0FFFFFh 000000h-07FFFFh 000000h-03FFFFh 0 100000h-1FFFFFh 180000h-1FFFFFh 1C0000h-1FFFFFh 2 Meg x 16 1 Meg x 16 512K x 16 256K x 16 0 Meg x 16 1 Meg x 16 512K x 16 256K x 16 32Mb 16Mb 8Mb 4Mb 0Mb 16Mb 8Mb 4Mb Deep Power-Down (RCR[4]) Default = DPD Disabled The deep power-down bit enables and disables all refresh-related activity. This mode is used if the system does not require the storage provided by the CellularRAM device. Any stored data will become corrupted when DPD is enabled. When refresh activity has been reenabled, the CellularRAM device will require 150s to perform an initialization procedure before normal operations can resume. Deep power-down is enabled when RCR[4] = 0 and remains enabled until RCR[4] is set to "1." DPD should not be enabled or disabled with the software access sequence; instead, use CRE to access the RCR. Page Mode Operation (RCR[7]) Default = Disabled The page mode operation bit determines whether page mode is enabled for asynchronous READ operations. In the power-up default state, page mode is disabled. Electrical Characteristics Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Table 7: Absolute Maximum Ratings Parameter Rating Voltage to any ball except VCC; VCCQ relative to VSS Voltage on VCC supply relative to VSS Voltage on VCCQ supply relative to VSS Storage temperature (plastic) Operating temperature (case) Wirelessnote: Industrial Soldering temperature and time 10 seconds (solder ball only) Note: PDF: 09005aef82832fa2/Source: 09005aef82832f5f 32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN -0.5V to (4.0V or VCCQ + 0.3V, whichever is less) -0.2V to +2.45V -0.2V to +4.0V -55C to +150C -30C to +85C -40C to +85C +260C -30C exceeds the CellularRAM Workgroup 1.0 specification of -25C. 32 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Electrical Characteristics Table 8: Electrical Characteristics and Operating Conditions Wireless temperature1 (-30C < TC < +85C); industrial temperature (-40C < TC < +85C) Description Conditions Supply voltage I/O supply voltage Input high voltage Input low voltage Output high voltage Output low voltage Input leakage current Output leakage current IOH = -0.2mA IOL = +0.2mA VIN = 0 to VCCQ OE# = VIH or chip disabled Operating Current Asynchronous random READ/ WRITE Asynchronous page READ VIN = VCCQ or 0V chip enabled; IOUT = 0 Initial access, burst READ/WRITE Symbol VCC VCCQ VIH VIL VOH VOL ILI ILO 1.7 1.7 1.4 -0.2 0.8 VCCQ - - - 1.95 3.6 VCCQ + 0.2 0.4 - 0.2 VCCQ 1 1 V V V V V V A A 2, 3 4 5 5 20 - 15 - 40 35 25 18 40 35 110 mA 6 mA 6 mA 6 mA 6 mA 6 A 7 ICC1P -70 - ICC2 104 MHz 80 MHz 104 MHz 80 MHz 104 MHz 80 MHz Standard - ICC3W PDF: 09005aef82832fa2/Source: 09005aef82832f5f 32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN Notes - Continuous burst WRITE Notes: Units -70 ICC3R VIN = VCCQ or 0V CE# = VCCQ Max ICC1 Continuous burst READ Standby current Min ISB - - - - - 1. 2. 3. 4. 5. 6. -30C exceeds the CellularRAM Workgroup 1.0 specification of -25C. Input signals may overshoot to VCCQ + 1.0V for periods less than 2ns during transitions. VIH (MIN) value is not aligned with CellularRAM Workgroup 1.0 specification of VCCQ - 0.4V. Input signals may undershoot to VSS - 1.0V for periods less than 2ns during transitions. BCR[5] = 0b. This parameter is specified with the outputs disabled to avoid external loading effects. The user must add the current required to drive output capacitance expected in the actual system. 7. ISB (MAX) values measured with PAR set to FULL ARRAY. To achieve low standby current, all inputs must be driven either to VCCQ or VSS. ISB might be slightly higher for up to 500ms after power-up, after changes to the PAR array partition, or when entering standby mode. 33 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Electrical Characteristics Maximum and Typical Standby Currents The following table and figure refer to the maximum and typical standby currents for the MT45W2MW16BGB device. The typical values shown in Figure 25 are measured with the default on-chip temperature sensor control enabled. Table 9: Partial-Array Refresh Specifications and Conditions Description Conditions VIN = VCCQ or 0V; CE# = VCCQ Partial-array refresh standby current Note: Figure 25: Symbol IPAR Array Partition Max Unit Full 1/2 1/4 1/8 0 110 105 95 95 70 A Standard power (no designation) IPAR (MAX) values measured at 85C. IPAR might be slightly higher for up to 500ms after changes to the PAR array partition or when entering standby mode. To achieve low standby current, all inputs must be driven either to VCCQ or VSS. Typical Refresh Current vs. Temperature 70 60 PAR full PAR 1/2 PAR 1/4 PAR 0 ISB (A) 50 40 30 20 10 0 -45 -35 -25 -15 -05 05 15 25 35 45 55 65 75 85 95 Temperature (C) PDF: 09005aef82832fa2/Source: 09005aef82832f5f 32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN 34 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Electrical Characteristics Table 10: Deep Power-Down Specifications Description Deep power-down Table 11: Conditions Symbol Typ Units VIN = VCCQ or 0V; +25C IZZ 10 A Capacitance Description Input capacitance Input/output capacitance (DQ) Note: Figure 26: Conditions Symbol Min Max Units Notes TC = +25C; f = 1 MHz; VIN = 0V CIN CIO 2.0 3.0 6.5 6.5 pF pF Note: Note: These parameters are verified in device characterization and are not 100% tested. AC Input/Output Reference Waveform VCCQ Input 1 VCCQ/2 2 Test points 3 VCCQ/2 Output VSSQ Notes: Figure 27: 1. AC test inputs are driven at VCCQ for a logic 1 and VSSQ for a logic 0. Input rise and fall times (10% to 90%) < 1.6ns. 2. Input timing begins at VCCQ/2. 3. Output timing ends at VCCQ/2. Output Load Circuit Test point 50W VccQ/2 DUT 30pF Note: PDF: 09005aef82832fa2/Source: 09005aef82832f5f 32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN All tests are performed with the outputs configured for full drive strength (BCR[5] = 0b). 35 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Timing Requirements Timing Requirements Table 12: Asynchronous READ Cycle Timing Requirements 70ns Parameter 1 Symbol t Address access time ADV# access time Page access time Address hold from ADV# HIGH Address setup to ADV# HIGH LB#/UB# access time LB#/UB# disable to DQ High-Z output LB#/UB# enable to Low-Z output Maximum CE# pulse width CE# LOW to WAIT valid Chip select access time CE# LOW to ADV# HIGH Chip disable to DQ and WAIT High-Z output Chip enable to Low-Z output Output enable to valid output Output hold from address change Output disable to DQ High-Z output Output enable to Low-Z output Page cycle time READ cycle time ADV# pulse width LOW ADV# pulse width HIGH Notes: PDF: 09005aef82832fa2/Source: 09005aef82832f5f 32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN t AA AADV t APA t AVH tAVS t BA tBHZ tBLZ tCEM tCEW tCO tCVS tHZ tLZ tOE tOH tOHZ tOLZ tPC tRC tVP tVPH Min Max Units - - - 5 5 - - 10 - 1 - 10 - 10 - 5 - 3 20 70 10 10 70 70 20 - - 70 8 - 8 7.5 70 - 8 - 20 - 8 - - - - - ns ns ns ns ns ns ns ns s ns ns ns ns ns ns ns ns ns ns ns ns ns Notes 2 3 4 2 3 2 3 1. All tests are performed with the outputs configured for full drive strength (BCR[5] = 0b). 2. Low-Z to High-Z timings are tested with the circuit shown in Figure 27 on page 35. The High-Z timings measure a 100mV transition either from VOH or VOL toward VCCQ/2. 3. High-Z to Low-Z timings are tested with the circuit shown in Figure 27 on page 35. The LowZ timings measure a 100mV transition away from the High-Z (VCCQ/2) level either toward VOH or VOL. 4. Page mode enabled only. 36 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Timing Requirements Table 13: Burst READ Cycle Timing Requirements 104 MHz Parameter1 Symbol Burst to READ access time CLK to output delay Burst OE# LOW to output delay CE# HIGH between subsequent burst and mixed-mode operations Maximum CE# pulse width CE# LOW to WAIT valid CLK period CE# setup time to active CLK edge Hold time from active CLK edge Chip disable to DQ and WAIT High-Z output CLK rise or fall time CLK to WAIT valid Output HOLD from CLK CLK HIGH or LOW time Output disable to DQ High-Z output Output enable to Low-Z output Setup time to active CLK edge Notes: PDF: 09005aef82832fa2/Source: 09005aef82832f5f 32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN 80 MHz Min Max Min Max Units Notes ABA ACLK t BOE t CBPH - - - 5 35.9 7 20 - - - - 5 46.5 9 20 - ns ns ns ns 2 tCEM - 1 9.62 3 2 - - - 2 3 - 3 3 8 7.5 - - - 8 1.6 7 - - 8 - - - 1 12.5 4.5 2 - - - 2 4 - 3 3 8 7.5 - - - 8 1.8 9 - - 8 - - s ns ns ns ns ns ns ns ns ns ns ns ns t t t CEW tCLK t CSP tHD tHZ tKHKL tKHTL tKOH tKP tOHZ tOLZ tSP 3 3 4 1. All tests are performed with the outputs configured for full drive strength (BCR[5] = 0b). 2. When configured for synchronous mode (BCR[15] = 0), a refresh opportunity must be provided every tCEM. A refresh opportunity is satisfied by either of the following two conditions: clocked CE# HIGH or CE# HIGH for greater than 15ns. 3. Low-Z to High-Z timings are tested with the circuit shown in Figure 27 on page 35. The High-Z timings measure a 100mV transition either from VOH or VOL toward VCCQ/2. 4. High-Z to Low-Z timings are tested with the circuit shown in Figure 27 on page 35. The LowZ timings measure a 100mV transition away from the High-Z (VCCQ/2) level either toward VOH or VOL. 37 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Timing Requirements Table 14: Asynchronous WRITE Cycle Timing Requirements 70ns Parameter Symbol t AS AVH t AVS t AW tBW t CEW t CKA tCPH tCVS t CW tDH tDW tHZ tLZ tOW tVP tVPH tVS tWC tWHZ tWP tWPH tWR Address and ADV# LOW setup time Address hold from ADV# going HIGH Address setup to ADV# going HIGH Address valid to end of WRITE LB#/UB# select to end of WRITE CE# LOW to WAIT valid Asynchronous address-to-burst transition time CE# HIGH between subsequent asynchronous operations CE# LOW to ADV# HIGH Chip enable to end of WRITE Data hold from WRITE time Data WRITE setup time Chip disable to WAIT High-Z output Chip enable to Low-Z output End WRITE to Low-Z output ADV# pulse width ADV# pulse width HIGH ADV# setup to end of WRITE WRITE cycle time WRITE to DQ High-Z output WRITE pulse width WRITE pulse width HIGH WRITE recovery time Notes: PDF: 09005aef82832fa2/Source: 09005aef82832f5f 32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN t Min Max Units 0 5 5 70 70 1 70 5 10 70 0 23 - 10 5 10 10 70 70 - 46 10 0 - - - - - 7.5 - - - - - - 8 - - - - - - 8 - - - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Notes 2 1 2 3 1. High-Z to Low-Z timings are tested with the circuit shown in Figure 27 on page 35. The LowZ timings measure a 100mV transition away from the High-Z (VCCQ/2) level either toward VOH or VOL. 2. Low-Z to High-Z timings are tested with the circuit shown in Figure 27 on page 35. The High-Z timings measure a 100mV transition either from VOH or VOL toward VCCQ/2. 3. WE# LOW time must be limited to tCEM (8s). 38 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Timing Requirements Table 15: Burst WRITE Cycle Timing Requirements 104 MHz Parameter Symbol CE# HIGH between subsequent burst and mixed-mode operations Maximum CE# pulse width CE# LOW to WAIT valid Clock period CE# setup to CLK active edge Hold time from active CLK edge Chip disable to WAIT High-Z output CLK rise or fall time Clock to WAIT valid CLK HIGH or LOW time Setup time to active CLK edge Note: Figure 28: 80 MHz Min Max Min Max Units Notes CBPH 5 - 5 - ns 1 tCEM - 1 9.62 3 2 - - - 3 3 8 7.5 - - - 8 1.6 7 - - - 1 12.5 4.5 2 - - - 4 3 8 7.5 - - - 8 1.8 9 - - s ns ns ns ns ns ns ns ns ns 1 t t CEW CLK tCSP t HD tHZ t KHKL tKHTL tKP tSP t When configured for synchronous mode (BCR[15] = 0), a refresh opportunity must be provided every tCEM. A refresh opportunity is satisfied by either of the following two conditions: clocked CE# HIGH or CE# HIGH for greater than 15ns. Initialization Period Vcc (MIN) Vcc, VccQ = 1.7V Device ready for normal operation tPU Table 16: Initialization Timing Parameters -70 Parameter Initialization period (required before normal operations) PDF: 09005aef82832fa2/Source: 09005aef82832f5f 32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN 39 Symbol Min Max Units tPU 150 - s Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Timing Diagrams Timing Diagrams Figure 29: Asynchronous READ tRC VIH A[20:0] Valid address VIL tAA ADV# VIH VIL tHZ CE# VIH VIL tCO LB#/UB# tBHZ tBA VIH VIL tOE OE# WE# tOHZ VIH VIL VIH tOLZ tBLZ tLZ VIL VOH DQ[15:0] VOL VOH WAIT VOL High-Z Valid output tCEW tHZ High-Z High-Z Don't Care PDF: 09005aef82832fa2/Source: 09005aef82832f5f 32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN 40 Undefined Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Timing Diagrams Figure 30: Asynchronous READ Using ADV# A[20:0] VIH Valid address VIL tAVS tVPH tAA tAVH VIH ADV# VIL tAADV tVP tCVS tHZ VIH CE# VIL tCO tBA tBHZ VIH LB#/UB# VIL tOE tOHZ VIH OE# VIL VIH WE# tOLZ tBLZ VIL tLZ DQ[15:0] VOH High-Z Valid output VOL tCEW WAIT tHZ VOH VOL High-Z High-Z Don't Care PDF: 09005aef82832fa2/Source: 09005aef82832f5f 32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN 41 Undefined Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Timing Diagrams Figure 31: Page Mode READ tRC A[20:4] VIH Valid address VIL VIH A[3:0] ADV# Valid address VIL Valid address Valid address tPC tAA VIH Valid address VIL tCEM tCO VIH tHZ CE# VIL LB#/UB# tBA VIH tBHZ VIL tOHZ tOE VIH OE# VIL VIH WE# tOLZ tBLZ VIL tLZ VOH DQ[15:0] VOL VOH WAIT VOL tAPA tOH Valid output High-Z tCEW Valid output Valid output Valid output tHZ High-Z High-Z Don't Care PDF: 09005aef82832fa2/Source: 09005aef82832f5f 32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN 42 Undefined Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Timing Diagrams Figure 32: Single-Access Burst READ Operation tCLK tKP tKP tKHKL VIH CLK A[20:0] VIL VIH VIL tSP tHD Valid address tSP tHD VIH ADV# CE# VIL VIH tHD tCEM tCSP tHZ tABA VIL tOHZ tBOE VIH OE# VIL tSP WE# tHD tOLZ VIH VIL VIH LB#/UB# tSP VIL VOH WAIT tCEW tKHTL High-Z High-Z VOL DQ[15:0] tKOH tACLK VOH High-Z VOL Valid output READ burst identified (WE# = HIGH) Note: PDF: 09005aef82832fa2/Source: 09005aef82832f5f 32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN Don't Care Undefined Nondefault BCR settings for single-access burst READ operation: latency code 2 (3 clocks); WAIT active LOW; WAIT asserted during delay. 43 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Timing Diagrams Figure 33: 4-Word Burst READ Operation tKHKL CLK A[20:0] tKP VIL VIH VIL tSP tHD Valid address tSP ADV# tKP tCLK VIH tHD VIH VIL tCEM CE# OE# VIH VIL tHZ tBOE VIH tOHZ VIL tSP WE# LB#/UB# tCBPH tHD tABA tCSP tHD tOLZ VIH VIL VIH tSP VIL WAIT VOL tKHTL tCEW VOH High-Z High-Z tKOH tACLK DQ[15:0] VOH High-Z VOL Valid output READ burst identified (WE# = HIGH) Note: PDF: 09005aef82832fa2/Source: 09005aef82832f5f 32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN Valid output Valid output Valid output Don't Care Undefined Nondefault BCR settings for 4-word burst READ operation: latency code 2 (3 clocks); WAIT active LOW; WAIT asserted during delay. 44 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Timing Diagrams Figure 34: READ Burst Suspend tCLK VIH CLK VIL tSP VIH A[20:0] VIL VIH tHD Valid address Valid address tHD tSP ADV# VIL tCBPH tHZ tCEM VIH tCSP CE# VIL tOHZ tOHZ OE# VIH VIL VIH tSP tHD WE# VIL VIH LB#/UB# VIL tSP VOH tOLZ WAIT VOLHigh-Z VOH DQ[15:0] VOL tBOE tKOH tOLZ Valid output High-Z Valid output Valid output Valid output High-Z tBOE Valid output Valid output tACLK Don't Care Note: PDF: 09005aef82832fa2/Source: 09005aef82832f5f 32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN Undefined Nondefault BCR settings for READ burst suspend: latency code 2 (3 clocks); WAIT active LOW; WAIT asserted during delay. 45 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Timing Diagrams Figure 35: CLK Output Delay in Continuous Burst READ with BCR[8] = 0 for End-of-Row Condition VIH VIL tCLK A[20:0] VIH VIL ADV# VIH VIL LB#/UB# VIH VIL CE# VIH Note 3 VIL OE# VIH VIL WE# VIH VIL tKHTL tKHTL WAIT VOH Note 2 VOL DQ[15:0] VOH Valid output VOL Valid output Valid output tACLK Valid output tKOH Don't Care Notes: PDF: 09005aef82832fa2/Source: 09005aef82832f5f 32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN 1. Nondefault BCR settings for continuous burst READ showing an output delay, BCR[8] = 0 for end-of-row condition: latency code 2 (3 clocks); WAIT active LOW; WAIT asserted during delay. 2. WAIT will be asserted a maximum of LC cycles (BCR[8] = 0; WAIT asserted during delay). LC = latency code (BCR[13:11]). 3. CE# must not remain LOW longer than tCEM. 46 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Timing Diagrams Figure 36: CE#-Controlled Asynchronous WRITE tWC A[20:0] VIH Valid address VIL tAW tWR tAS VIH ADV# CE# VIL tCW VIH tCPH VIL tBW VIH LB#/UB# OE# VIL VIH VIL tWPH tWP VIH WE# VIL tDW DQ[15:0] in VIH DQ[15:0] out VOH High-Z VIL tLZ WAIT tDH Valid input tWHZ VOL VOH VOL tHZ tCEW High-Z High-Z Don't Care PDF: 09005aef82832fa2/Source: 09005aef82832f5f 32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN 47 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Timing Diagrams Figure 37: LB#/UB#-Controlled Asynchronous WRITE tWC A[20:0] VIH Valid address VIL tAW tAS ADV# tWR VIH VIL tCW CE# LB#/UB# OE# VIH VIL tBW VIH VIL VIH VIL tWP tWPH VIH WE# VIL tDW DQ[15:0] in VIH DQ[15:0] out VOH High-Z VIL Valid input tWHZ tLZ VOL tCEW WAIT tDH tHZ VOH VOL High-Z High-Z Don't Care PDF: 09005aef82832fa2/Source: 09005aef82832f5f 32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN 48 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Timing Diagrams Figure 38: WE#-Controlled Asynchronous WRITE tWC VIH A[20:0] Valid address VIL tAW tWR VIH ADV# VIL tCW VIH CE# VIL tBW VIH LB#/UB# VIL VIH OE# VIL tAS tWP tWPH VIH WE# VIL tDW DQ[15:0] in High-Z VIL Valid input VOH VOL tCEW tHZ VOH WAIT tOW tWHZ tLZ DQ[15:0] out tDH VIH VOL High-Z High-Z Don't Care PDF: 09005aef82832fa2/Source: 09005aef82832f5f 32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN 49 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Timing Diagrams Figure 39: Asynchronous WRITE Using ADV# A[20:0] VIH Valid address VIL tAVS tVS tVPH ADV# tAVH tVP tAS VIH VIL tAS tAW tCW VIH CE# VIL tBW VIH LB#/UB# OE# VIL VIH VIL tWPH tWP WE# VIH VIL tDW DQ[15:0] VIH in VIL DQ[15:0] VOH out VOL Valid input High-Z tWHZ tLZ tCEW WAIT tOW tHZ VOH VOL tDH High-Z High-Z Don't Care PDF: 09005aef82832fa2/Source: 09005aef82832f5f 32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN 50 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Timing Diagrams Figure 40: Burst WRITE Operation tCLK CLK tKP tKP tKHKL VIH VIL tSP A[20:0] VIL Valid address tSP ADV# tHD VIH tHD VIH VIL tSP tHD LB#/UB# VIH VIL tCEM CE# VIH tCSP tHD tCBPH VIL OE# VIH VIL tSP WE# tHD VIH VIL tCEW VOH WAIT tKHTL tHZ High-Z VOL High-Z tSP tHD VIH DQ[15:0] D[0] VIL WRITE burst identified (WE# = LOW) Note: PDF: 09005aef82832fa2/Source: 09005aef82832f5f 32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN D[1] D[2] D[3] Don't Care Nondefault BCR settings for burst WRITE operation: latency code 2 (3 clocks); WAIT active LOW; WAIT asserted. 51 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Timing Diagrams Figure 41: CLK Output Delay in Continuous Burst WRITE with BCR[8] = 0 for End-of-Row Condition VIH VIL tCLK A[20:0] VIH VIL ADV# VIH VIL LB#/UB# VIH VIL CE# VIH Note 4 VIL VIH WE# VIL VIH OE# VIL tKHTL tKHTL WAIT VOH Note 3 VOL tSP tHD VIH DQ[15:0] Valid input VIL Valid input Valid input End of row Start of row (A[6:0] = 7Fh) (A[6:0] = 00h) (Note 4) Notes: PDF: 09005aef82832fa2/Source: 09005aef82832f5f 32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN Valid input Don't Care 1. Nondefault BCR settings for continuous burst WRITE, BCR[8] = 0; WAIT active LOW; WAIT asserted during delay. Do not cross row boundaries with fixed latency. 2. CE# must not remain LOW longer than tCEM. 3. WAIT asserts anywhere from LC to 2LC cycles. LC = latency code (BCR[13:11]). 4. Taking CE# HIGH or ADV# LOW on the start-of-row cycle will abort the burst and not write the start-of-row data. Devices from different CellularRAM vendors can assert WAIT so that the start-of-row data is input just before (as shown) or just after WAIT asserts. This difference in behavior will not be noticed by controllers that monitor WAIT or that use WAIT to abort on the start-of-row input cycle. 52 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Timing Diagrams Figure 42: Burst WRITE Followed by Burst READ tCLK CLK VIH VIL tSP tSP tHD VIH A[20:0] VIL Valid address Valid address tHD tSP tHD tSP VIH ADV# VIL LB#/UB# tHD tSP VIH tCSP VIL tCSP CE# OE# WE# WAIT tHD tHD VIH VIL tCBPH2 tABA tCSP VIH tOHZ tHD VIL tSP VIH VIL tSP tHD VOH VOL DQ[15:0] VIH in/out VIL tBOE High-Z tACLK tSP tHD VOH High-Z D[0] D[1] D[2] D[3] VOL High-Z High-Z tKOH Valid output Valid output Valid output Don't Care Notes: PDF: 09005aef82832fa2/Source: 09005aef82832f5f 32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN Valid output Undefined 1. Nondefault BCR settings for burst WRITE followed by burst READ: latency code 2 (3 clocks); WAIT active LOW; WAIT asserted during delay. 2. When configured for synchronous mode (BCR[15] = 0), a refresh opportunity must be provided every tCEM. A refresh opportunity is satisfied by either of the following two conditions: clocked CE# HIGH or CE# HIGH for greater than 15ns. Note that the CellularRAM Workgroup 1.0 specification requires CE# to be clocked HIGH to terminate the burst. 53 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Timing Diagrams Figure 43: Asynchronous WRITE Followed by Burst READ tCLK VIH CLK VIL A[20:0] VIH VIL ADV# VIH VIL VIH LB#/UB# VIL tCKA tSP tHD Valid address tSP tVPH tVP tCVS tVS tBW tHD tSP tCBPH2 tCW VIH CE# VIL VIH tABA tCSP tOHZ tAS OE# VIL VIH tWC Valid address tAW tWR tWC Valid address tAVS tAVH tAS tWC tWPH tWP tSP tHD WE# VIL WAIT tCEW VOH VOL DQ[15:0] VIH in/out VIL tWHZ High-Z Data tDH Notes: PDF: 09005aef82832fa2/Source: 09005aef82832f5f 32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN Data tDW VOH VOL tBOE High-Z tKOH tACLK High-Z Valid output Valid output Valid output Don't Care Valid output Undefined 1. Nondefault BCR settings for asynchronous WRITE followed by burst READ: latency code 2 (3 clocks); WAIT active LOW; WAIT asserted during delay. 2. When configured for synchronous mode (BCR[15] = 0), a refresh opportunity must be provided every tCEM. A refresh opportunity is satisfied by either of the following two conditions: clocked CE# HIGH or CE# HIGH for greater than 15ns. Note that the CellularRAM Workgroup 1.0 specification requires CE# to be clocked HIGH to terminate the burst. 54 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Timing Diagrams Figure 44: Asynchronous WRITE Followed by Burst READ with ADV# LOW tCLK VIH CLK VIL A[20:0] VIH VIL ADV# VIH VIL VIH LB#/UB# VIL tCKA tSP tHD Valid address tSP tVPH tVP tCVS tVS tBW tHD tSP tCBPH2 tCW VIH CE# VIL VIH tABA tCSP tOHZ tAS OE# VIL VIH tWC Valid address tAW tWR tWC Valid address tAVS tAVH tAS tWC tWPH tWP tSP tHD WE# VIL WAIT tCEW VOH VOL DQ[15:0] VIH in/out VIL tWHZ High-Z Data tDH Notes: PDF: 09005aef82832fa2/Source: 09005aef82832f5f 32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN Data tDW VOH VOL tBOE High-Z tKOH tACLK High-Z Valid output Valid output Valid output Don't Care Valid output Undefined 1. Nondefault BCR settings for asynchronous WRITE followed by burst READ: latency code 2 (3 clocks); WAIT active LOW; WAIT asserted during delay. 2. When configured for synchronous mode (BCR[15] = 0), a refresh opportunity must be provided every tCEM. A refresh opportunity is satisfied by either of these conditions: clocked CE# HIGH or CE# HIGH for greater than 15ns. Note that the CellularRAM Workgroup 1.0 specification requires CE# to be clocked HIGH to terminate the burst. 55 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Timing Diagrams Figure 45: Burst READ Followed by Asynchronous WRITE (WE#-Controlled) CLK A[20:0] ADV# CE# tCLK VIH VIL VIH VIL tSP tHD tWC Valid address Valid address tSP tAW tHD VIL tCSP VIH tHD tABA WE# tHZ tCW tCBPH1 VIL tBOE OE# tWR VIH tOHZ VIH tAS VIL tSP tHD tOLZ tWP tWPH VIH VIL tBW tSP LB#/UB# WAIT DQ[15:0] VIH VIL tCEW VOH tKHTL tCEW High-Z High-Z VOL High-Z Valid output READ burst identified (WE# = HIGH) Note: PDF: 09005aef82832fa2/Source: 09005aef82832f5f 32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN tDH tDW tKOH tACLK VOH VOL tHZ Valid input Don't Care Undefined When configured for synchronous mode (BCR[15] = 0), a refresh opportunity must be provided every tCEM. A refresh opportunity is satisfied by either of the following two conditions: clocked CE# HIGH or CE# HIGH for greater than 15ns. Note that CellularRAM Workgroup specification 1.0 requires CE# to be clocked HIGH to terminate the burst. 56 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Timing Diagrams Figure 46: Burst READ Followed by Asynchronous WRITE Using ADV# CLK A[20:0] VIL VIH VIL ADV# CE# OE# WE# LB#/UB# tCLK VIH tSP VIH Valid address VIH tABA tVS tAW tAS tHZ tCW tCBPH1 tOHZ tBOE VIH VIL tSP VIH VIL VIH tHD tAS tOLZ tSP tCEW VOH tKHTL tKOH High-Z Valid output READ burst identified (WE# = HIGH) PDF: 09005aef82832fa2/Source: 09005aef82832f5f 32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN tHZ High-Z VOH Note: tWPH tCEW High-Z VOL tWP tBW tACLK DQ[15:0] tAVH tVP tHD tCSP VIL VOL tAVS tVPH tHD VIL VIL WAIT tHD tSP Valid address tDH tDW Valid input Don't Care Undefined When configured for synchronous mode (BCR[15] = 0), a refresh opportunity must be provided every tCEM. A refresh opportunity is satisfied by either of the following two conditions: clocked CE# HIGH or CE# HIGH for greater than 15ns. Note that CellularRAM Workgroup specification 1.0 requires CE# to be clocked HIGH to terminate the burst. 57 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Timing Diagrams Figure 47: A[20:0] Asynchronous WRITE Followed by Asynchronous READ with ADV# LOW VIH VIL Valid address Valid address tAW VIH ADV# LB#/UB# CE# Valid address tAA tWR VIL tBHZ tBLZ tBW VIH VIL tHZ tCO tCPH1 tCW VIH VIL tLZ OE# WE# WAIT tOHZ tOE VIH tWC tWPH VIL tWP VIH VIL tHZ tHZ VOH VOL DQ[15:0] VIH in/out VIL tOLZ High-Z Data Data tDH Note: PDF: 09005aef82832fa2/Source: 09005aef82832f5f 32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN High-Z VOH Valid output VOL tDW Don't Care Undefined When configured for synchronous mode (BCR[15] = 0), CE# must remain HIGH for at least 5ns (tCPH) to schedule the appropriate internal refresh operation. Otherwise, tCPH is only required after CE#-controlled WRITEs. 58 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Timing Diagrams Figure 48: A[20:0] Asynchronous WRITE Followed by Asynchronous READ VIH Valid address tAVS tAVH VIL ADV# VIH tVPH Valid address tAW tVP tVS tCVS tBW Valid address tAA tWR tAVS tVP VIL LB#/UB# VIH CE# VIH tCPH1 tCVS tOHZ tLZ VIH VIL WE# tHZ tCO VIL tAS OE# tBHZ tAADV tBLZ VIL tCW tAVH VIH tAS tWP tWC tWPH tOLZ VIL WAIT VOH VOL DQ[15:0] in/out tOE VIH VIL High-Z Data tDH Note: PDF: 09005aef82832fa2/Source: 09005aef82832f5f 32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN VOH Data VOL tDW High-Z Valid output Don't Care Undefined When configured for synchronous mode (BCR[15] = 0), CE# must remain HIGH for at least 5ns (tCPH) to schedule the appropriate internal refresh operation. Otherwise, tCPH is only required after CE#-controlled WRITEs. 59 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Package Dimensions Package Dimensions Figure 49: 54-Ball VFBGA 0.70 0.05 Seating plane A Solder ball material: 96.5% Sn, 3% Ag, 0.5% Cu 0.10 A Substrate material: plastic laminate 54X O0.37 Dimensions apply to solder balls post-reflow. Pre-reflow ball diameter is 0.35 on a 0.30 SMD ball pad. 3.75 Mold compound: epoxy novolac 0.75 TYP Ball A1 ID Ball A1 ID 4.00 0.05 Ball A6 Ball A1 8.00 0.10 6.00 3.00 0.75 TYP 1.875 3.00 0.05 1.00 MAX 6.00 0.10 Notes: 1. All dimensions are in millimeters. 2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side. 3. The MT45W2MW16BGB uses "green" packaging. (R) 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 prodmktg@micron.com www.micron.com Customer Comment Line: 800-932-4992 Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc. CellularRAM is a trademark of Micron Technology, Inc., inside the U.S. and a trademark of Qimonda AG outside the U.S. All other trademarks are the property of their respective owners. This data sheet contains minimum and maximum limits specified over the complete power supply and temperature range for production devices. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. PDF: 09005aef82832fa2/Source: 09005aef82832f5f 32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN 60 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved. 32Mb: 2 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Revision History Revision History Rev. E, Production . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .09/08 * "Options" on page 1: Added "Low Power: L" to table. * Table 2, "Bus Operations: Asynchronous Mode," on page 8: Changed note 1 from "CLK must be low..." to "CLK must be static HIGH or LOW..." * Table 3, "Bus Operations: Burst Mode," on page 9: Changed note 1 from "CLK must be low..." to "CLK must be static HIGH or LOW..." * Figure 26: "AC Input/Output Reference Waveform," on page 35: Changed "VCC" to "VCCQ" in two instances in the diagram; revised note 2 to read, "Input timing begins at VCCQ/2." * Figure 32: "Single-Access Burst READ Operation," on page 43: Changed symbol for LB#/UB# from tCSP to tSP. * Figure 33: "4-Word Burst READ Operation," on page 44: Changed symbol for LB#/ UB# from tCSP to tSP. * Figure 34: "READ Burst Suspend," on page 45: Changed symbol for LB#/UB# from t CSP to tSP. Rev. D, Production . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .02/08 * Table 15, "Burst WRITE Cycle Timing Requirements," on page 39: Corrected tCEM parameter label from minimum to maximum. Rev. C, Production . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .07/07 * Renumbered the notes in Table 12 on page 36. * Replaced "`" with "2" in the "Notes" column in Table 12 on page 36. Rev. B, Production . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .05/07 * Changed revision status to Production. * Removed "Contact factory" note from the "Options" section on page 1. * Changed burst initial latency from "39ns" to "38.5ns" in the "Features" section on page 1. * Removed "...(contact factory)" from Figure 3 on page 10. * Moved the "WAIT Polarity (BCR[10]) Default = WAIT Active HIGH" section to page 29. * Changed A6 and A5 to "Ignored" and added the following text in Figure 24 on page 31: "Setting is ignored (default 00b)." Rev. A, Preliminary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .02/07 * Initial release. PDF: 09005aef82832fa2/Source: 09005aef82832f5f 32mb_burst_cr1_0_p24z_2.fm - Rev. E 9/08 EN 61 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2007 Micron Technology, Inc. All rights reserved.