DS90LV049HMT/NOPB - Texas Instruments

GND

VDD

RIN1-

RIN1+

RIN2+

RIN2-

DOUT2-

DOUT2+

DOUT1+

DOUT1-

ROUT1

ROUT2

DIN2

DIN1

NRND

DS90LV049H

www.ti.com

SNLS200A –SEPTEMBER 2005–REVISED APRIL 2013

DS90LV049H High Temperature 3V LVDS Dual Line Driver and Receiver Pair

Check for Samples: DS90LV049H

1FEATURES DESCRIPTION

The DS90LV049H is a dual CMOS flow-through

2• High Temperature +125°C Operating Range differential line driver-receiver pair designed for

• Up to 400 Mbps Switching Rates applications requiring ultra low power dissipation,

• Flow-Through Pinout Simplifies PCB Layout exceptional noise immunity, and high data

throughput. The device is designed to support data

• 50 ps Typical Driver Channel-to-Channel Skew rates in excess of 400 Mbps utilizing Low Voltage

• 50 ps Typical Receiver Channel-to-Channel Differential Signaling (LVDS) technology.

Skew The DS90LV049H drivers accept LVTTL/LVCMOS

• 3.3 V Single Power Supply Design signals and translate them to LVDS signals. The

• TRI-STATE Output Control receivers accept LVDS signals and translate them to

• Internal Fail-Safe Biasing of Receiver Inputs 3 V CMOS signals. The LVDS input buffers have

internal failsafe biasing that places the outputs to a

• Low Power Dissipation (70 mW at 3.3 V Static) known H (high) state for floating receiver inputs. In

• High Impedance on LVDS Outputs on Power addition, the DS90LV049H supports a TRI-STATE

Down function for a low idle power state when the device is

• Conforms to TIA/EIA-644-A LVDS Standard not in use.

• Available in Low Profile 16 Pin TSSOP The EN and EN inputs are ANDed together and

Package control the TRI-STATE outputs. The enables are

common to all four gates.

CONNECTION DIAGRAM

Dual-In-Line

Order Number DS90LV049HMT

Order Number DS90LV049HMTX (Tape and Reel)

PW0016A Package

1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

RIN1-

RIN1+

RIN2+

RIN2-

DOUT2-

DOUT2+

DOUT1+

DOUT1-

ROUT1

ROUT2

DIN2

DIN1

AND EN

NRND

DS90LV049H

SNLS200A –SEPTEMBER 2005–REVISED APRIL 2013

www.ti.com

FUNCTIONAL DIAGRAM

Table 1. TRUTH TABLE

EN EN LVDS Out LVCMOS Out

L or Open L or Open OFF OFF

H L or Open ON ON

L or Open H OFF OFF

H H OFF OFF

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

Product Folder Links: DS90LV049H

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SNLS200A –SEPTEMBER 2005–REVISED APRIL 2013

ABSOLUTE MAXIMUM RATINGS(1)(2)

Supply Voltage (VDD)−0.3 V to +4 V

LVCMOS Input Voltage (DIN)−0.3 V to (VDD + 0.3 V)

LVDS Input Voltage (RIN+, RIN-)−0.3 V to +3.9 V

Enable Input Voltage (EN, EN) −0.3 V to (VDD + 0.3 V)

LVCMOS Output Voltage (ROUT)−0.3 V to (VDD + 0.3 V)

LVDS Output Voltage (DOUT+, DOUT-)−0.3 V to +3.9 V

LVCMOS Output Short Circuit Current (ROUT) 100 mA

LVDS Output Short Circuit Current (DOUT+, DOUT−) 24 mA

LVDS Output Short Circuit Current Duration (DOUT+, DOUT−) Continuous

Storage Temperature Range −65°C to +150°C

Lead Temperature Range

Soldering (4 sec.) +260°C

Maximum Junction Temperature +150°C

Maximum Package Power Dissipation @ +25°C

PW0016A Package 866 mW

Derate PW0016A Package 6.9 mW/°C above +25°C

ESD Rating

(HBM, 1.5 kΩ, 100 pF) ≥7 kV

(MM, 0 Ω, 200 pF) ≥250 V

(1) “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be specified. They are not meant to imply

that the devices should be operated at these limits. ELECTRICAL CHARACTERISTICS specifies conditions of device operation.

(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and

specifications.

RECOMMENDED OPERATING CONDITIONS Min Typ Max Units

Supply Voltage (VDD) +3.0 +3.3 +3.6 V

Operating Free Air Temperature (TA)−40 +25 +125 °C

ELECTRICAL CHARACTERISTICS

Over supply voltage and operating temperature ranges, unless otherwise specified.(1)(2)(3)

Symbol Parameter Conditions Pin Min Typ Max Units

LVCMOS Input DC Specifications (Driver Inputs, ENABLE Pins)

VIH Input High Voltage 2.0 VDD V

VIL Input Low Voltage GND 0.8 V

DIN

IIH Input High Current VIN = VDD EN −10 1 +10 μA

IIL Input Low Current VIN = GND −10 −0.1 +10 μA

VCL Input Clamp Voltage ICL =−18 mA −1.5 −0.6 V

LVDS Output DC Specifications (Driver Outputs)

(1) Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground

except: VTH, VTL, VOD and ΔVOD.

(2) All typical values are given for: VDD = +3.3 V, TA= +25°C.

(3) The DS90LV049H's drivers are current mode devices and only function within datasheet specifications when a resistive load is applied

to their outputs. The typical range of the resistor values is 90 Ωto 110 Ω.

Product Folder Links: DS90LV049H

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SNLS200A –SEPTEMBER 2005–REVISED APRIL 2013

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ELECTRICAL CHARACTERISTICS (continued)

Over supply voltage and operating temperature ranges, unless otherwise specified.(1)(2)(3)

Symbol Parameter Conditions Pin Min Typ Max Units

| VOD | Differential Output Voltage 250 350 450 mV

ΔVOD Change in Magnitude of VOD for 1 35 |mV|

Complementary Output States RL= 100 Ω

(Figure 1)

VOS Offset Voltage 1.125 1.23 1.375 V

ΔVOS Change in Magnitude of VOS for 1 25 |mV|

Complementary Output States

IOS Output Short Circuit Current(4) ENABLED, −5.8 −9.0 mA

DOUT−

DIN = VDD, DOUT+ = 0 V or DOUT+

DIN = GND, DOUT−= 0 V

IOSD Differential Output Short Circuit −5.8 −9.0 mA

ENABLED, VOD = 0 V

Current(4)

IOFF Power-off Leakage VOUT = 0 V or 3.6 V −20 ±1 +20 μA

VDD = 0 V or Open

IOZ Output TRI-STATE Current EN = 0 V and EN = VDD −10 ±1 +10 μA

VOUT = 0 V or VDD

LVDS Input DC Specifications (Receiver Inputs)

VTH Differential Input High Threshold −15 35 mV

VCM = 1.2 V, 0.05 V, 2.35 V

VTL Differential Input Low Threshold -100 −15 mV

VCMR Common-Mode Voltage Range VID = 100 mV, VDD=3.3 V 0.05 3 V

RIN+

VDD=3.6 V RIN- −12 ±4 +12 μA

VIN =0 V or 2.8 V

IIN Input Current VDD=0 V −10 ±1 +10 μA

VIN =0 V or 2.8 V or 3.6 V

LVCMOS Output DC Specifications (Receiver Outputs)

VOH Output High Voltage IOH = -0.4 mA, VID= 200 mV 2.7 3.3 V

VOL Output Low Voltage IOL = 2 mA, VID = 200 mV ROUT 0.05 0.25 V

IOZ Output TRI-STATE Current Disabled, VOUT =0 V or VDD -10 ±1 +10 μA

General DC Specifications

IDD Power Supply Current(5) EN = 3.3 V 21 35 mA

VDD

IDDZ TRI-State Supply Current EN = 0 V 15 25 mA

(4) Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only.

(5) Both driver and receiver inputs are static. All LVDS outputs have 100 Ωload. All LVCMOS outputs are floating. None of the outputs

have any lumped capacitive load.

Product Folder Links: DS90LV049H

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SNLS200A –SEPTEMBER 2005–REVISED APRIL 2013

SWITCHING CHARACTERISTICS

VDD = +3.3V ± 10%, TA=−40°C to +125°C(1) (2)

Symbol Parameter Conditions Min Typ Max Units

LVDS Outputs (Driver Outputs)

tPHLD Differential Propagation Delay High to Low 0.7 2 ns

tPLHD Differential Propagation Delay Low to High 0.7 2 ns

tSKD1 Differential Pulse Skew |tPHLD −tPLHD|(3)(4) 0 0.05 0.4 ns

RL= 100 Ω

tSKD2 Differential Channel-to-Channel Skew(3)(5) 0 0.05 0.5 ns

(Figure 2 and Figure 3)

tSKD3 Differential Part-to-Part Skew(3)(6) 0 1.0 ns

tTLH Rise Time(3) 0.2 0.4 1 ns

tTHL Fall Time(3) 0.2 0.4 1 ns

tPHZ Disable Time High to Z 1.5 3 ns

tPLZ Disable Time Low to Z 1.5 3 ns

RL= 100 Ω

(Figure 4 and Figure 5)

tPZH Enable Time Z to High 1 3 6 ns

tPZL Enable Time Z to Low 1 3 6 ns

fMAX Maximum Operating Frequency(7) 200 250 MHz

LVCMOS Outputs (Receiver Outputs)

tPHL Propagation Delay High to Low 0.5 2 3.5 ns

tPLH Propagation Delay Low to High 0.5 2 3.5 ns

tSK1 Pulse Skew |tPHL −tPLH|(8) 0 0.05 0.4 ns

tSK2 Channel-to-Channel Skew(9) (Figure 6 and Figure 7) 0 0.05 0.5 ns

tSK3 Part-to-Part Skew(10) 0 1.0 ns

tTLH Rise Time(3) 0.3 0.9 1.4 ns

tTHL Fall Time(3) 0.3 0.75 1.4 ns

tPHZ Disable Time High to Z 3 5.6 8 ns

tPLZ Disable Time Low to Z 3 5.4 8 ns

(Figure 8 and Figure 9)

tPZH Enable Time Z to High 2.5 4.6 7 ns

tPZL Enable Time Z to Low 2.5 4.6 7 ns

fMAX Maximum Operating Frequency(11) 200 250 MHz

(1) All typical values are given for: VDD = +3.3 V, TA= +25°C.

(2) Generator waveform for all tests unless otherwise specified: f = 1 MHz, ZO= 50 Ω, tr≤1 ns, and tf≤1 ns.

(3) These parameters are specified by design. The limits are based on statistical analysis of the device performance over PVT (process,

voltage, temperature) ranges.

(4) tSKD1 or differential pulse skew is defined as |tPHLD −tPLHD|. It is the magnitude difference in the differential propagation delays between

the positive going edge and the negative going edge of the same driver channel.

(5) tSKD2 or differential channel-to-channel skew is defined as the magnitude difference in the differential propagation delays between two

driver channels on the same device.

(6) tSKD3 or differential part-to-part skew is defined as |tPLHD Max −tPLHD Min| or |tPHLD Max −tPHLD Min|. It is the difference between the

minimum and maximum specified differential propagation delays. This specification applies to devices at the same VDD and within 5°C of

each other within the operating temperature range.

(7) fMAX generator input conditions: tr= tf< 1 ns (0% to 100%), 50% duty cycle, 0 V to 3 V. Output Criteria: duty cycle = 45%/55%, VOD >

250 mV, all channels switching.

(8) tSK1 or pulse skew is defined as |tPHL −tPLH|. It is the magnitude difference in the propagation delays between the positive going edge

and the negative going edge of the same receiver channel.

(9) tSK2 or channel-to-channel skew is defined as the magnitude difference in the propagation delays between two receiver channels on the

same device.

(10) tSK3 or part-to-part skew is defined as |tPLH Max −tPLH Min| or |tPHL Max −tPHL Min|. It is the difference between the minimum and maximum

specified propagation delays. This specification applies to devices at the same VDD and within 5°C of each other within the operating

temperature range.

(11) fMAX generator input conditions: tr= tf< 1 ns (0% to 100%), 50% duty cycle, VID = 200 mV, VCM = 1.2 V . Output Criteria: duty cycle =

45%/55%, VOH > 2.7 V, VOL < 0.25 V, all channels switching.

Product Folder Links: DS90LV049H

Transmission Line

DC Block

Signal

Generator Transmission Line D

50 :

Oscilloscope

Z0 = 50 :

C = 15 pF Distributed

Z0 = 50 :

C = 15 pF Distributed

DIN

DOUT+

DOUT-

Power

Supply VDD EN

100 :

SMU

SMU D

DIN

DOUT+

DOUT-

Power

Supply VDD EN

100 :

NRND

DS90LV049H

SNLS200A –SEPTEMBER 2005–REVISED APRIL 2013

www.ti.com

PARAMETER MEASUREMENT INFORMATION

Figure 1. Driver VOD and VOS Test Circuit

Figure 2. Driver Propagation Delay and Transition Time Test Circuit

Figure 3. Driver Propagation Delay and Transition Time Waveforms

Product Folder Links: DS90LV049H

Transmission Line

Power

Supply

950 :50 :

Oscilloscope

Z0 = 50 :

C = 15 pF Distributed

ROUT

Power

Supply

Transmission Line

100 :

Z0 = 50 :

C = 15 pF Distributed RIN+

Signal

Generator Transmission Line

RIN-

VDD

Transmission Line

Signal

Generator Transmission Line

50 :

Oscilloscope

Z0 = 50 :

C = 15 pF Distributed

Z0 = 50 :

C = 15 pF Distributed

DOUT+

DOUT-

3.3 V DIN

VDD

100 :

2.4 V

1 k:

950 :

Power Supplies

2.4 V

NRND

DS90LV049H

www.ti.com

SNLS200A –SEPTEMBER 2005–REVISED APRIL 2013

PARAMETER MEASUREMENT INFORMATION (continued)

Figure 4. Driver TRI-STATE Delay Test Circuit

Figure 5. Driver TRI-STATE Delay Waveform

Figure 6. Receiver Propagation Delay and Transition Time Test Circuit

Product Folder Links: DS90LV049H

Transmission Line

Signal

Generator Transmission Line

50 :

950 :

50 :

Oscilloscope

Z0 = 50 :

C = 15 pF Distributed

Z0 = 50 :

C = 15 pF Distributed

ROUT

1.4 V 100 :

RIN+

1.0 V RIN-

VDD

Power Supplies

2.5 V 1 k:

NRND

DS90LV049H

SNLS200A –SEPTEMBER 2005–REVISED APRIL 2013

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PARAMETER MEASUREMENT INFORMATION (continued)

Figure 7. Receiver Propagation Delay and Transition Time Waveforms

Figure 8. Receiver TRI-STATE Delay Test Circuit

Product Folder Links: DS90LV049H

1.5 V

3 V

0 V

tPLZ

tPHZ

0.5 V

1.5 V 1.5 V

1.5 V

tPZL

tPZH

VDD / 2

VOL

VDD / 2

VOH

50%

OUT

0 V

3 V

NRND

DS90LV049H

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SNLS200A –SEPTEMBER 2005–REVISED APRIL 2013

PARAMETER MEASUREMENT INFORMATION (continued)

Figure 9. Receiver TRI-STATE Delay Waveforms

TYPICAL APPLICATION

Figure 10. Point-to-Point Application

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APPLICATION INFORMATION

General application guidelines and hints for LVDS drivers and receivers may be found in the following application

notes: LVDS Owner's Manual (lit #550062-003), AN-808 (SNLA028), AN-977 (SNLA166), AN-971 (SNLA165),

AN-916 (SNLA219), AN-805 (SNOA233), AN-903 (SNLA034).

LVDS drivers and receivers are intended to be primarily used in an uncomplicated point-to-point configuration as

is shown in Figure 10. This configuration provides a clean signaling environment for the fast edge rates of the

drivers. The receiver is connected to the driver through a balanced media which may be a standard twisted pair

cable, a parallel pair cable, or simply PCB traces. Typically, the characteristic differential impedance of the media

is in the range of 100 Ω. A termination resistor of 100 Ω(selected to match the media), and is located as close to

the receiver input pins as possible. The termination resistor converts the driver output current (current mode) into

a voltage that is detected by the receiver. Other configurations are possible such as a multi-receiver

configuration, but the effects of a mid-stream connector(s), cable stub(s), and other impedance discontinuities as

well as ground shifting, noise margin limits, and total termination loading must be taken into account.

The TRI-STATE function allows the device outputs to be disabled, thus obtaining an even lower power state

when the transmission of data is not required.

The DS90LV049H has a flow-through pinout that allows for easy PCB layout. The LVDS signals on one side of

the device easily allows for matching electrical lengths of the differential pair trace lines between the driver and

the receiver as well as allowing the trace lines to be close together to couple noise as common-mode. Noise

isolation is achieved with the LVDS signals on one side of the device and the TTL signals on the other side.

POWER DECOUPLING RECOMMENDATIONS

Bypass capacitors must be used on power pins. Use high frequency ceramic (surface mount is recommended)

0.1 μF and 0.001 μF capacitors in parallel at the power supply pin with the smallest value capacitor closest to the

device supply pin. Additional scattered capacitors over the printed circuit board will improve decoupling. Multiple

vias should be used to connect the decoupling capacitors to the power planes. A 10 μF (35 V) or greater solid

tantalum capacitor should be connected at the power entry point on the printed circuit board between the supply

and ground.

PC BOARD CONSIDERATIONS

Use at least 4 PCB layers (top to bottom); LVDS signals, ground, power, TTL signals.

Isolate TTL signals from LVDS signals, otherwise the TTL may couple onto the LVDS lines. It is best to put TTL

and LVDS signals on different layers which are isolated by a power/ground plane(s).

Keep drivers and receivers as close to the (LVDS port side) connectors as possible.

DIFFERENTIAL TRACES

Use controlled impedance traces which match the differential impedance of your transmission medium (that is,

cable) and termination resistor. Run the differential pair trace lines as close together as possible as soon as they

leave the IC (stubs should be < 10 mm long). This will help eliminate reflections and ensure noise is coupled as

common-mode. In fact, we have seen that differential signals which are 1 mm apart radiate far less noise than

traces 3 mm apart since magnetic field cancellation is much better with the closer traces. In addition, noise

induced on the differential lines is much more likely to appear as common-mode which is rejected by the

receiver.

Match electrical lengths between traces to reduce skew. Skew between the signals of a pair means a phase

difference between signals which destroys the magnetic field cancellation benefits of differential signals and EMI

will result. (Note the velocity of propagation, v = c/Er where c (the speed of light) = 0.2997 mm/ps or 0.0118

in/ps). Do not rely solely on the autoroute function for differential traces. Carefully review dimensions to match

differential impedance and provide isolation for the differential lines. Minimize the number or vias and other

discontinuities on the line.

Avoid 90° turns (these cause impedance discontinuities). Use arcs or 45° bevels.

Within a pair of traces, the distance between the two traces should be minimized to maintain common-mode

rejection of the receivers. On the printed circuit board, this distance should remain constant to avoid

discontinuities in differential impedance. Minor violations at connection points are allowable.

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SNLS200A –SEPTEMBER 2005–REVISED APRIL 2013

TERMINATION

Use a termination resistor which best matches the differential impedance or your transmission line. The resistor

should be between 90 Ωand 130 Ω. Remember that the current mode outputs need the termination resistor to

generate the differential voltage. LVDS will not work without resistor termination. Typically, connecting a single

resistor across the pair at the receiver end will suffice.

Surface mount 1% to 2% resistors are best. PCB stubs, component lead, and the distance from the termination

to the receiver inputs should be minimized. The distance between the termination resistor and the receiver

should be < 10 mm (12 mm MAX).

PROBING LVDS TRANSMISSION LINES

Always use high impedance (> 100 kΩ), low capacitance (< 2 pF) scope probes with a wide bandwidth (1 GHz)

scope. Improper probing will give deceiving results.

CABLES AND CONNECTORS, GENERAL COMMENTS

When choosing cable and connectors for LVDS it is important to remember:

Use controlled impedance media. The cables and connectors you use should have a matched differential

impedance of about 100 Ω. They should not introduce major impedance discontinuities.

Balanced cables (for example, twisted pair) are usually better than unbalanced cables (ribbon cable, simple

coax.) for noise reduction and signal quality. Balanced cables tend to generate less EMI due to field canceling

effects and also tend to pick up electromagnetic radiation a common-mode (not differential mode) noise which is

rejected by the receiver.

FAIL-SAFE FEATURE

An LVDS receiver is a high gain, high speed device that amplifies a small differential signal (20 mV) to CMOS

logic levels. Due to the high gain and tight threshold of the receiver, care should be taken to prevent noise from

appearing as a valid signal.

The receiver's internal fail-safe circuitry is designed to source/sink a small amount of current, providing fail-safe

protection (a stable known state of HIGH output voltage) for floating receiver inputs.

The DS90LV049H has two receivers, and if an application requires a single receiver, the unused receiver inputs

should be left OPEN. Do not tie unused receiver inputs to ground or any other voltages. The input is biased by

internal high value pull up and pull down current sources to set the output to a HIGH state. This internal circuitry

will ensure a HIGH, stable output state for open inputs.

External lower value pull up and pull down resistors (for a stronger bias) may be used to boost fail-safe in the

presence of higher noise levels. The pull up and pull down resistors should be in the 5 kΩto 15 kΩrange to

minimize loading and waveform distortion to the driver. The common-mode bias point should be set to

approximately 1.2 V (less than 1.75 V) to be compatible with the internal circuitry.

For more information on failsafe biasing of LVDS interfaces please refer to AN-1194.

PIN DESCRIPTIONS

Pin No. Name Description

10, 11 DIN Driver input pins, LVCMOS levels. There is a pull-down current source present.

6, 7 DOUT+ Non-inverting driver output pins, LVDS levels.

5, 8 DOUT−Inverting driver output pins, LVDS levels.

2, 3 RIN+ Non-inverting receiver input pins, LVDS levels. There is a pull-up current source present.

1, 4 RIN- Inverting receiver input pins, LVDS levels. There is a pull-down current source present.

14, 15 ROUT Receiver output pins, LVCMOS levels.

9, 16 EN, EN Enable and Disable pins. There are pull-down current sources present at both pins.

12 VDD Power supply pin.

13 GND Ground pin.

Product Folder Links: DS90LV049H

40 60 80 100 120 140 160

Resistor Load - RL [:]

0.25

0.30

0.35

0.40

0.45

Differential Output Voltage - VOD [V]

VDD = 3.3 V

TA = 25o C

0.1 1 10 100 1000

Frequency - f [MHz]

Power Supply Current - IDD [mA]

Single

Receiver

Switching

All

Switching

Single

Driver

Switching

VDD = 3.3 V

TA = 25o C

RL = 100 :

CL = 15 pF

VID = 0.4 V

VIN = 3.3 V

NRND

DS90LV049H

SNLS200A –SEPTEMBER 2005–REVISED APRIL 2013

www.ti.com

TYPICAL PERFORMANCE CURVES

Differential Output Voltage Power Supply Current

vs Load Resistor vs Frequency

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SNLS200A –SEPTEMBER 2005–REVISED APRIL 2013

REVISION HISTORY

Changes from Original (April 2013) to Revision A Page

• Changed layout of National Data Sheet to TI format .......................................................................................................... 12

Product Folder Links: DS90LV049H

PACKAGE OPTION ADDENDUM

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Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead/Ball Finish

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

DS90LV049HMT/NOPB NRND TSSOP PW 16 92 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM 90LV049

HMT

DS90LV049HMTX/NOPB NRND TSSOP PW 16 2500 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM 90LV049

HMT

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish

value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

PACKAGE OPTION ADDENDUM

www.ti.com 30-Oct-2013

Addendum-Page 2

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

DS90LV049HMTX/NOPB TSSOP PW 16 2500 330.0 12.4 6.95 5.6 1.6 8.0 12.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 6-Nov-2015

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

DS90LV049HMTX/NOPB TSSOP PW 16 2500 367.0 367.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 6-Nov-2015

Pack Materials-Page 2

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