KT3395Z - OPTEK TECHNOLOGY

128-Macrocell MAX® EPLDs

fax id: 6107

CY7C342B

Cypress Semiconductor Corporation • 3901 North First Stre et • S an Jo se • CA 95134 • 408-943-2600

October 1989 – Revised October 1995

1CY7C342B

Features

• 128 macrocells in 8 LAB s

• 8 dedicated input s, 52 bidirectional I/O pins

• Programmable i nterconnect array

• Advanced 0.65-micron CMOS technology to increase

performance

• Available in 68-pin HLCC, PLCC, and PGA

Functio nal Description

The CY7C342B is an Erasable Programmable Logic Device

(EPLD) in which CMOS EPROM cells are used to configure

logic functions within the device. The MAX architecture is

100% user configurable, allowing the devices to accommodate

a variety of independent logic functi ons.

The 128 macrocells in the CY7C342B are divided into 8 Logic

Array Blocks (LABs), 16 per LAB. There are 256 expander

product terms, 32 per LAB, to be used and shared by the mac-

rocells within each LAB.

Each LAB is interconnected with a programmable interconnect

arr ay, allowin g all signals to be r o uted throughout th e chip.

The speed and densi ty of the CY7 C3 42B allows it to be u sed i n a

wide range of applic ations, fr om replacem ent of lar ge amounts of

7400-series TTL logic, to complex controllers and multifunction

chips. With greater than 25 tim es the functional ity of 20-pin PLDs,

the CY7C342B allows the replacement of over 50 TTL devices. By

replacing large amounts of logic, the CY7C342B reduces board

space, part count, and increases system reliability.

MAX is a registered trademark of Altera Corporation.

Warp2

and

Warp3

are registered trademarks of Cypress Semiconductor.

MACROCELL 101

MACROCELL 100

MACROCELL 99

MACROCELL 98

MACROCELL 97

LogicBlockDiagram

C342B-1

MACROCELL 85

MACROCELL 84

MACROCELL 83

MACROCELL 82

MACROCELL 81

MACROCELL 33

MACROCELL 34

MACROCELL 35

MACROCELL 36

MACROCELL 37

MACROCELL 17

MACROCELL 18

MACROCELL 19

MACROCELL 20

MACROCELL 21

MACROCELL 1

MACROCELL 2

MACROCELL 3

MACROCELL 4

MACROCELL 5

MACROCELL 6

MACROCELL 7

MACROCELL 8 MACROCELL 121-128

MACROCELL 102-112

MACROCELL 86-96MACROCELL 38-48

MACROCELL 22-32

MACROCELL 9-16

SYSTEM CLOCK

INPUT (A7) 68

INPUT (A8) 66

INPUT (L6) 36

INPUT (K6) 35

(B8) 65

(A9) 64

(B9) 63

(A10) 62

(B10) 61

(B11) 60

(C11) 59

(C10) 58

(D11) 57

(D10) 56

(E11) 55

(F11) 53

(F10) 52

(G11) 51

(H11) 49

(H10) 48

(J11) 47

(J10) 46

(K11) 45

(K10) 44

(L10) 43

(L9) 42

(K9) 41

(L8) 40

(K8) 39

(L7) 38

4 (A5)

5(B4)

6 (A4)

7(B3)

8 (A3)

9 (A2)

10 (B2)

11 (B1)

12 (C2)

13 (C1)

14 (D2)

15 (D1)

17(E1)

18 (F2)

19 (F1)

21(G1)

22 (H2)

23 (H1)

24 (J2)

25 (J1)

26 (K1)

27 (K2)

28(L2)

29 (K3)

30(L3)

31 (K4)

LABH

LABG

LABF

LABE

LABA

LABB

LABC

LABD

3,20,37,54(B5,G2,K7,E10)

16, 33,50, 67 (E2, K5, G10,B7)

VCC

GND

( ) –PERTAIN TO 68-PIN PGA PACKAGE

1 (B6) INPUT/CLK

2 (A6) INPUT

32 (L4) INPUT

34 (L5) INPUT

MACROCELL 120

MACROCELL 119

MACROCELL 118

MACROCELL 117

MACROCELL 116

MACROCELL 115

MACROCELL 114

MACROCELL 113

MACROCELL 73-80

MACROCELL 72

MACROCELL 71

MACROCELL 70

MACROCELL 69

MACROCELL 68

MACROCELL 67

MACROCELL 66

MACROCELL 65

MACROCELL 57-64

MACROCELL 49

MACROCELL 50

MACROCELL 51

MACROCELL 52

MACROCELL 53

MACROCELL 54

MACROCELL 55

MACROCELL 56

CY7C342B

Selection Guide

7C342B–12 7C342B–15 7C342B–20 7C342B–25 7C342B–30 7C342B–35

Maximum Access Time (ns) 12 15 20 25 30 35

Maximum Operating

Cur rent (mA) Commercial 250 250 250 250 250 250

Military 320 320 320 320 320

Industrial 320 320 320 320 320

Maximum Static

Cur rent (mA) Commercial 225 225 225 225 225 225

Military 275 275 275 275 275

Industrial 275 275 275 275 275

Pin Configurations

I/O

Top View

PLCC

76 453

4342 44

4140

26 27

28 29 3130 32 33 3635 37 38 3934

C342B-2

66 65 6364 62

68 67 61

I/O

GND

I/O

VCC

I/O

GND

I/O

VCC

I/O

VCC

I/O

INPUT/

CLK

INPUT

GND

I/O I/O

VCC I/O

I/O I/O

GND I/O

I/O I/O

I/OI/O

I/O

VCC

INPUT

GND

INPUT

I/O

INPUT

I/O

I/OI/O

VCC

I/O

I/OI/O

GNDI/O

I/O

PGA

BottomView

C342B-3

I/O

INPUT INPUT I/O I/O

I/O I/O I/O I/O

1234567891011

7C342B

CY7C342B

Maximum Ratings

(Above which the useful life may be impaired. For user guide-

lines, not tested.)

Storage Temperat ure ......... ........................ .–65°C to+150°C

Ambient Temperature with

Power Applied............................ ........................0°C to+70°C

Maximum Junction Temperature

(under bias)........ ............................. ........................... ..150°C

Supply Volt age to Gro und Pote ntial.. ..............–3.0V to+7.0V

Maximum Power Dissipation........... ........................2500 mW

DC VCC or GND Current.. .......... ............ ............ ........500 mA

DC Output Curre nt per Pin.. ......... .............–25 mA t o+ 25 mA

DC Input Voltage[1] ..................... .. .................–3.0V to + 7.0V

DC Program Voltage ........................... ... ..... .................13.0V

Static Discharge Voltage...........................................>1100V

(pe r MIL-STD-883, Method 3015)

Operating Range

Range Ambient

Temperature VCC

Commercial 0°C to +70°C 5V ± 5%

Industrial –40°C to +85°C 5V ± 10%

Military –55°C to +125°C (Case) 5V ± 10%

Electrical Characteristics Over the Operating Range[2]

Parameter Description Test Conditions Min. Max. Unit

VOH Output HIGH Voltage VCC = Min., IOH = –4.0 mA 2.4 V

VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA 0.45 V

VIH Inp u t HIGH Voltage 2.2 VCC +0.3 V

VIL Input LOW Voltage –0.3 0.8 V

IIX Input Current GND < VIN < VCC –10 +10 µA

IOZ Outp ut Leakage Current VO = VCC or GND –40 +40 µA

IOS Output Short Circuit Current VCC = Max., VOUT = 0.5V[3, 4] –30 –90 mA

ICC1 Power Supply Current (Static) VI = GND (No Load) Com’l 225 mA

Mil/Ind 275

ICC2 Power Supply Current[5] VI = VCC or GND (No Load)

f = 1.0 MHz[4] Com’l 250 mA

Mil/Ind 320

tRRecommende d Inpu t Ris e T ime 100 ns

tFRecommended Input Fall Time 100 ns

Capacitance[6]

Parameter Description Test Conditions Max. Unit

CIN Input Capacitance VIN = 2V, f = 1.0 MH z 10 pF

COUT Output Capacitance VOUT = 2V, f = 1.0 MHz 10 pF

Notes:

1. Minimum DC input is –0.3V. During transitions, the inputs may undershoot to –3.0V for periods less than 20 ns.

2. Typical values are for TA = 25°C and VCC = 5V.

3. Not more than one output should be tested at a time. Duration of the short circuit should not be more than one second. VOUT = 0.5V has been chosen to avoid

test problems caused by tester ground degradation.

4. Guaranteed but not 100% tested.

5. This parameter is measured with device programmed as a 16-b it counter in each LAB.

6. Part (a) in AC Test Load and Waveforms is used for all parameters exce pt tER and tXZ, which is used for part (b) in AC Test Load and Waveforms. All external

timing parameters are measured referenced to external pins of the device.

CY7C342B

Logic Array Blocks

There are 8 logic array blocks in the CY7C342B. Each LAB

consists of a macrocell array containing 16 macrocells, an ex-

pander product term array containing 32 expanders, and an

I/O block. T he LAB is fed by the programmable interconnect

array and the dedicated input bus. All macrocell feedbacks go

to the macrocell array, th e expander array, and the program-

mable interco nnect array. Expanders feed themse lves and th e

macrocell array. All I/O feedbacks go to the programmable in-

terconnect array so that they may be accessed by macrocells

in other LABs as well as the macrocells in the LAB in which

they are situated.

Externally, the CY7C342B provides eight dedicated inputs,

one of wh ich may be used as a system cloc k. There are 52 I/O

pins that may be individually configured for input, output, or

bidirectio nal data f low.

Programmable Interconnect Array

The Programmable Interconnect Arra y (PIA) solves intercon-

nect limitations by routing only the signals needed by each

logic array block. The inputs to the PIA a re the outputs of every

macro cell within the device and the I/O pin feedback of every

pin on the device.

Unlike masked or programmable gate arrays, which induce

variable delay depe ndent on routing, the PIA has a fixed delay .

This eliminates undesired skews among logic signals that may

cause glitches in internal or external logic. The fixed delay,

regardless of programma ble interconnect array configuration,

simplifies design by assuring that internal signal skews or rac-

es are avoided. T he result is ease of design implementation,

often in a signal pas s, without the multiple internal logic place-

ment and routing iterations required for a programmable gate

array to achieve design timing objectives.

Timing Delays

Timing delay s within the CY7C342B may be easily determined

using

Warp2

® or

Warp3

® software by the model sh own in

Fig-

ure 1

. The CY7C342B ha s fixed internal delays, al lowing the

user to determine the worst case timing delays for an y des ign.

For complete timing informat ion the

Warp3

software provides

a timing simulator.

Design Recommendations

Operation of the devices described herein with conditions

above those li sted under “Maximum Ratings” may cause per-

manent damage to the device. This is a stress rating only and

functional operation of the device at these or any other condi-

tions above those indicated in the operational sections of this

datasheet is not implie d. Exposure to absolute maximum rat-

in gs conditions for extended periods o f time may affect device

reliabili ty. The CY7C342B contains circuitry to protect device

pins from high static voltages or electric fields, but normal pre-

cautions should be taken to avoid application of any voltage

higher than the maximum rated voltages.

For proper operation, input and output pins must be con-

strained to the range GND < (VIN or VOUT) < VCC. Unused

inputs must always be tied to an a ppropriate logic level (ei-

ther V CC or GND). E ach set of VCC and GN D pi ns must be

connecte d together directly at the device. Power supply de-

coupling capacitors of at least 0.2 µF must be connected

between VCC and GND. For the mo st effective decoupling,

each VCC pin should be separately decoupled to GND direct-

ly at the device. Decoupling capacitors should have good

frequency response, such as monolithic ceramic types have.

AC Test Loads and Waveforms[5]

3.0V

OUTPUT

R1 464Ω

250Ω

50 pF

INCLUDING

JIG AN D

SCOPE

GND

90%

10% 90%

10%

≤6ns ≤6ns

OUTPUT

R1 464Ω

250Ω

5pF

INCLUDING

JIG AND

SCOPE

(a) (b)

OUTPUT 1.75V

E quivalen t to: THÉ VENIN EQUIVALENT (commercial/military)

ALL INPUT PULSES

C342B-4 C342B-5

163Ω

CY7C342B

Figure 1. CY7C342B Internal Timing Model

LOGIC ARRAY

CONTROLDELAY

tLAC

EXPANDER

DELAY

tEXP

CLOCK

DELAY

tIC

tRD

tCOMB

tLATCH

INPUT

DELAY

tIN

OUTPUT

DELAY

tOD

tXZ

tZX

LOGIC ARRAY

DELAY

tLAD

FEEDBACK

DELAY

tFD

OUTPUT

INPUT

C342B-6

SYSTEM CLOCK DELAY tICS

tRH

tRSU

tPRE

tCLR

PIA

DELAY

tPIA

I/O DELAY

tIO

CY7C342B

Design Security

The CY7C342 B contains a programmable design se curity fea-

ture that controls th e a ccess to the data programmed into the

device. If this programmable feature is used, a proprietary de-

sign implemented in the device cannot be copied or retrieved.

This enables a high level of design control to be obtained since

programmed data within EPROM cells is invisible. The bit that

controls this function, along with all other program data, ma y

be reset simply by erasing t he entire device.

The CY7C342B is fully functionally tested and guaranteed

through complete testing of each programmable EPROM bit

and all internal lo gi c elements thus ensuring 100% pr ogram-

ming yield.

The erasable nature of th ese devices allows te st pr ograms to

be used and erased during ea rly stages of the production flow .

The devices also c ontain on- board logic te st circuit ry to allow

verification of function and AC specification once encapsulat-

ed in non-windowed packages.

Timing Considerations

Unless otherwise stated, propagation delays do not include

expanders. When using expanders, add the maximum ex-

pander delay tEXP to the o verall delay. Similarly, there is an

a ddi ti o nal t PIA delay for an input from an I/O pin whe n com -

pared to a signal from straight input pin.

When calculating synchronous frequencies, use tS1 if all in-

puts are on dedicated input pins. The parameter tS2 should

be used if data is applied at an I/O pin. If tS2 is gr eater t ha n

tCO1, 1/tS2 beco mes the lim iting frequency in th e data path

mode unless 1/(tWH + tWL) is less than 1/tS2.

When expander logic is used in t he data path, add the appro-

priate maximum expander delay , tEXP to tS1. De te rmine which

of 1/(tWH + tWL), 1/tCO1, or 1/(tEXP + tS1) is the lowest fre-

quency. The lowest of these frequencies is the maximum

data path frequency for the synchronous configuration.

When calculating external asynchronous frequencies, use

tAS1 if all inputs are on the dedicated input pins. If any data

is applied to an I/O pin, tAS2 must be used as the required

set-up time. If (tAS2 + tAH) is greate r than tACO1, 1 /(tAS2 + tAH)

becomes the limiting frequency in the data path mode unless

1/(tAWH + tAWL) is less than 1/(tAS2 + tAH).

When expander logic is used in t he data path, add the appro-

priate maximum expander delay, tEXP to tAS1. Determine

which of 1/(tAWH + tAWL), 1/tACO1, or 1/(tEXP + tAS1) is the

lowest frequency. The lowest of these frequencies is the

maximum data path frequency for the asynchronous config -

uration.

The parameter tOH indicates the system compatibility of this

device when driving other synchronous logic with positive

input hold times, which is controlled by the same synchro-

nous clock. If tOH is gre ater t han th e minimu m requ ired in put

h ol d ti me of the sub s eq u ent sy n c hro nou s logi c, then the de-

vices are guaranteed to function properly with a common

synchronous clock under worst-case environmental and

supply voltage conditions.

The parameter tAOH indicate s the syste m compatib ility of this

d evice when driving su bsequent registered logic wi th a pos -

itive hold time and using the same asynchronous clock as

the C Y7C34 2B.

In general, if tAOH is greate r than the minimum requ ired inp ut

hold time of the subsequent logic (synchronous or asynchro-

nous) then the d evices are guar anteed to function properly

under worst-case environmental and supply voltage condi-

tions, provided the clock signal source is the same. This also

applies if expand er logic is use d in the cl ock signal path of

the driving devic e, but not for th e driven dev ice. This is due

to the expander logic in the second device’s clock signal

path adding an additional delay (tEXP) causing the output

data from the preceding device to change prior to the arrival

o f t he c lo c k signa l at t h e f ol l ow i ng d e vi ce’s regist e r.

Typi c al ICC vs. fMAX

Output Drive Current

400

300

200

100

1 kHz 10 kHz 100 kHz 1 MHz

MAXIMUM FREQUENCY

10 MHz

050 MHz100 Hz

VCC=5.0V

RoomTemp.

01 2 3 4

OUTPUTVOLTAGE (V)

100

IOH

IOL

VCC=5.0V

RoomTemp.

0.45

CY7C342B

Commercial and I ndustri al External Synchronous Switching Characteristics[6] O ver Operat i ng R a n g e

7C342B–12 7C342B–15 7C342B–20

Parameter Description Min. Max. Min. Max. Min. Max. Unit

tPD1 Dedicated Input to Combinatorial Output Delay[7] 12 15 20 ns

tPD2 I/O Input to Combinatorial Output Delay[8] 20 25 32 ns

tPD3 Dedicated Input to Combinatorial Output Delay with

Expander Delay[9] 18 23 30 ns

tPD4 I/O Input to Combinatorial Output Delay with Expander

Delay[4,10] 26 33 42 ns

tEA Input to Output Enable Delay[4,7] 12 15 20 ns

tER Input to Output Di sable Delay[4,7] 12 15 20 ns

tCO1 Synchronous Clock Input to Output Delay 6 7 8 ns

tCO2 Synchronous Clock to Local Feedback to

Combinatorial Output [4,11] 14 17 20 ns

tS1 Dedicated Input or Feedback Set-Up Time to

Synchronous Clock Input[4,12] 810 13 ns

tS2 I/O Input Set-Up Time to Synchronous Clock Input[7] 16 20 24 ns

tHInput Hold Time from S ynchronous Clock Input[7] 0 0 0 ns

tWH Synchronous Clock Input HIGH Tim e 4.5 5 7 ns

tWL Synchronous Clock Input LOW Time 4.5 5 7 ns

tRW Asynchronous Clear Widt h[4,7] 12 15 20 ns

tRR Asynchronous Clear Recovery Time[4, 7] 12 15 20 ns

tRO Asyn chronous Clear to Registered Output Delay[7] 12 15 20 ns

tPW Asynchronous Preset W idth[4,7] 12 15 20 ns

tPR Asynchronous Preset Recovery Time[4,7] 12 15 20 ns

tPO Asynchronous Preset to Register ed Output Del ay[7] 12 15 20 ns

tCF Synchronous Clock to L ocal Feedback Input[4,13] 3 3 3 ns

tPExternal Synchronous Clock Period (1/(fMAX3))[4] 912 15 ns

fMAX1 External Feedback Maximum Fre quency

(1/(tCO1 + tS1))[4,14] 71.4 58.8 47.6 MHz

fMAX2 Internal Local Feedback Maximum Frequency, lesser of

(1/(tS1 + tCF)) or (1/tCO1)[4,15] 90.9 76.9 62.5 MHz

Notes:

7. This specification is a measure of the delay from input signal applied to a dedicated input (68-pin PLCC input pin 1, 2, 32, 34, 35, 66, or 68) to combinatorial

output on any output pin. This delay assumes no expander terms are used to form the logic function.

When th is note is appli ed to any parameter specificati on it indicates that the signal (d ata, asynchrono us clo ck, a synchronous clear, and/or a synchronous

preset) is applied to a dedicated input only and no signal path (either clock or data) employs expander logic.

If an input signal is applied to an I/O pin an additional delay equal to tPIA shoul d be added to t he com para ble delay for a dedica t ed inpu t. If expan d ers are

used, add the maximum expander delay tEXP to the overall delay for the comparable delay without expanders.

8. This specification is a measure of the delay from input signal applied to an I/O macroc ell pin to any output. This delay assumes no expander terms are used

to form the logic function.

9. This specification is a measure of the delay from an input signal applied to a dedicated input (68-pin PLCC input pin 1, 2, 32, 34, 35, 36, 66, or 68) to combinatorial output

on any output pin. This delay assumes expander terms are used to form the logic function and includes the worst-case expander logic delay for one pass through the

expander logic.

10. This specification is a measure of the delay from an input signal applied to an I/O macroc ell pin to any output. This delay assumes expander terms are used

to form the logic function and includes the worst-case expander logic delay for one pass through the expander logic. This parameter is tested periodically by

sampling production material.

11. This specification is a measure of the delay from synchronous register clock to internal feedback of the register output signal to the input of the LAB logic

array and then to a combinatorial output. This delay assumes no expanders are used, register is synchronously clocked and all feedback is within the same

LAB. This parameter is tested periodically by sampling production material.

12. If data is applied to an I/O input for capture by a macrocell register , the I/O pin input set-up time minimums should be observed. These parameters are tS2 for

synchronous operation and tAS2 for asynchronous operation.

13. This specification is a measure of the delay associated with the internal register feedback path. This is the delay from synchronous clock to LAB logic array

input. This delay plus the register set-up time, tS1, is the minimum internal period for an internal s ynchronous state machine configuration. This delay is for feedbac k

within the same LAB. This parameter is tested periodically by sampling production material.

14. This specification indicates the guaranteed maximum frequency, in synchronous mode, at which a state machine configuration with external feedback can

operate. It is assumed that all data inputs and feedback signals are applied to dedicated inputs. All feedback is assumed to be local originating within the

same LAB.

15. This specification indicates the guaranteed maximum frequency at which a state machine with internal-only feedback can operate. If register output states

must also control external points, this frequency can still be observed as long as this frequency is less than 1/tCO1.

CY7C342B

fMAX3 Data Path Maximum Frequenc y, lesser of ( 1/(tWL + tWH)),

(1/(tS1 + t H)) or (1/tCO1)[4,16] 111.1 100 71.4 MHz

fMAX4 Maximum Register To ggle Frequency (1/(tWL+tWH))[4,17] 111.1 100 71.4 MHz

tOH Output Data Stable Time from Synchronous Cloc k Input[4,18] 3 3 3 ns

Commercial and I ndustri al External Synchronous Switching Characteristics[6] O ver Operat i ng R a n g e

7C342B–12 7C342B–15 7C342B–20

Parameter Description Min. Max. Min. Max. Min. Max. Unit

7C342B–25 7C342B–30 7C342B–35

Parameter Description Min. Max. Min. Max. Min. Max. Unit

tPD1 Dedicated Input to Combinatorial Output Delay[7] 25 30 35 ns

tPD2 I/O Input to Combinatorial Output Delay[8] 39 46 55 ns

tPD3 Dedicated Input to Combinatorial Output Delay with

Expander Delay[9] 37 44 55 ns

tPD4 I/O Input to Combinatorial Output Delay with Expander

Delay[4,8] 51 60 75 ns

tEA Input to Output Enable Delay[4,8] 25 30 35 ns

tER Input to Output Di sable Delay[4,7] 25 30 35 ns

tCO1 Synchronous Clock Input to Output Delay 14 16 20 ns

tCO2 Synchronous Clock to Local Feedback to Combinator ial

Output[4,9] 30 35 42 ns

tS1 Dedicated Input or Feedback Set-Up Time to Synchronous

Clock Input[7,10] 15 20 25 ns

tS2 I/O Input Set-Up Time to Synchronous Clock Input[7] 29 36 45 ns

tHInput Hold Time from S ynchronous Clock Input[7] 0 0 0 ns

tWH Synchronous Clock Input HIGH Tim e 8 10 12.5 ns

tWL Synchronous Clock Input LOW Time 8 10 12.5 ns

tRW Asynchronous Clear Widt h[4,7] 25 30 35 ns

tRR Asynchronous Clear Recovery Time[4, 7] 25 30 35 ns

tRO Asyn chronous Clear to Registered Output Delay[7] 25 30 35 ns

tPW Asynchronous Preset W idth[4,7] 25 30 35 ns

tPR Asynchronous Preset Recovery Time[4,7] 25 30 35 ns

tPO Asynchronous Preset to Register ed Output Del ay[7] 25 30 35 ns

tCF Synchronous Clock to L ocal Feedback Input[4,11] 3 3 6 ns

tPExternal Synchronous Clock Period (1/(fMAX3))[4] 16 20 25 ns

fMAX1 External Feedback Maximum Fre quency

(1/(tCO1 + tS1))[4,12] 34.5 27.7 22.2 MHz

fMAX2 Internal Local Feedback Maximum Frequency, lesser of

(1/(tS1 + tCF)) or (1/tCO1)[4,13] 55.5 43.4 32.2 MHz

fMAX3 Data Path Maximum Frequenc y, lesser of ( 1/(tWL + tWH)),

(1/(tS1 + t H)) or (1/tCO1)[4,14] 62.5 50 40 MHz

fMAX4 Maximum Register To ggle Frequency (1/(tWL+tWH))[4,15] 62.5 50 40 MHz

tOH Output Data Stable Time from Synchronous Cloc k Input[4,16] 3 3 3 ns

Notes:

16. This frequency indicates the maximum frequency at which the device may operate in data path mode (dedicated input pin to output pin). This assumes data

input signals are applied to dedicated input pins and no expander logic is used. If any of the data inputs are I/O pins, tS2 is the appropriate tS for calculation.

17. This specification indicates the guaranteed maximum frequency, in synchronous mode, at which an individual output or buried register can be cycled by a

clock signal applied to the dedicated clock input pin.

18. This parameter indicates the minimum time after a synchronous register clock input that the previous register output data is maintained on the output pin.

CY7C342B

Commercial and I ndustri al External Asynchronous Switching Characteri stics[6] Over Oper at in g Ra nge

7C342B–12 7C342B–15 7C342B–20

Parameter Description Min. Max. Min. Max. Min. Max. Unit

tACO1 As ynchronous Clock Input to Output Delay[7] 12 15 20 ns

tACO2 Asy nchronou s Clock Input t o Lo cal Feedback t o Combinatori-

al Output[19] 20 25 32 ns

tAS1 Dedicate d Input or Feedback Set-Up Time to Asynchronous

Clock Input[7] 455ns

tAS2 I/O Input Set-U p Tim e to Asynchronous Clock Input[7] 12 14.5 17 ns

tAH Input H old Ti me from Asynchronous Clock Input[7] 456ns

tAWH As ynchronous Clock Input HIGH Time[7] 8 9 10 ns

tAWL Asynchronous Clock Input LOW Tim e[7 , 20 ] 678ns

tACF Asynchronous Clock to Local Feedback Input[4,21] 911 13 ns

tAP External Asynchronous Clock Period (1/(fMAXA4))[4] 14 16 18 ns

fMAXA1 External Feedback Maximum Frequency i n Asynchronous

Mode (1/(tACO1 + tAS1))[4,22] 62.5 50 40 MHz

fMAXA2 Maximum Internal Asynchronous Fr e quency[4,23] 71.4 62.5 55.5 MHz

fMAXA3 Data Path Maximum Frequency in Asynchronous Mode[4,24] 83.3 66.6 50 MHz

fMAXA4 Maximum Asynchronous Register Toggle Frequency

1/(tAWH + tAWL)[4,25] 71.4 62.5 55.5 MHz

tAOH Output Data Stable Time from Asynchronous Clock Input[4,26] 12 12 12 ns

Notes:

19. This specification is a measure of the delay from an asynchronous register clock input to internal feedback of the register output signal to the input of the LAB

logic array and then to a combinatorial output. This delay assumes no expanders are used in the logic of combinatorial output or the asynchronous clock input.

The clock signal is applied to the dedicated clock input pin and all feedback is within a single LAB. This parameter is tested periodically by sampling production

material.

20. This parameter is measured with a positive-edge triggered clock at the register. For negative edge triggering, the tAWH and tAWL parameters must be swapped.

If a given input is used to clock multiple registers with both positive and negative polarity, tAWH should be used for both tAWH and tAWL.

21. This specification is a measure of the delay associated with the internal register feedback path for an asynchr onous clock to LAB logic array input. This delay

plus the asynchronous register set-up time, tAS1, is the minimum internal period for an internal asynchronously clocked state machine configuration. This delay is for

feedback within the same LAB, assumes no expander logic in the clock path, and assumes that the clock input signal is applied to a dedicated input pin. This parameter

is tested periodically by sampling production material.

22. This specification indicates the guaranteed maximum frequency at which an asynchronously clocked state machine configuration with external feedback can

operate. It is assumed that all data inputs, clock inputs, and feedback signals are applied to dedicated inputs and that no expander logic is employed in the

clock signal path or data path.

23. This specification indicates the guaranteed maximum frequency at which an asynchronously clocked state machine with internal-only feedback can operate.

This parameter is determined by the lesser of (1/(tACF + tAS1)) or (1/(t AWH + tAWL)). If register output states must also control external points, this frequency can still be

observed as long as this frequency is less than 1/tACO1.

Thi s specif icatio n as sumes no e xpander l ogic i s util ized, all data in puts and clo c k inputs a re appl ied to d edi cate d in puts, and all state feedb a ck is withi n a

sing le LAB. This parameter is t ested periodically b y sam pling produ ction m aterial.

24. This frequency is the maximum frequency at which the device may operate in the asynchronously clocked data path mode. This specification is determined

by the lesser of 1/(tAWH + tAWL), 1/ (tAS1 + tAH) or 1/tACO1. It assumes data and clock input signals are applied to dedicated input pins and no expander logic is used.

25. This specification indicates the guaranteed maximum frequency at which an individual output or buried register can be cycled in asynchronously clocked mode

by a clock signal applied to an external dedicated input pin.

26. This parameter indicates the minimum time that the previous register output data is maintained on the output after an async hronous register clock i nput applied

to an external dedicated input pin.

CY7C342B

Commercial and I ndustri al External Asynchronous Switching Characteri stics[6] Over Oper at in g Ra nge

(continued)

7C342B–25 7C342B–30 7C342B–35

Parameter Description Min. Max. Min. Max. Min. Max. Unit

tACO1 As ynchronous Clock Input to Output Delay[7] 25 30 35 ns

tACO2 Asy nchronou s Clock Input to Loc al Feed back to Combinatori-

al Output[19] 39 46 55 ns

tAS1 Dedicate d Input or Feedback Set-Up Time to Asynchronous

Clock Input[7] 568ns

tAS2 I/O Input Set-U p Tim e to Asynchronous Clock Input[7] 19 22 28 ns

tAH Input H old Ti me from Asynchronous Clock Input[7] 6 8 10 ns

tAWH As ynchronous Clock Input HIGH Time[7] 11 14 16 ns

tAWL Asynchronous Clock Input LOW Tim e[7 , 20 ] 911 14 ns

tACF Asynchronous Clock to Local Feedback Input[4,21] 15 18 22 ns

tAP External Asynchronous Clock Period (1/(fMAXA4))[4] 20 25 30 ns

fMAXA1 External Feedback Maximum Frequency i n Asynchronous

Mode (1/(tACO1 + tAS1))[4,22] 33.3 27.7 23.2 MHz

fMAXA2 Maximum Internal Asynchronous Fr e quency[4,23] 50 40 33.3 MHz

fMAXA3 Data Path Maximum Frequency in Asynchronous Mode[4,24] 40 33.3 28.5 MHz

fMAXA4 Maximum Asynchronous Register Toggle Frequency

1/(tAWH + tAWL)[4,25] 50 40 33.3 MHz

tAOH Output Data Stable Time from Asynchronous Clock Input[4,26] 15 15 15 ns

Commercial and Industri al Typical Intern al Switching C h aracte ristics Over Operating Range

7C342B–12 7C342B–15 7C342B–20

Parameter Description Min. Max. Min. Max. Min. Max. Unit

tIN Dedicated Input Pad and Buffer Delay 2.5 3 4 ns

tIO I/O Input Pad and Buffer Delay 2.5 3 4 ns

tEXP Expander Array Delay 6 8 10 ns

tLAD L ogic Arra y Data Delay 6 8 10 ns

tLAC L o gic Arr ay Co ntrol Delay 5 5 7 ns

tOD Output Buffer and Pad Delay 3 3 3 ns

tZX Output Buffer Enable Delay[27] 5 5 5 ns

tXZ Output Buffer Disable Dela y 5 5 5 ns

tRSU Register Set-Up Tim e Relati ve t o Clock Signal at Register 2 4 5 ns

tRH Register Hold Time Relative to Clock Signal at Register 4 4 5 ns

tLATCH Flow Through Latch Delay 1 1 2 ns

tRD Register Delay 0.5 1 1 ns

tCOMB Transparent Mode Delay[28] 1 1 2 ns

tCH Clock HIGH Tim e 3 4 6 ns

tCL Clock LOW Tim e 3 4 6 ns

tIC Asynchronous Clock Logic Delay 5 6 8 ns

tICS Synchronous Clock Delay 0.5 0.5 0.5 ns

tFD Feedback Delay 1 1 1 ns

tPRE Asynchronous Register Preset Time 3 3 3 ns

Notes:

27. Sample tested only for an output change of 500 mV.

28. This specification guarantees the maximum combinatorial delay associated with the macrocell register bypass when the macrocell is configured for combi-

natorial operation.

CY7C342B

tCLR A s ynchronous Register Clear Time 3 3 3 ns

tPCW Asynchronous Preset and Cl ear Pulse Width 2 3 4 ns

tPCR Asynchronous Preset and Clear Recovery Time 2 3 4 ns

tPIA Programmable Interconnect Array Delay Time 8 10 12 ns

Commercial and Industri al Typical Intern al Switching C h aracte ristics Over Operating Range (continued)

7C342B–12 7C342B–15 7C342B–20

Parameter Description Min. Max. Min. Max. Min. Max. Unit

Commercial and Industri al Typical Intern al Switching C h aracte ristics Over Operating Range (continued)

7C342B–25 7C342B–30 7C342B–35

Parameter Description Min. Max. Min. Max. Min. Max. Unit

tIN Dedicated Input Pad and Buffer Delay 5 7 9 ns

tIO I/O Input Pad and Buffer Delay 6 6 9 ns

tEXP Expander Array Delay 12 14 20 ns

tLAD Logic Array Dat a Delay 12 14 16 ns

tLAC Logic Array Control Delay 10 12 13 ns

tOD O utp ut Buffer a nd Pad Delay 5 5 6 ns

tZX Output Buffer Enable Delay[27] 10 11 13 ns

tXZ Output Buffer Disable Delay 10 11 13 ns

tRSU Register Set-Up Time Relative to Clock Signal at Register 6 8 10 ns

tRH Register Hold Time Relative to Clock Signal at Register 6 8 10 ns

tLATCH Fl ow Through Latch Delay 3 4 4 ns

tRD R egister Delay 1 2 2 ns

tCOMB Transparent Mode Delay[28] 344ns

tCH C lock HIGH Time 8 10 12.5 ns

tCL Clock LOW Time 8 10 12.5 ns

tIC Asynchro nous Clock Logic Delay 14 16 18 ns

tICS Synchronous Clock Delay 2 2 3 ns

tFD Feedback Delay 1 1 2 ns

tPRE Asynchronous Register Preset Time 5 6 7 ns

tCLR Asynchronous Register Clear Tim e 5 6 7 ns

tPCW Asynchronous Preset and Clear Pulse Width 5 6 7 ns

tPCR Asynchronous Preset and Clear Recovery Tim e 5 6 7 ns

tPIA Programmable Interconnect Array Delay Time 14 16 20 ns

CY7C342B

Military External Synchronous Switching Characteristics[6] Over Operating Range

7C342B–15 7C342B–20 7C342B–25 7C342B–30 7C342B–35

Parameter Description Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit

tPD1 Dedicated Input to Combinatori-

al Output Delay[7] 15 20 25 30 35 ns

tPD2 I/O Input to Combinator ial

Output Delay[8] 25 32 39 46 55 ns

tPD3 Dedicated Input to Combinatori-

al Output Delay with Expander

Delay[9]

23 30 37 44 55 ns

tPD4 I/O Input to Combinator ial

Output Delay with

Expander Delay[4,10]

33 42 51 60 75 ns

tEA Inp u t to Output Enable

Delay[4,7] 15 20 25 30 35 ns

tER Input to Output Disable

Delay[4,7] 15 20 25 30 35 ns

tCO1 Synchronous Clock Input to

Output Delay 7 8 14 16 20 ns

tCO2 Synchronous Clock to Local

Feedback to Combinatorial

Output[4, 1 1]

17 20 30 35 42 ns

tS1 Dedicated Input or Feedback

Set-Up Time to Synchronous

Clock I nput[7,12]

10 13 15 20 25 ns

tS2 I/O Input Set-Up Time to

Synchronous Clock Input[7] 20 24 29 36 45 ns

tHInput Hold Time from

Synchronous Clock Input[7] 00000ns

tWH Synchronous Clock Input

HIGH Time 5 7 8 10 12.5 ns

tWL Synchronous Clock Input

LOW Time 5 7 8 10 12.5 ns

tRW Asynchronous Clear Width[4, 7] 15 20 25 30 35 ns

tRR Asynchronous Clear Recovery

Time[4, 7] 15 20 25 30 35 ns

tRO Asynchronous Clear to Regis-

tered Output Delay[7] 15 20 25 30 35 ns

tPW Asynchronous Preset Width[4,7] 15 20 25 30 35 ns

tPR Asynchronous Preset

Recover y Time[4,7] 15 20 25 30 35 ns

tPO Asynchronous Preset to Regis-

tered Output Delay[7] 15 20 25 30 35 ns

tCF Synchronous Clock to Local

Feedback Input[4,13] 33336ns

tPExtern al Synchronous Clock

Period (1/(fMAX3))[4] 12 14 16 20 25 ns

fMAX1 Extern al Feedback Maximum

Frequency (1/(tCO1 + tS1))[4,14] 58.8 47.6 34.5 27.7 22.2 MHz

fMAX2 Internal Local Feedback

Maximum Frequency, lesser of

(1/(tS1 + tCF)) or (1/t CO1)[4,15]

76.9 62.5 55.5 43.4 32.2 MHz

CY7C342B

fMAX3 Data Path Maximum Frequency ,

lesser of ( 1/(t WL + tWH)),

(1/(tS1 + tH)) or (1/tCO1)[4,16]

100 71.4 62.5 50 40 MHz

fMAX4 M aximum Register Tog gle

Frequency (1/(tWL + tWH))[4,17] 100 71.4 62.5 50 40 MHz

tOH Output Data Stable Time from

Synchronous Clock Input[4,18] 33333ns

Military External Synchronous Switching Characteristics[6] Over Operating Range (continued)

7C342B–15 7C342B–20 7C342B–25 7C342B–30 7C342B–35

Parameter Description Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit

Military External Asynchronous Switching Characteristics[6] Over Operating Range

7C342B–15 7C342B–20 7C342B–25 7C342B–30 7C342B–35

Parameter Description Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit

tACO1 Asynchronous Clock Input to

Output Delay[7] 15 20 25 30 35 ns

tACO2 Asynchronous Clock Input to

Local Fe edback to Co mbina tori-

al Output[19]

25 32 39 46 55 ns

tAS1 Dedicated Input or Feedback

Set-Up Time to Asynchronous

Clock Input[7]

5 5 5 6 8 ns

tAS2 I/O Input Set-Up Time to

Asynchronous Clock Input[7] 14.5 17 19 22 28 ns

tAH Input Hold Time from

Asynchronous Clock Input[7] 5 6 6 8 10 ns

tAWH Asynchronous Clock Input

HIGH Time[7] 910 11 14 16 ns

tAWL Asynchronous Clock Input

LOW Time[7, 20] 7 8 9 11 14 ns

tACF Asynchronous Clock to Local

Feedback Input[4,21] 11 13 15 18 22 ns

tAP External Asynchronous Clock

Period (1/(fMAXA4))[4] 16 18 20 25 30 ns

fMAXA1 Ext ernal Feedback Maximum

Frequency in Asynchr onous

Mo de (1/( tACO1 + tAS1))[4,22]

50.0 40 33.3 27.7 23.2 MHz

fMAXA2 Maxi mum Internal Asynchro-

nous Frequency[4,23] 62.5 55.5 50 40 33.3 MHz

fMAXA3 Data Path Maximum Frequency

in Asynchronous Mode[4,24] 66.6 50 40 33.3 28.5 MHz

fMAXA4 Maxi mum Asynchronous

1/(tAWH + tAWL)[4,25]

62.5 55.5 50 40 33.3 MHz

tAOH Output Data Stable Time from

Asynchronous Clock Input[4,26] 12 12 15 15 15 ns

CY7C342B

Mil itary Typical Internal Switching Characteristics Over Operating Range

7C342B–15 7C342B–20 7C342B–25 7C342B–30 7C342B–35

Parameter Description Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit

tIN Dedicated Input Pad and

Buffer Delay 34579ns

tIO I/O Input Pad and Buffer Delay 3 4 6 6 9 ns

tEXP Expander Array Delay 8 10 12 14 20 ns

tLAD Logic Array Data Dela y 8 10 12 14 16 ns

tLAC Logic Array Control Delay 5 7 10 12 13 ns

tOD Out put Buffer and Pad Dela y 3 3 5 5 6 ns

tZX Output Buffer Enable Delay[27] 5 5 10 11 13 ns

tXZ Output Buffer Disable Delay 5 5 10 11 13 ns

tRSU Register Set-Up Time Relative

to Clock Signal at Register 4 5 6 8 10 ns

tRH Register Hold Time R elative

to Clock Signal at Register 4 5 6 8 10 ns

tLATCH Flow T hrough Latch Dela y 1 2 3 4 4 ns

tRD Register Delay 1 1 1 2 2 ns

tCOMB Transparent Mode Delay[28] 12344ns

tCH Clock HIGH Time 4 6 8 10 12.5 ns

tCL Clock LOW Time 4 6 8 10 12.5 ns

tIC Asynchronous Clock Logic Delay 6 8 14 16 18 ns

tICS Synchronous Clock Delay 0.5 0.5 2 2 3 ns

tFD Feedback Delay 1 1 1 1 2 ns

tPRE Asynchronous Register Preset

Time 33567ns

tCLR Asynchronous Register Clear

Time 33567ns

tPCW Asynchronous Preset and

Clear Pulse Width 34567ns

tPCR Asynchronous Preset and

Clear Recovery Time 34567ns

tPIA Programmable Interconnect

Array Delay Time 10 12 14 16 20 ns

CY7C342B

Switching Waveforms

tACO1

External Combinatorial

External Synchronous

External Asynchronous

tER

tEA VALID OUTPUT

DEDICATED INPUT/

I/O INPUT

COMBINATORIAL

OUTPUT

COMBINATORIAL OR

REGISTERED OUTPUT

C342B-7

HIGH-IMPEDANCE

THREE-STATE

HIGH-IMPEDANC

THREE-STATE

tS1 tWH tWL

tRR/tPR

tRW/tPW

tOH

tCO1

tRO/tPO

tCO2

C342B-8

DEDICATED INPUTS OR

REGISTERED

FEEDBACK

SYNCHRONOUS

CLOCK

ASYNCHRONOUS

CLEAR/PRESET

REGISTERED

OUTPUTS

COMBINATORIAL

REGISTERED FEEDBACK

tAH

tAS1 tAWH tAWL

tRR/tPR

tRW/tPW

tAOH

tRO/tPO

tACO2

ASYNCHRONOUS

CLOCK INPUT

ASYNCHRONOUS

OUTPUTS

DEDICATED INPUTS OR

REGISTERED FEEDBACK

ASYNCHRONOUS

CLEAR/PRESET

COMBINATORIAL

ASYNCHRONOUS

FEEDBACK C342B-9

[7]

[11]

[7]

tPD1 /tPD2[8]

OUTPUT FROM

REGISTERED

OUTPUT FROM

REGISTERED

CY7C342B

Switching Waveforms (continued)

Internal Combinatorial

Internal Asynchronous

InternalSynchronous

tIN

tIO tPIA

tEXP

tLAC,tLAD

C342B-10

INPUT PIN

EXPANDER

I/O PIN

LOGIC ARRAY

tIO tAWH tAWL tF

tIN

tIC

tRSU tRH

tRD,tLATCH tFD tCLR,tPRE tFD

ARRAY DELAY

OUTPUT

LOGIC ARRAY

INPUT

CLOCK PIN

LOGIC ARRAY

CLOCK FROM

DATA FROM

CLOCK INTO

LOGIC ARRAY

TO ANOTHER LAB

tPIA

TO LOCAL LAB

LOGIC ARRAY

C342B-11

tCH tCL

tIN tICS

tRSU tRH

C342B-12

SYSTEM CLOCK PIN

SYSTEM CLOCK

AT REGISTER

DATA FROM

LOGIC ARRAY

CY7C342B

Switching Waveforms (continued)

Internal Synchronous

C342B-13

tXZ tZX

tOD

HIGH IMPEDANCE

CLOCK FROM

LOGIC ARRAY

DATA FROM

OUTPUT PIN

tRD

STATE

Orde rin g Inf orm a tio n

Speed

(ns) Orderi n g Cod e Package

Name Package Type Operating

Range

12 CY7C342B–12HC H81 68-Pin Windowed Leaded Chip Car rier Commercial

CY7C342B–12JC J81 68-Lead Pl a stic Leaded Chip Carrier

CY7C342B–12RC R68 68-Pin Windowed Ceramic Pin Grid Array

15 CY7C342B–15HC/HI H81 68-Pin Windowed Leaded Chip Carrier Commercial/

Industrial

CY7C342B–15JC/JI J81 68-Lead Pl a stic Leaded Chi p Carrier

CY7C342B–15RC/RI R68 68-Pin Windowed Ceramic Pin Grid Array

CY7C342B–15HMB H81 68-Pin Windowed Leaded Chip Car rier Military

CY7C342B–15RMB R68 68-Pin Windowed Ceramic Pin Grid Array

20 CY7C342B–20HC/HI H81 68-Pin Windowed Leaded Chip Carrier Commercial/

Industrial

CY7C342B–20JC/JI J81 68-Lead Pl a stic Leaded Chi p Carrier

CY7C342B–20RC/RI R68 68-Pin Windowed Ceramic Pin Grid Array

CY7C342B–20HMB H81 68-Pin Windowed Leaded Chip Car rier Military

CY7C342B–20RMB R68 68-Pin Windowed Ceramic Pin Grid Array

25 CY7C342B–25HC/HI H81 68-Pin Windowed Leaded Chip Carrier Commercial/

Industrial

CY7C342B–25JC/JI J81 68-Lead Pl a stic Leaded Chi p Carrier

CY7C342B–25RC R68 68-Pin Windowed Ceramic Pin Grid Array

CY7C342B–25HMB H81 68-Pin Windowed Leaded Chip Car rier Military

CY7C342B–25RMB R68 68-Pin Windowed Ceramic Pin Grid Array

30 CY7C342B–30HC/HI H81 68-Pin Windowed Leaded Chip Carrier Commercial/

Industrial

CY7C342B–30JC/JI J81 68-Lead Pl a stic Leaded Chi p Carrier

CY7C342B–30RC/RI R68 68-Pin Windowed Ceramic Pin Grid Array

CY7C342B–30HMB H81 68-Pin Windowed Leaded Chip Car rier Military

CY7C342B–30RMB R68 68-Pin Windowed Ceramic Pin Grid Array

35 CY7C342B–35HC/HI H81 68-Pin Windowed Leaded Chip Carrier Commercial/

Industrial

CY7C342B–35JC/JI J81 68-Lead Pl a stic Leaded Chi p Carrier

CY7C342B–35RC/RI R68 68-Pin Windowed Ceramic Pin Grid Array

CY7C342B–35HMB H81 68-Pin Windowed Leaded Chip Car rier Military

CY7C342B–35RMB R68 68-Pin Windowed Ceramic Pin Grid Array

CY7C342B

MIL ITARY SPECIFICATIONS

Group A Subgroup Testing

Document #: 38–00119–G

DC Characteristics

Parameter Subgroups

VOH 1, 2, 3

VOL 1, 2, 3

VIH 1, 2, 3

VIL 1, 2, 3

IIX 1, 2, 3

IOZ 1, 2, 3

ICC1 1, 2, 3

Switching Characteristics

Parameter Subgroups

tPD1 7, 8, 9, 10, 11

tPD2 7, 8, 9, 10, 11

tPD3 7, 8, 9, 10, 11

tCO1 7, 8, 9, 10, 11

tS1 7, 8, 9, 10, 11

tS2 7, 8, 9, 10, 11

tH7, 8, 9, 10, 11

tWH 7, 8, 9, 10, 11

tWL 7, 8, 9, 10, 11

tRO 7, 8, 9, 10, 11

tPO 7, 8, 9, 10, 11

tACO1 7, 8, 9, 10, 11

tAS1 7, 8, 9, 10, 11

tAH 7, 8, 9, 10, 11

tAWH 7, 8, 9, 10, 11

tAWL 7, 8, 9, 10, 11

CY7C342B

Package Diagrams

68-Pin WindowedLeaded Chip Carrier H81

CY7C342B

of any circuitry othe r than circui try embodi ed in a Cy press Semi conductor p roduct. Nor does it convey o r imply any li cense under patent o r other rights. Cypress Semicondu ctor does not authorize

its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

Semiconductor products in life-support systems application implies that the manufacturer as sumes all risk of such use and in doing so indemnifies Cypress Semiconductor again st all charges.

Package Diagrams (continued)

68-Lead Plastic Leaded Chip Carrier J81

68-Pin Windowed PGA Ceramic R68