Rev.1.00, May.24.2007, page 1 of 15
R1LV0416D Series
4M SRAM (256-kword × 16-bit)
REJ03C0311-0100
Rev.1.00
May.24.2007
Description
The R1LV0416D is a 4-Mbit static RAM organized 256-kword × 16-bit, fabricated by Renesas's high-performance 0.15µm
CMOS and TFT technologies. R1LV0416D Series has realized higher density, higher performance and low power
consumption. The R1LV0416D Series offers low power standby power dissipation; therefore, it is suitable for battery
backup systems. The R1LV0416D Series is packaged in a 44-pin thin small outline mount device, or a 48-ball fine pitch
ball grid array.
Features
Single 3.0 V supply: 2.7 V to 3.6 V
Fast access time: 55/70 ns (max)
Power dissipation:
Standby: 3 µW (typ) (VCC = 3.0 V)
Equal access and cycle times
Common data input and output.
Three state output
Battery backup operation.
2 chip selection for battery backup
Temperature Range: -40 to +85°C
R1LV0416D Series
Ordering Information
Type No. Access time Package
R1LV0416DSB-5SI 55 ns 400-mil 44-pin plastic TSOP II
R1LV0416DSB-7LI 70 ns PTSB0044GA-A (44P3W-H)
R1LV0416DBG-5SI 55 ns 48-ball CSP with 0.75 mm ball pitch
R1LV0416DBG-7LI 70 ns PTBG0048HB-A (48FHH)
Rev.1.00, May.24.2007, page 2 of 15
R1LV0416D Series
Pin Arrangement
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A4
A3
A2
A1
A0
CS1#
I/O0
I/O1
I/O2
I/O3
V
V
I/O4
I/O5
I/O6
I/O7
WE#
A17
A16
A15
A14
A13
CC
SS
A5
A6
A7
OE#
UB#
LB#
I/O15
I/O14
I/O13
I/O12
V
V
I/O11
I/O10
I/O9
I/O8
CS2
A8
A9
A10
A11
A12
CC
SS
(Top view)
44-pin TSOP
(Top view)
48-ball CSP
A
B
C
D
E
F
G
H
1 2 3 4 5 6
LB#
I/O8
I/O9
VSS
VCC
I/O14
I/O15
NC
OE#
UB#
I/O10
I/O11
I/O12
I/O13
NC
A8
A3
A5
A17
NC
A14
A0
A12
A9
A1
A4
A6
A7
A16
A15
A13
A10
A2
CS1#
I/O1
I/O3
I/O4
I/O5
WE#
A11
CS2
I/O0
I/O2
VCC
VSS
I/O6
I/O7
NC
Pin Description
Pin name Function
A0 to A17 Address input
I/O0 to I/O15 Data input/output
CS1# (CS1) Chip select 1
CS2 Chip select 2
OE# (OE) Output enable
WE# (WE) Write enable
LB# (LB) Lower byte select
UB# (UB) Upper byte select
VCC Power supply
VSS Ground
NC No connection
Rev.1.00, May.24.2007, page 3 of 15
R1LV0416D Series
Block Diagram
I/O0
I/O15
CS2
WE#
OE#
A0 A1 A2 A4 A17
V
V
CC
SS
Row
decoder
Memory matrix
2,048 x 2,048
Column I/O
Column decoder
Input
data
control
Control logic
A5
A13
A7
A8
A9
A10
A11
A12
A6
A14
A15
A16
CS1#
LB#
UB#
A3
LSB
MSB
LSB MSB
Rev.1.00, May.24.2007, page 4 of 15
R1LV0416D Series
Operation Table
CS1# CS2 WE# OE# UB# LB# I/O0 to I/O7 I/O8 to I/O15 Operation
H × × × × × High-Z High-Z Standby
× L × × × × High-Z High-Z Standby
× × × × H H High-Z High-Z Standby
L H H L L L Dout Dout Read
L H H L H L Dout High-Z Lower byte read
L H H L L H High-Z Dout Upper byte read
L H L × L L Din Din Write
L H L × H L Din High-Z Lower byte write
L H L × L H High-Z Din Upper byte write
L H H H × × High-Z High-Z Output disable
Note: H: VIH, L: VIL, ×: VIH or VIL
Absolute Maximum Ratings
Parameter Symbol Value Unit
Power supply voltage relative to VSS V
CC 0.5 to +4.6 V
Terminal voltage on any pin relative to VSS V
T 0.5*1 to VCC + 0.3*2 V
Power dissipation PT 0.7 W
Operating temperature1 Topr 40 to +85 °C
Storage temperature range Tstg 65 to +150 °C
Storage temperature range under bias Tbias 40 to +85 °C
Notes: 1. VT min: 3.0 V for pulse half-width 30 ns.
2. Maximum voltage is +4.6 V.
DC Operating Conditions
Parameter Symbol Min Typ Max Unit Note
VCC 2.7 3.0 3.6 V Supply voltage
VSS 0 0 0 V
Input high voltage VIH 2.2 V
CC + 0.3 V
Input low voltage VIL 0.3 0.6 V 1
Ambient temperature range Ta 40+85 °C
Note: 1. VIL min: 3.0 V for pulse half-width 30 ns.
Rev.1.00, May.24.2007, page 5 of 15
R1LV0416D Series
DC Characteristics
Parameter Symbol Min Typ Max Unit Test conditions
Input leakage current |ILI|   1 µA Vin = VSS to VCC
Output leakage current |ILO|   1 µA CS1# = VIH or CS2 = VIL or
OE# = VIH or WE# = VIL or
LB# = UB# = VIH,
VI/O = VSS to VCC
Operating current ICC   20 mA CS1# = VIL, CS2 = VIH,
Others = VIH/VIL, II/O = 0 mA
ICC1   25 mA Min. cycle, duty = 100%,
II/O = 0 mA, CS1# = VIL,
CS2 = VIH,
Others = VIH/VIL
Average operating current
ICC2   5 mA Cycle time = 1 µs,
duty = 100%,
II/O = 0 mA, CS1# 0.2 V,
CS2 VCC 0.2 V
VIH VCC 0.2 V, VIL 0.2 V
Standby current ISB 0.1*1 0.3 mA CS2 = VIL
to +85°C ISB1   10 µA
to +70°C ISB1   8 µA
to +40°C ISB1   3 µA
5SI
to +25°C ISB1 1*1 2.5 µA
to +85°C ISB1   20 µA
to +70°C ISB1   16 µA
to +40°C ISB1   10 µA
Standby current
7LI
to +25°C ISB1 1*1 10 µA
Vin 0 V
(1) 0 V CS2 0.2 V or
(2) CS1# VCC 0.2 V,
CS2 VCC 0.2 V or
(3) LB# = UB# VCC 0.2 V,
CS2 VCC 0.2 V,
CS1# 0.2 V
Average values
VOH 2.4 V IOH = 1 mA Output high voltage
VOH2 V
CC 0.2 V IOH = 100 µA
VOL 0.4 V IOL = 2 mA Output low voltage
VOL2 0.2 V IOL = 100 µA
Note: 1. Typical values are at VCC = 3.0 V, Ta = +25°C and specified loading, and not guaranteed.
Capacitance
(Ta = +25°C, f = 1.0 MHz)
Parameter Symbol Min Typ Max Unit Test conditions Note
Input capacitance Cin   8 pF Vin = 0 V 1
Input/output capacitance CI/O   10 pF VI/O = 0 V 1
Note: 1. This parameter is sampled and not 100% tested.
Rev.1.00, May.24.2007, page 6 of 15
R1LV0416D Series
AC Characteristics
(Ta = -40 to +85°C, VCC = 2.7 V to 3.6 V)
Test Conditions
Input pulse levels: VIL = 0.4 V, VIH = 2.4 V
50pF
Dout
RL=500
1.4 V
Output load
Input rise and fall time: 5 ns
Input/output timing reference levels: 1.4 V
Output load: See figures (Including scope and jig)
Rev.1.00, May.24.2007, page 7 of 15
R1LV0416D Series
Read Cycle
R1LV0416D
-5SI -7LI
Parameter Symbol Min Max Min Max Unit Notes
Read cycle time tRC 55 70 ns
Address access time tAA 55 70 ns
tACS1 55 70 ns Chip select access time
tACS2 55 70 ns
Output enable to output valid tOE 35 40 ns
Output hold from address change tOH 10 10 ns
LB#, UB# access time tBA 55 70 ns
tCLZ1 10 10 ns 2, 3 Chip select to output in low-Z
tCLZ2 10 10 ns 2, 3
LB#, UB# disable to low-Z tBLZ 5 5 ns 2, 3
Output enable to output in low-Z tOLZ 5 5 ns 2, 3
tCHZ1 0 20 0 25 ns 1, 2, 3 Chip deselect to output in high-Z
tCHZ2 0 20 0 25 ns 1, 2, 3
LB#, UB# disable to high-Z tBHZ 0 20 0 25 ns 1, 2, 3
Output disable to output in high-Z tOHZ 0 20 0 25 ns 1, 2, 3
Rev.1.00, May.24.2007, page 8 of 15
R1LV0416D Series
Write Cycle
R1LV0416D
-5SI -7LI
Parameter Symbol Min Max Min Max Unit Notes
Write cycle time tWC 55 70 ns
Address valid to end of write tAW 50 60 ns
Chip selection to end of write tCW 50 60 ns 5
Write pulse width tWP 40 50 ns 4
LB#, UB# valid to end of write tBW 50 55 ns
Address setup time tAS 0 0 ns 6
Write recovery time tWR 0 0 ns 7
Data to write time overlap tDW 25 30 ns
Data hold from write time tDH 0 0 ns
Output active from end of write tOW 5 5 ns 2
Output disable to output in high-Z tOHZ 0 20 0 25 ns 1, 2, 3
Write to output in high-Z tWHZ 0 20 0 25 ns 1, 2
Notes: 1. tCHZ, tOHZ, tWHZ and tBHZ are defined as the time at which the outputs achieve the open circuit conditions and are not
referred to output voltage levels.
2. This parameter is sampled and not 100% tested.
3. At any given temperature and voltage condition, tHZ max is less than tLZ min both for a given device and from
device to device.
4. A write occurs during the overlap of a low CS1#, a high CS2, a low WE# and a low LB# or a low UB#. A write
begins at the latest transition among CS1# going low, CS2 going high, WE# going low and LB# going low or UB#
going low. A write ends at the earliest transition among CS1# going high, CS2 going low, WE# going high and
LB# going high or UB# going high. tWP is measured from the beginning of write to the end of write.
5. tCW is measured from the later of CS1# going low or CS2 going high to the end of write.
6. tAS is measured from the address valid to the beginning of write.
7. tWR is measured from the earliest of CS1# or WE# going high or CS2 going low to the end of write cycle.
Rev.1.00, May.24.2007, page 9 of 15
R1LV0416D Series
Timing Waveform
Read Timing Waveform (WE# = VIH)
tAA
tACS1
tACS2
tCLZ2
tCLZ1
tBLZ
tBA
tOH
tRC
Valid data
Address
Dout
Valid address
High impedance
CS1#
CS2
LB#, UB#
OE#
*1, 2, 3
*1, 2, 3
*2, 3
*2, 3
*2, 3
*1, 2, 3
tOLZ*2, 3
*1, 2, 3
tOE
tCHZ1
tCHZ2
tBHZ
tOHZ
Rev.1.00, May.24.2007, page 10 of 15
R1LV0416D Series
Write Timing Waveform (1) (WE# Clock)
Address
WE#
tWC
tAW
tWP*4
tWR*7
tCW*5
tCW*5
tBW
tAS*6
tOW*2
tWHZ*1, 2
tDW tDH
Valid address
Valid data
CS1#
LB#, UB#
Dout
Din
High impedance
CS2
Rev.1.00, May.24.2007, page 11 of 15
R1LV0416D Series
Write Timing Waveform (2) (CS# Clock, OE# = VIH)
Address
WE#
tWC
tAW
tWP*4
tWR*7
tCW*5
tCW*5
tBW
tAS*6
tDW tDH
Valid address
Valid data
LB#, UB#
Dout
Din
High impedance
CS2
CS1#
Rev.1.00, May.24.2007, page 12 of 15
R1LV0416D Series
Write Timing Waveform (3) (LB#, UB# Clock, OE# = VIH)
Address
WE#
t
WC
t
AW
t
WP
*
4
t
CW
*
5
t
CW
*
5
t
BW
t
WR
*
7
t
DW
t
DH
Valid address
Valid data
LB#, UB#
Dout
Din
High impedance
CS2
CS1#
t
AS
*
6
Rev.1.00, May.24.2007, page 13 of 15
R1LV0416D Series
Low VCC Data Retention Characteristics
(Ta = -40 to +85°C)
Parameter Symbol Min Typ Max Unit Test conditions
VCC for data retention VDR 2.0 V Vin 0V
(1) 0 V CS2 0.2 V or
(2) CS2 VCC 0.2 V,
CS1# VCC 0.2 V or
(3) LB# = UB# VCC 0.2 V,
CS2 VCC 0.2 V,
CS1# 0.2 V
to +85°C ICCDR 10 µA
to +70°C ICCDR 8 µA
to +40°C ICCDR 3 µA
5SI
to +25°C ICCDR 1*1 2.5 µA
to +85°C ICCDR 20 µA
to +70°C ICCDR 16 µA
to +40°C ICCDR 10 µA
Data
retention
current
7LI
to +25°C ICCDR 1*1 10 µA
VCC = 3.0 V, Vin 0V
(1) 0 V CS2 0.2 V or
(2) CS2 VCC 0.2 V,
CS1# VCC 0.2 V or
(3) LB# = UB# VCC 0.2 V,
CS2 VCC 0.2 V,
CS1# 0.2 V
Average values
Chip deselect to data retention time tCDR 0 ns
Operation recovery time tR 5 ms
See retention waveform
Note: 1. Typical values are at VCC = 3.0 V, Ta = +25°C and specified loading, and not guaranteed.
Rev.1.00, May.24.2007, page 14 of 15
R1LV0416D Series
Rev.1.00, May.24.2007, page 15 of 15
Low VCC Data Retention Timing Waveform (1) (CS1# Controlled)
CC
V
2.2 V
2.7 V
0 V
CS1#
t
CDR
t
R
CS1# V – 0.2 V
CC
DR
V
Data retention mode
CC
V
2.7 V
0.6 V
0 V
CS2
CDR
t
R
0 V CS2 0.2 V
DR
V
Data retention modet
<<
CC
V
2.2 V
2.7 V
0 V
LB#, UB#
tCDR tR
LB#, UB# V – 0.2 V
CC
DR
V
Data retention mode
Low VCC Data Retention Timing Waveform (2) (CS2 Controlled)
Low VCC Data Retention Timing Waveform (3) (LB#, UB# Controlled)
Revision History R1LV0416D Series Data Sheet
Contents of Modification Rev. Date Page Description
0.01 Dec. 25, 2006 Initial issue
1.00 May. 24, 2007 2
3
4
5
5
6
7
14
Ordering Information
R1LV0416DSB-5S% to R1LV0416DSB-5SI
R1LV0416DSB-7L% to R1LV0416DSB-7LI
R1LV0416DBG-5S% to R1LV0416DBG-5SI
R1LV0416DBG-7L% to R1LV0416DBG-7LI
Pin Arrangement
A6 to A13, A13 to A6
Change of Block Diagram
Absolute Maximum Ratings: Deletion of R ver. specification
DC Operating Conditions: Deletion of R ver. specification
DC Characteristics
ISB1 (-5SI) (to +25°C) max: 3 µA to 2.5 µA
AC Characteristics: Change of Test Conditions
Low VCC Data Retention Characteristics
ICCDR (-5SI) (to +25°C) max: 3 µA to 2.5 µA
Deletion of note 2
Notes:
1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes
warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property
rights or any other rights of Renesas or any third party with respect to the information in this document.
2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including,
but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples.
3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass
destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws
and regulations, and procedures required by such laws and regulations.
4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this
document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document,
please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be
disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com )
5. Renesas has used reasonable care in compiling the information included in this document, but Renesas assumes no liability whatsoever for any damages incurred as a
result of errors or omissions in the information included in this document.
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On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology
Corporation, and Renesas Electronics Corporation took over all the business of both
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subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please
confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to
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expressl y specified in a Renesas Electro nics data sheets or data books, etc.
“Standard”: Computers; office equipment; communications equipment; test and measurement equipment; audio and visual
equipment; home electro nic app liances; machine tools; personal electro nic equipment; and industrial ro bots.
“High Quality”: Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anti-
crime systems; safety equipment; and medical equipment not specifically designed for life support.
“Specific”: Aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or
systems for life support (e.g. artificial life support devices or systems), surgical implantations, or healthcare
interven tion (e.g. exci sion, et c.), and any other applicatio ns or purposes that pose a direct threat t o human life.
8. You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics,
especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation
characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or
damages arising out of the use of Renesas Electronics products beyond such specified ranges.
9. Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have
specific chara cteristi cs such as the o ccurren ce of failure at a certai n rat e and malfun cti on s under certain u se cond itions. Further,
Renesas Electronics pr oducts are not subject to radi ation resi stance design. Please b e sure to implement safety measures to
guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a
Renesas Electronics product, such as safety design for hardware and software including but not limited to redundancy, fire
control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because
the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system
manufactured by you.
10. Please contact a Renesas Electronics sal es office for d etails as to envi ronmental matters such as t he enviro nmental
compatibility of each Renesas Electronics product. Please use Renesas Electronics products in compliance with all applicable
laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS
Directive. Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with
applicable laws and regulations.
11. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of Renesas
Electronics.
12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this
document or Renesas Electronics products, or if you have any other inquiries.
(Note 1) “Ren esas E lectroni cs” as used in th is document means Renesas Ele ct r onics Co rporation and al so includes its majority-
owned subsidiaries.
(Note 2) “Renesas Electronics product(s)” means any product developed or manufactured by or for Renesas Electronics.