11AA010-I/MN - Microchip Technology, Inc.

11AA010/11LC010 11AA080/11LC080

11AA020/11LC020 11AA160/11LC160

11AA040/11LC040

Features:

• Single I/O, UNI/O® Serial Interface Bus

• Low-Power CMOS Technology

- 1 mA active current , typical

- 1 µA standby current (max.) (I-temp)

• 128 x 8 through 2,048 x 8 Bit Organizations

• Schmitt Trigger Inputs for Noise Suppression

• Output Slop e C o ntro l t o El im ina te Gro und Bounc e

• 100 kbps Max. Bit Rate – Equivalent to 100 kHz

Clock Frequency

• Self-Timed Write Cycle ( including Auto-Erase )

• Page-Write Buffer for up to 16 Bytes

• STATUS Register for Added Control:

- Write enable latch bit

- Write-In-Progress bit

• Block Write Protection

- Protect none, 1/4, 1/2 or all of array

• Built -in W ri te Prot ection

- Power-on/off data protection circuitry

- Write enable latch

• High Reliability

- Endurance: 1,000,000 erase/write cycles

- Data retention: > 200 years

- ESD protection: > 4,000V

• 3-lead SOT-23 Package

• 8-lead PDIP, SOIC, MSOP, TDFN Packages

• Pb-Free and RoHS Compliant

• Available Temperature Ranges:

Pin Function Table

Description:

The Microchip Technology Inc. 11AAXXX/11LCXXX

(11XX*) devices are a family of 1 Kbit through 16 Kbit

Serial Electrically Erasable PROMs. The devices are

organized in blocks of x8-bit memory and support the

patented** single I/O UNI/O® serial bus. By using

Manchester encoding techniques, the clock and data

are combined into a single, serial bit stream (SCIO),

where the clock signal is extracted by the receiver to

corr ectly deco de the timing an d value of each bit.

Low-voltage design permits operatio n down to 1.8V (for

11AAXXX devic es), with st andby and active c urrents of

only 1 uA and 1 mA, respectively.

The 11XX family is available in standard packages

including 8-lead PDIP and SOIC, and advanced

packaging including 3-lead SOT-23, 8-lead TDFN,

and 8-lead MSOP.

Package Types (not to scale)

- Industrial (I): -40°C to +85°C

- Automotive (E): -40°C to +125°C

Name Function

SCIO Serial Clock, Data Input/Output

VSS Ground

VCC Supply Voltage

VSS

VCC

SCIO

PDIP/SOIC

(P, SN)

SCIO

(MS)

TDFN

VSS

SCIO

1VCC

(MN)

MSOP

SOT23

1SCIO

VCC

VSS

(TT)

1K-16K UNI/O® Serial EEPROM Family Data Sheet

* 11XX is used in this document as a generic part number for the 11 series devices.

** Microchip’s UNI/O® Bus products are covered by the following patent issued in the U.S.A.: 7,376,020.

11AAXXX/11LCXXX

DEVICE SELECTION TABLE

Part Number Density

(bits) Organization VCC Range Page Size

(Bytes) Temp.

Ranges Packages

11LC010 1K 128 x 8 2.5-5.5V 16 I,E P, SN, MS, MN, TT

11AA010 1K 128 x 8 1.8-5.5V 16 I P, SN, MS, MN, TT

11LC020 2K 256 x 8 2.5-5.5V 16 I,E P, SN, MS, MN, TT

11AA020 2K 256 x 8 1.8-5.5V 16 I P, SN, MS, MN, TT

11LC040 4K 512 x 8 2.5-5.5V 16 I,E P, SN, MS, MN, TT

11AA040 4K 512 x 8 1.8-5.5V 16 I P, SN, MS, MN, TT

11LC080 8K 1,024 x 8 2.5-5.5V 16 I,E P, SN, MS, MN, TT

11AA080 8K 1,024 x 8 1.8-5.5V 16 I P, SN, MS, MN , TT

11LC160 16K 2,048 x 8 2.5-5.5V 16 I,E P, SN, MS, MN, TT

11AA160 16K 2,048 x 8 1.8-5.5V 16 I P, SN, MS, MN , TT

11AAXXX/11LCXXX

1.0 ELECTRICAL CHARAC TERISTICS

Absolute Maximum Ratings (†)

VCC.............................................................................................................................................................................6.5V

SCIO w.r.t. VSS.....................................................................................................................................-0.6V to VCC+1.0V

Storage temperature .................................................................................................................................-65°C to 150°C

Ambient temperature under bias...............................................................................................................-40°C to 125°C

ESD protection on all pins..........................................................................................................................................4 kV

TABLE 1-1: DC CHARACTERISTICS

† NOTICE: Stresses above those listed under ‘Absolute Maximum Ratings’ may cause permanent damage to the

device . This i s a stres s ratin g only and functio nal operati on of the device at thos e or any other co nditio ns abov e thos e

indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for an

extended period of time may affect device reliability.

DC CHARACTERISTICS

Electrical Characteristics :

Industrial (I): VCC = 2.5V to 5.5V TA = -40°C to +85°C

VCC = 1.8V to 2.5V TA = -20°C to +85°C

Automotive (E): VCC = 2.5V to 5.5V TA = -40°C to +125°C

Param.

No. Sym. Characteristic Min. Max. Units Test Conditions

D1 VIH High-level input

voltage 0.7*VCC VCC+1 V

D2 VIL Low-level input

voltage -0.3

-0.3 0.3*VCC

0.2*VCC V

VVCC ≥ 2.5V

VCC < 2.5V

D3 VHYS Hysteresis of Schmitt

Trigge r i npu t s (SC IO) 0.05*Vcc — V VCC ≥ 2.5V (Note 1)

D4 VOH High-level output

voltage VCC -0.5

VCC -0.5 —

—V

VIOH = -300 μA, VCC = 5.5V

IOH = -200 μA, Vcc = 2.5V

D5 VOL Low-level output

voltage —

—0.4

0.4 V

VIOI = 300 μA, VCC = 5.5V

IOI = 200 μA, Vcc = 2.5V

D6 IOOutput curr ent lim it

(Note 2) —

—±4

±3 mA

mA VCC = 5.5V (Note 1)

Vcc = 2.5V (Note 1)

D7 ILI Input leakage current

(SCIO) —±1μAVIN = VSS or VCC

D8 CINT Internal Capa ci t anc e

(all inputs and

outputs)

—7pFT

A = 25°C, FCLK = 1 MHz,

VCC = 5.0V (Note 1)

D9 ICC Read Read Operating

Current —

—3

1mA

mA VCC=5.5V; FBUS=100 kHz, CB=100 pF

VCC=2.5V; FBUS=100 kHz, CB=100 pF

D10 ICC Write Write Operatin g

Current —

—5

3mA

mA VCC = 5.5V

VCC = 2.5V

D11 Iccs Standby Current —

—

μA

VCC = 5.5V

TA = 125°C

VCC = 5.5V

TA = 85°C

D12 ICCI Idle Mode Current — 50 μAVCC = 5.5V

Note 1: This parameter is periodically sampled and not 100% tested.

2: The SCIO output driver impedance will vary to ensure IO is not exceeded.

11AAXXX/11LCXXX

TABLE 1-3: AC TEST CONDITIONS

TABLE 1-2: AC CHARACTERISTICS

AC CHARACTERISTICS

Electrical Characteristics:

Industri al (I): VCC = 2.5V to 5.5V TA = -40°C to +85°C

VCC = 1.8V to 2.5V TA = -20°C to +85°C

Automotive (E): VCC = 2.5V to 5.5V TA = -40°C to +125°C

Param.

No. Sym. Characteristic Min. Max. Units Test Conditions

BUS Serial bus frequency 10 100 kHz —

EBit period 10 100 µs —

3TIJIT Input edge jitter tolerance — ±0.08 UI (Note 3)

4FDRIFT Serial bus frequency drift

rate tolerance — ±0.75 % per byte —

DEV Serial bus frequency drift

limit —±5% per

command —

OJIT Output edge jitter — ±0.25 UI (Note 3)

RSCIO input rise time

(Note 1) — 100 ns —

FSCIO input fall time

(Note 1) — 100 ns —

STBY Standby pulse time 600 — µs —

10 TSS Start header setup time 10 — µs —

11 THDR Start header low pulse

time 5—µs—

12 TSP Input filter spike

suppression (SCIO) —50ns(Note 1)

13 TWC Write cy cl e time

(byte or page) —

—5

10 ms

ms Write, WRSR commands

ERAL, SETAL commands

14 — Endurance (per page) 1M — cycles 25°C, VCC = 5.5V (Note 2)

Note 1: This parameter is periodically sampled and not 100% tested.

2: This parameter is not tested but ensured by characterization . For enduranc e estimates in a specific

application, please consult the Total Endurance™ Model which can be obtained on Microchip’s web site:

www.microchip.com.

3: A Unit Interval (UI) is equal to 1-bit period (TE) at the current bus frequency.

AC Waveform:

VLO = 0.2V

VHI = VCC - 0.2V

CL = 100 pF

Timing Measurement Refere nce Lev el

Input 0.5 VCC

Output 0.5 VCC

11AAXXX/11LCXXX

FIGURE 1-1: BUS TIMING – START HEADER

FIGURE 1-2: BUS TIMING – DATA

FIGURE 1-3: BUS TIMING – STANDBY PULSE

FIGURE 1-4: BUS TIMING – JITTER

SCIO

Data ‘0’Data ‘1’Data ‘0’Data ‘1’Data ‘0’Data ‘1’Data ‘0’Data ‘1’MA K bit NoSAK bit

1110

SCIO

7 8

Data ‘0’Data ‘1’Data ‘1’Data ‘0’

SCIO 9

Standby

Mode

Ideal Edge

323 6 6

26 6

Ideal Edge Ideal Edge Ideal Edge

from Master from Master from Slave from Slave

11AAXXX/11LCXXX

2.0 FUNCTIONAL DESCRIPTION

2.1 Principles of Operation

The 11XX family of serial EEPROMs support the

UNI/O® protocol. They can be interfaced with

microcontrollers, including Microchip’s PIC® microcon-

trollers, ASICs, or any other device with an available

discrete I/O line that can be configured properly to

match the UNI / O prot oco l.

The 11XX devices contain an 8-bit instruction register.

The devices are accessed via the SCIO pin.

Table 4-1 contains a list of the possible instruction

bytes and format for device operation. All instructions,

addresses, and data are transferred MSb first, LSb

last.

Data is embedded into the I/O stream through

Manchester encoding. The bus is controlled by a

master de vic e whi ch de term in es the clo ck perio d, co n-

trols the bus access and initiates all operations, while

the 11XX works as slave. Both master and slave can

operate as transmitter or receiver, but the master

device determines which mode is active.

FIGURE 2-1: BLOCK DIAGRAM

SCIO

STATUS

I/O Contro l Memory

Control

Logic

Dec

HV Generator

EEPROM

Array

Page Latches

Y Decoder

Sense Amp.

R/W Control

Logic

Vcc

Vss

Current-

Limited

Slope

Control

11AAXXX/11LCXXX

3.0 BUS CHARACTERISTICS

3.1 Standby Pulse

When the m as ter h as co ntro l of SCIO, a s tandby p uls e

can be generated by holding SCIO high for TSTBY. At

this time, the 11XX will reset and return to Standby

mode. Subsequently, a high-to-low transition on SCIO

(the first low pulse of the header) will return the device

to the active state.

Once a command is terminated satisfactorily (i.e., via

a NoMAK/SAK combination during the Acknowledge

sequence), performing a standby pulse is not required

to begin a new command as long as the device to be

selected is the same device selected during the previ-

ous command. However, a period of TSS must be

observe d a fter the end of th e c om m and an d b efo re the

beginning of the start header. After TSS, the start

header (including THDR low pulse) can be transmitted

in order to begin the new command.

If a com mand i s termina ted in a ny ma nner ot her t han a

NoMAK/SAK combination, then the master must per-

form a standby pulse before beginning a new com-

mand, regardless of which device is to be selected.

An exampl e of two con secutiv e comm ands is shown in

Figure 3-1. Note that the device address is the same

for both commands, indicating that the same device is

being selected both times.

A standby pulse cannot be generated while the slave

has control of SCIO. In this situation, the master must

wait for the slave to finish transmitting and to release

SCIO before the pulse can be generated.

If, at any point during a command, an error is detected

by the master, a standby pulse should be generated

and the command should be performed again.

FIGURE 3-1: CONSECUTIVE CO MMAN DS EX AMP LE

3.2 Start Data Transfer

All ope rations mu st be p recede d by a s tar t head er. The

start header consists of holding SCIO low for a period

of THDR, followe d by trans mi tti ng an 8-bit ‘01010101’

code. This code is used to synchronize the slave’s

internal clock period with the master’s clock period, so

accurate timing is very important.

When a standby pulse is not required (i.e., between

successive commands to the same device), a period of

TSS must be observed after the end of the command

and before the beginning of the start header.

Figure 3-2 shows the waveform for the start header,

including the required Acknowledge sequence at the

end of the byte.

FIGURE 3-2: START HEADER

Note: After a POR/BOR event occurs, a low-

to-high transition on SCIO must be gen-

erated before proceeding with communi-

cation, including a standby pulse.

11010100

Start Header

SCIO

Devi ce A ddress

MAK

00001010

MAK

NoSAK

SAK

Standby Pulse(1)

11010100

Start Header

SCIO

Device Address

MAK

00001010

MAK

NoSAK

SAK

NoMAK

SAK

TSS

Note 1: After a POR/BOR event, a low-to-high transition on SCIO is required to occur before the first

standby pulse.

SCIO

Data ‘0’Data ‘1’Data ‘0’Data ‘1’Data ‘0’Data ‘1’Data ‘0’Data ‘1’MAK NoSAKTSS THDR

11AAXXX/11LCXXX

3.3 Acknowledge

An Acknowledge routine occurs after each byte is

transmitted, including the start header. This routine

consists of two bits. The first bit is transmitted by the

master, and the second bit is transmitted by the slave.

The Master Acknowledge, or MAK, is signified by trans-

mitting a ‘1’, and informs the slave that the current

operation is to be continued. Conversely, a Not

Acknowledge, or NoMAK, is signified by transmitting a

‘0’, and is used to end the current operation (and initiate

the write cycle for write operations).

The slave Acknowledge, or SAK, is also signified by

transmitting a ‘1’, and con firm s proper co mm unicatio n.

However, unlike the No MAK, the NoSAK is sign ified b y

the lack of a middle edge during the bit period.

A NoSAK will occur for the following events:

• Following the start header

• Following the device address, if no slave on the

bus matches the transmitted address

• Following the command byte, if the command is

invalid, including Read, CRRD, Write, WRSR,

SETAL, and ERAL during a write cycle.

• If the slave becomes out of sync with the master

• If a command is terminated prematurely by using

a NoMAK, with the exce pti on of imme dia tely after

the device address.

See Figure 3.3 and Figure 3-4 for details.

If a NoSAK is received from the slave after any byte

(except the start header), an error has occurred. The

master sh ould then perfor m a stan dby pul se and begi n

the desired command again.

FIGURE 3-3: ACKNOWLEDGE

ROUTINE

FIGURE 3-4: ACKNOWLEDGE BITS

3.4 Device Addressing

A devic e address byte is the first byte received from th e

master device following the start header. The device

address byte consists of a four-bit family code, for the

11XX this is set as ‘1010’. The last four bits of the

device address byte are the device code, which is

hardwi red to ‘0000’.

FIGURE 3-5: DEVICE ADDRESS BYTE

ALLOCATION

3.5 Bus Conflict Protection

To help guard against high current conditions arising

from bus conflicts, the 11XX features a current-limited

output driver. The IOL and IOH specifications describe

the maximum current that can be sunk or sourced,

respectively, by the SCIO pin. The 11XX will vary the

output driver impedance to ensure that the maximum

current level is not exceeded.

Note: A MAK must always be transmitted

following the start header.

Note: When a NoMAK is used to end a WRITE

or WRSR instruction, the write cycle is

not initiated if no bytes of data have

been rece ived.

Note: In o rder to gua rd against b us contenti on,

a NoSAK will occur after the start

header.

Master Slave

MAK SAK

MAK (‘1’)

NoMAK (‘0’)

SAK (‘1’)

NoSAK(1)

Note 1: valid SAK.

A NoSAK is defined as any sequen ce that is not a

1010000

MAK

SLAVE ADDRESS

SAK

11AAXXX/11LCXXX

3.6 Device Standby

The 11XX fe atures a l ow-po wer Standby mode during

which the device is waiting to begin a new command.

A high-to-low transition on SCIO will exit low-power

mode and prepare the device for receiving the start

header.

Standby mode will be entered upon the following

conditions:

• A NoMAK followed by a SAK (i.e., valid termina-

tion of a command)

• Reception of a standby pulse

3.7 Device Idle

The 11XX features an Idle m ode du ring w hi ch all s eria l

data is ignore d unt il a s tandby pul se occ urs . Idle mod e

will be entered upon the following conditions:

• Invalid device address

• Invalid command byte, including Read, CRRD,

Write, WRSR, SETAL and ERAL during a write

cycle.

• Missed edge transition

• Reception of a MAK following a WREN, WRDI,

SETAL, or ERAL command byte

• Reception of a MAK following the data byte of a

WRSR command

An invalid start header will indirectly cause the device

to enter Idle mode. Whether or not the start header is

invalid cannot be detected by the slave, but will

prevent the slave from synchronizing properly with the

master. If the slave is not synchronized with the

master, a n e dge t r ans iti on will be missed , th us c au sin g

the device to enter Idle mode.

3.8 Synchronization

At the beginning of every command, the 11XX utilizes

the start header to determine the master’s bus clock

period. This period is then used as a reference for all

subsequent communication within that command.

The 11XX features re-synchronization circuitry which

will monitor the position of the middle data edge during

each MAK bi t and subs equently adju st the internal tim e

reference in order to remain synchronized with the

master.

There are two variables which can cause the 11XX to

lose synchronization. The first is frequency drift,

defined as a ch ange i n the bit period, TE. The second is

edge jitter, which is a single occurrence change in the

position of an edge within a bit period, while the bit

period itself remains constant.

3.8.1 FREQUENCY DRIFT

With in a syst em, th ere is a p ossibi lity that fr equen cies

can drift due to changes in voltage, temperature, etc.

The re-synchronization circuitry provides some toler-

ance for such frequency drift. The tolerance range is

specified by two parameters, FDRIFT and FDEV. FDRIFT

specifies the maximum tolerable change in bus fre-

quency per byte. FDEV specifies the overall limit in fre-

quency deviation within an operati on (i.e., from the en d

of the start header until communication is terminated

for that o pera tion). T he sta rt head er at th e begi nning of

the next operation will reset the re-synchronization cir-

cuitr y an d a l low fo r an o t her FDEV amount of frequency

drift.

3.8.2 EDGE JITTER

Ensuring that edge transitions from the master always

occur exactly in the middle or end of the bit period is not

alwa ys po s si bl e. T h er ef or e, t he re - sy nc hro ni z at i on cir -

cuitry is designed to provide some tolerance for edge

jitter.

The 11XX adjusts its phase every MAK bit, so TIJIT

specifies the maximum allowable peak-to-peak jitter

relative to the previous MAK bit. Since the position of

the previous MAK bit would be difficult to measure by

the maste r , the m inimum and maximum jitte r values for

a system should be considered the worst-case. These

values will be based on the execution time for different

branch paths in software, jitter due to thermal noise,

etc.

The difference between the minimum and maximum

values , as a percent age of the b it period, should be cal-

culated and then compared against TIJIT to determine

jitter compliance.

Note: In the case of the WRITE, WRSR, SETAL, or

ERAL command s, the write cycl e is initiated

upon receipt of the NoMAK, assuming all

other write requirements have be en met.

Note: Because the 11XX only re-synchronizes

during the MAK bit, the overall ability to

remain synchronized depends on a combi-

nation of frequency drift and edge jitter (i.e.,

if the MAK bit ed ge is experien cing the max -

imum allowable edge jitter, then there is no

room for frequency drift). Conversely, if the

frequency has drifted to the maximum

amount tolerable within a byte, then no edge

jitter can be present.

11AAXXX/11LCXXX

4.0 DEVICE COMMANDS

After the device address byte, a command byte must

be sent by the master to indicate the type of operation

to be performed. The code for ea ch instruc ti on i s li ste d

in Table 4-1.

TABLE 4-1: INSTRUCTION SET

4.1 Read Instruction

The Read command allows the master to access any

memory location in a random manner. After the READ

instruction has been sent to the slave, the two bytes of

the Word Address are transmitted, with an Acknowl-

edge se quence being performed af ter each byte. The n,

the sla ve sends the first data byte to the mast er . If more

data is to be read, the master sends a MAK, indicating

that the slave should output the next data byte. This

continu es until t he master se nds a NoMAK, w hich ends

the operation.

To provide sequential reads in this manner, the 11XX

contains an internal Address Pointer which is incre-

mented by one after the transmission of each byte. This

Address Pointer allows the entire memory contents to

be serially read during one operation. Wh en the highest

address is reached, the Address Pointer rolls over to

address ‘0x000’ if the master chooses to continue the

operation by providing a MAK.

FIGURE 4-1: READ COMMAND SEQUENCE

Instruction Name Instruction Code Hex Code Description

READ 0000 0011 0x03 Read data from memory array beginning at spe cified ad dress

CRRD 0000 0110 0x06 Read data from current location in memory array

WRITE 0110 1100 0x6C Write data to memory array beginning at specified address

WREN 1001 0110 0x96 Set the write enable latch (enable write operations)

WRDI 1001 0001 0x91 Reset the write enable latch (disable write operations)

RDSR 0000 0101 0x05 Read STATUS register

WRSR 0110 1110 0x6E Write STATUS register

ERAL 0110 1101 0x6D Write ‘0x00’ to entire array

SETAL 0110 0111 0x67 Write ‘0xFF’ to entire array

7654

Data Byte 1

32107654

Data Byte 2

32107654

Data Byte n

3210

SCIO

MAK

NoMAK

11010100

Start Header

SCIO

Device Address

MAK

00001010

MAK

Command

01000001

MAK

NoSAK

SAK

Standby Pulse

SCIO

SAK

15 14 13 12

Word Address M SB

11 10 9 8

MAK

SAK

7654

Word Address LSB

3210

MAK

SAK

11AAXXX/11LCXXX

4.2 Current Address Read (CRRD)

Instruction

The internal address counter featured on the 11XX

maintains the address of the last memory array loca-

tion accessed. The CRRD instruction allows the mas-

ter to read data back beginning from this current

location. Consequently, no word address is provided

upon issuing this command.

Note that, except for the initial word address, the

READ and CRRD instructions are identical, including

the ability to continue requesting data through the use

of MAKs in order to sequentially read from the array.

As with the READ instruction, the CRRD instruction is

termina ted by transmitt ing a NoMAK.

Table 4-2 lists the events upon which the internal

address counter is modified.

TABLE 4-2: INTERNAL ADDRESS

COUNTER

FIGURE 4-2: CRRD COMMAND SEQUENCE

Command Event Action

— Power-on Reset Counter is undefined

READ or

WRITE MAK edge fol-

lowing each

Address byt e

Counter is updated

with newly received

value

READ,

WRITE, or

CRRD

MAK/NoMAK

edge following

each data byte

Counter is incre-

mented by 1

Note: If, following each data byte in a READ,

WRITE, or CRRD instruction, neither a

MAK nor a NoMAK edge is received

(i.e., if a standby pulse occurs instead),

the internal address counter will not be

incremented.

Note: During a Write command, once the last

data byte for a page has been loaded,

the internal Address Pointer will rollover

to the beginning of the selected page.

7654

Data Byte 1

32107654

Data Byte 2

3210

7654

Data Byte n

3210

SCIO

MAK

NoMAK

11010100

Start Header

SCIO

Devi ce A ddre ss

MAK

00001010

MAK

Command

10000001

MAK

NoSAK

SAK

Standby Puls e

SCIO

SAK

11AAXXX/11LCXXX

4.3 Wr ite Instruction

Prior to a ny att em pt t o wri te data to th e 11XX, the wri te

enable latch must be set by issuing the WREN

instruction (see Section 4.4).

Once the write enable latch is set, the user may pro-

ceed with issuing a WRITE instruction (including the

header a nd device ad dress bytes) fo llowed by t he MSB

and LSB of the Word Address. Once the la st Acknowl-

edge sequence has been performed, the master

transmits the data byte to be written.

The 11XX features a 16-byte p age buf fer, meaning that

up to 16 byt es can be writt en at one time . To utiliz e this

feature, the master can transmit up to 16 data bytes to

the 11XX, which are tempo rarily stor ed in the p age buf-

fer . Af ter each dat a byte, the m aster sends a MAK, indi-

cating whether or not another data byte is to follow. A

NoMAK in dicate s that no mo re dat a is to follo w, and as

such will initiate the internal write cycle.

Upon receipt of each word, the four lower-order

Address Po inter bit s are internal ly incremen ted by one.

The higher-order bits of the word address remain con-

stan t. If the mas ter shoul d transmit data p ast the e nd of

the page, the address counter will roll over to the begin-

ning of the page, where further received data will be

written.

FIGURE 4-3: WRITE COMMAND SEQUENCE

Note: If a NoMAK is generated before any d ata

has be en provid ed, or if a standby pulse

occurs before the NoMAK is generated,

the 11XX will be reset, and the write

cycle will not be initiated.

Note: Page w rite opera tions ar e limited to writ-

ing bytes within a single physical page,

regardless of the numbe r of by tes ac tu-

ally being written. Physical page bound-

aries start at addresses that are integer

multip les of the page size (16 bytes ) and

end at addresses that are integer multi-

ples of the page size minus 1. As an

example, the page that begins at

address 0x30 ends at address 0x3F. If a

page Write command attempts to write

across a physical page boundary, the

result is that the data wraps around to

the beginning of the current page (over-

writing data previously stored there),

instea d of being w ritten to th e next page

as might be expected. It is therefore

necessary for the application software to

prevent page write operations that

would attempt to cross a page bound-

ary.

7654

Data Byte 1

32107654

Data Byte 2

32107654

Data Byte n

3210

SCIO

MAK

No MAK

11010100

Start Header

SCIO

Device Address

MAK

00001010

MAK

Command

10101100

MAK

NoSAK

SAK

Standby Pulse

SCIO

SAK

15 14 13 12

Word Addre ss MSB

11 10 9 8

MAK

SAK

7654

Word Address LSB

3210

MAK

SAK

Twc

11AAXXX/11LCXXX

4.4 Wr ite Enable (WREN) and Wri te

Disable (WRDI) Instructions

The 11XX contains a write enable latch. See Table 6-1

for the Write-Protect Functionality Matrix. This latch

must be set before any write operation will be com-

pleted internally. The WREN instruction will set the

latch, and the WRDI instruction will reset the latch.

The following is a list of conditions under which the

write enab le latc h wi ll be reset:

• Power-up

•WRDI instruction successfully executed

•WRSR instruction successfully executed

•WRITE instruction successfully executed

•ERAL instruction successfully executed

•SETAL instruction successfully executed

FIGURE 4-4: WRITE ENABLE COMMAND SEQUENCE

FIGURE 4-5: WRITE DISABLE COMMAND SEQUENCE

Note: The WREN and WRDI instructions must

be terminated with a NoMAK following

the command byte. If a NoMAK is not

received at this point, the command will

be considered invalid, and the device

will go into Idle mode without responding

with a SAK or executing the command.

11010100

Start Header

SCIO

Devi ce A ddre ss

MAK

00001010

MAK

Command

10010011

NoMAK

NoSAK

SAK

Standby Pulse

SCIO

SAK

11010100

Start Header

SCIO

Devi ce A ddre ss

MAK

00001010

MAK

Command

01010010

NoMAK

NoSAK

SAK

Standby Pulse

SCIO

SAK

11AAXXX/11LCXXX

4.5 Read Status Register (RDSR)

Instruction

The RDSR instruction provides access to the STATUS

even during a write cycle. The STATUS register is

formatted as follows:

The Write-In-Process (WIP) bit indicates whether the

11XX is busy with a write operation. When set to a ‘1’,

a write is in progress, when set to a ‘0’, no write is in

progress. This bit is read-only.

The Write Enable La tch (WEL) bit indi cat es the st atu s

of the write enable latch. When set to a ‘1’, the latch

allows writes to the array, when set to a ‘0’, the latch

prohibits writes to the array. This bit is set and cleared

using the WREN and WRDI instructions, respectively.

This bit is read-only for any other instruction.

The Block Protection (BP0 and BP1) bits indicate

which blocks are currently write-protected. These bits

are set by the user through the WRSR instruction.

These bits are nonvolatile.

The WIP and WEL bits will update dynamically (asyn-

chronous to issuing the RDSR instruction). Further-

more, after the STATUS register data is received, the

master can provide a MAK during the Acknowledge

sequence to request that the data be transm itted again.

This allows the master to continuously monitor the WIP

and WEL bits without the need to issue another full

command.

Once the master is finished, it provides a NoMAK to

end the operation.

FIGURE 4-6: READ STATUS REGISTER COMMAND SEQUENCE

7654 3 2 1 0

XXXXBP1 BP0 WEL WIP

Note: Bit s 4-7 are don ’t cares, and will read as ‘0’.

Note: If Read Status Register command is

initiated while the 11XX is currently

executing an internal write cycle on the

STATUS register, the new Block

Protection bit values will be read during

the entire command.

Note: The current drawn for a Read Status

is a combination of the ICC Read and ICC

Write operating currents.

11010100

Start Header

SCIO

Device Address

MAK

00001010

MAK

Command

11000000

MAK

NoSAK

SAK

Standby Pulse

SCIO

SAK

STATUS Register Data

3210

NoMAK

SAK

The STATUS register data can continuously be read, or polled, by transmitting a MAK in place of the NoMAK.Note:

0000

11AAXXX/11LCXXX

4.6 Wr it e Stat us Regist er (WRSR)

Instruction

The WRSR instruction allows the user to select one of

four levels of protection for the array by writing to the

appropriate bits in the STATUS register. The array is

divided up into four segments. The user has the ability

to write-protect none, one, two, or all four of the seg-

ments of the array. The partitioning is controlled as

illustrated in Table 4-3.

Aft er transmitting the ST ATUS regis ter data, th e master

must transmit a NoMAK during the Acknowledge

sequence in order to initiate the internal write cycle.

TABLE 4-3: ARRAY PROTECTION

TABLE 4-4: PROTECTED ARRAY ADDRESS LOCATIONS

FIGURE 4-7: WRITE STATUS REGISTER COMMAND SEQUENCE

Note: The WRSR instruction must be termi-

nated with a NoMAK following the data

byte. If a NoMAK is not received at this

point, the command will be considered

invalid, and the device will go into Idle

mode without responding with a SAK or

executing th e command.

BP1 BP0 Address Ranges Write-Protected Address Ranges Unprotected

00 None All

01 Upper 1/4 Lower 3/4

10 Upper 1/2 Lower 1/2

11 All None

Density Upper 1/4 Upper 1/2 All Sectors

1K 60h-7Fh 40h-7Fh 00h-7Fh

2K C0h-FFh 80h-FFh 00h-FFh

4K 180h-1FFh 100h-1FFh 000h-1FFh

8K 300h-3FFh 200h-3FFh 000h-3FFh

16K 600h-7FFh 400h-7FFh 000h-7FFh

11010100

Start Header

SCIO

Devi ce A ddre ss

MAK

00001010

MAK

Command

10101101

MAK

NoSAK

SAK

Standby Puls e

SCIO

SAK

7654

Status Register Data

3210

NoMAK

SAK

Twc

11AAXXX/11LCXXX

4.7 Erase All (ERAL) Inst ruction

The ERAL instruction allows the user to write ‘0x00’ to

the entire memory array with one command. Note that

the write enab le latch (WEL) must first be set by issuing

the WREN instruction.

Once the write enable latch is set, the user may pro-

ceed with issuing a ERAL instruction (including the

header and device address bytes). Immediately after

the No MAK bit has been tra nsmi tted by the maste r, the

internal write cycle is initiated, during which time all

words of the memory array are written to ‘0x00’.

The ERAL instruction is ignored if either of the Block

Protect bits (BP0, BP1) are not 0, meaning 1/4, 1/2, or

all of the array is protected.

FIGURE 4-8: ERASE ALL COMMAND SEQUENCE

4.8 Set All (SETAL) Inst ruction

The SETAL instruction allows the user to write ‘0xFF’

to the entire memory array with one command. Note

that the write enable latch (WEL) must first be set by

issuing the WREN ins tru cti on.

Once the write enable latch is set, the user may pro-

ceed with issuing a SETAL instruction (including the

header and device address bytes). Immediately after

the No MAK bit has been tra nsmi tted by the maste r, the

internal write cycle is initiated, during which time all

words of the memory array are written to ‘0xFF’.

The SETAL instruction is ignored if either of the Block

Protect bits (BP0, BP1) are not 0, meaning 1/4, 1/2, or

all of the array is protected.

FIGURE 4-9: SET ALL COMMAND SEQUENCE

Note: The ERAL instruction must be termi-

nated with a NoMAK following the com-

mand byte. If a NoMAK is not received at

this point, the command will be consid-

ered invalid, and the device will go into

Idle mode without responding with a

SAK or executing the command.

11010100

Start Header

SCIO

Devi ce A ddre ss

MAK

00001010

MAK

Command

11101100

NoMAK

NoSAK

SAK

Standby Pulse

SCIO

SAK

Twc

Note: The SETAL instruction must be termi-

nated with a NoMAK following the com-

mand byte. If a NoMAK is not received at

this point, the command will be consid-

ered invalid, and the device will go into

Idle mode without responding with a

SAK or executing the command.

11010100

Start Header

SCIO

Device Address

MAK

00001010

MAK

Command

11001101

NoMAK

NoSAK

SAK

Standby Pulse

SCIO

SAK

Twc

11AAXXX/11LCXXX

5.0 DATA PROTECTION

The following protection has been implemented to

prevent ina dv erte nt wri tes to the array:

• The Write Enable Latch (WEL) is reset on power-

•A Write Enable (

WREN) instructi on must be issued

to set the write enable latch

• After a write , ERAL , SETAL, or WRSR command,

the write enable latch is reset

• Commands to access the array or write to the

stat us register are ig nored during an internal write

cycl e and programming is not affected

6.0 POWER-ON STATE

The 11XX powers on in the following state:

• The devi ce is in low -po wer Shutdown mode,

requiring a l ow-to -high transit ion o n SCIO to e nter

Idle mode

• The Write Enable Latch (WEL) is reset

• The internal Address Pointer is undefined

• A low- to -hig h tra ns iti on, standby pul se and subse-

quent high-to-low transition on SCIO (the first low

pulse of the header) are required to enter the

active stat e

TABLE 6-1: WRITE PROTECT FUNCTIONALITY MATRIX

WEL Protected Blocks Unprotected Blocks Status Register

0Protected Protected Protected

1Protected Writable Writable

11AAXXX/11LCXXX

7.0 PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 7-1.

TABLE 7-1: PIN FUNCTION TABLE

7.1 Serial Clock, Data Input/Output

(SCIO)

SCIO is a bidirectional pin used to transfer commands

and addresses in to, a s w e ll as data in to a nd o ut o f, th e

device. The serial clock is embedded into the data

stream through Manchester encoding. Each bit is rep-

resented by a signal transition at the middle of the bit

period.

Name 3-pin SOT-23 8-pin PDIP/SOIC/

MSOP/TDFN Description

SCIO 1 5 Serial Clock, Data Inpu t/O utp ut

VCC 2 8 Supply Voltage

VSS 3 4 Ground

NC — 1,2,3,6,7 No Internal Connection

11AAXXX/11LCXXX

8.0 PACKAGING INFORMATION

8.1 Package Marking Information

T/XXXNNN

XXXXXXXX

YYWW

8-Lead PDIP

I/P 1L7

11AA160

0828

Example:

8-Lead PDIP Package Marking (Pb-Free)

Device Line 1 Marking Device Line 1 Marking

11AA010 11AA010 11LC010 11LC010

11AA020 11AA020 11LC020 11LC020

11AA040 11AA040 11LC040 11LC040

11AA080 11AA080 11LC080 11LC080

11AA160 11AA160 11LC160 11LC160

Note: T = Temperature Grade (I, E)

Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)

YY Year code (last 2 digits of calendar year)

WW Week code (week of January 1 is week ‘01’)

NNN Alphanumeric traceability code

Pb-free JEDEC designator for Matte Tin (Sn)

*This package is Pb-fr ee. The Pb- fre e JED EC designator ( )

can be found on the outer packaging for this package.

Note: In the event the full M icroc hip p art numb er cann ot be mark ed on one line, it wil l

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

11AAXXX/11LCXXX

8-Lead SO IC

XXXXYYWW

XXXXXXXT

NNN

Example:

SN 0828

11AA160I

1L7

8-Lead SOIC Package Marking (Pb-Free)

Device Line 1 Marking Device Line 1 Marking

11AA010 11AA010T 11LC010 11LC010T

11AA020 11AA020T 11LC020 11LC020T

11AA040 11AA040T 11LC040 11LC040T

11AA080 11AA080T 11LC080 11LC080T

11AA160 11AA160T 11LC160 11LC160T

Note: T = Temperature Grade (I, E)

Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)

YY Year code (last 2 digits of calendar year)

WW Week code (week of January 1 is week ‘01’)

NNN Alphanumeric traceability code

Pb-free JEDEC designator for Matte Tin (Sn)

*This package is Pb-fr ee. The Pb- fre e JED EC designator ( )

can be found on the outer packaging for this package.

Note: In the event the full M icroc hip p art numb er cann ot be mark ed on one line, it wil l

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

11AAXXX/11LCXXX

8-Lead MSOP (150 mil) Example:

XXXXXXT

YWWNNN 11A01I

8281L7

8-Lead MSOP Package Marking (Pb-Free)

Device Line 1 Marking Device Line 1 Marking

11AA010 11A01T 11LC010 11L01T

11AA020 11A02T 11LC020 11L02T

11AA040 11A04T 11LC040 11L04T

11AA080 11A08T 11LC080 11L08T

11AA160 11AAT 11LC160 11LAT

Note: T = Temperature Grade (I, E)

Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)

YY Year code (last 2 digits of calendar year)

WW Week code (week of January 1 is week ‘01’)

NNN Alphanumeric traceability code

Pb-free JEDEC designator for Matte Tin (Sn)

*This package is Pb-fr ee. The Pb- fre e JED EC designator ( )

can be found on the outer packaging for this package.

Note: In the event the full M icroc hip p art numb er cann ot be mark ed on one line, it wil l

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

11AAXXX/11LCXXX

8-Lead 2x3 TD FN Example:

XXX

YWW

D51

828

8-Lead 2x3 TDFN Package Marking (Pb-Free)

Device I-Temp Marking Device I-Temp Marking E-Temp Marking

11AA010 D11 11LC010 D14 D15

11AA020 D21 11LC020 D24 D25

11AA040 D31 11LC040 D34 D35

11AA080 D41 11LC080 D44 D45

11AA160 D51 11LC160 D54 D55

Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)

YY Year code (last 2 digits of calendar year)

WW Week code (week of January 1 is week ‘01’)

NN Alphanumeric traceability code

Pb-free JEDEC designator for Matte Tin (Sn)

*This package is Pb-fr ee. The Pb- fre e JED EC designator ( )

can be found on the outer packaging for this package.

Note: In the event the full M icroc hip p art numb er cann ot be mark ed on one line, it wil l

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

11AAXXX/11LCXXX

3-Lead SOT-23

XXNN

Example:

B517

3-Lead SOT-23 Package Marking (Pb-Free)

Device I-Temp Marking Device I-Temp Marking E-Temp Marking

11AA010 B1NN 11LC010 M1NN N1NN

11AA020 B2NN 11LC020 M2NN N2NN

11AA040 B3NN 11LC040 M3NN N3NN

11AA080 B4NN 11LC080 M4NN N4NN

11AA160 B5NN 11LC160 M5NN N5NN

Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)

YY Year code (last 2 digits of calendar year)

WW Week code (week of January 1 is week ‘01’)

NNN Alphanumeric traceability code

Pb-free JEDEC designator for Matte Tin (Sn)

*This package is Pb-fr ee. The Pb- fre e JED EC designator ( )

can be found on the outer packaging for this package.

Note: In the event the full M icroc hip p art numb er cann ot be mark ed on one line, it wil l

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

11AAXXX/11LCXXX



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&  1,

&&  = = 

##44!!   - 

1!&&   = =

"#&"#>#& .  - -

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: 9&  -< -? 

&& 9  - 

9#4!!  <  

69#>#& )  ? 

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: *+ 1 = = -

NOTE 1

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11AAXXX/11LCXXX

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  !"#$%&"' ()"&'"!&)&#*&&&#

 +%&,&!&

- '!!#.#&"#'#%!&"!!#%!&"!!!&$#''!#

 '!#&.0

1,2 1!'!&$& "!**&"&&!

.32 %'!("!"*&"&&(%%'&"!!

&&255***''54

6&! 99..

'!9'&! 7 7: ;

7"')%! 7 <

&  1,

: 8&  = = 

##44!!   = =

&#%%+  = 

: >#& . ?1,

##4>#& . -1,

: 9&  1,

,'%@&A   = 

3&9& 9  = 

3&& 9 .3

3& IB = <B

9#4!!   = 

9#>#& ) - = 

#%& DB = B

#%&1&&' EB = B

NOTE 1

12 3

  * ,1

11AAXXX/11LCXXX

 ! ""#$%& !'

&&255***''54

11AAXXX/11LCXXX

(" !)*( ( !



  !"#$%&"' ()"&'"!&)&#*&&&#

 '!!#.#&"#'#%!&"!!#%!&"!!!&$#''!#

- '!#&.0

1,2 1!'!&$& "!**&"&&!

.32 %'!("!"*&"&&(%%'&"!!

&&255***''54

6&! 99..

'!9'&! 7 7: ;

7"')%! 7 <

&  ?1,

: 8&  = = 

##44!!   < 

&#%%   = 

: >#& . 1,

##4>#& . -1,

: 9&  -1,

3&9& 9  ? <

3&& 9 .3

3& IB = <B

9#4!!  < = -

9#>#& )  = 

NOTE 1

L1 L

  * ,1

11AAXXX/11LCXXX

+$)*(,--%./0+

&&255***''54

11AAXXX/11LCXXX

+$)*(,--%./0+

&&255***''54

11AAXXX/11LCXXX

 !0""00 !0,



 '!!#.#&"#'#%!&"!!#%!&"!!!&$#''!#

 '!#&.0

1,2 1!'!&$& "!**&"&&!

&&255***''54

6&! 99..

'!9'&! 7 7: ;

7"')%! 7 -

9#&  1,

:"&!#9#&  1,

: 8&  < = 

##44!!    

&#%%   = 

: >#& .  = ?

##4>#& . ? - 

: 9&  ?  -

3&9& 9 -  ?

3& IB = B

9#4!!  < = 

9#>#& ) - = 

  * ,1

11AAXXX/11LCXXX

APPENDIX A: REVISION HISTORY

Revision A (10/07)

Original release of this document.

Revision B (01/08)

Revised SOT-23 Package Type; Revised DFN

pac kage to TDFN; Sec tion 3.3 (ad ded new bul let item);

Section 4.5 note; Table 7-1.

Revision C (03/08)

Removed patent pending notice; Revised Tables 1-1

and 1-2; Section 3.3 (bullet 3) and 3.7 (bullet 2);

Product ID System.

Revision D (04/08)

Revised document status to Preliminary; General

updates.

Revision E (09/08)

Updated UNI/O trademark; Revised Table 1-2,

parameters 3 and 5; Updated package drawings.

11AAXXX/11LCXXX

NOTES:

11AAXXX/11LCXXX

THE MICROCHIP WEB SITE

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www.microchi p.c om . Thi s web si te i s us ed as a m ean s

to make files and information easily available to

customers. Accessible by using your favorite Internet

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Technical s upport is a vailable through the web si te

at: http://support.microchip.com

11AAXXX/11LCXXX

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3. Do you find the organization of this document easy to follow? If not, why?

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11AAXXX/11LCXXX

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

PART NO. X X /XXX

PackageTemperatureTape & Reel

Device

Device: 11AA010 = 1 Kbit, 1.8V UNI/O Serial EEPROM

11LC010 = 1 Kbit, 2.5V UNI/O Serial EEPROM

11AA020 = 2 Kbit, 1.8V UNI/O Serial EEPROM

11LC020 = 2 Kbit, 2.5V UNI/O Serial EEPROM

11AA040 = 4 Kbit, 1.8V UNI/O Serial EEPROM

11LC040 = 4 Kbit, 2.5V UNI/O Serial EEPROM

11AA080 = 8 Kbit, 1.8V UNI/O Serial EEPROM

11LC080 = 8 Kbit, 2.5V UNI/O Serial EEPROM

11AA160 = 16 Kbit, 1.8V UNI/O Serial EEPROM

11LC160 = 16 Kbit, 2.5V UNI/O Serial EEPROM

Tape & Reel: T = Tape and Reel

Blank = Tube

Temperature

Range: I= -40°C to +85°C (Industrial)

E= -40°C to +125°C (Extended)

Package: P = 8-lead Plastic DIP (300 mil body)

SN = 8-lead Plastic SOIC (3.90 mm body)

MS = 8-lead Plastic Micro Small Outline (MSOP)

MNY(1) = 8-lead 2x3 mm TDFN

TT = 3-lead SOT 23 (Tape and Reel only)

Examples:

a) 11AA010-I/P = 1 Kbit, 1.8V Serial EEPROM,

Industrial temp., PDIP package

b) 11LC160T-E/TT = 16 Kbit, 2.5V Serial

EEPROM, Extended temp., Tape & Reel,

SOT-23 package

c) 11AA080-I/MS = 8 Kbit, 1.8V Seria l EEPROM,

Industrial temp., MSOP package

d) 11LC020T -I/SN = 2 Kb it, 2.5V Serial EEPROM,

Industrial temp., Tape & Reel, SOIC package

e) 11AA040T-I/MNY = 4 Kbit, 1.8V Serial

EEPROM, Industrial temp., Tape and Reel,

2x3 mm TDFN package, Nickel Palladium Gold

finish

Range

Note 1: “Y” indicates a Nickel Palladium Gold (NiPdAu) finish.

11AAXXX/11LCXXX

NOTES:

Information contained in this publication regarding device

applications a nd the lik e is pro vid ed only for your c on venience

and may be supers eded by u pdates. It is y o u r r es ponsibil i ty to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron,

dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,

PICSTART, rfPIC, SmartShunt and UNI/O are registered

trademarks of Microchip Technology Incorporated in the

U.S.A. and other countries.

FilterLab, Linear Active Thermistor, MXDEV, MXLAB,

SEEV AL, SmartSensor and The Embedded Control Solutions

Company are registered trademarks of Microchip Technology

Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard,

dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,

ECONOMONITOR, FanSense, In-Circuit Serial

Prog ra m ming , IC SP, ICEPIC , M i n di , MiWi, MPASM, MP L AB

Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM,

PICDEM.net, PICtail , PIC32 logo, PowerCal, PowerInfo,

PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total

Endurance, WiperLock and ZENA are trademarks of

Microchip Technology I ncorporat ed in the U.S.A. and other

countries.

SQTP is a service mark of Microchip T echnology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure famili es of its kind on t he market today, when used in the

intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is c onstantly evolving. We a t Microc hip are co m mitted to continuously improving the code prot ect ion featur es of our

products. Attempts to break Microchip’ s code protection feature may be a violation of the Digital Mill ennium Copyright Act. If such act s

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Microchip received ISO/TS-16949:2002 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresham, Oregon and design centers in California

and India. The Company’s quality system processes and procedures

are for its PIC® MCUs and dsPI C® DSCs, KEELOQ® code hopping

devices, Serial EEPROMs, microperiph erals, nonvolatile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

AMERICAS

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Web Address:

www.microchip.com

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01/02/08