Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 1
Rev.  A
02/03/2011
Copyright © 2011 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI
assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device
specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be ex-
pected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon
Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
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c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
IS63WV1288DALL/DALS
IS63WV1288DBLL/DBLS
IS64WV1288DBLL/DBLS
128K x 8  HIGH-SPEED CMOS STATIC RAM
FEATURES
HIGH SPEED: (IS63/64WV1288DALL/DBLL)
• High-speed access time: 8, 10, 12, 20 ns
• Low Active Power: 135 mW (typical)
• Low Standby Power: 12 µW (typical)
CMOS standby
LOW POWER: (IS63/64WV1288DALS/DBLS)
• High-speed access time: 25, 35 ns
• Low Active Power: 55 mW (typical)
• Low Standby Power: 12 µW (typical)
CMOS standby
• Single power supply
— Vdd 1.65V to 2.2V (IS63WV1288DAxx)
— Vdd 2.4V to 3.6V (IS63/64WV1288DBxx)
• Multiple center power and ground pins for
greater noise immunity
• Easy memory expansion with CE and OE options
• CE power-down
• Fully static operation: no clock or refresh
required
• TTL compatible inputs and outputs
• Lead-free available
DESCRIPTION
The ISSI IS63/64WV1288Dxxx is a very high-speed,
low power, 131,072-word by 8-bit CMOS static RAM.
The IS63/64WV1288DBLL is fabricated using ISSI's
high-performance CMOS technology. This highly reliable
process coupled with innovative circuit design
techniques, yields higher performance and low power
consumption devices.
When CE is HIGH (deselected), the device assumes a
standby mode at which the power dissipation can be re-
duced down to 25 µW (typical) with CMOS input levels.
The IS63/64WV1288DBLL operates from a single Vdd
power supply. The IS63/64WV1288Dxxx is available in
32-pin TSOP (Type II), 32-pin sTSOP (Type I), 48-Ball
miniBGA (6mm x 8mm), and 32-pin SOJ (300-mil) pack-
ages.
FUNCTIONAL BLOCK DIAGRAM
A0-A16
CE
OE
WE
128K X 8
MEMORY ARRAY
DECODER
COLUMN I/O
CONTROL
CIRCUIT
GND
VDD
I/O
DATA
CIRCUIT
I/O0-I/O7
MARCH 2011
2 Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
02/03/2011
IS63WV1288DALL/DALS
IS63WV1288DBLL/DBLS
IS64WV1288DBLL/DBLS
PIN DESCRIPTIONS
A0-A16 Address Inputs
CE Chip Enable Input
OE Output Enable Input
WE Write Enable Input
I/O0-I/O7 Bidirectional Ports
Vdd Power
GND Ground
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A0
A1
A2
A3
CE
I/O0
I/O1
VDD
GND
I/O2
I/O3
WE
A4
A5
A6
A7
A16
A15
A14
A13
OE
I/O7
I/O6
GND
VDD
I/O5
I/O4
A12
A11
A10
A9
A8
PIN CONFIGURATION
32-Pin TSOP (Type II) (T)
32-Pin sTSOP (Type I) (H)
PIN CONFIGURATION
48-mini BGA (B)  (6 mm x 8 mm)
PIN CONFIGURATION
32-Pin SOJ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A0
A1
A2
A3
CE
I/O0
I/O1
VDD
GND
I/O2
I/O3
WE
A4
A5
A6
A7
A16
A15
A14
A13
OE
I/O7
I/O6
GND
VDD
I/O5
I/O4
A12
A11
A10
A9
A8
1 2 3 4 5 6
A
B
C
D
E
F
G
H
NC OE A2 A6 A7 NC
I/O
0
NC A1 A5 CE I/O
7
I/O
1
NC A0 A4 NC I/O
6
GND NC NC A3 NC V
DD
V
DD
NC NC NC NC GND
I/O
2
NC A14 A11 I/O
4
I/O
5
I/O
3
NC A15 A12 WE A8
NC A10 A16 A13 A9 NC
Integrated Silicon Solution, Inc. — www.issi.com 3
Rev. A
02/03/2011
IS63WV1288DALL/DALS
IS63WV1288DBLL/DBLS
IS64WV1288DBLL/DBLS
TRUTH TABLE
  Mode  WE CE OE  I/O Operation  VDD Current
 Not Selected X H X High-Z Isb1, Isb2
(Power-down)
Output Disabled H L H High-Z Icc1, Icc2
Read H L L dout Icc1, Icc2
Write L L X dIn Icc1, Icc2
ABSOLUTE MAXIMUM RATINGS(1)
  Symbol  Parameter  Value  Unit
 Vterm Terminal Voltage with Respect to GND –0.5 to Vdd+0.5 V
tstg Storage Temperature –65 to +150 °C
Pt Power Dissipation 1.5 W
Vdd Vdd Related to GND -0.2 to +3.9 V
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
4 Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
02/03/2011
IS63WV1288DALL/DALS
IS63WV1288DBLL/DBLS
IS64WV1288DBLL/DBLS
AC TEST LOADS
Figure 1.
R1
5 pF
Including
jig and
scope
R2
OUTPUT
VTM
Figure 2.
ZO = 50Ω
VDD/2
50Ω
OUTPUT
30 pF
Including
jig and
scope
AC TEST CONDITIONS
 
Parameter  Unit  Unit  Unit     
    (2.4V-3.6V)  (3.3V + 5%)  (1.65V-2.2V)
 Input Pulse Level 0.4V to Vdd - 0.3V 0.4V to Vdd - 0.3V 0.4V to Vdd - 0.3V
Input Rise and Fall Times 1V/ ns 1V/ ns 1V/ ns
Input and Output Timing VDD /2 VDD + 0.05 0.9V
and Reference Level (VRef) 2
Output Load See Figures 1 and 2 See Figures 1 and 2 See Figures 1 and 2
R1 ( Ω ) 1909 317 13500
R2 ( Ω ) 1105 351 10800
Vtm (V) 3.0V 3.3V 1.8V
Integrated Silicon Solution, Inc. — www.issi.com 5
Rev. A
02/03/2011
IS63WV1288DALL/DALS
IS63WV1288DBLL/DBLS
IS64WV1288DBLL/DBLS
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
VDD = 2.4V-3.6V
  Symbol  Parameter  Test Conditions  Min.  Max.  Unit
 Voh Output HIGH Voltage Vdd = Min., Ioh = –1.0 mA 1.8 — V
Vol Output LOW Voltage Vdd = Min., Iol = 1.0 mA — 0.4 V
VIh Input HIGH Voltage 2.0 Vdd + 0.3 V
VIl Input LOW Voltage(1) –0.3 0.8 V
IlI Input Leakage GND ≤ VIn ≤ Vdd –1 1 µA
Ilo Output Leakage GND ≤ Vout ≤ Vdd, Outputs Disabled –1 1 µA
Note:
1. VIl (min.) = –0.3V DC; VIl (min.) = –2.0V AC (pulse width < 10 ns). Not 100% tested.
VIh (max.) = Vdd + 0.3V dc; VIh (max.) = Vdd + 2.0V Ac (pulse width < 10 ns). Not 100% tested.
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
VDD = 3.3V + 5%
  Symbol  Parameter  Test Conditions  Min.  Max.  Unit
 Voh Output HIGH Voltage Vdd = Min., Ioh = –4.0 mA 2.4 — V
Vol Output LOW Voltage Vdd = Min., Iol = 8.0 mA — 0.4 V
VIh Input HIGH Voltage 2 Vdd + 0.3 V
VIl Input LOW Voltage(1) –0.3 0.8 V
IlI Input Leakage GND ≤ VIn ≤ Vdd –1 1 µA
Ilo Output Leakage GND ≤ Vout ≤ Vdd, Outputs Disabled –1 1 µA
Note:
1. VIl (min.) = –0.3V DC; VIl (min.) = –2.0V AC (pulse width < 10 ns). Not 100% tested.
VIh (max.) = Vdd + 0.3V dc; VIh (max.) = Vdd + 2.0V Ac (pulse width < 10 ns). Not 100% tested.
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
VDD = 1.65V-2.2V
  Symbol  Parameter  Test Conditions  VDD  Min.  Max.  Unit
 Voh Output HIGH Voltage Ioh = -0.1 mA 1.65-2.2V 1.4 — V
Vol Output LOW Voltage Iol = 0.1 mA 1.65-2.2V — 0.2 V
VIh Input HIGH Voltage 1.65-2.2V 1.4 Vdd + 0.2 V
VIl(1) Input LOW Voltage 1.65-2.2V –0.2 0.4 V
IlI Input Leakage GND ≤ VIn ≤ Vdd –1 1 µA
Ilo Output Leakage GND ≤ Vout ≤ Vdd, Outputs Disabled –1 1 µA
Note:
1. VIl (min.) = –0.3V DC; VIl (min.) = –2.0V AC (pulse width < 10 ns). Not 100% tested.
VIh (max.) = Vdd + 0.3V dc; VIh (max.) = Vdd + 2.0V Ac (pulse width < 10 ns). Not 100% tested.
6 Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
02/03/2011
IS63WV1288DALL/DALS
IS63WV1288DBLL/DBLS
IS64WV1288DBLL/DBLS
OPERATING RANGE (VDD) (IS63WV1288DBLL)(1)
  Range  Ambient Temperature VDD (8 nS)1 VDD (10 nS)1
 Commercial 0°C to +70°C 3.3V + 5% 2.4V-3.6V
Industrial –40°C to +85°C 3.3V + 5% 2.4V-3.6V
Note:
1. When operated in the range of 2.4V-3.6V, the device meets 10ns. When operated in the range of 3.3V + 5%,
the device meets 8ns.
OPERATING RANGE (VDD) (IS64WV1288DBLL)(2)
  Range  Ambient Temperature VDD (8 nS)2 VDD (10 nS)2
 Automotive –40°C to +125°C 3.3V + 5% 2.4V-3.6V
Note:
2. When operated in the range of 2.4V-3.6V, the device meets 10ns. When operated in the range of 3.3V + 5%,
the device meets 8ns.
HIGH SPEED (IS63WV1288DALL/DBLL)
OPERATING RANGE (VDD) (IS63WV1288DALL)
  Range  Ambient Temperature VDD Speed
 Commercial 0°C to +70°C 1.65V-2.2V 20ns
Industrial –40°C to +85°C 1.65V-2.2V 20ns
Automotive –40°C to +125°C 1.65V-2.2V 20ns
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
    -8  -10  -12  -20 
  Symbol  Parameter  Test Conditions    Min.    Max.  Min.    Max.  Min.    Max.  Min.    Max.  Unit
Icc Vdd Dynamic Operating Vdd = Max., Com. — 65 — 50 — 45 — 40 mA
Supply Current Iout = 0 mA, f = fmAx Ind. — 70 — 55 — 50 — 45
CE = VIl Auto.(3) — — — 65 — 55 — 50
VIn ≥ Vdd – 0.3V, or typ.(2) 45 45
VIn ≤ 0.4V
Isb2 CMOS Standby Vdd = Max., Com. — 40 — 40 — 40 — 40
µ
A
Current (CMOS Inputs) CE ≥ Vdd – 0.2V, Ind. — 55 — 55 — 55 — 55
VIn ≥ Vdd – 0.2V, or Auto. — — — 90 — 90 — 90
VIn ≤ 0.2V
, f = 0 typ.(2) 4 4
Note:
1. At f = fmAx, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
2. Typical values are measured at Vdd = 3.0V, TA = 25oC and not 100% tested.
3. For Automotive grade at 15ns, typ. Icc = 38mA, not 100% tested.
Integrated Silicon Solution, Inc. — www.issi.com 7
Rev. A
02/03/2011
IS63WV1288DALL/DALS
IS63WV1288DBLL/DBLS
IS64WV1288DBLL/DBLS
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
    -25  -35  -45 
  Symbol  Parameter  Test Conditions    Min.  Max.  Min.  Max.  Min.  Max.  Unit
Icc Vdd Dynamic Operating Vdd = Max., Com. — 15 — 15 — 12 mA
Supply Current Iout = 0 mA, f = fmAx Ind. — 20 — 20 — 18
CE = VIl Auto. — 30 — 30 — 25
VIn ≥ Vdd – 0.3V, or typ.(2) 18
VIn ≤ 0.4V
Isb2 CMOS Standby Vdd = Max., Com. — 40 — 40 — 40
µ
A
Current (CMOS Inputs) CE ≥ Vdd – 0.2V, Ind. — 50 — 50 — 50
VIn ≥ Vdd – 0.2V, or Auto. — 75 — 75 — 75
VIn ≤ 0.2V
, f = 0 typ.(2) 4
Note:
1. At f = fmAx, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
2. Typical values are measured at Vdd = 3.0V, TA = 25oC and not 100% tested.
OPERATING RANGE (VDD) (IS63WV1288DBLS)
  Range  Ambient Temperature VDD (35 nS)
 Commercial 0°C to +70°C 2.4V-3.6V
Industrial –40°C to +85°C 2.4V-3.6V
LOW POWER (IS63WV1288DALS/DBLS)
OPERATING RANGE (VDD) (IS63WV1288DALS)
  Range  Ambient Temperature VDD Speed
 Commercial 0°C to +70°C 1.65V-2.2V 45ns
Industrial –40°C to +85°C 1.65V-2.2V 45ns
Automotive –40°C to +125°C 1.65V-2.2V 55ns
OPERATING RANGE (VDD) (IS64WV1288DBLS)
  Range  Ambient Temperature VDD (35 nS)
 Automotive –40°C to +125°C 2.4V-3.6V
8 Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
02/03/2011
IS63WV1288DALL/DALS
IS63WV1288DBLL/DBLS
IS64WV1288DBLL/DBLS
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
    -8 ns  -10 ns  -12 ns 
  Symbol  Parameter      Min.  Max.  Min.  Max.  Min.  Max.  Unit
trc Read Cycle Time 8 — 10 — 12 — ns
tAA Address Access Time — 8 — 10 — 12 ns
tohA Output Hold Time 2 — 2 — 2 — ns
tAce CE Access Time — 8 — 10 — 12 ns
tdoe OE Access Time — 4 — 5 — 6 ns
tlzoe(2) OE to Low-Z Output 0 — 0 — 0 — ns
thzoe(2) OE to High-Z Output 0 4 0 5 0 6 ns
tlzce(2) CE to Low-Z Output 3 — 3 — 3 — ns
thzce(2) CE to High-Z Output 0 4 0 5 0 6 ns
tPu CE to Power Up Time 0 — 0 — 0 — ns
tPd CE to Power Down Time — 8 — 10 — 12 ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V load-
ing specified in Figure 1.
2. Tested with the loading specified in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
                                                         
-20 ns    -25 ns     -35 ns    -45 ns 
  Symbol  Parameter    Min.  Max.  Min.    Max.  Min.   Max.  Min.    Max.  Unit
trc Read Cycle Time 20 — 25 — 35 — 45 — ns
tAA Address Access Time — 20 — 25 — 35 — 45 ns
tohA Output Hold Time 2.5 — 6 — 8 — 10 — ns
tAce CE Access Time — 20 — 25 — 35 — 45 ns
tdoe OE Access Time — 8 — 12 — 15 — 20 ns
thzoe(2) OE to High-Z Output 0 8 0 8 0 10 0 15 ns
tlzoe(2) OE to Low-Z Output 0 — 0 — 0 — 0 — ns
thzce(2 CE to High-Z Output 0 8 0 8 0 10 0 15 ns
tlzce(2) CE to Low-Z Output 3 — 10 — 10 — 10 — ns
Notes:
1. Test conditions assume signal transition times of 1.5 ns or less, timing reference levels of 1.25V, input pulse levels of 0.4V to
Vdd-0.3V and output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. Not 100% tested.
Integrated Silicon Solution, Inc. — www.issi.com 9
Rev. A
02/03/2011
IS63WV1288DALL/DALS
IS63WV1288DBLL/DBLS
IS64WV1288DBLL/DBLS
DATA VALID
READ1.eps
PREVIOUS DATA VALID
t
AA
t
OHA
t
OHA
t
RC
DOUT
ADDRESS
t
RC
t
OHA
t
AA
t
DOE
t
LZOE
t
ACE
t
LZCE
t
HZOE
HIGH-Z DATA VALID
CE_RD2.eps
ADDRESS
OE
CE
D
OUT
t
HZCE
READ CYCLE NO. 2(1,3)
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE = VIl.
3. Address is valid prior to or coincident with CE LOW transitions.
AC WAVEFORMS
READ CYCLE NO. 1(1,2)
10 Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
02/03/2011
IS63WV1288DALL/DALS
IS63WV1288DBLL/DBLS
IS64WV1288DBLL/DBLS
WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range)
    -8 ns  -10 ns  -12 ns 
  Symbol  Parameter      Min.  Max.  Min.  Max.  Min.  Max.  Unit
twc Write Cycle Time 8 — 10 — 12 — ns
tsce CE to Write End 7 — 7 — 8 — ns
tAw Address Setup Time to 8 — 8 — 8 — ns
Write End
thA Address Hold from 0 — 0 — 0 — ns
Write End
tsA Address Setup Time 0 — 0 — 0 — ns
tPwe1
(1) WE Pulse Width (OE High) 7 — 7 — 8 — ns
tPwe2
(2) WE Pulse Width (OE Low) 8 — 10 — 12 — ns
tsd Data Setup to Write End 5 — 5 — 6 — ns
thd Data Hold from Write End 0 — 0 — 0 — ns
thzwe(2) WE LOW to High-Z Output — 4 — 5 — 6 ns
tlzwe(2) WE HIGH to Low-Z Output 3 — 3 — 3 — ns
Notes:
1. Test conditions assume signal transition times of 3ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the Write.
WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range)
                  
   -20 ns    -25 ns    -35 ns   -45ns
  Symbol  Parameter    Min.    Max.  Min.    Max.  Min.   Max.  Min.    Max.  Unit
twc Write Cycle Time 20 — 25 — 35 — 45 — ns
tsce CE to Write End 12 — 18 — 25 — 35 — ns
tAw Address Setup Time 12 — 15 — 25 — 35 — ns
to Write End
thA Address Hold from Write End 0 — 0 — 0 — 0 — ns
tsA Address Setup Time 0 — 0 — 0 — 0 — ns
tPwe1 WE Pulse Width (OE = HIGH) 12 — 18 — 30 — 35 — ns
tPwe2 WE Pulse Width (OE = LOW) 17 — 20 — 30 — 35 — ns
tsd Data Setup to Write End 9 — 12 — 15 — 20 — ns
thd Data Hold from Write End 0 — 0 — 0 — 0 — ns
thzwe(3) WE LOW to High-Z Output — 9 — 12 — 20 — 20 ns
tlzwe(3) WE HIGH to Low-Z Output 3 — 5 — 5 — 5 — ns
Notes:
1. Test conditions for IS61WV6416LL assume signal transition times of 1.5ns or less, timing reference levels of 1.25V, input pulse
levels of 0.4V to Vdd-0.3V and output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the write.
Integrated Silicon Solution, Inc. — www.issi.com 11
Rev. A
02/03/2011
IS63WV1288DALL/DALS
IS63WV1288DBLL/DBLS
IS64WV1288DBLL/DBLS
AC WAVEFORMS
WRITE CYCLE NO. 1(1,2  (CE Controlled, OE = HIGH or LOW)
12 Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
02/03/2011
IS63WV1288DALL/DALS
IS63WV1288DBLL/DBLS
IS64WV1288DBLL/DBLS
AC WAVEFORMS
WRITE CYCLE NO. 2(1)
(WE Controlled, OE = hIgh during Write Cycle)
WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle)
Notes:
1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the Write.
2. I/O will assume the High-Z state if OE > VIh.
DATA UNDEFINED
LOW
t WC
VALID ADDRESS
t PWE1
t AW
t HA
HIGH-Z
t HD
t SA t HZWE
ADDRESS
CE
WE
D
OUT
D
IN
OE
DATA
IN
VALID
t LZWE
t SD
CE_WR2.eps
DATA UNDEFINED
t
WC
VALID ADDRESS
LOW
LOW
t
PWE2
t
AW
t
HA
HIGH-Z
t
HD
t
SA
t
HZWE
ADDRESS
CE
WE
D
OUT
D
IN
OE
DATA
IN
VALID
t
LZWE
t
SD
CE_WR3.eps
Integrated Silicon Solution, Inc. — www.issi.com 13
Rev. A
02/03/2011
IS63WV1288DALL/DALS
IS63WV1288DBLL/DBLS
IS64WV1288DBLL/DBLS
DATA RETENTION WAVEFORM (CE Controlled)
HIGH SPEED (IS63/4WV1288DALL/DBLL)
DATA RETENTION SWITCHING CHARACTERISTICS  (2.4V-3.6V)
    Symbol  Parameter  Test Condition  Options  Min.  Typ.(1)  Max.  Unit
Vdr Vdd for Data Retention See Data Retention Waveform 2.0 — 3.6 V
Idr Data Retention Current Vdd = 2.0V, CE ≥ Vdd – 0.2V Com. — 4 40
µA
Ind. — — 55
Auto. 90
tsdr Data Retention Setup Time See Data Retention Waveform 0 — — ns
trdr Recovery Time See Data Retention Waveform trc — — ns
Note 1: Typical values are measured at Vdd = 3.0V, TA = 25
o
c and not 100% tested.
VDD
CE ≥ V
DD
- 0.2V
t
SDR
t
RDR
V
DR
CE
GND
Data Retention Mode
DATA RETENTION SWITCHING CHARACTERISTICS  (1.65V-2.2V)
    Symbol  Parameter  Test Condition  Options  Min.  Typ.(1)  Max.  Unit
Vdr Vdd for Data Retention See Data Retention Waveform 1.2 — 3.6 V
Idr Data Retention Current Vdd = 1.2V, CE ≥ Vdd – 0.2V Com. — 4 40
µA
Ind. — — 55
Auto. — — 90
tsdr Data Retention Setup Time See Data Retention Waveform 0 — — ns
trdr Recovery Time See Data Retention Waveform trc — — ns
Note 1: Typical values are measured at Vdd = 1.8V, TA = 25
o
c and not 100% tested.
14 Integrated Silicon Solution, Inc. — www.issi.com
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IS63WV1288DALL/DALS
IS63WV1288DBLL/DBLS
IS64WV1288DBLL/DBLS
DATA RETENTION WAVEFORM (CE Controlled)
LOW POWER (IS63/4WV1288DALS/DBLS)
DATA RETENTION SWITCHING CHARACTERISTICS  (2.4V-3.6V)
    Symbol  Parameter  Test Condition  Options  Min.  Typ.(1)  Max.  Unit
Vdr Vdd for Data Retention See Data Retention Waveform 2.0 — 3.6 V
Idr Data Retention Current Vdd = 2.0V, CE ≥ Vdd – 0.2V Com. — 4 40
µA
Ind. — — 50
Auto. 75
tsdr Data Retention Setup Time See Data Retention Waveform 0 — — ns
trdr Recovery Time See Data Retention Waveform trc — — ns
Note 1: Typical values are measured at Vdd = 3.0V, TA = 25
o
c and not 100% tested.
VDD
CE ≥ V
DD
- 0.2V
t
SDR
t
RDR
V
DR
CE
GND
Data Retention Mode
DATA RETENTION SWITCHING CHARACTERISTICS  (1.65V-2.2V)
    Symbol  Parameter  Test Condition  Options  Min.  Typ.(1)  Max.  Unit
Vdr Vdd for Data Retention See Data Retention Waveform 1.2 — 3.6 V
Idr Data Retention Current Vdd = 1.2V, CE ≥ Vdd – 0.2V Com. — 4 40
µA
Ind. — — 50
Auto. — — 75
tsdr Data Retention Setup Time See Data Retention Waveform 0 — — ns
trdr Recovery Time See Data Retention Waveform trc — — ns
Note 1: Typical values are measured at Vdd = 1.8V, TA = 25
o
c and not 100% tested.
Integrated Silicon Solution, Inc. — www.issi.com 15
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IS63WV1288DALL/DALS
IS63WV1288DBLL/DBLS
IS64WV1288DBLL/DBLS
ORDERING INFORMATION
Industrial Range: –40°C to +85°C
 Speed (ns)  Order Part No.  Package
8 IS63WV1288DBLL-8TI 32-pin TSOP (Type II)
IS63WV1288DBLL-8TLI 32-pin TSOP (Type II), Lead-free
IS63WV1288DBLL-8HI sTSOP (Type I) (8mm x13.4mm)
IS63WV1288DBLL-8HLI sTSOP (Type I) (8mm x13.4mm), Lead-free
IS63WV1288DBLL-8JI 32-pin SOJ (300-mil)
IS63WV1288DBLL-8JLI 32-pin SOJ (300-mil), Lead-free
10 IS63WV1288DBLL-10TI 32-pin TSOP (Type II)
IS63WV1288DBLL-10TLI 32-pin TSOP (Type II), Lead-free
IS63WV1288DBLL-10HI sTSOP (Type I) (8mm x13.4mm)
IS63WV1288DBLL-10HLI sTSOP (Type I) (8mm x13.4mm), Lead-free
IS63WV1288DBLL-10JI 32-pin SOJ (300-mil)
IS63WV1288DBLL-10JLI 32-pin SOJ (300-mil), Lead-free
Automotive Range (A3): –40°C to +125°C
 Speed (ns)  Order Part No.  Package
10(8*) IS64WV1288DBLL-10TA3 32-pin TSOP (Type II)
IS64WV1288DBLL-10TLA3 32-pin TSOP (Type II), Lead-free
IS64WV1288DBLL-10HA3 sTSOP (Type I) (8mm x13.4mm)
IS64WV1288DBLL-10HLA3 sTSOP (Type I) (8mm x13.4mm), Lead-free
Note:
1. Speed = 8ns for Vdd = 3.3V + 5%. Speed = 10ns for Vdd = 2.4V-3.6V.
16 Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
02/03/2011
IS63WV1288DALL/DALS
IS63WV1288DBLL/DBLS
IS64WV1288DBLL/DBLS
Integrated Silicon Solution, Inc. — www.issi.com 17
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IS63WV1288DALL/DALS
IS63WV1288DBLL/DBLS
IS64WV1288DBLL/DBLS
18 Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
02/03/2011
IS63WV1288DALL/DALS
IS63WV1288DBLL/DBLS
IS64WV1288DBLL/DBLS
Integrated Silicon Solution, Inc. — www.issi.com 19
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IS63WV1288DALL/DALS
IS63WV1288DBLL/DBLS
IS64WV1288DBLL/DBLS
2. Reference document : JEDEC MO-207
1. CONTROLLING DIMENSION : MM .
NOTE :
08/12/2008
Package Outline