REV. D
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
ADG438F/ADG439F
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 2000
High Performance 4/8 Channel
Fault-Protected Analog Multiplexers
FUNCTIONAL BLOCK DIAGRAMS
S1
S8
A0
D
A1 A2 EN
ADG438F
1 OF 8
DECODER
A0
ADG439F
A1 EN
S1A DA
S4A
S1B
S4B DB
1 OF 4
DECODER
FEATURES
Fast Switching Times
tON 250 ns max
tOFF 150 ns max
Fault and Overvoltage Protection (–40 V, +55 V)
All Switches OFF with Power Supply OFF
Analog Output of ON Channel Clamped Within Power
Supplies If an Overvoltage Occurs
Latch-Up Proof Construction
Break Before Make Construction
TTL and CMOS Compatible Inputs
APPLICATIONS
Data Acquisition Systems
Industrial and Process Control Systems
Avionics Test Equipment
Signal Routing Between Systems
High Reliability Control Systems
GENERAL DESCRIPTION
The ADG438F/ADG439F are CMOS analog multiplexers, the
ADG438F comprising 8 single channels and the ADG439F
comprising four differential channels. These multiplexers pro-
vide fault protection. Using a series n-channel, p-channel, n-
channel MOSFET structure, both device and signal source
protection is provided in the event of an overvoltage or power
loss. The multiplexer can withstand continuous overvoltage
inputs from –40 V to +55 V. During fault conditions, the multi-
plexer input (or output) appears as an open circuit and only a
few nanoamperes of leakage current will flow. This protects not
only the multiplexer and the circuitry driven by the multiplexer,
but also protects the sensors or signal sources which drive the
multiplexer.
The ADG438F switches one of eight inputs to a common out-
put as determined by the 3-bit binary address lines A0, A1 and
A2. The ADG439F switches one of four differential inputs to a
common differential output as determined by the 2-bit binary
address lines A0 and A1. An EN input on each device is used to
enable or disable the device. When disabled, all channels are
switched OFF.
PRODUCT HIGHLIGHTS
1. Fault Protection.
The ADG438F/ADG439F can withstand continuous volt-
age inputs up to –40 V or +55 V. When a fault occurs due
to the power supplies being turned off, all the channels
are turned off and only a leakage current of a few nano-
amperes flows.
2. ON channel turns OFF while fault exists.
3. Low R
ON.
4. Fast Switching Times.
5. Break-Before-Make Switching.
Switches are guaranteed break-before-make so that input
signals are protected against momentary shorting.
6. Trench Isolation Eliminates Latch-up.
A dielectric trench separates the p- and n-channel MOSFETs
thereby preventing latch-up.
7. Improved OFF Isolation.
Trench isolation enhances the channel-to-channel isolation
of the ADG438F/ADG439F.
–2– REV. D
ADG438F/ADG439F–SPECIFICATIONS
1
Dual Supply
B Version
–40ⴗC to –40ⴗC to
Parameter +25ⴗC +85ⴗC +105ⴗC Units Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range V
SS
+ 1.2 V
SS
+ 1.2 V min
V
DD
– 0.8 V
DD
– 0.8 V max
R
ON
400 400 Ω max –10 V < V
S
< +10 V, I
S
= 1 mA;
∆R
ON
5 5 % max –5 V < V
S
< +5 V, I
S
= 1 mA;
R
ON
Drift 0.6 %/°C typ V
S
= 0 V, I
S
= 1 mA
R
ON
Match 3 3 3 % max V
S
= ±10 V, I
S
= 1 mA
LEAKAGE CURRENTS
Source OFF Leakage I
S
(OFF) ±0.01 nA typ V
D
= ±10 V, V
S
= ⫿10 V;
±0.5 ±2±5 nA max Test Circuit 2
Drain OFF Leakage I
D
(OFF) ±0.01 nA typ V
D
= ±10 V, V
S
= ⫿10 V;
ADG438F ±0.5 ±5±30 nA max Test Circuit 3
ADG439F ±0.5 ±5±15 nA max
Channel ON Leakage I
D
, I
S
(ON) ±0.01 nA typ V
S
= V
D
= ±10 V;
ADG438F ±0.5 ±5±30 nA max Test Circuit 4
ADG439F ±0.5 ±5±15 nA max
FAULT
Output Leakage Current ±0.02 nA typ V
S
= –33 V, +33 V or +50 V, V
D
= 0 V, Test Circuit 3
(With Overvoltage) ±0.1 ±2±10 µA max
Input Leakage Current ±0.005 µA typ V
S
= ±25 V, V
D
= ⫿10 V, Test Circuit 5
(With Overvoltage) ±0.1 ±1±2µA max
Input Leakage Current ±0.001 µA typ V
S
= ±25 V, V
D
= V
EN
= A0, A1, A2 = 0 V
(With Power Supplies OFF) ±0.1 ±1±4µA max Test Circuit 6
DIGITAL INPUTS
Input High Voltage, V
INH
2.4 2.4 V min
Input Low Voltage, V
INL
0.8 0.8 V max
Input Current
I
INL
or I
INH
±1±1µA max V
IN
= 0 or V
DD
C
IN
, Digital Input Capacitance 5 pF typ
DYNAMIC CHARACTERISTICS
2
t
TRANSITION
170 ns typ R
L
= 1 MΩ, C
L
= 35 pF;
220 300 320 ns max V
S1
= ±10 V, V
S8
= ⫿10 V; Test Circuit 7
t
OPEN
10 10 10 ns min R
L
= 1 kΩ, C
L
= 35 pF;
V
S
= +5 V; Test Circuit 8
t
ON
(EN) 200 ns typ R
L
= 1 kΩ, C
L
= 35 pF;
250 300 300 ns max V
S
= +5 V; Test Circuit 9
t
OFF
(EN) 110 ns typ R
L
= 1 kΩ, C
L
= 35 pF;
150 180 180 ns max V
S
= +5 V; Test Circuit 9
t
SETT
, Settling Time
0.1% 0.5 0.5 µs typ R
L
= 1 kΩ, C
L
= 35 pF;
0.01% 1.7 1.7 µs typ V
S
= +5 V
Charge Injection 4 pC typ V
S
=0V,R
S
=0Ω,C
L
= 1 nF; Test Circuit 10
OFF Isolation 80 dB typ R
L
= 1 kΩ, C
L
= 15 pF, f = 100 kHz;
V
S
= 7 V rms; Test Circuit 11
Channel-to-Channel Crosstalk 85 dB typ R
L
= 1 kΩ, C
L
= 15 pF, f = 100 kHz;
V
S
= 7 V rms; Test Circuit 12
C
S
(OFF) 5 pF typ
C
D
(OFF)
ADG438F 50 pF typ
ADG439F 25 pF typ
POWER REQUIREMENTS
I
DD
0.05 mA typ V
IN
= 0 V or 5 V
0.15 0.25 0.25 mA max
I
SS
0.01 mA typ
0.02 0.04 0.04 mA max
NOTES
1
Temperature range is as follows: B Version: –40°C to +105°C.
2
Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
(VDD = +15 V, VSS = –15 V, GND = 0 V, unless otherwise noted)
ADG438F/ADG439F
–3–REV. D
ABSOLUTE MAXIMUM RATINGS*
(T
A
= +25°C unless otherwise noted)
V
DD
to V
SS
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+44 V
V
DD
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +25 V
V
SS
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –25 V
V
EN
, V
A
Digital Input . . . . . . . – 0.3 V to V
DD
+ 2 V or 20 mA,
Whichever Occurs First
V
S
, Analog Input Overvoltage with Power ON . . . . . V
SS
– 25 V
to V
DD
+ 40 V
V
S
, Analog Input Overvoltage with Power OFF
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–40 V to +55 V
Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . . 20 mA
Peak Current, S or D
(Pulsed at 1 ms, 10% Duty Cycle max) . . . . . . . . . . . 40 mA
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . . –40°C to +105°C
Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
Plastic Package
θ
JA
, Thermal Impedance . . . . . . . . . . . . . . . . . . . . 117°C/W
Lead Temperature, Soldering (10 sec) . . . . . . . . . . . +260°C
SOIC Package
θ
JA
, Thermal Impedance
Narrow Body . . . . . . . . . . . . . . . . . . . . . . . . . . . 125°C/W
Wide Body . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Only one absolute
maximum rating may be applied at any one time.
Table I. ADG438F Truth Table
A2 A1 A0 EN ON SWITCH
XXX0 NONE
00011
00112
01013
01114
10015
10116
11017
11118
X = Don’t Care
Table II. ADG439F Truth Table
A1 A0 EN ON SWITCH PAIR
X X 0 NONE
0011
0112
1013
1114
X = Don’t Care
ADG438F/ADG439F PIN CONFIGURATIONS
DIP/SOIC DIP/SOIC
A0
EN
A1
A2
S2
S3
S4
S5
S6
S7
S1
GND
VDD
DS8
1
2
16
15
5
6
7
12
11
10
3
4
14
13
89
TOP VIEW
(Not to Scale)
ADG438F
VSS
A0
EN
A1
GND
S2A
S3A
S4A
S2B
S3B
S4B
VSS
S1A
VDD
S1B
DA DB
1
2
16
15
5
6
7
12
11
10
3
4
14
13
89
TOP VIEW
(Not to Scale)
ADG439F
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADG438F/ADG439F features proprietary ESD protection circuitry, permanent
damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper
ESD precautions are recommended to avoid performance degradation or loss of functionality.
ORDERING GUIDE
Model Temperature Range Package Option*
ADG438FBN –40°C to +105°C N-16
ADG438FBR –40°C to +105°C R-16N
ADG439FBN –40°C to +105°C N-16
ADG439FBR –40°C to +105°C R-16N
ADG439FBRW –40°C to +105°C R-16W
*N = Plastic DIP; R-16N = 0.15" Small Outline IC (SOIC); R-16W = 0.3"
Small Outline IC (SOIC).
WARNING!
ESD SENSITIVE DEVICE
ADG438F/ADG439F
–4– REV. D
TERMINOLOGY
V
DD
Most positive power supply potential.
V
SS
Most negative power supply potential.
GND Ground (0 V) reference.
R
ON
Ohmic resistance between D and S.
∆R
ON
R
ON
variation due to a change in the analog
input voltage with a constant load current.
R
ON
Drift Change in R
ON
when temperature changes
by one degree Celsius.
R
ON
Match Difference between the R
ON
of any two
channels.
I
S
(OFF) Source leakage current when the switch is
off.
I
D
(OFF) Drain leakage current when the switch is off.
I
D
, I
S
(ON) Channel leakage current when the switch is
on.
V
D
(V
S
) Analog voltage on terminals D, S.
C
S
(OFF) Channel input capacitance for “OFF”
condition.
C
D
(OFF) Channel output capacitance for “OFF”
condition.
C
D
, C
S
(ON) “ON” switch capacitance.
C
IN
Digital input capacitance.
t
ON
(EN) Delay time between the 50% and 90% points
of the digital input and switch “ON”
condition.
t
OFF
(EN) Delay time between the 50% and 90% points
of the digital input and switch “OFF”
condition.
t
TRANSITION
Delay time between the 50% and 90% points
of the digital inputs and the switch “ON”
condition when switching from one address
state to another.
t
OPEN
“OFF” time measured between 80% points of
both switches when switching from one
address state to another.
V
INL
Maximum input voltage for Logic “0”.
V
INH
Minimum input voltage for Logic “1”.
I
INL
(I
INH
) Input current of the digital input.
Off Isolation A measure of unwanted signal coupling
through an “OFF” channel.
Charge Injection A measure of the glitch impulse transferred
from the digital input to the analog output
during switching.
I
DD
Positive supply current.
I
SS
Negative supply current.
Typical Performance Graphs
2000
1000
0
–15 –5 155010–10
500
1750
1500
1250
750
250
VD (VS) – Volts
RON – V
TA = +258C
VDD = +5V
VSS = –5V
VDD = +10V
VSS = –10V
VDD = +15V
VSS = –15V
Figure 1. On Resistance as a Function of V
D
(V
S
)
1m
1m
1p
–50 –30 5010–20 20–40
1n
30 40
100m
10m
10n
100n
10p
100p
–10 0
VIN – INPUT VOLTAGE – Volts
IS – INPUT LEAKAGE – A
OPERATING RANGE
VDD = 0V
VSS = 0V
VD = 0V
60
Figure 2. Input Leakage Current as a Function of V
S
(Power Supplies OFF) During Overvoltage Conditions
1m
1m
1p–50 –30 5010–20 20–40
1n
30 40
100m
10m
10n
100n
10p
100p
–10 0
VIN – INPUT VOLTAGE – Volts
ID – OUTPUT LEAKAGE – A
OPERATING RANGE
VDD = +15V
VSS = –15V
VD = 0V
60
Figure 3. Output Leakage Current as a Function of V
S
(Power Supplies ON) During Overvoltage Conditions
ADG438F/ADG439F
–5–REV. D
100
10
0.01
25 45 6555 7535 85 95 105
1
0.1
TEMPERATURE – 8C
LEAKAGE CURRENTS – nA
IS (OFF)
ID (OFF)
ID (ON)
VDD = +15V
VSS = –15V
VD = +10V
VS = –10V
Figure 7. Leakage Currents as a Function of Temperature
260
240
10010 1512 1311
120
14
tON (EN)
VIN = +2V
220
200
180
160
140
t – ns
VSUPPLY – Volts
tOFF (EN)
tTRANSITION
Figure 8. Switching Time vs. Power Supply
280
240
10025 10565 8545
120
tON (EN)
220
200
180
160
140
t – ns
TEMPERATURE – 8C
tOFF (EN)
tTRANSITION
260 VDD = +15V
VSS = –15V
VIN = +5V
Figure 9. Switching Time vs. Temperature
2000
1000
0–15 –5 155010–10
500
1750
1500
1250
750
250
VD (VS) – Volts
RON – V
+258C
VDD = +15V
VSS = –15V
+1058C
+858C
Figure 4. On Resistance as a Function of V
D
(V
S
) for
Different Temperatures
1m
1m
1p
–50 –30 6010–20 20–40 30 40–10 0 50
1n
100m
10m
10n
100n
10p
100p
VS – INPUT VOLTAGE – Volts
IS – INPUT LEAKAGE – A
OPERATING RANGE
VDD = +15V
VSS = –15V
VD = 0V
Figure 5. Input Leakage Current as a Function of V
S
(Power Supplies ON) During Overvoltage Conditions
0.3
0.2
–0.2
–14 –6 142–2 6–10
0.1
10
0.0
–0.1
VS, VD – Volts
LEAKAGE CURRENTS – nA
IS (OFF)
ID (OFF)
ID (ON)
VDD = +15V
VSS = –15V
TA = +258C
Figure 6. Leakage Currents as a Function of V
D
(V
S
)
ADG438F/ADG439F
–6– REV. D
n-channel threshold voltage (V
TN
). When a voltage more nega-
tive than V
SS
is applied to the multiplexer, the p-channel
MOSFET will turn off since the analog input is more negative
than the difference between V
SS
and the p-channel threshold
voltage (V
TP
).
When the power supplies are present but the channel is off,
again either the p-channel MOSFET or one of the n-channel
MOSFETs will remain off when an overvoltage occurs.
Finally, when the power supplies are off, the gate of each
MOSFET will be at ground. A negative overvoltage switches on
the first n-channel MOSFET but the bias produced by the
overvoltage causes the p-channel MOSFET to remain turned
off. With a positive overvoltage, the first MOSFET in the series
will remain off since the gate to source voltage applied to this
MOSFET is negative.
During fault conditions, the leakage current into and out of the
ADG438F/ADG439F is limited to a few microamps. This pro-
tects the multiplexer and succeeding circuitry from over stresses
as well as protecting the signal sources which drive the multi-
plexer. Also, the other channels of the multiplexer will be
undisturbed by the overvoltage and will continue to operate
normally.
Q1 Q2 Q3
+55V
OVERVOLTAGE
n-CHANNEL
MOSFET IS
OFF
Figure 12. +55 V Overvoltage with Power OFF
Q1 Q2 Q3
–40V
OVERVOLTAGE
n-CHANNEL
MOSFET IS
ON p-CHANNEL
MOSFET IS
OFF
Figure 13. –40 V Overvoltage with Power OFF
THEORY OF OPERATION
The ADG438F/ADG439F multiplexers are capable of with-
standing overvoltages from –40 V to +55 V, irrespective of
whether the power supplies are present or not. Each channel of
the multiplexer consists of an n-channel MOSFET, a p-channel
MOSFET and an n-channel MOSFET, connected in series.
When the analog input exceeds the power supplies, one of the
MOSFETs will switch off, limiting the current to sub-microamp
levels, thereby preventing the overvoltage from damaging any
circuitry following the multiplexer. Figure 12 illustrates the
channel architecture that enables these multiplexers to with-
stand continuous overvoltages.
When an analog input of V
SS
+ 1.2 V to V
DD
– 0.8 V is applied
to the ADG438F/ADG439F, the multiplexer behaves as a
standard multiplexer, with specifications similar to a standard
multiplexer, for example, the on-resistance is 180 Ω typically.
However, when an overvoltage is applied to the device, one of
the three MOSFETs will turn off.
Figures 10 to 13 show the conditions of the three MOSFETs for
the various overvoltage situations. When the analog input ap-
plied to an ON channel approaches the positive power supply
line, the n-channel MOSFET turns OFF since the voltage on
the analog input exceeds the difference between V
DD
and the
Q1 Q2 Q3
+55V
OVERVOLTAGE
n-CHANNEL
MOSFET IS
OFF
VDD VSS
Figure 10. +55 V Overvoltage Input to the ON Channel
Q1 Q2 Q3
–40V
OVERVOLTAGE
n-CHANNEL
MOSFET IS
ON VDD
VSS
p-CHANNEL
MOSFET IS
OFF
Figure 11. –40 V Overvoltage on an OFF Channel with
Multiplexer Power ON
Test Circuits
IDS
S
RON = V1/IDS
V1
VS
D
Test Circuit 1. On Resistance
Test Circuit 3. I
D
(OFF)
VS
IS (OFF)
VD
S1
S2
S8
VSS
VDD
VSS
VDD
+0.8V
D
EN
A
Test Circuit 2. I
S
(OFF)
ADG438F/ADG439F
–7–REV. D
VD
S1
S2
S8
VS
VSS
VDD
VSS
VDD
+0.8V
D
EN
A
Test Circuit 5. Input Leakage Current
(with Overvoltage)
VS
0V0V
0V A
* SIMILAR CONNECTION FOR ADG439F
A2
VSS
VDD
D
A1
A0
EN
GND
ADG438F*
S1
S8
Test Circuit 6. Input Leakage Current
(with Power Supplies OFF)
ID (ON)
VD
S1
S8
VS
VSS
VDD
VSS
VDD
+2.4V
D
EN
A
S2
Test Circuit 4. I
D
(ON)
3V
50%
VOUT
tTRANSITION
90%
90%
tTRANSITION
ADDRESS
DRIVE (VIN)50%
A2
VOUT
VSS
VDD
D
VS1
* SIMILAR CONNECTION FOR ADG439F
A1
A0
EN
GND
ADG438F*
S1
S8
S2 THRU S7
VIN
+2.4V
50V
VS8
RL
1MV
CL
35pF
VSS
VDD
Test Circuit 7. Switching Time of Multiplexer, t
TRANSITION
A2
VOUT
VSS
VDD
D
VS
* SIMILAR CONNECTION FOR ADG439F
A1
A0
EN
GND
ADG438F*
S1
S8
S2 THRU S7
VIN
+2.4V
50V
RL
1kVCL
35pF
VSS
VDD
ADDRESS
DRIVE (VIN)
3V
VOUT
tOPEN
80% 80%
Test Circuit 8. Break-Before-Make Delay, t
OPEN
3V
50%
OUTPUT
0.9VO
50%
tON (EN)
0.9VO
0V
VO
0V
tOFF (EN)
ENABLE
DRIVE (VIN)
A2
VOUT
VSS
VDD
D
VS
* SIMILAR CONNECTION FOR ADG439F
A1
A0
EN
GND
ADG438F*
S1
S2 THRU S8
VIN 50VRL
1kV
CL
35pF
VSS
VDD
Test Circuit 9. Enable Delay, t
ON
(EN), t
OFF
(EN)
ADG438F/ADG439F
–8– REV. D
C1992c–0–2/00 (rev. D)
PRINTED IN U.S.A.
VOUT
VSS
D
* SIMILAR CONNECTION FOR ADG439F
A1
A0
EN
GND
ADG438F*
RL
1kV
VSS
VDD
S1
VS
S8
A2 VDD
Test Circuit 11. OFF Isolation
A2
VOUT
VSS
VDD
D
A1
A0 EN
GND
ADG438F*
1kV
VSS
VDD
S1
VS
2.4V
S2
S8
1kV
CROSSTALK = 20 LOG VOUT/VIN
* SIMILAR CONNECTION FOR ADG439F
Test Circuit 12. Channel-to-Channel Crosstalk
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
16-Lead Plastic (N-16)
16
18
9
0.840 (21.34)
0.745 (18.92)
0.280 (7.11)
0.240 (6.10)
PIN 1
SEATING
PLANE
0.022 (0.558)
0.014 (0.356)
0.060 (1.52)
0.015 (0.38)
0.210 (5.33)
MAX 0.130
(3.30)
MIN
0.070 (1.77)
0.045 (1.15)
0.100
(2.54)
BSC
0.160 (4.06)
0.115 (2.93)
0.325 (8.26)
0.300 (7.62)
0.015 (0.381)
0.008 (0.204)
0.195 (4.95)
0.115 (2.93)
16-Lead SOIC (R-16N)
(Narrow Body)
16 9
81
0.3937 (10.00)
0.3859 (9.80)
0.2440 (6.20)
0.2284 (5.80)
0.1574 (4.00)
0.1497 (3.80)
PIN 1
SEATING
PLANE
0.0098 (0.25)
0.0040 (0.10)
0.0192 (0.49)
0.0138 (0.35)
0.0688 (1.75)
0.0532 (1.35)
0.0500
(1.27)
BSC 0.0099 (0.25)
0.0075 (0.19) 0.0500 (1.27)
0.0160 (0.41)
88
08
0.0196 (0.50)
0.0099 (0.25) 3 458
16-Lead SOIC (R-16W)
(Wide Body)
16 9
81
0.4133 (10.50)
0.3977 (10.00)
0.4193 (10.65)
0.3937 (10.00)
0.2992 (7.60)
0.2914 (7.40)
PIN 1
SEATING
PLANE
0.0118 (0.30)
0.0040 (0.10)
0.0192 (0.49)
0.0138 (0.35)
0.1043 (2.65)
0.0926 (2.35)
0.0500
(1.27)
BSC 0.0125 (0.32)
0.0091 (0.23)
0.0500 (1.27)
0.0157 (0.40)
8°
0°
0.0291 (0.74)
0.0098 (0.25)x 45°
D VOUT
3V
VOUT
LOGIC
INPUT (VIN)
QINJ = CL 3 DVOUT
0V
A2
VOUT
VSS
VDD
D
* SIMILAR CONNECTION FOR ADG439F
A1
A0
EN
GND
ADG438F*
VIN
CL
1nF
VSS
VDD
S
RS
VS
Test Circuit 10. Charge Injection