LOO OE EE G E SOLID STATE O1 Def 3875081 0013357 3 3875081 G E SOLID STATE O16 13357 0 CMOS Presettable Up/Down Counters High-Voltage Types (20-Volt Rating) CD4510B BCD Type CD4516B Binary Type The RCA-CD4510B Presettable BCD Up/Down Counter and the CD4516 Presettable Binary Up/Down Counter consist of four synchron- ously clocked D-type flip-flops (with a gating structure to provide T-type flip-flop capa- bility) connected as counters. These counters can be cleared by a high level on the RESET line, and can be preset to any binary number present on the jam inputs by a high level on the PRESET ENABLE line. The CD4510B will count out of non-BCD counter states in a maximum of two clock pulses in the up mode, and a maximum of four clock pulses in the down made. { the CARRY-IN input is held low, the counter advances up or down on each positive-going clock transition. Synchronous cascading is accomplished by connecting all clock inputs in parallel and connecting the CARRY-OUT of a less significant stage to the CARRY-IN of a more significant stage. The CD45108 and CD4516B can be cascaded in the ripple mode by connecting the CARRY: OUT to the clock of the next stage. If the UP/DOWN input changes during a terminal count, the CARRY-OUT must be gated with the clock, and the UP/DOWN input must change while the clock is high. This method provides a clean clock signal to the subse- quent counting stage. (See Fig. 15). These devices are similar to types MC14510 and MC14516. The CD45108 and CD4516B Series types are supplied in 16-lead hermetic dual-in- tIne ceramic packages (D and F suffixes), 16-lead dual-in-line plastic packages (E suf- fix), 16-lead ceramic flat packages (K suffix), and in chip form (H suffix). PRESET ENABLE (TOP VIEW) 9268-27915 D46108, CD4516B TERMINAL ASSIGNMENT 7 Y5-23-OF CD4510B, CD4516B Types , Features: @ Medium-speed operation -- foy = 8 MHz typ. at 10V @ Synchronous internal carry propagation @ Reset and Preset capability 100% tested for quiescent current at 20 V = 5-V, 10-V, and 15-V parametric ratings = Standardized symmetrical output characteristics @ Maximum input current of 1 LA at 18 V over full package temperature range, 100 nA at 18 V and 25C = Noise margin (full package-temperature range)? 1 Vat Vpp =5V 2V at Vpp = 10 V 2.5 Vat Vpp = 15 V Meets all requirements of JEDEC Tentative Standard No. 13A, Standard Specifications for Description of B Series CMOS Devices PRESET ENABLE pa} Qt P24 az P3>4 a p4 a4 Yoo 16 clock ~ Yesre UP/DOWN 2 waa A TARRY COT RESET CD45108, CD4516B FUNCTIONAL DIAGRAM 92CS-24824 Applications: Up/Down difference counting & Multistage synchronous counting 8 Multistage ripple counting = Synchronous frequency dividers OPERATING CONDITIONS AT Tap = 25C, Unless Otherwise Specified For maximum reliability, nominal operating conditions should be selected so that operation is always within the following ranges. Characteristic Vpp | Min.| Max. Units Supply Voltage Range (At Tq = Full Package- Temperature Range) 3118 v 5 150 | - Clock Pulse Width, ty 10 75) ns 15 60] - 5 - 2 Clock Input Frequency, fcy 10 - 4 MHz 15 |5.5 5 150} Preset Enable or Reset Removal Time 10 80 | ns 15 60} - 5 | 15 Clock Rise and Fal! Time, t-CL, tL A 718 | 4s 5 130 | Carry-In Setup Time, tg 10 60 | nas 15 45| - 5 360 | - Up-Down Setup Time, ts 10 160 | ns 15 10] - 5 220 | - Preset Enable or Reset Pulse Width, tw 10 100 | ns 15 7m | - Time required after the falling edge of the reset or preset enable inputs before the rising edge of the clock will trigger the counter (similar to setup time). *1f more than one unit is cascaded in the parallel clocked application, 1,CL should be made less than or equal to the sum of the fixed propagation delay at 15 pF and the transition time of the carry output driving stage for the estimated capacitive load.G E SOLID STATE OL DEM 3875081 0013358 5 I 3875081 GE SOLID STATE O1E 13358 OD CD4510B, CD4516B Types MAXIMUM RATINGS, Absolute-Maximum Values: DC SUPPLY-VOLTAGE RANGE, (Vpp) (Voltages referenced to Vg Terminal) .........cceece rece nen tence rete etree tne eee eeens -0.5 to +20 V INPUT VOLTAGE RANGE, ALL INPUTS ... ~0.5 to Vpop +0.5 V DC INPUT CURRENT, ANY ONE INPUT 20... .0 ccc e cece cece rere renee teen teen ee en anes +10 mA POWER DISSIPATION PER PACKAGE (Pp): Pendent eet eeeeennes peeeeeees SOO MW For T, = -40 to +60C (PACKAGE TYPE ) ... For T, = +60 to +85C (PACKAGE TYPE E) ..... . Osrate Linearly at 12 mW/C to 200 mW For Ty = -55 to +100C (PACKAGE TYPES D, F, K) ...... See e seen tea e tees eee eees beaten seeeee 500 mW For Tg = +100 to +#125C (PACKAGE TYPES D, F, K) ......+06- Derate Linearly at 12 mW/C to 200 mW DEVICE DISSIPATION PER OUTPUT TRANSISTOR: For T, = FULL PACKAGE-TEMPERATURE RANGE (All Package Types) ........-..eeeeeeeeees 100 mW OPERATING-TEMPERATURE RANGE (Ta): PACKAGE TYPES D, FF, K,H oo... cece ene cece cnet e eee e reer eet tne eee e eens ter erees -55 to +125C PACKAGE TYPE E ....... 0. cee e ee eeee .. ~40 to +85C STORAGE TEMPERATURE RANGE (Totg) .- sss seee reer cere ere e rere reer tenennne cee sess 65 to +150C LEAD TEMPERATURE (DURING SOLDERING), At distance 1/16 + 1/32 inch (1.59 + 0.79 mm) from case for 10S MAX. ...... cscs eect e eee eee +265C 92CL-2700382 Fig.3 Logic Diagram for CDO45108. DRAIN-TO-SOURCE VOLTAGE (Vos] AMBIENT TEMPERATURE (T,]= OUTPUT HIGH [SOURCE] CURRENTIL oni mA TRANSITION Time (Hypytooe a 9208-24322R1 gees 2eszie? LOAD CAPACITANCE (Cy lF Fig.5 Minimum output high (source) current Fig.6 Typical transition time vs. load characteristics. capacitance. OUTPUT LOW (SINK) CURRENT DRAIN-TO-SOURCE VOLTAGE (Vps]V : 9205 2431883 Fig.1 Typical output low (sink} current characteristics. DRAIN-TO-SOURCE VOLTAGE (ps)V sacs -zesiam Fig.2 Minimum output tow (sink) current characteristics. ORAIN~ TO- SOURCE VOLTAGE [Vps}- OUTPUT HIGH 92es-zeszeay Fig.4 Typical output high (source) current characteristics. tpuiins | PROPAGATION DELAY TIME (pi y, 40 LOAD CAPACITANCE (CL} pF secs-27005 Fig.7 Typical propagation delay time vs. load capacitance for clock-to-Q outputs.Fe G E SOLID STATE 01 Def 3875081 0013359 7 3875081 GE SOLID STATE T- 45-23-07 O1E 13359 D STATIC ELECTRICAL CHARACTERISTICS ALL INPUTS PROTECTED BY COS/MOS PROTECTION NETWORK. ss Fig.10 Logic Diagram for CD45 168. LIMITS AT INDICATED TEMPERATURES (C) CONDITIONS Values at -55, +25, +125 Apply to D, F, K, H Packages CHARACTER- Values at 40, +25, +85 Apply to E Package ISTIC 735 UNITS Vo | Vin |YDD (v) tv) | (Vv) 5 ; 40 +85 +125 | Min. Typ. | Max. Quiescent Device = 0,5 5 5 5 150 180 - 0.04 5 Current, ~ 0,10| 10 | 10 10 300 | 300 | - 0.04 | 10 A 'DD Max. Tors} 15] 20 | 20 | soo | 600 [ - | 004 | 20 H 0,20| 20 | 100 | 100 } 3000 | 3000) - 0.08 | 100 Output Low 0.4 o5 | 5 | 064 | 061 | 042 | 0.36 | 0.51 1 - (Sink) Current os loi] wl] ie | 15 | 11 [ 09 | 13 | 26 | - 'o Min. 15 1015) 15) 42] 4 {| 28 | 24134 [| 68 | - Output High 46 o5 | 5 | -0.64)-0.61|-0.42 | -0.36|-0.51| -1 {| mA {Source} 2.5 05} 5 ~2 |-1.8 | -1.3 [-1.15]-1.6 | -3.2 ~ Current, a5 10,10| 10 |-16|-15 |-11 | 09 |-1.3 | -26 [| - 10H Min. 135 10,15] 15 |-4.2] -4 | -2.8 | -2.4 |-34 | -68 | Output Voltage: - 0,5 5 0.05 - 0 0.05 Low-Level, [0,10] 10 0.05 - 0 | 0.05 VoL Max. - 0,15! 15 0.05 = 6 foo] , Output Voltage: = 0,5 5 4.95 4.95 5 = High-Level, [010] 10 9.95 9.95; 10 | - VOH Min. [0,15] 15 14.95 14.95 | 15 Input Low 05,45| - | 5 15 -|- 15 Voltage, 1,9 [| 10 3 fo 3 VIL Max. Max. T7513.5| | 18 4 T=] y Input High 0.5,4.5[ - 5 3.5 3.5 _ _ Voltage, 1,9 - 10 7 7 - Vin Ming [7513.5] - | 15 nN mn] ~ Input Current . 5 iN Max. - 01g] 18 | +01} 20.4 | #1 1H - |210 +0.1| pA pi* al P2 a2 P3* 93 pa a4 926L- 2700482 CD4510B, CD4516B Types AMBIENT TEMPERATURE (Ta}=25C> LOAD CAPACITANCE (CL)+50 pF 3 - MHz (re, MAO o MAXIMUM CLOCK INPUT FREQUENCY 10 20 SUPPLY VOLTSVoo s2cs-z1006 Fig.8 ~ Typical maximum clock input frequency vs. supply voltage. tea ly* 20 ns CL *50 oF 115 pF 107 92C$-27007 Ol 1 10 1? CLOCK INPUT FREQUENCY (fcL} kHz Fig.9 Typical dynamic power dissipation vs. frequency. INPUTS acs- 27400RL Yes Fig, 11 Quiescent-device-cur- rent test circuit. vi INPUTS Yoo NOTE Not MEASURE INPUTS SEQUENTIALLY, ss TO BOTH Vpp AND Vsg- CONNECT ALL UNUSED INPUTS TO EITHER Vp OF Vgg- ss s2cs-27402 Fig, 12 (nput-current test circuit.ee | r G SOLID STATE 01 def 3875081 0013360 3 i 3875081 G E SOLID STATE T- 45-23-09 O1E 13360 D CD4510B, CD4516B Types DYNAMIC ELECTRICAL CHARACTERISTICS at Ta = 25C, C, = 50 pF, Input ty, te = 20 ns, RL = 200 kQ Condit- Limits isti ions All Pack: Uni Characteristic Vpop ackages nits (V) [| Min. Typ. Max. Propagation Delay Time (tp, tpLH): 5 - 200 400 Ciock-to-Q Output (See Fig. 10) 10 _ 100 200 ns 15 - 75 150 5 - 210 420 Preset or Reset-to-O Output 10 _ 105 210 ns 15 _ 80 160 5 - 240 480 Clock-to-Carry Out 10 - 120 240 ns 15 - 90 180 5 _ 125 250 Carry-tn-to-Carry Out 10 - 60 120 ns 15 - 50 100 5 ~ 320 640 Preset or Reset-to-Carry Out 10 - 160 320 ns 15 - 125 250 5 - 100 200 Transition Time (t7y1, tTLH) (See Fig. 9) 10 - 50 100 ns 15 - 40 80 5 2 4 - Max. Clock Input Frequency (fc) 10 4 8 _ MHz 15 5.5 11 ~ Input Capacitance (Cin) - 5 7.5 pF Set-up Time, ts 5 25 12 _ Preset Enable to J, 10 10 6 _ 18 10 5 - Hold times, ty 5 60 30 _ Clock to Carry-In 10 30 4 _ 15 30 1 _ ns 5 30 10 _ Clock to Up/Down 10 30 4 - 15 30 5 _ : 5 70 35 - Preset Enable to J, 10 40 20 _ 15 40 20 _ Yoo INPUTS OUTPUTS 24 = Noe t | 9 4 Yin -_ LL _ NOTE: TEST ANY ONE INPUT, Vss WITH OTHER INPUTS AT Voo OR Vss- 9208- 27400A1 Fig. 13 Input-voitage test circuit. Ht 5 ia GENERATOR = oh sect 4 13 1 p15 12 cue clo] 7 4 a > fr2om {fm 20ns | fee 90% Lfson | Pxlow y2cu-27012 Fig.14 Power-dissipation test circuit and input waveform,3875081 GE SOLID STATE QO1E 13361 D G E SOLID STATE OL Def 3875081 coLaaEy 5 [ T= 45 -2Q3-OF 4/3) 2]; 1]/o};o)9 Fig. 15 Timing Diagram for CD4510B, cLocK CARRY UP/DOWN RESET PE PI 2 P3 Pa a a2 93 04 CARRY OUT COUNT) S| Gi 7; 8] FS] IOfP Ue | izpis} 4p) os}aetr,_ ae; stays] 2 6;7])0 92c~7 1008 Yoo Ves Py, oO Iis|o $2CM-27009R1 Fig. 16 Timing diagram tor CD4516B. 7 Le } 4 SAMPLE [L = an |- L a = HOLO lo-BtT [7 PARALLEL =a 7o (7S joata ANALOG | e} 16-CHANNEL CONVERTER |g | OUTPUTS DATA | { )MULTIPL START = INPUTS | o EXER Le Te] co4c67 cock Cr - CONVERSION = a Losic a] SELE el BIPUTS END =e = ai G4 preset(ay SO48IG INPUTS | 4 CLOCK PRESET ENABLE 925-2704 This acquisition system can be operated in the random access mode by jamming in the channel number at the present inputs, or in the sequential mode by clocking the CD4516B. Fig. 17 Typical 16-channel, 10-bit data acquisition system. CD4510B, CD4516B Types PE| RI] ACTION 0}NO COUNT oO xX 1 Q 9 Q X = OONT CARE TRUTH TABLE re EI ae l. 4-10 (0.102-0.254) 97-105 (2 464- 2.667) Dimensions and Pad Layout for CD45108H. 60-86. {2.032- 2.235) 1 Dimensions and Pad Layout for CD45 168H, The photographs and dimensions of each CMOS chip represent a chip when it is part of the water. When the wafer is separated into individual chips, the angle of cleavage may vary with respect to the chip face for different chips. The actual dimensions of the isolated chip, therefore, may differ slightly from the nominal dimensions shown. The user should consider a tolerance af ~3 mils to +16 mils applicable io the nominal dimensions shown. Dimensions in parentheses are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10~3 inch). 92-100 (2.337- 2.540) 92CS- 27O37RI 90-98 (2.266- 2.489} 92CS-27036R1 309G E SOLID STATE OL a | 3675081 O01349be 7? I T= Y5-23-OF 3875081 G E SOLID STATE O1E 13362 D CD4510B, CD4516B Types PARALLEL CLOCKING" UP/DOWN > PRESET > ENABLE is UP/D PE J) da vy ug UPD PE v2 v3 v4 UPD PE vj Jo Jz Ja : we Te CI. Cc04510/16 .0.{0O]c.I. cp4510716 c.0.O-_c.I. cpssion6e co. O> RCL Q Q2 03 Og R cL @; Qn Os % RCL Q@ Q2 Qy Qy CLOCK > RESET > * CARRY OUT lines at the 2nd, 3rd, etc., stages may have a negative-going glitch pulse resulting from difterential delays of different CO4510/16 IC's. These negative- aint giltches do not affect proper CO4510/16 operation. However, {f the signals are used to trigger other edge-senaitive logic devices, such as FF's orcounters, the CARRY out signais should be gated with the clock signal using a 2-input OR gate such as CD40718. "RIPPLE CLOCKING, UP/DOWN > PRESET ENABLE 4 | | | - UP/D PE Jo Ug U4 UPD PE Wy Jp ux vq UP/D PE J Jo Ja da 4 CI. cp4siosis co I cI. coasiosis co [9 C1 co4sio/i6 = 6.0. O-"> R CL Q; Q2 Q3 4 R CL GQ: Qo Q3 Qq R ch & Q5 Qy Qg c Lock LL vacosons Or RESET > RIPPLE CLOCKING MOOE: THE UP/DOWN CONTROL CAN BE CHANGED AT ANY COUNT. THE ONLY RESTRICTION ON CHANGING THE UP/DOWN CONTROL IS THAT THE CLOCK INPUT TO THE FIRST COUNTING STAGE MUST BE HIGH For cascading counters operating ina fixed up-count or down-count mode, the OR gates are not required between stages, and Is connected directly to the CL input of the next stage with CI grounded. 92CL-{Ti94R5 Fig. 18 Cascading counter packages.