1.5KE24ATR - MICROSEMI - Datasheet.Live

May 2005 1/215

Rev. 5

ST72F521, ST72521B

80/64-PIN 8-BIT MCU WITH 32 TO 60K FLASH/ROM, ADC,

FIVE TIMERS, SPI, SCI, I2C, CAN INTERFACE

■Memories

– 32K to 60K dual voltage High Density Flash

(HDFlash) or ROM with read-out protection

capability. In-Application Programming and

In-Circuit Programming for HDFlash devices

– 1K to 2K RAM

– HDFlash endurance: 100 cycles, data reten-

tion: 20 years at 55°C

■Clock, Reset And Supply Management

– Enhanced low voltage supervisor (LVD) for

main supply and auxiliary voltage detector

(AVD) with interrupt capability

– Clock sources: crystal/ceramic resonator os-

cillators, internal RC oscillator and bypass for

external clock

– PLL for 2x frequency multiplication

– Four power saving modes: Halt, Active-Halt,

Wait and Slow

■Interrupt Management

– Nested interrupt controller

– 14 interrupt vectors plus TRAP and RESET

– Top Level Interrupt (TLI) pin

– 15 external interrupt lines (on 4 vectors)

■Up to 64 I/O Ports

– 48 multifunctional bidirectional I/O lines

– 34 alternat e function lines

– 16 high sink outputs

■5 Timers

– Main Clock Controller with: Real time base,

Beep and Clock-out capabilities

– Configurable watchdog timer

– Two 16-bit timers with: 2 input captures, 2 out-

put compares, external clock input on one tim-

er, PWM and pulse generator modes

– 8-bit PWM Auto-Reload timer with: 2 input

captures, 4 PWM outputs, output compare

and time base interrupt, external clock with

event detector

■4 Communications Interfaces

– SPI synchronous seria l interface

– SCI asynchronous serial interface

–I

2C multimaster interface

(SMbus V1.1 compliant)

– CAN interface (2.0B Passive)

■Analog periperal (low current coupling)

– 10-bit ADC with 16 input robust input ports

■Instruction Set

– 8-bit Data Manipulation

– 63 Basic Instructions

– 17 main Addressing Modes

– 8 x 8 Unsigned Multiply Instruction

■Development Tools

– Full hardware/sof tware development package

– In-Circuit Testing capability

Device Summary

TQFP80

14 x 14

TQFP64

10 x 10

TQFP64

14 x 14

Features ST72F521(M/R/AR)9 ST72F521(R/AR)6 ST72521B(M/R/AR)9 ST72521B(R/AR)6

Program memory - bytes Flash 60K Flash 32K ROM 60K ROM 32K

RAM (stack) - bytes 2048 (256) 1024 (256) 2048 (256) 1024 (256)

Operating Voltage 3.8V to 5.5V

Temp. Range up to -40°C to +125 °C

Package TQF P8 0 14 x14 (M),

TQFP64 14x14 (R),

TQFP64 10x10 (AR)

TQFP64 14x14 (R), TQFP64

10x10 (AR)

TQFP80 14x14 (M),

TQFP64 14x1 4 (R ),

TQFP64 10x10 (AR)

TQFP64 14x14 (R), TQFP64

10x10 (AR)

Table of Contents
215
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INTRODUCTION    . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  7
PIN DESCRIPTION  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  8
REGISTER & MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  14
FLASH PROGRAM MEMORY  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  18
1 INTRODUCTION  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2 MAIN FEATURES  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3 STRUCTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  18
3.1 Read-out Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  18
4 ICC INTERFACE  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  19
5 ICP (IN-CIRCUIT PROGRAMMING)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  20
6 IAP (IN-APPLICATION PROGRAMMING) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  20
7 RELATED DOCUMENTATION  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  20
7.1 Register Description  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  20
CENTRAL PROCESSING UNIT  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  21
1 INTRODUCTION  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2 MAIN FEATURES  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3 CPU REGISTERS  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
SUPPLY, RESET AND CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  24
1 PHASE LOCKED LOOP   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  24
2 MULTI-OSCILLATOR (MO)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  25
3 RESET SEQUENCE MANAGER (RSM)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  26
3.1 Introduction  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  26
3.2 Asynchronous External RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  26
3.3 External Power-On RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  27
3.4 Internal Low Voltage Detector (LVD) RESET  . . . . . . . . . . . . . . . . . . . . . . . . . . . .  27
3.5 Internal Watchdog RESET   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  27
4 SYSTEM INTEGRITY MANAGEMENT (SI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  28
4.1 Low Voltage Detector (LVD)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  28
4.2 Auxiliary Voltage Detector (AVD)   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  29
4.3 Low Power Modes   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  31
4.4 Register Description  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  32
INTERRUPTS  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  33
1 INTRODUCTION  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2 MASKING AND PROCESSING FLOW  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  33
3 INTERRUPTS AND LOW POWER MODES  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  35
4 CONCURRENT & NESTED MANAGEMENT  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  35
5 INTERRUPT REGISTER DESCRIPTION  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  36
6 EXTERNAL INTERRUPTS   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  38
6.1 I/O Port Interrupt Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  38
7 EXTERNAL INTERRUPT CONTROL REGISTER (EICR) . . . . . . . . . . . . . . . . . . . . . . . . .  40
POWER SAVING MODES   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
1 INTRODUCTION  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
2 SLOW MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  42
3 WAIT MODE   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  43
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4 ACTIVE-HALT AND HALT MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  44
4.1 ACTIVE-HALT MODE  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  44
4.2 HALT MODE  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  45
I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  47
1 INTRODUCTION  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
2 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  47
2.1 Input Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  47
2.2 Output Modes  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  47
2.3 Alternate Functions  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  47
3 I/O PORT IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  50
4 LOW POWER MODES   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  50
5 INTERRUPTS   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  50
5.1 I/O Port Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  51
ON-CHIP PERIPHERALS  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
1WATCHDOG TIMER (WDG)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  53
1.1 Introduction  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
1.2 Main Features  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  53
1.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  53
1.4 How to Program the Watchdog Timeout  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  54
1.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  56
1.6 Hardware Watchdog Option  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  56
1.7 Using Halt Mode with the WDG (WDGHALT option) . . . . . . . . . . . . . . . . . . . . . . .  56
1.8 Interrupts  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
1.9 Register Description  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  56
2MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK AND BEEPER (MCC/RTC)  . .  58
2.1 Programmable CPU Clock Prescaler  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  58
2.2 Clock-out Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  58
2.3 Real Time Clock Timer (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  58
2.4 Beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
2.5 Low Power Modes   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  59
2.6 Interrupts  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
2.7 Register Description  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  59
3PWM AUTO-RELOAD TIMER (ART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  61
3.1 Introduction  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
3.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  62
3.3 Register Description  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  66
416-BIT TIMER   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  70
4.1 Introduction  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
4.2 Main Features  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  70
4.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  70
4.4 Low Power Modes   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  82
4.5 Interrupts    . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
4.6 Summary of Timer modes   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  82
4.7 Register Description  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  83
5SERIAL PERIPHERAL INTERFACE (SPI)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  89
5.1 Introduction  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
5.2 Main Features  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  89
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5.3 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  89
5.4 Clock Phase and Clock Polarity   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  93
5.5 Error Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
5.6 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  96
5.7 Interrupts    . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
5.8 Register Description  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  97
6SERIAL COMMUNICATIONS INTERFACE (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  100
6.1 Introduction  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  100
6.2 Main Features  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  100
6.3 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  100
6.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  102
6.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  109
6.6 Interrupts  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  109
6.7 Register Description  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  110
7I2C BUS INTERFACE (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  116
7.1 Introduction  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  116
7.2 Main Features  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  116
7.3 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  116
7.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  118
7.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  122
7.6 Interrupts  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  122
7.7 Register Description  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  123
8CONTROLLER AREA NETWORK (CAN)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  129
8.1 Introduction  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  129
8.2 Main Features  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  130
8.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  130
8.4 Register Description  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  136
8.5 List of CAN Cell Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  146
910-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  155
9.1 Introduction  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  155
9.2 Main Features  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  155
9.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  156
9.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  156
9.5 Interrupts  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  156
9.6 Register Description  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  157
INSTRUCTION SET   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  159
1CPU ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  159
1.1 Inherent  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  160
1.2 Immediate  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  160
1.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
1.4 Indexed (No Offset, Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  160
1.5 Indirect (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  160
1.6 Indirect Indexed (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  161
1.7 Relative mode (Direct, Indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  161
2INSTRUCTION GROUPS  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  162
ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  165
1PARAMETER CONDITIONS  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  165

Table of Contents
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1.1 Minimum and Maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  165
1.2 Typical values  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  165
1.3 Typical curves  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  165
1.4 Loading capacitor  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  165
1.5 Pin input voltage  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  165
2ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  166
2.1 Voltage Characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  166
2.2 Current Characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  166
2.3 Thermal Characteristics   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  167
3OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  167
3.1 General Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  167
3.2 Operating Conditions with Low Voltage Detector (LVD)  . . . . . . . . . . . . . . . . . . .  168
3.3 Auxiliary Voltage Detector (AVD) Thresholds  . . . . . . . . . . . . . . . . . . . . . . . . . . .  168
3.4 External Voltage Detector (EVD) Thresholds  . . . . . . . . . . . . . . . . . . . . . . . . . . .  168
4SUPPLY CURRENT CHARACTERISTICS  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  169
4.1 CURRENT CONSUMPTION    . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  169
4.2 Supply and Clock Managers  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  171
4.3 On-Chip Peripherals  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  172
5CLOCK AND TIMING CHARACTERISTICS  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  173
5.1 General Timings  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  173
5.2 External Clock Source   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  173
5.3 Crystal and Ceramic Resonator Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  174
5.4 RC Oscillators  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  176
5.5 PLL Characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  177
6MEMORY CHARACTERISTICS  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  178
6.1 RAM and Hardware Registers   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  178
6.2 FLASH Memory   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  178
7EMC CHARACTERISTICS   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  179
7.1 Functional EMS (Electro Magnetic Susceptibility) . . . . . . . . . . . . . . . . . . . . . . . .  179
7.2 Electro Magnetic Interference (EMI)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  180
7.3 Absolute Maximum Ratings (Electrical Sensitivity)  . . . . . . . . . . . . . . . . . . . . . . .  181
8I/O PORT PIN CHARACTERISTICS  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  182
8.1 General Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  182
8.2 Output Driving Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  183
9CONTROL PIN CHARACTERISTICS  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  185
9.1 Asynchronous RESET Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  185
9.2 ICCSEL/VPP Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  187
10TIMER PERIPHERAL CHARACTERISTICS  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  188
10.1 8-Bit PWM-ART Auto-Reload Timer  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  188
10.2 16-Bit Timer   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  188
11COMMUNICATION INTERFACE CHARACTERISTICS   . . . . . . . . . . . . . . . . . . . . . . . .  189
11.1 SPI - Serial Peripheral Interface  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  189
11.2 I2C - Inter IC Control Interface   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  191
11.3 CAN - Controller Area Network Interface   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  192
1210-BIT ADC CHARACTERISTICS  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  193
12.1 Analog Power Supply and Reference Pins  . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  195
12.2 General PCB Design Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  195

Table of Contents
215
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12.3 ADC Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  196
PACKAGE CHARACTERISTICS  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  197
1PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  197
2THERMAL CHARACTERISTICS   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  199
3SOLDERING INFORMATION  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  200
ST72521 DEVICE CONFIGURATION AND ORDERING INFORMATION . . . . . . . . . . . . . . .  201
1FLASH OPTION BYTES  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  201
2DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE  . . . . .  203
2.1 Version-Specific Sales Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  203
3DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  206
3.1 Socket and Emulator Adapter Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  207
4ST7 APPLICATION NOTES   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  208
KNOWN LIMITATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
1ALL FLASH AND ROM DEVICES  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  211
1.1 External RC option   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  211
1.2 Safe Connection of OSC1/OSC2 Pins   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  211
1.3 Reset pin protection with LVD Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  211
1.4 Unexpected Reset Fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  211
1.5 Clearing active interrupts outside interrupt routine  . . . . . . . . . . . . . . . . . . . . . . .  211
1.6 SCI Wrong Break duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  212
1.7 16-bit Timer PWM Mode  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  212
1.8 CAN Cell Limitations  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  212
1.9 I2C Multimaster  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  212
2ALL FLASH DEVICES  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  213
2.1 Internal RC Oscillator with LVD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  213
2.2 I/O behaviour during ICC mode entry sequence . . . . . . . . . . . . . . . . . . . . . . . . .  213
2.3 Read-out protection with LVD  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  213
REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  214

ST72F521, ST72521B

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1 INTRODUCTION

The ST72F521 and ST72521B devices are mem-

bers of the ST7 micr ocontroller family designed for

mid-range applications with a CAN bus interface

(Controller Area Network).

All devices are based on a common industry-

standard 8-bit core, featuring an en hanced instruc-

tion set and are available with FLASH or ROM pro-

gram memory.

Under software control, all devices can be placed

in WAIT, SLOW, ACTIVE-HALT or HALT mode,

reducing power consumption whe n the application

is in idle or stand-by state.

The enhanced instruction set and addressing

modes of the ST7 offer both power and flexibility to

software developers, e nabling the design of highly

efficient and comp act app lica tion cod e. I n a dditi on

to standard 8-bit data management, all ST7 micro-

controllers feature true bit manipulation, 8x8 un-

signed multiplication and indirect addressing

modes.

Related Documentation

AN1131: Migrating applications from ST72511/

311/314 to ST72521/321/324

Figure 1. Device Block Diagram

8-BIT CORE

ALU

ADDRESS AND DATA BUS

OSC1

VPP CONTROL

PROGRAM

(32K - 60K Bytes)

VDD

RESET

PORT F

PF7:0

(8-bits) TIMER A

BEEP

PORT A

RAM

(1024-2048 Bytes)

PORT C

10-BIT ADC

VAREF

VSSA

PORT B PB7:0

(8-bits)

PWM ART

PORT E

CAN

PE7:0

(8-bits)

SCI

TIMER B

PA7:0

(8-bits)

PORT D

PD7:0

(8-bits)

SPI

PC7:0

(8-bits)

VSS

WATCHDOG

TLI

OSC

LVD

OSC2

MEMORY

MCC/RTC/BEEP

EVD AVD

I2C

1On some devices only, see Device Summary on page 1

PORT G1PG7:0

(8-bits)

PORT H1PH7:0

(8-bits)

ST72F521, ST72521B

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2 PIN DESCRIPTION

Figure 2. 80-Pin TQFP 14x14 Package Pinout

PA4 (HS)

VSS_1

VDD_1

PA3 (HS)

PC3 (HS) /ICAP1 _B

PC2(HS) / ICAP2_B

PC1 / OCMP1_B / AIN 13

PC0 / OCMP2_B /AIN12

PA7 (HS) / SCLI

PA6 (HS) / SDAI

PA5 (HS)

PA2

PA1

PA0

PC7 / SS / AI N15

PH2

PC5 / MOSI / AIN14

PWM0 / PB3

PG0

PG1

PG2

AIN3 / PD3

(HS) PE7

PWM3 / PB0

PWM2 / PB1

PWM1 / PB2

PG3

ARTCLK / (HS) PB4

ARTIC1 / PB5

ARTIC2 / PB6

PB7

AIN0 / PD0

AIN1 / PD1

AIN2 / PD2

(HS) PE4

(HS) PE5

(HS) PE6

VDD3

VSS3

MCO /AIN8 / PF0

BEEP / (HS) PF1

ICAP1_A / (HS) / PF6

AIN6 / PD6

AIN7 / PD7

VAREF

VSSA

(HS) PF2

OCMP2_A / AIN9 /PF3

OCMP1_A/AIN10 /PF4

EXTCLK_A / (HS) PF7

PG6

PG7

AIN4/PD4

AIN5 / PD5 PE0 / TDO

VSS_2

TLI

EVD

RESET

VPP / ICCSEL

PE3 / CANRX

PE2 / CANTX

PE1 / RDI

PH7

PH6

OSC1

OSC2

PC4 / MISO / ICCDATA

PH1

PH3

PC6 / SCK /ICCCLK

PH4

PH5

VDD_2

PG4

PG5

VSS_0

VDD_0

ICAP2_A/ AIN11 /PF5

PH0

(HS) 20mA high sink capability

eix associated external interrupt vector

ei1

ei3

ei2

ei0

ST72F521, ST72521B

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PIN DESCRIPTION (Cont’d)

Figure 3. 64-Pin TQFP 14x14 and 10x10 Package Pinout

VAREF

VSSA

VDD_3

VSS_3

MCO / AIN8 / PF0

BEEP / (HS) PF1

(HS) PF2

OCMP2_A / AIN9 / PF3

OCMP1_A / AIN10 / PF4

ICAP2_A / AIN11 / PF5

ICAP1_A / (HS) PF6

EXTCLK_A / (HS) PF7

AIN4 / PD4

AIN5 / PD5

AIN6 / PD6

AIN7 / PD7

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

17 18 19 20 21 22 23 24 29 30 31 3225 26 27 28

ei2

ei3

ei0

ei1

PWM3 / PB0

PWM2 / PB1

PWM1 / PB2

PWM0 / PB3

ARTCLK / (HS) PB4

ARTIC1 / PB5

ARTIC2 / PB6

PB7

AIN0 / PD0

AIN1 / PD1

AIN2 / PD2

AIN3 / PD3

(HS) PE4

(HS) PE5

(HS) PE6

(HS) PE7 PA1

PA0

PC7 / SS / AIN15

PC6 / SCK / ICCCLK

PC5 / MOSI / AIN14

PC4 / MISO / ICCDATA

PC3 (HS) / ICAP1_B

PC2 (HS) / ICAP2_B

PC1 / OCMP1_B / AIN13

PC0 / OCMP2_B / AIN12

VSS_0

VDD_0

VSS_1

VDD_1

PA3 (HS)

PA2

VDD_2

OSC1

OSC2

VSS_2

TLI

EVD

RESET

VPP / ICCSEL

PA7 (HS) / SCLI

PA6 (HS) / SDAI

PA5 (HS)

PA4 (HS)

PE3 / CANRX

PE2 / CANTX

PE1 / RDI

PE0 / TDO

(HS) 20mA high sink capability

eix associated external interrupt vector

ST72F521, ST72521B

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PIN DESCRIPTION (Cont’d)

For external pin connection guidelines, refer to See “ ELECTRICAL CHARACTERISTICS” on page 165.

Legend / Abbreviations for Table 1:

Type: I = input, O = output, S = supply

Input level: A = Dedicated analog input

In/Output level: C = CMOS 0.3VDD/0.7VDD

CT= CMOS 0.3VDD/0.7VDD with input trigger

TT= TTL 0.8V / 2V with Schmitt trigger

Output level: HS = 20mA high sink (on N-buffer only)

Port and control configuration:

– Input: float = floating, wpu = weak pull-up, int = interrupt 1), ana = analog

– Output: OD = open drain 2), PP = push-pull

Refer to “I/O PORTS” on page 47 for more details on the software configuration of the I/O ports.

The RESET configuration of each pin is shown in bold. This configuration is valid as long as the device is

in reset state.

Table 1. Device Pin Description

Pin n°

Pin Name

Type

Level Port Main

function

(after

reset)

Alternate function

TQFP80

TQFP64

Input

Output

Input Output

float

wpu

int

ana

11PE4 (HS) I/OC

THS XXXXPort E4

22PE5 (HS) I/OC

THS XXXXPort E5

33PE6 (HS) I/OC

THS XXXXPort E6

44PE7 (HS) I/OC

THS XXXXPort E7

55PB0/PWM3 I/OC

TXei2 X X Port B0 PWM Output 3

66PB1/PWM2 I/OC

TXei2 X X Port B1 PWM Output 2

77PB2/PWM1 I/OC

TXei2 X X Port B2 PWM Output 1

88PB3/PWM0 I/OC

TXei2 X X Port B3 PWM Output 0

9-PG0 I/OT

TXXXXPort G0

10 - PG1 I/O TTXXXXPort G1

11 - PG2 I/O TTXXXXPort G2

12 - PG3 I/O TTXXXXPort G3

13 9 PB4 (HS)/ARTCLK I/O CTHS Xei3 X X Port B4 PWM-ART External Clock

14 10 PB5/ARTIC1 I/O CTXei3 X X Port B5 PWM-ART Input Capture 1

15 11 PB6/ARTIC2 I/O CTXei3 X X Port B6 PWM-ART Input Capture 2

16 12 PB7 I/O CTXei3 X X Port B7

17 13 PD0 /AIN0 I/O CTXX X X X Port D0 ADC Analog Input 0

18 14 PD1/AIN1 I/O CTXX X X X Port D1 ADC Analog Input 1

19 15 PD2/AIN2 I/O CTXX X X X Port D2 ADC Analog Input 2

20 16 PD3/AIN3 I/O CTXX X X X Port D3 ADC Analog Input 3

21 - PG6 I/O TTXXXXPort G6

22 - PG7 I/O TTXXXXPort G7

23 17 PD4/AIN4 I/O CTXX X X X Port D4 ADC Analog Input 4

ST72F521, ST72521B

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24 18 PD5/AIN5 I/O CTXX X X X Port D5 ADC Analog Input 5

25 19 PD6/AIN6 I/O CTXX X X X Port D6 ADC Analog Input 6

26 20 PD7/AIN7 I/O CTXX X X X Port D7 ADC Analog Input 7

27 21 VAREF I Analog Reference Voltage for ADC

28 22 VSSA S Analog Ground Voltage

29 23 VDD_3 S Digital Main Supply Voltage

30 24 VSS_3 S Digital Ground Voltage

31 - PG4 I/O TTXXXXPort G4

32 - PG5 I/O TTXXXXPort G5

33 25 PF0/MCO/AIN8 I/O CTXei1 X X X Port F0 Main clock

out (fCPU)ADC Analog

Input 8

34 26 P F1 (H S)/BEEP I/O CTHS Xei1 X X Port F1 Beep signal output

35 27 P F2 (H S) I/O CTHS Xei1 X X Port F2

36 28 PF3/OCMP2_A/AIN9 I/O CTXXXXXPort F3

Timer A Out-

put Compare

ADC Analog

Input 9

37 29 PF4/OCMP1_A/AIN10 I/O CTXXXXXPort F4

Timer A Out-

put Compare

ADC Analog

Input 10

38 30 PF5/ICAP2_A/AIN11 I/O CTXXXXXPort F5

Timer A Input

Capture 2 ADC Analog

Input 11

39 31 P F6 (H S)/ICAP 1_A I/O CTHS XX X X Port F6 Timer A Input Capture 1

40 32 P F7 (HS)/EXTCLK_A I/O CTHS XXXXPort F7

Timer A External Clock

Source

41 33 VDD_0 S Digital Main Supply Voltage

42 34 VSS_0 S Digital Ground Voltage

43 35 PC0/OCMP2_B/AIN12 I/O CTXXXXXPort C0

Timer B Out-

put Compare

ADC Analog

Input 12

44 36 PC1/OCMP1_B/AIN13 I/O CTXXXXXPort C1

Timer B Out-

put Compare

ADC Analog

Input 13

45 37 PC2 (HS)/ICAP2_B I/O CTHS XX X X Port C2 Timer B Input Capture 2

46 38 PC3 (HS)/ICAP1_B I/O CTHS XX X X Port C3 Timer B Input Capture 1

47 39 PC4/MISO/ICCDATA I/O CTXXXXPort C4

SPI Master In

/ Slave Out

Data

ICC Data In-

put

48 40 PC5/MOSI/AIN14 I/O CTXXXXXPort C5

SPI Master

Out / Slave In

Data

ADC Analog

Input 14

49 - PH0 I/O TTXXXXPort H0

50 - PH1 I/O TTXXXXPort H1

51 - PH2 I/O TTXXXXPort H2

Pin n°

Pin Name

Type

Level Port Main

function

(after

reset)

Alternate function

TQFP80

TQFP64

Input

Output

Input Output

float

wpu

int

ana

ST72F521, ST72521B

12/215

Notes:

1. In the interr upt inpu t column, “ eiX” defines the asso ciated exte rnal inte rrupt vect or. If the we ak pull-u p

52 - PH3 I/O TTXXXXPort H3

53 41 PC6/SCK/ICCCLK I/O CTXXXXPort C6

SPI Serial

Clock ICC Clock

Output

Caution: Negative current

injection not allowed on this

pin5)

54 42 PC7/SS/AIN15 I/O CTXXXXXPort C7

SPI Slave

Select (active

low)

ADC Analog

Input 15

55 43 PA0 I/O CTXei0 X X Port A0

56 44 PA1 I/O CTXei0 X X Port A1

57 45 PA2 I/O CTXei0 X X Port A2

58 46 PA3 (HS) I/O CTHS Xei0 X X Port A3

59 47 VDD_1 S Digital Main Supply Voltage

60 48 VSS_1 S Digital Ground Voltage

61 49 PA4 (HS) I/O CTHS XXXXPort A4

62 50 PA5 (HS) I/O CTHS XXXXPort A5

63 51 PA6 (HS)/SDAI I/O CTHS XTPort A6 I

2C Data 1)

64 52 PA7 (HS)/SCLI I/O CTHS XTPort A7 I

2C Clock 1)

65 53 VPP/ ICCSEL I

Must be tied low. In flash programming

mode, this pin acts as the programming

voltage input VPP. See Section 12.9.2

for more details. High voltage must not

be applied to ROM devices

66 54 RESET I/O CTTop priority non maskable interrupt.

67 55 EVD External voltage detector

68 56 TLI I CTXX Top level interrupt input pin

69 - PH4 I/O TTXXXXPort H4

70 - PH5 I/O TTXXXXPort H5

71 - PH6 I/O TTXXXXPort H6

72 - PH7 I/O TTXXXXPort H7

73 57 VSS_2 S Digital Ground Voltage

74 58 OSC23) I/O Resonator oscillator inverter output

75 59 OSC13) IExternal clock input or Resonator oscil-

lator inverter input

76 60 VDD_2 S Digital Main Supply Voltage

77 61 PE0/TDO I/O CTXX X X Port E0 SCI Transmi t Data Out

78 62 PE1/RDI I/O CTXX X X Port E1 SCI Receive Data In

79 63 PE2/CANTX I/O CTXPort E2 CAN Transmit Data Output

80 64 PE3/CANRX I/O CTXX X X Port E3 CAN Receive Data Input

Pin n°

Pin Name

Type

Level Port Main

function

(after

reset)

Alternate function

TQFP80

TQFP64

Input

Output

Input Output

float

wpu

int

ana

ST72F521, ST72521B

13/215

column (wpu) is merged with the interrupt column (int), then t he I/O configuration is pull-up interrupt input,

else the configuration is f loating interrupt input.

2. In the open dr ain output column, “T” define s a true open drain I/O (P-Buffer and protectio n diode to VDD

are not implemente d). See See “I/O PORTS” on page 47. and Section 12.8 I/O PORT PIN CHARACTER-

ISTICS for more details.

3. OSC1 and OSC2 pins connect a crystal/ceramic resonator, or an external source to the on-chip oscil-

lator; see Section 1 INTRODUCTION and Section 12.5 CLOCK AND TIMING CHARACTERISTICS for

more details.

4. On the chip, each I/ O port may have up to 8 pads. Pads that are n ot bonded to extern al pins are in input

pull-up configuratio n after reset. T he configur ation of these pad s must be kep t at reset state to avoid add-

ed current consumption.

ST72F521, ST72521B

14/215

3 REGISTER & MEMORY MAP

As shown in Figure 4, the MCU is capable of ad-

dressing 64K bytes of memories and I/ O registers.

The available memory locations consist of 128

bytes of register locations, up to 2Kbytes of RAM

and up to 60Kbyt e s of user pro gr am me mor y. The

RAM space includes up to 256 bytes for the stack

from 0100h to 01FFh.

The highest address bytes contain the user reset

and interrupt vectors.

IMPORTANT: Memory locations marked as “Re-

served” must never be accessed. Accessing a re-

seved area can have unpredic table effects on the

device.

Related Documentation

AN 985: Executing Code in ST7 RAM

Figure 4. Memory Map

0000h

RAM

Program Memory

(60K or 32K)

Interrupt & Reset Vectors

HW Registers

0080h

007Fh

0FFFh

(see Table 2)

1000h

FFDFh

FFE0h

FFFFh (see Table 7)

0880h Reserved

087Fh

Short Addressing

RAM (zero page)

256 Bytes Stack

16-bit Addressing

RAM

0100h

01FFh

0080h

0200h

00FFh

or 087Fh 32 KBytes

8000h

60 KBytes

FFFFh

1000h

(2048 or 1024 Bytes)

or 067Fh

or 047Fh

ST72F521, ST72521B

15/215

Table 2. Hardware Register Map

Address Block Register

Label Register Name Reset

Status Remarks

0000h

0001h

0002h Port A PADR

PADDR

PAOR

Port A Data Register

Port A Data Direction Register

Port A Option Register

00h1)

00h

R/W

0003h

0004h

0005h Port B PBDR

PBDDR

PBOR

Port B Data Register

Port B Data Direction Register

Port B Option Register

00h1)

00h

R/W

0006h

0007h

0008h Port C PCDR

PCDDR

PCOR

Port C Data Register

Port C Data Direction Register

Port C Option Register

00h1)

00h

R/W

0009h

000Ah

000Bh Port D PDDR

PDDDR

PDOR

Port D Data Register

Port D Data Direction Register

Port D Option Register

00h1)

00h

R/W

000Ch

000Dh

000Eh Port E PEDR

PEDDR

PEOR

Port E Data Register

Port E Data Direction Register

Port E Option Register

00h1)

00h

R/W

R/W2)

000Fh

0010h

0011h Port F PFDR

PFDDR

PFOR

Port F Data Register

Port F Data Direction Register

Port F Option Register

00h1)

00h

R/W

0012h

0013h

0014h Port G 2) PGDR

PGDDR

PGOR

Port G Data Register

Port G Data Direction Register

Port G Option Register

00h1)

00h

R/W

0015h

0016h

0017h Port H 2) PHDR

PHDDR

PHOR

Port H Data Register

Port H Data Direction Register

Port H Option Register

00h1)

00h

R/W

0018h

0019h

001Ah

001Bh

001Ch

001Dh

001Eh

I2C

I2CCR

I2CSR1

I2CSR2

I2CCCR

I2COAR1

I2COAR2

I2CDR

I2C Control Register

I2C Status Register 1

I2C Status Register 2

I2C Clock Control Register

I2C Own Address Register 1

I2C Own Address Register2

I2C Data Register

00h

R/W

Read Only

R/W

001Fh

0020h Reserved Area (2 Bytes)

0021h

0022h

0023h SPI SPIDR

SPICR

SPICSR

SPI Data I/O Register

SPI Control Register

SPI Control/Status Register

xxh

0xh

00h

R/W

ST72F521, ST72521B

16/215

0024h

0025h

0026h

0027h ITC

ISPR0

ISPR1

ISPR2

ISPR3

Interrupt Software Priority Register 0

Interrupt Software Priority Register 1

Interrupt Software Priority Register 2

Interrupt Software Priority Register 3

FFh

R/W

0028h EICR External Interrupt Control Register 00h R/W

0029h FLASH FCSR Flash Control/Status Register 00h R/W

002Ah WATCHDOG WDGCR Watchdog Control Register 7Fh R/W

002Bh SICSR System Integrity Control/Status Register 000x 000x b R/W

002Ch

002Dh MCC MCCSR

MCCBCR Main Clock Control / Status Register

Main Clock Controller: Beep Control Register 00h

00h R/W

R/W

002Eh

0030h Reserved Area (3 Bytes)

0031h

0032h

0033h

0034h

0035h

0036h

0037h

0038h

0039h

003Ah

003Bh

003Ch

003Dh

003Eh

003Fh

TIMER A

TACR2

TACR1

TACSR

TAIC1HR

TAIC1LR

TAOC1HR

TAOC1LR

TACHR

TACLR

TAACHR

TAACLR

TAIC2HR

TAIC2LR

TAOC2HR

TAOC2LR

Timer A Control Register 2

Timer A Control Register 1

Timer A Control/Status Register

Timer A Input Capture 1 High Register

Timer A Input Capture 1 Low Register

Timer A Output Compare 1 High Register

Timer A Output Compare 1 Low Register

Timer A Counter High Register

Timer A Counter Low Register

Timer A Alternate Counter High Register

Timer A Alternate Counter Low Register

Timer A Input Capture 2 High Register

Timer A Input Capture 2 Low Register

Timer A Output Compare 2 High Register

Timer A Output Compare 2 Low Register

00h

xxxx x0xx b

xxh

80h

00h

FFh

FCh

FFh

FCh

xxh

80h

00h

R/W

Read Only

R/W

Read Only

R/W

0040h Reserved Area (1 Byte)

0041h

0042h

0043h

0044h

0045h

0046h

0047h

0048h

0049h

004Ah

004Bh

004Ch

004Dh

004Eh

004Fh

TIMER B

TBCR2

TBCR1

TBCSR

TBIC1HR

TBIC1LR

TBOC1HR

TBOC1LR

TBCHR

TBCLR

TBACHR

TBACLR

TBIC2HR

TBIC2LR

TBOC2HR

TBOC2LR

Timer B Control Register 2

Timer B Control Register 1

Timer B Control/Status Register

Timer B Input Capture 1 High Register

Timer B Input Capture 1 Low Register

Timer B Output Compare 1 High Register

Timer B Output Compare 1 Low Register

Timer B Counter High Register

Timer B Counter Low Register

Timer B Alternate Counter High Register

Timer B Alternate Counter Low Register

Timer B Input Capture 2 High Register

Timer B Input Capture 2 Low Register

Timer B Output Compare 2 High Register

Timer B Output Compare 2 Low Register

00h

xxxx x0xx b

xxh

80h

00h

FFh

FCh

FFh

FCh

xxh

80h

00h

R/W

Read Only

R/W

Read Only

R/W

Address Block Register

Label Register Name Reset

Status Remarks

ST72F521, ST72521B

17/215

Legend: x=undefined, R/W=read/write

Notes:

1. The contents of the I/O port DR registers are readable only in output configuration. In input configura-

tion, the values of the I/O pins are returned instead of the DR register contents.

2. The bits associated with unavailable pins must always keep their reset value.

0050h

0051h

0052h

0053h

0054h

0055h

0056h

0057h

SCI

SCISR

SCIDR

SCIBRR

SCICR1

SCICR2

SCIERPR

SCIETPR

SCI Status Register

SCI Data Register

SCI Baud Rate Register

SCI Control Register 1

SCI Control Register 2

SCI Extended Receive Prescaler Register

Reserved area

SCI Extended Transmit Prescaler Register

C0h

xxh

00h

x000 0000b

00h

---

00h

Read Only

R/W

0058h

0059h Reserved Area (2 Bytes)

005Ah

005Bh

005Ch

005Dh

005Eh

005Fh

0060h

006Fh

CAN

CANISR

CANICR

CANCSR

CANBRPR

CANBTR

CANPSR

CAN Interrupt Status Register

CAN Interrupt Control Register

CAN Control / Status Register

CAN Baud Rate Prescaler Register

CAN Bit Timing Register

CAN Page Selection Register

First address

Last address of CAN page x

00h

23h

00h

R/W

See CAN

Description

0070h

0071h

0072h ADC ADCCSR

ADCDRH

ADCDRL

Control/Status Register

Data High Register

Data Low Register

00h

R/W

Read Only

0073h

0074h

0075h

0076h

0077h

0078h

0079h

007Ah

007Bh

007Ch

007Dh

PWM ART

PWMDCR3

PWMDCR2

PWMDCR1

PWMDCR0

PWMCR

ARTCSR

ARTCAR

ARTARR

ARTICCSR

ARTICR1

ARTICR2

PWM AR Timer Duty Cycle Register 3

PWM AR Timer Duty Cycle Register 2

PWM AR Timer Duty Cycle Register 1

PWM AR Timer Duty Cycle Register 0

PWM AR Timer Control Register

Auto-Reload Timer Control/Status Register

Auto-Reload Timer Counter Access Register

Auto-Reload Timer Auto-Reload Register

AR Timer Input Capture Control/Status Reg.

AR Timer Input Capture Register 1

00h

R/W

Read Only

007Eh

007Fh Reserved Area (2 Bytes)

Address Block Register

Label Register Name Reset

Status Remarks

ST72F521, ST72521B

18/215

4 FLASH PROGRAM MEMORY

4.1 Introduction

The ST7 dual voltage High Density Flash

(HDFlash) is a non-volatile memory that can be

electrically erased as a single block or b y individu-

al sectors and programmed o n a Byt e-by-Byte ba-

sis using an external VPP supply.

The HDFlash devices can be programmed and

erased off-board (plugged in a programming tool)

or on-board using ICP ( In-Circuit Progra mming) or

IAP (In-Application Programming).

The array matrix organisation allows each sector

to be erased and reprogrammed without affecting

other sectors.

4.2 Main Features

■Three Flash programming modes:

– Insertion in a programming tool. In this mode,

all sectors including option bytes can be pro-

grammed or erased.

– ICP (In-Circuit Programming). In this mode, all

sectors including option bytes can be pro-

grammed or erased without removing the de-

vice from the application board.

– IAP (In-Application Programming) In this

mode, all sectors exce pt Sector 0, can be pro-

grammed or erased without removing the de-

vice from the application board and while the

application is running.

■ICT (In-Circuit Testing) for downloading and

executing user application test patterns in RAM

■Read-out protection

■Register Access Security System (RASS) to

prevent accidental programming or erasing

4.3 Structure

The Flash memory is organised in sectors and can

be used for both code and data storage.

Depending on the overall Flash memory size in the

microcontroller device, there are up to three user

sectors (see Table 3). Each of these sectors can

be erased independently to avoid unnecessary

erasing of the whole Flash memory when only a

partial erasing is required.

The first two sectors have a fixed size of 4 Kbytes

(see Fig ure 5). They are mapped in the up per par t

of the ST7 addressing space so the reset and in-

terrupt vectors are located in Sector 0 (F000h-

FFFFh).

Table 3. Sectors available in Flash devices

4.3.1 Read-out Protection

Read-out protection, when selected, provides a

protection against Program Memory content ex-

traction and against write access to Flash memo-

ry. Even if no protection can be considered as to-

tally unbreaka ble, t he f eatu re provides a ver y high

level of protection for a general purpose microcon-

troller.

In flash devices, this protection is removed by re-

programming the option. In this case, the entire

program memory is first automatically erased and

the device can be reprogrammed.

Read-out protection selection depends on the de-

vice type:

– In Flash devices it is enabled and removed

through the FMP_R bit in the option byte.

– In ROM devices it is enabled by mask option

specified in the Option List.

Note: In flash devices, the LVD is not supported if

read-out protection is enabled.

Figure 5. Memory Map and Sector Address

Flash Size (bytes) Available Sectors

4K Sector 0

8K Sectors 0,1

> 8K Sectors 0,1, 2

4 Kbytes

2Kbytes SECTOR 1

SECTOR 0

16 Kbytes

SECTOR 2

8K 16K 32K 60K FLASH

FFFFh

EFFFh

DFFFh

3FFFh

7FFFh

1000h

24 Kbytes

MEMORY SIZE

8Kbytes 40 Kbytes 52 Kbytes

9FFFh

BFFFh

D7FFh

4K 10K 24K 48K

ST72F521, ST72521B

19/215

FLASH PROGRAM MEMORY (Cont’d)

4.4 ICC Interface

ICC needs a minimum of 4 and up to 6 pins to be

connected t o the progra mming too l (see Figure 6).

These pins ar e:

– RESET: device reset

–V

SS: device power supp ly grou nd

– ICCCLK: ICC output serial clock pin

– ICCDATA: ICC input/output serial data pin

– ICCSEL/VPP: programming voltage

– OSC1(or OSCIN): main clock input for exter-

nal source (optional)

–V

DD: application board power supply (option-

al, see Figure 6, Note 3)

Figure 6. Typical ICC Interface

Notes:

1. If the ICCCLK or ICCDATA pins are only used

as outputs in the application, no signal isolation is

necessary. As soon as the Programming Tool is

plugged to the boar d, even if an ICC session is n ot

in progress, the ICCCLK and ICCDATA pins are

not available for the application. If they are used as

inputs by the applicatio n, isolat ion such as a seria l

resistor has to implemented in case another de-

vice forces the signal. Refer to the Programming

Tool documentation for recommended resistor val-

ues.

2. During the ICC session, the programming tool

must control the RESET pin. This can le ad to con-

flicts between the pr ogram ming t ool an d the a ppli-

cation reset circuit if it drives more than 5mA at

high level (push pull output or pull-up resistor<1K).

A schottky dio de can be used to isolate the ap pli-

cation RESET circuit in this case. When using a

classical RC network with R>1K or a reset man-

agement IC with open drain output and pull-up re-

sistor>1K, no additional components are needed.

In all cases the us er must ensure tha t no external

reset is generated by the application during the

ICC session.

3. The use of Pin 7 of the ICC connector depends

on the Programming Tool architecture. This pin

must be connected when using most ST Program-

ming Tools (it is used to monitor the application

power supply). Please refer to the Programming

Tool manual.

4. Pin 9 has to be connected to the OSC1 or OS-

CIN pin of the ST7 when the clock is not available

in the applicatio n or if the selected clock option is

not programmed in the option byte. ST7 devices

with multi-oscillator capability need to have OSC 2

grounded in this case.

ICC CONNECTOR

ICCDATA

ICCCLK

RESET

VDD

HE10 CONNECTOR TYPE

APPLICATION

POWER SUPPLY

246810

975 3

PROGRAMMING TOOL ICC CONNECTOR

APPLICATION BOARD

ICC Cable

(See Note 3)

10kΩ

VSS

ICCSEL/VPP

ST7

CL2 CL1

OSC1

OSC2

OPTIONAL

See Note 1

See Note 2

APPLICATION

RESET SOURCE

APPLICATION

I/O

(See Note 4)

ST72F521, ST72521B

20/215

FLASH PROGRAM MEMORY (Cont’d)

4.5 ICP (In-Circuit Programming)

To perform ICP the microcontroller must be

switched to ICC (In-Circu it Communication) mode

by an external controller or programming tool.

Depending o n the ICP code downlo aded in RAM,

Flash memory programming can be fully custom-

ized (number of bytes to program, program loca-

tions, or selection serial communication interface

for downloading).

When using an STMicroelectronics or third-party

programming tool that supports ICP and the spe-

cific microcontroller device, t he user n eed s only to

implement the ICP hardware interface on the ap-

plication board (see Figure 6). F or more det ails on

the pin locations, refer to the device pinout de-

scription.

4.6 IAP (In-Application Programming)

This mode uses a BootLoa der pr og ram pr eviously

stored in Sector 0 by the user (in ICP mode or by

plugging the device in a programming tool).

This mode is fully controlled by user software. This

allows it to be adapted to th e user applicat ion, (us-

er-defined strategy for entering programming

mode, choice of communications protocol used to

fetch the dat a to be st ored, etc. ). For examp le, it is

possible to download co de from the SPI, SCI, USB

or CAN interface and program it in the Flash. IAP

mode can be used to program any of the Flash

sectors except Sector 0, which is write/erase pro-

tected to allow recovery in case errors occur dur-

ing the programming operation.

4.7 Related Documentation

For details on Flash programming and ICC proto-

col, refer to the ST7 Flash Programming Refer-

ence Manual and to the ST7 ICC Protocol Refer-

ence Manual.

4.7.1 Register Description

FLASH CONTROL/STATUS REGISTER (FCSR)

Read/Write

Reset Value: 00 0 0 00 00 (0 0h )

This register is reserved for use by Programming

Tool software. It controls the Flash programming

and erasing operations.

Figure 7. Flash Control/Status Register Address and Reset Value

00000000

Address

(Hex.) Register

Label 76543210

0029h FCSR

Reset Value00000000

ST72F521, ST72521B

21/215

5 CENTRAL PROCESSING UNIT

5.1 INTRODUCTION

This CPU has a full 8-bit architecture and contains

six internal registers allowing efficient 8-bit data

manipulation.

5.2 MAIN FEATURES

■Enable executing 63 basic instructions

■Fast 8-bit by 8-bit multiply

■17 main addressing modes (with indirect

addressing mode)

■Two 8-bit index registers

■16-bit stack pointer

■Low power HALT and WAIT modes

■Priority maskable hardware interrupts

■Non-maskable software/hardwa r e in te r ru pt s

5.3 CPU REGISTERS

The 6 CPU registers shown in Figure 8 are not

present in the memory m apping and are ac cessed

by specific instructions.

Accumulator (A)

The Accumulator is an 8-bit general purpose reg-

ister used to hold operands and the results of the

arithmetic and lo gic calculations and to manipulate

data.

Index Registers (X and Y)

These 8-bit registers are used to create effective

addresses or as temporary storage areas for data

manipulation. (The Cross-Assembler generates a

precede instruction (PRE) to indicate that the fol-

lowing instruction refers to the Y register.)

The Y register is not affecte d by the interrupt auto-

matic procedures.

Program Counter (PC)

The program count er is a 16-bit register conta ining

the address of the next instruction to be executed

by the CPU. It is made of two 8-bit registers PCL

(Program Counter Lo w which is the LSB) and PCH

(Program Counter High which is the MSB).

Figure 8. CPU Registers

ACCUMULATOR

X INDEX REGISTER

Y INDEX REGISTER

STACK POINTER

CONDITION CODE REGISTER

PROGRAM COUNTER

1C1I1HI0NZ

RESET VALUE = RESET VECTOR @ FFFEh-FFFFh

15 8

PCH PCL

15 870

RESET VALUE = STACK HIGHER ADDRESS

RESET VALUE = 1X11X1XX

RESET VALUE = XXh

X = Undefined Value

ST72F521, ST72521B

22/215

CENTRAL PROCESSING UNIT (Cont’d)

Condition Code Register (CC)

Read/Write

Reset Value: 111x1xxx

The 8-bit Condition Code register contains the in-

terrupt masks and four flags representative of the

result of the inst ruction just executed. Th is register

can also be handled by the PUSH and POP in-

structions.

These bits can be individually tested and/or con-

trolled by specific instructions.

Arithmetic Management Bits

Bit 4 = H Half carry.

This bit is set by hardware when a carry occurs be-

tween bits 3 and 4 of the ALU during an ADD or

ADC instructions. It is reset by hardware during

the same instructions.

0: No half carry has occurred.

1: A half carry has occurred.

This bit is tested using the JRH or JRNH instruc-

tion. The H bit is useful in BCD arithmetic subrou-

tines.

Bit 2 = N Negative.

This bit is set and cl ear ed by h ardwar e. I t is r epr e-

sentative of the result sign of the last arithmetic,

logical or data manipulation. It’s a copy of the re-

sult 7th bit.

0: The result of the last operation is positive or null.

1: The result of the last operation is negative

(i.e. the most signif icant bit is a logic 1).

This bit is accessed by the JRMI and JRPL instruc-

tions.

Bit 1 = Z Zero.

This bit is set and cleared by hardware. This b it in-

dicates that the result of the last arithm et ic, log ica l

or data manipulation is zero.

0: The result of the last operation is different from

zero.

1: The result of the last operation is zero.

This bit is accessed by the JREQ and JRNE test

instructions.

Bit 0 = C Carry/borrow.

This bit is set and cleared by hardware and soft-

ware. It indicates an overflow or an underflow has

occurred during the last arithmetic operation.

0: No overflow or underflow has occurred.

1: An overflow or underflow has occurred.

This bit is driven by the SCF and RCF instructions

and tested by the JRC and JRNC instru ctions. I t is

also affected by the “bit test and br anch”, shift and

rotate instr uct ions .

Interrupt Management Bits

Bit 5,3 = I1, I0 Interrupt

The combination of the I1 and I0 bit s gives the cur-

rent interrupt software priority.

These two bits are set/cleared by hardware when

entering in interrupt. The loaded value is given by

the corresponding bits in the interrupt softwa re pri-

ority registers (IxSPR). They can be also set/

cleared by software with the RIM, SIM, IRET,

HALT, WFI and PUSH/POP instructions.

See the interrupt management chapter for more

details.

11I1HI0NZC

Interrupt Software Pri ori ty I1 I0

Level 0 (main) 1 0

Level 1 0 1

Level 2 0 0

Level 3 (= interrupt disable) 1 1

ST72F521, ST72521B

23/215

CENTRAL PROCESSING UNIT (Cont’d)

Stack Pointer (SP)

Read/Write

Reset Value: 01 FFh

The Stack Pointer is a 16-bit register which is al-

ways pointing to the n ext free location in the sta ck.

It is then de cremented aft er data has been p ushed

onto the stack and incremented before data is

popped from the stack (see Figure 9).

Since the stack is 256 bytes deep, the 8 most sig-

nificant bits are forced by hardware. Following an

MCU Rese t, or after a Reset Stack Pointer instruc-

tion (RSP), the Stack Pointer co ntains its reset val-

ue (the SP7 to SP0 bits are set) which is the stack

higher address.

The least significant byte of the Stack Pointer

(called S) can be directly accessed by a LD in-

struction.

Note: When the lower limit is exceeded, the Stack

Pointer wraps around to the stack upper limit, with-

out indicating the stack overflow. The previously

stored information is then overwritten and there-

fore lost. The stack also wraps in case of an under-

flow.

The stack is used to save the return address dur-

ing a subroutine call and the CPU context during

an interrupt. The user may also directly manipulate

the stack by means of the PUSH an d POP instruc-

tions. In the case of a n inte rrupt, the PCL is stored

at the first location pointed t o by th e SP. Then the

other registers are stored in the next locations as

shown in Figure 9.

– When an inte rr up t is received, the SP is decre-

mented and the context is pushed on the stack.

– On return from interrupt, the SP is incremented

and the context is popped from the stack.

A subroutine call occupi es two locations and an in-

terrupt five locations in the stack area.

Figure 9. Stack Manipulation Example

15 8

00000001

SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0

PCH

PCL

PCH

PCL

PCH

PCL

PCH

PCL

PCH

PCL

CALL

Subroutine Interrupt

Event PUSH Y POP Y IRET RET

or RSP

@ 01FFh

@ 0100h

Stack Higher Address = 01FFh

Stack Lower Address = 0100h

ST72F521, ST72521B

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6 SUPPLY, RESET AND CLOCK MANAGEMENT

The device includes a range of utility features for

securing the application in critical situations (for

example in case of a power brown-out), and re-

ducing the number of external components. An

overview is shown in Figure 11.

For more details, refer to dedicated parametric

section.

Main features

■Optional PLL for multiplying the frequency by 2

(not to be used with internal RC oscillator)

■Reset Sequen ce Manager (RSM)

■Multi-Oscillator Clock Management (MO)

– 5 Crystal/Ceramic resonator oscillators

– 1 Internal RC oscillator

■System Integrity Management (SI)

– Main supply Low voltage detection (LVD)

– Auxiliary Voltage detector (AVD) with interrupt

capability for monitoring the main supply or

the EVD pin

6.1 PHASE LOCKED LOOP

If the clock frequency input to the PLL is in the

range 2 to 4 MHz, t he PLL can be used to m ult iply

the frequency by two to obtain an fOSC2 of 4 to 8

MHz. The PLL is enabled b y option byte. I f the PLL

is disabled, then fOSC2 = fOSC/2.

Caution: The PLL is not recommended for appli-

cations where timing accuracy is required. See

“PLL Charac te rist ics” on pa g e 177.

Figure 10. PLL Block Diagram

Figure 11. Clock, Reset and Supply Block Diagram

PLL OPT ION BIT

PLL x 2 fOSC2

/ 2

fOSC

LOW VOLTAGE

DETECTOR

(LVD)

fOSC2

AUXILIARY VOLTAGE

DETECTOR

(AVD)

MULTI-

OSCILLATOR

(MO)

OSC1

RESET

VSS

EVD

VDD

RESET SEQUENCE

MANAGER

(RSM)

OSC2 MAIN CLOCK

AVD Interrupt Request

CONTROLLER

PLL

SYSTEM INTEGRITY MANAGEMENT WATCHDOG

SICSR TIMER (WDG)

WITH REALTIME

CLOCK (MCC/RTC)

AVDAVD AVD LVD

IE WDG

fOSC

(option)

fCPU

ST72F521, ST72521B

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6.2 MULTI-OSCILLATOR (M O)

The main clock of the ST7 can be generated by

three differe nt source types comin g from the multi-

oscillator block:

■an external source

■4 crystal or ceramic resonator oscillators

■an internal high frequency RC oscillator

Each oscillator is optimized for a given frequency

range in terms of consumption and is selectable

through the option byte. The associated hardware

configurations are shown in Table 4. Refer to the

electrical characteristics section for more details.

Caution: The OSC1 and/or OSC2 pins must not

be left unconnected. For the purposes of Failure

Mode and Effect Analysis, it should be noted that if

the OSC1 and/or OSC2 pins are lef t unconnected,

the ST7 main oscillator may start and, in this con-

figuration, could generate a n fOSC clock frequency

in excess of the allowed maximum (>16MHz.),

putting the ST7 in an unsafe/undefined state. The

product behaviour must therefore be considered

undefined when the OSC pins are left unconnect-

ed.

External Clock Source

In this external clock mode, a clock signal (square,

sinus or triangle) with ~50% duty cycle has to drive

the OSC1 pin while the OSC2 pin is tied to ground.

Crystal/Cer amic Oscillators

This family of oscillators has the advantage of pro-

ducing a very accurate rate on the main clock of

the ST7. The selection within a list of 4 oscillators

with different frequency ranges has to be done by

option byte in order to reduce consumption (refer

to section 14.1 on page 201 for more details on the

frequency ranges). In this mode of the multi-oscil-

lator, the resonator and the load capacitors have

to be placed as close as possible to the oscillator

pins in order to minimize output distortion and

start-up stabilization time. The loading capaci-

tance values must be adjusted according to the

selected oscillator.

These oscillators are not stopped during the

RESET phase to avoid losing time in the oscillator

start-u p ph as e.

Internal RC Osci lla tor

This oscillator allows a low cost solution for the

main clock of the ST7 using only an internal resis-

tor and capacitor. Internal RC oscillator mode has

the drawback of a lower frequency accuracy and

should not be used in applications that require ac-

curate timin g.

In this mode, the two oscillator pins have to be tied

to ground.

Table 4. ST7 Clock Sources

Hardware Configuration

External ClockCrystal/Ceramic ResonatorsInternal RC Oscillator

OSC1 OSC2

EXTERNAL

ST7

SOURCE

OSC1 OSC2

LOAD

CAPACITORS

ST7

CL2

CL1

OSC1 OSC2

ST7

ST72F521, ST72521B

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6.3 RESET SEQUENCE MANAGER (RSM)

6.3.1 Introduction

The reset sequence manager includes three RE-

SET sources as shown in Figure 13:

■External RESET source pulse

■Internal LVD RESET (Low Voltage Detection)

■Internal WATCHDOG RESET

These sources act on the RESET pin and it is al-

ways kept low during the delay phase.

The RESET service routine vector is fixed at ad-

dresses FFFEh-FFFFh in the ST7 memory map.

The basic RESET sequence consists of 3 phases

as shown in Figure 12:

■Active Phase depending on the RESET source

■256 or 4096 CPU clock cycle delay (selected by

option byte )

■RESET vector fetch

The 256 or 4096 CPU clock cycle de lay allows the

oscillator to stabilise and ensures that recovery

has taken place from the Reset state. The shorter

or longer clock cycle delay should be selected by

option byte to correspond to the stabilization time

of the external oscillator used in the application

(see section 14.1 on page 201).

The RESET vector fetch phase duration is 2 clock

cycles.

Figure 12. RESET Sequence Phases

6.3.2 Asynchronous External RESET pin

The RESET pin is both an input and an open -drain

output with integrated RON weak pull-up resistor.

This pull-up has no fixed value but varies in ac-

cordance with the input voltage. It can be pulled

low by external circuitry to reset the device. See

“CONTROL PIN CHARACTERISTICS” on

page 185 for more details.

A RESET signal originating from an external

source must h ave a duration of at least th(RSTL)in in

order to be recognized (see Figure 14). This de-

tection is asynchronous and therefore the MCU

can enter reset state even in HALT mode.

Figure 13. Reset Block Diagram

RESET

Active Phase INTERNAL RESET

256 or 4096 CLOCK CYCLES FETCH

VECTOR

RESET

RON

VDD

WATCHDOG RESET

LVD RESET

INTERNAL

RESET

PULSE

GENERATOR

Filter

ST72F521, ST72521B

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RESET SEQUENCE MANAGER (Cont’d)

The RESET pin is an asynchronous signal which

plays a major role in EMS performance. In a noisy

environment, it is recommended to follow the

guidelines mentioned in the electrical characteris-

tics section.

If the external RESET pulse is shorter than

tw(RSTL)out (see sh ort ext. Rese t in Figure 14), the

signal on the RESET pin may be stre tched. Othe r-

wise the delay will not be applied (see long ext.

Reset in Figure 14). Starting fr om the external RE-

SET pulse recognition, the device RESET pin acts

as an output that is pulled low during at least

tw(RSTL)out.

6.3.3 External Power-On RESET

If the LVD is disable d by option byte, to star t up the

microcontroller correctly, the user must ensure by

means of an external reset circuit that the reset

signal is held low until VDD is over the minimum

level specified for the selected fOSC frequency.

(see “OPERATING CONDITIONS” on page 167)

A proper reset signal for a slow rising VDD supply

can generally be provided by an external RC net-

work connected to the RESET pin.

6.3.4 Internal Low Voltage Detector (LVD)

RESET

Two different RESET sequ ences caused by the in-

ternal LVD circuitry can be distinguished:

■Power-On RESET

■Voltage Drop RESET

The device RESET pin acts as an output that is

pulled low when VDD<VIT+ (rising edge) or

VDD<VIT- (falling edge) as shown in Figure 14.

The LVD filters spikes on VDD lar ger than tg(VDD) to

avoid parasitic resets.

6.3.5 Internal Watchdog RESET

The RESET sequence generated by a internal

Watchdog counter over flow is shown in Figur e 1 4 .

Starting fr om the Watchdog counter underflo w, the

device RESET pin acts as an output that is pulled

low during at least tw(RSTL)out.

Figure 14. RESET Sequences

VDD

RUN

RESET PIN

EXTERNAL

WATCHDOG

ACTIVE PHASE

VIT+(LVD)

VIT-(LVD)

th(RSTL)in

tw(RSTL)out

RUN

th(RSTL)in

ACTIVE

WATCHDOG UNDERFLOW

tw(RSTL)out

RUN RUN RUN

RESET

SOURCE

SHORT EXT.

RESET

LVD

RESET LONG EXT.

RESET WATCHDOG

RESET

INTERNAL RESET ( 256 or 4096 TCPU)

VECTOR FETCH

tw(RSTL)out

PHASE ACTIVE

PHASE

ACTIVE

PHASE

DELAY

ST72F521, ST72521B

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6.4 SYSTEM INTEGRITY MANAGEMENT (SI)

The System Integrity Management block contains

the Low Voltage Detector (LVD) and Auxiliary Volt-

age Detector (AVD) functions. It is managed by

the SICSR register.

6.4.1 Low Voltage Detector (LVD)

The Low Voltage Detector function (LVD) gener-

ates a static reset when the VDD supply voltage is

below a VIT- reference value. This means that it

secures the power-up as well as the power-down

keeping the ST7 in reset.

The VIT- reference value for a voltage drop is lower

than the VIT+ r eference value for power- on in order

to avoid a parasitic reset whe n the MCU starts run-

ning and sinks cu rr en t on the supply (hysteresis).

The LVD Reset circuitry generates a reset when

VDD is below:

–V

IT+ when VDD is rising

–V

IT- when VDD is falling

The LVD function is illustrated in Figure 15.

The voltage threshold can be conf igured b y option

byte to be low, medium or high.

Provided the minimum VDD value (guaranteed for

the oscillator frequency) is above VIT-, the MCU

can only be in two modes:

– under full software control

– in static safe reset

In these conditions, secur e operation is always en-

sured for the application without the need for ex-

ternal reset hardware.

During a Low Voltage Detector Reset, the RESET

pin is held low, thus permitting the MCU to reset

other devices.

Notes:

The LVD allows the device to be used without any

external RESET circuitry.

If the medium or low thresholds are selected, the

detection may occur outside the specified operat-

ing voltage range. Below 3.8V, device oper ation is

not guaranteed.

The LVD is an optional function which can be se-

lected by optio n by te .

It is recommended to make sure that the V DD sup-

ply voltage rises monoto nously when the device is

exiting from Reset, to ensure the application func-

tions prope rly.

Figure 15. Low Voltage Detector vs Reset

VDD

VIT+

RESET

VIT-

Vhys

ST72F521, ST72521B

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SYSTEM INTEGRITY MANAGEMENT (Cont’d)

6.4.2 Auxiliary Voltage Detector (AVD)

The Voltage Detector function (AVD) is based on

an analog comparison between a VIT-(AVD) and

VIT+(AVD) reference value and the VDD main sup-

ply or the external EVD pin voltage level (VEVD).

The VIT- reference value for falling voltage is lower

than the VIT+ reference value for rising voltage in

order to avoid parasitic detection (hysteresis).

The output of t he AVD comparator is directly read-

able by the application software through a real

time status bit (AVDF) in the SICS R register. This

bit is read only.

Caution: The AVD function is active only if the

LVD is enabled through the option byte.

6.4.2.1 Monitoring the VDD Main Supply

This mode is selected by clearing the AVDS bit in

the SICSR register.

The AVD voltage threshold value is relative to the

selected LVD threshold configured by option byte

(see section 14.1 on page 201).

If the AVD interr upt is enabled, an interr upt is gen-

erated when the voltage crosses the VIT+(AVD) or

VIT-(AVD) threshold (AVDF bit toggles).

In the case of a drop in voltage, the AVD interrupt

acts as an early warning, a llowing software t o shut

down safely before the LVD resets the microcon-

troller. See Figure 16.

The interrupt on the rising edge is used to inform

the application t hat the VDD warning state is over.

If the voltage rise time trv is less than 256 or 4096

CPU cycles (depending on the reset delay select-

ed by option byte), no AVD interrupt will be gener-

ated when VIT+(AVD) is reached.

If trv is greater than 256 or 4096 cycles then:

– If the AVD interrupt is enabled before the

VIT+(AVD) threshold is reached, then 2 AVD inter-

rupts will be received: the first when the AVDIE

bit is set, and the second when the threshold is

reached.

– If the AVD interrupt is enabled after the VIT+(AVD)

threshold is reached then only one AVD interrupt

will occur.

Figure 16. Using the AVD to Monitor VDD (AVDS bit=0)

VDD

VIT+(AVD)

VIT-(AVD)

AVDF bit 0 0RESET VALUE

IF AVDIE bit = 1

Vhyst

AVD INTERRUPT

REQUEST

INTERRUPT PROCESS INTERRUPT PROCESS

VIT+(LVD)

VIT-(LVD)

LVD RESET

Early Warning Interrupt

(Power has dropped, MCU not

not yet in reset)

trv VOLTAGE RISE TIME

ST72F521, ST72521B

30/215

SYSTEM INTEGRITY MANAGEMENT (Cont’d)

6.4.2.2 Monitoring a Voltage on the EVD pin

This mode is selected by setting the AVDS bit in

the SICSR register.

The AVD circuitry can generate an interrupt when

the AVDIE bit o f the SICSR r egister is set . Th is in-

terrupt is generated on the rising and falling edges

of the comparat or output. This means it is generat-

ed when either one of t hese two events occur:

–V

EVD rises up to VIT+(EVD)

–V

EVD falls down to VIT-(EVD)

The EVD function is illustrated in Figure 17.

For more det ails, refer to the Elec trical C haracter-

istics section.

Figure 17. Using t he Voltage Detector to Monitor the EVD pin (AVDS bit=1)

VEVD

VIT+(EVD)

VIT-(EVD)

AVDF 0 01

IF AVDIE = 1

Vhyst

AVD INTERRUPT

REQUEST

INTERRUPT PROCESS INTERRUPT PROCESS

ST72F521, ST72521B

31/215

SYSTEM INTEGRITY MANAGEMENT (Cont’d)

6.4.3 Low Power Modes

6.4.3.1 Interrupts

The AVD interrupt event generates an interrupt if

the corresponding Enable Control Bit (AVDIE) is

set and the interrupt mask in the CC register is re-

set (RIM instruction).

Mode Description

WAIT No effect on SI. AVD interrupts cause the

device to exit from Wait mode.

HALT The CRSR register is frozen.

Interrupt Event Event

Flag

Enable

Control

Bit

Exit

from

Wait

Exit

from

Halt

AVD event AVDF AVDIE Yes No

ST72F521, ST72521B

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SYSTEM INTEGRITY MANAGEMENT (Cont’d)

6.4.4 Register Description

SYSTEM INTEGRITY (SI) CONTROL/STATUS REGISTER (SICSR)

Read/Write

Reset Value: 000x 000x (00h)

Bit 7 = AVDS Voltage Detection selection

This bit is set and cleared by software. Voltage De-

tection is available only if the LVD is enabled by

option byte.

0: Voltage detectio n on VDD supply

1: Voltage detectio n on EVD pin

Bit 6 = AVDIE Voltage Detector interrupt enable

This bit is set and cleared by software. It enables

an interrupt to be generated when the AVDF flag

changes (toggles). The pending interrupt informa-

tion is automatically cleared when software enters

the AVD interrupt routine.

0: AVD interrupt disabled

1: AVD interrupt enabled

Bit 5 = AVDF Voltage Detector flag

This read-only bit is set and cleared by hardware.

If the AVDIE b it is se t, an inte rrupt r equ est is gen -

erated when the AVDF bit ch anges value. Ref er to

Figure 16 and to Section 6.4.2.1 for additional de-

tails.

0: VDD or VEVD over VIT+(AVD) threshold

1: VDD or VEVD und er VIT-(AVD) threshold

Bit 4 = LVDRF LVD reset flag

This bit indicates that the last Reset was generat-

ed by the LVD block. It is set by hardware ( LVD re-

set) and cleared by software (writing zero). See

WDGRF flag description for more details. When

the LVD is disabled by OPTION BYTE, the LVDRF

bit value is undefined.

Bits 3:1 = Reserved, must be kept cleared.

Bit 0 = WDGRF Watchdog reset flag

This bit indicates that the last Reset was generat-

ed by the Watchdog peripheral. It is set by hard-

ware (watchdog reset) and cleared by software

(writing zero) or an LVD Reset (to ensure a stable

cleared state of the WDGRF flag when CPU

starts).

Combined with the LVDRF flag information, the

flag description is given by the following table.

Application notes

The LVDRF flag is not cleared when another RE-

SET type occurs (external or watchdog), the

LVDRF flag remains set to keep trace of the origi-

nal failure.

In this cas e, a watc hdog re set c an be dete cted by

software while an external reset can not.

CAUTION: When the LVD is not activated with the

associated option byte, the WDGRF flag can not

be used in the application.

AVD

SAVD

IE AVD

FLVD

RF 000

WDG

RESET Sources LVDRF WDGRF

External RESET pin 0 0

Watchdog 0 1

LVD 1 X

ST72F521, ST72521B

33/215

7 INTERRUPTS

7.1 INTRODUCTION

The ST7 enhanced interrupt management pro-

vides the following features:

■Hardware interrupts

■Software interrupt (TRAP)

■Nested or concurrent interrupt management

with flexible interrupt priority and level

management:

– Up to 4 software prog rammable nesting levels

– Up to 16 interrupt vectors fixed by hardware

– 2 non maskable events: RESET, TRAP

– 1 maskable Top Level event: TLI

This interrupt manag ement is based on:

– Bit 5 and bit 3 of the CPU CC register (I1:0),

– Interrupt software priority registers (ISPRx),

– Fixed interrupt vector addresses located at the

high addresses of the memory map (FFE0h to

FFFFh) sorted by hardware priority order.

This enhanced interrupt controller guarantees full

upward compatibility with the standard (not nest-

ed) ST7 interrup t controller.

7.2 MASKING AND PROCESSING FLOW

The interrupt ma sking is managed by the I1 an d I0

bits of the CC register and the ISPRx registers

which give the interrupt software priority level of

each interrupt vector (see Table 5). The process-

ing flow is shown in Figure 18

When an interrupt request has to be serviced:

– Normal processing is suspended at the end of

the current instruction execution.

– The PC, X, A and CC registers are saved onto

the stack.

– I1 and I0 bits of CC register are se t according t o

the corresponding valu es in t he ISPRx regist er s

of the serviced inte rr upt ve cto r.

– The PC is then loaded with the interrupt vector of

the interrupt to service and the first instruction of

the interrupt service routine is fetched (refer to

“Interrupt Mapping” table for vector addresses).

The interrupt service routine should end with the

IRET instruction which causes the contents of the

saved registers to be recovered from the stack.

Note: As a consequence of the IRET instruction,

the I1 and I0 bits will be restored from the stack

and the program in the previous level will resume.

Table 5. Interrupt Software Priority Levels

Figure 18. Interrupt Processing Flowchart

Interrupt software priority Level I1 I0

Level 0 (main) Low

High

Level 1 0 1

Level 2 0 0

Level 3 (= interrupt disable) 1 1

“IRET”

RESTORE PC, X, A, CC STACK PC, X, A, CC

LOAD I1:0 FROM INTERRUPT SW REG.

FETCH NEXT

RESET TRAP

PENDING

INSTRUCTION

I1:0

FROM STACK

LOAD PC FROM IN TERRUPT VECT OR

Interrupt has the same or a

lower software priority

THE INTERRUPT

STAYS PENDING

than current one

Interrupt has a higher

software priority

than current one

EXECUTE

INSTRUCTION

INTERRUPT

ST72F521, ST72521B

34/215

INTERRUPTS (Cont’d)

Servicing Pending Interrupts

As several interrupts can be pending at the same

time, the interrupt to be taken into account is deter-

mined by the following two-step process:

– the highest software priority int errupt is serviced,

– if several interrupts have the same software pri-

ority then the in terrupt with the highest hardware

priority is serviced first.

Figure 19 describes this decision process.

Figure 19. Priority Decision Process

When an interrupt request is not serviced immedi-

ately, it is latched and then processed when its

software priority combined with the hardware pri-

ority becomes the highest one.

Note 1: The hardware priority is exclusive while

the software one is not. This allows the previous

process to succeed with only one interrupt.

Note 2: TL I, RESET and TRAP can be considered

as having th e highes t softwar e priorit y in the dec i-

sion process.

Different Interrupt Vector Sources

Two interrupt source types are managed by the

ST7 interrupt controller: the non-maskable type

(RESET, TRAP) and the maskable type (external

or from internal peripherals).

Non-Maskable Sources

These sources are processed regardless of the

state of the I1 and I0 bits of the CC register (see

Figure 18). After stacking the PC, X, A and CC

registers (except for RESET), the corresponding

vector is loaded in the PC register and the I1 and

I0 bits of the CC are set to disable interrupts (level

3). These sources allow the processor to exit

HALT mode.

■TRAP (Non Maskable Software Interrupt)

This software interrupt is serviced when the TRAP

instruction is executed. It will be serviced accord-

ing to the flowch art in Figure 18.

Caution: TRAP can be interrupted by a TLI.

■RESET

The RESET source has the highest priority in the

ST7. This means that the first current routine has

the highest soft ware prior ity (l evel 3) and th e high-

est hardware priority.

See the RESET chapter for more details.

Maskable Sources

Maskable interrupt vector sources can be serviced

if the corresponding interrupt is enabled and if its

own interrupt software priority (in ISPRx registers)

is higher than the one currently being serviced (I1

and I0 in CC register). If any of these two condi-

tions is false, the interrupt is latched and thus re-

mains pending.

■TLI (Top Level Hardware Interrupt)

This hardware interrupt occurs when a specific

edge is detected on the dedicated TLI pin. It will be

serviced according t o the flowcha rt in Figu re 18 as

a trap.

Caution: A TRAP instruction must not be used in a

TLI service ro ut ine .

■External Interrupts

External interrupts allo w the processor to exit from

HALT low power mode . External interrupt se nsitiv-

ity is software selectable through the External In-

terrupt Control register (EICR).

External interrupt triggered on edge will be latched

and the interrupt request automatically cleared

upon entering the interrupt service routine.

If several input pins of a group connected to the

same interrupt line are selected simultaneously,

these will be logically ORed.

■Peripheral Interrupts

Usually the peripher al interrupts cause the MCU to

exit from HALT mode except those mentioned in

the “Interrupt Mapping” table. A peripheral inter-

rupt occurs when a specific flag is set in the pe-

ripheral status registers and if the corresponding

enable bit is set in the peripheral control register.

The general sequence for clearing an interrupt is

based on an access to the statu s regist er followed

by a read or write to an associated register.

Note: The clearing sequence resets the internal

latch. A pending interrupt (i.e. waiting for being

serviced) will therefore be lost if the clear se-

quence is executed.

PENDING

SOFTWARE Different

INTERRUPTS

Same

HIGHEST HARDWARE

PRIORITY SERVICED

PRIORITY

HIGHEST SOFTWARE

PRIORITY SERVICED

ST72F521, ST72521B

35/215

INTERRUPTS (Cont’d)

7.3 INTERRUPTS AND LOW POWER MODES

All interrupts allow the processor to exit the WAIT

low power mode. On the contrary, only external

and other specified interrupts allow the processor

to exit from the HALT modes (see column “Exit

from HALT” in “Interrupt Mapping” table). When

several pending interrupts are present while exit-

ing HALT mode, the first one se rviced can on ly be

an interrupt with exit from HALT mode capability

and it is selected thr oug h the same dec ision pr oc-

ess shown in Figure 19.

Note: If an interrupt, that is not able to Exit from

HALT mode, is pending with the highest priority

when exiting HALT mode, this interrupt is serviced

after the first one serviced.

7.4 CONCURRENT & NESTED MANAGEMENT

The following Figure 20 and Figure 21 show two

different inter rupt man age ment m ode s. Th e f irst is

called concurrent mode and does not allow an in-

terrupt to be int errupted, unlike the nested mode in

Figure 21. The interrupt hardware priority is given

in this order from the lowest to the highest: MAIN,

IT4, IT3, IT2, IT1, IT0, TLI. The software priority is

given for each interrupt.

Warning: A stack over flow may o ccur with out no-

tifying the software o f the failure.

Figure 20. Concurrent Interrupt Management

Figure 21. Nested Interrupt Management

MAIN

IT4

IT2

IT1

TRAP

IT1

MAIN

IT0

HARDWARE PRIORITY

SOFTWARE

3/0

11 / 10

RIM

IT2

IT1

IT4

TRAP

IT3

IT0

IT3

PRIORITY

LEVEL

USED STACK = 10 BYTES

MAIN

IT2

TRAP

MAIN

IT0

IT2

IT1

IT4

TRAP

IT3

IT0

HARDWARE PRIORITY

3/0

RIM

IT1

IT4 IT4

IT1

IT2

IT3

I1 I0

11 / 10 10

SOFTWARE

PRIORITY

LEVEL

USED STACK = 20 BYTES

ST72F521, ST72521B

36/215

INTERRUPTS (Cont’d)

7.5 INTERRUPT REGISTER DESCRIPTION

CPU CC REGISTER INTERRUPT BITS

Read/Write

Reset Value: 111x 1010 (xAh)

Bit 5, 3 = I1, I0 Software Interru p t Prio rity

These two bits indicate the current interrupt soft-

ware priority.

These two bits are set/cleared by hardware when

entering in interrupt. The loaded value is given by

the corresponding bi ts in the interrupt sof tware pri-

ority registers (ISPRx).

They can be also set/cleared by software with the

RIM, SIM, HALT, WFI, IRET and PUSH/POP in-

structions (see “Interrupt Dedicated Instruction

Set” table).

*Note: TLI, TRAP and RESET events can interrupt

a level 3 program.

INTERRUPT SOFTWARE PRIORITY REGIS-

TERS (ISPRX)

Read/Write (bit 7:4 of ISPR3 are read only)

Reset Value: 1111 1111 (FFh)

These four registers contain the interrupt software

priority of each interrupt vector.

– Each interrupt vector (except RESET and TRAP)

has corresponding bits in these registers where

its own software priority is stored. This corre-

spondance is shown in the following tabl e.

– Each I1_x and I0_x bit value in the ISPRx regis-

ters has the same meaning as the I1 and I0 bits

in the CC registe r.

– Level 0 can not be written (I1_x=1, I0_x=0) . In

this case, the previously stored value is kept. (ex-

ample: previous=CFh, write=64h, result=44h)

The TLI, RESET, and TRAP vectors have no soft-

ware priorities. When one is serviced, the I1 and I0

bits of the CC register are both set.

*Note: Bits in the ISPRx registers which corre-

spond to the TLI can be read and written but they

are not significant in the interrupt process man-

agement.

Caution: If the I1_x and I0_x bits are modified

while the interrupt x is executed the following be-

haviour has to be considered: If the interrupt x is

still pending (new interrupt or flag not cleared) and

the new software priority is higher than the previ-

ous one, the interrupt x is re-entered. Otherwise,

the software priority stays unchanged up to the

next interrupt request (after the IRET of the inter-

rupt x).

11I1 HI0 NZC

Interrupt Software Priority Level I1 I0

Level 0 (main) Low

High

Level 1 0 1

Level 2 0 0

Level 3 (= interrupt disable*) 1 1

ISPR0 I1_3 I0_3 I1_2 I0_2 I1_1 I0_1 I1_0 I0_0

ISPR1 I1_7 I0_7 I1_6 I0_6 I1_5 I0_5 I1_4 I0_4

ISPR2 I1_11 I0_11 I1_10 I0_10 I1_9 I0_9 I1_8 I0_8

ISPR3 1 1 1 1 I1_13 I0_13 I1_12 I0_12

Vector address ISPRx bits

FFFBh-FFFAh I1_0 and I0_0 bits*

FFF9h-FFF8h I1_1 and I0_1 bits

... ...

FFE1h-FFE0h I1_13 and I0_13 bits

ST72F521, ST72521B

37/215

INTERRUPTS (Cont’d)

Table 6. Dedicated Interrupt Instruction Set

Note: During the execution of an interrupt routine, the HALT, POPCC, RIM, SIM and WFI instructions change the current

software priority up to the next IRET instruction or one of the previously mentioned instructions.

Instruction New Description Function/Example I1 H I0 N Z C

HALT Entering Halt mode 1 0

IRET Interrupt routine return Pop CC, A, X, PC I1 H I0 N Z C

JRM Jump if I1:0=11 (level 3) I1:0=11 ?

JRNM Jump if I1:0<>11 I1:0<>11 ?

POP CC Pop CC from the Stack Mem => CC I1 H I0 N Z C

RIM Enable interrupt (level 0 set) Load 10 in I1:0 of CC 1 0

SIM Disable interrupt (level 3 set) Load 11 in I1:0 of CC 1 1

TRAP Software trap Software NMI 1 1

WFI Wait for interrupt 1 0

ST72F521, ST72521B

38/215

INTERRUPTS (Cont’d)

Table 7. Interrupt Mapping

Notes:

1. Exit from HALT possible when SPI is in slave mode.

2. Exit from HALT possible when PWM ART is in external clock mode.

3. In Flash devices only a RESET or MCC/RTC interrupt can be used to wake-up from Active Halt mode.

7.6 EXTERNAL INTERRUPTS

7.6.1 I/O Port Interrupt Sensitivity

The external interrupt sensitivity is controlled by

the IPA, IPB and ISxx bits of the EICR register

(Figure 22). This control allows to have up to 4 fully

independent external interrupt source sensitivities.

Each external interrupt source can be generated

on four (or five) dif ferent events on the pin:

■Falling edge

■Rising edge

■Falling and rising edge

■Falling edge and low level

■Rising edge and high leve l (only for ei0 and e i2)

To guarantee correct functionality, the sensitivity

bits in the EICR register can be modified only

when the I1 and I0 bits of the CC register are both

set to 1 (level 3). This means that inte rrupts must

be disabled before changing sensitivity.

The pending inte rrupts are cleare d by writing a dif-

ferent value in the ISx[1:0], IPA or IPB bits of the

EICR.

N° Source

Block Description Register

Label Priority

Order

Exit

from

HALT/

ACTIVE

HALT3)

Address

Vector

RESET Reset N/A yes FFFEh-FFFFh

TRAP Software interrupt no FFFCh-FFFDh

0 TLI External top level interrupt EICR yes FFFAh-FFFBh

1 MCC/RTC Ma in clock controller time base interrupt MCCSR Higher

Priority yes FFF8h-FFF9h

2 ei0 External interrupt port A3..0

N/A

yes FFF6h-FFF7h

3 ei1 External interrupt port F2..0 yes FFF4h-FFF5h

4 ei2 External interrupt port B3..0 yes FFF2h-FFF3h

5 ei3 External interrupt port B7..4 yes FFF0h-FFF1h

6 CAN CAN peripheral interrupts CANISR yes FFEEh-FFEFh

7 SPI SPI peripheral interrupts SPICSR yes1FFECh-FFEDh

8 TIMER A TIMER A peripheral interrupts TASR no FFEAh-FFEBh

9 TIMER B TIMER B peripheral interrupts TBSR no FFE8h-FFE9h

10 SCI SCI Peripheral interrupts SCISR Lower

Priority no FFE6h-FFE7h

11 AVD Auxiliary Voltage detector interrupt SICSR no FFE4h-FFE5h

12 I2C I2C Peripheral interrupts (see periph) no FFE2h-FFE3h

13 PWM ART PW M ART interrupt ARTCSR yes2FFE0h-FFE1h

ST72F521, ST72521B

39/215

INTERRUPTS (Cont’d)

Figure 22. External Interrupt Control bits

IS10 IS11

EICR

SENSITIVITY

CONTROL

PBOR.3

PBDDR.3

IPB BIT

PB3 ei2 INTERRUPT SOURCE

PORT B [3:0] INTERRUPTS

PB3

PB2

PB1

PB0

IS10 IS11

EICR

SENSITIVITY

CONTROL

PBOR.7

PBDDR.7

PB7 ei3 INTERRUPT SOURCE

PORT B [7:4] INTERRUPTS

PB7

PB6

PB5

PB4

IS20 IS21

EICR

SENSITIVITY

CONTROL

PAOR.3

PADDR.3

IPA BIT

PA3 ei0 INTERRUPT SOURCE

PORT A [3:0] INTERRUPTS

PA3

PA2

PA1

PA0

IS20 IS21

EICR

SENSITIVITY

CONTROL

PFOR.2

PFDDR.2

PF2 ei1 INTERRUPT SOURCE

PORT F [2:0] INTERRU PTS

PF2

PF1

PF0

ST72F521, ST72521B

40/215

7.7 EXTERNAL INTERRUPT CONTROL REGISTER (EICR)

Read/Write

Reset Value: 0000 0000 (00h)

Bit 7:6 = IS1[1:0] ei 2 and ei3 sensitivity

The interrupt sensitivit y, defined usi ng the IS1[ 1:0]

bits, is applied to the following external interrupts:

- ei2 (port B3..0)

- ei3 (port B7..4)

These 2 bits can be written only when I1 and I0 of

the CC register are both set to 1 (level 3).

Bit 5 = IPB Interrupt polarity for port B

This bit is used to invert the sensitivity of the port B

[3:0] external interrupts. It can be set and cleared

by software only when I 1 an d I0 of th e CC r eg ist er

are both set to 1 (level 3).

0: No sensitivity inversion

1: Sensitivity inversion

Bit 4:3 = IS2[1:0] ei 0 and ei1 sensitivity

The interrupt sensitivit y, defined usi ng the IS2[ 1:0]

bits, is applied to the following external interrupts:

- ei0 (port A3..0)

- ei1 (port F2..0)

These 2 bits can be written only when I1 and I0 of

the CC register are both set to 1 (level 3).

Bit 2 = IPA Interrupt polarity for po rt A

This bit is used to invert the sensitivity of the port A

[3:0] external interrupts. It can be set and cleared

by software only when I 1 and I 0 of the CC r egister

are both set to 1 (level 3).

0: No sensitivity inversion

1: Sensitivity inversion

Bit 1 = TLIS TLI sensitivity

This bit allows to toggle the TLI edge sensitivity. It

can be set and cleared by software only when

TLIE bit is cleared.

0: Falling edge

1: Rising edge

Bit 0 = TLIE TLI enable

This bit allows to enable or disable th e TLI capabil-

ity on the dedicated pin. It is set and cleared by

software.

0: TLI disabled

1: TLI enabled

Note: a parasitic interrupt can be generated when

clearing the TLIE bit.

IS11 IS10 IPB IS21 IS20 IPA TLIS TLIE

IS11 IS10 External Interrupt Sensitivity

IPB bit =0 IPB bit =1

00 Falling edge &

low level Rising edge

& high level

0 1 Rising edge only Falling edge only

1 0 Falling edge only Rising edge only

1 1 Rising and falling edge

IS11 IS10 External Interrupt Sensitivity

0 0 Falling edge & low level

0 1 Rising edge only

1 0 Falling edge only

1 1 Rising and falling edge

IS21 IS20 External Interrupt Sensitivity

IPA bit =0 IPA bit =1

00 Falling edge &

low level Rising edge

& high level

0 1 R ising edge only Falling edge only

1 0 Falling edge only Rising edge only

1 1 Rising and falling edge

IS21 IS20 External Interrupt Sensitivity

0 0 Falling edge & low level

0 1 Rising edge only

1 0 Falling edge only

1 1 Rising and falling edge

ST72F521, ST72521B

41/215

INTERRUPTS (Cont’d)

Table 8. Nested I nterrupts Register Map and Reset Values

Address

(Hex.) Register

Label 76543210

0024h ISPR0

Reset Valu e

ei1 ei0 MCC TLI

I1_3

1I0_3

1I1_2

1I0_2

1I1_1

1I0_1

111

0025h ISPR1

Reset Valu e

SPI CAN ei3 ei2

I1_7

1I0_7

1I1_6

1I0_6

1I1_5

1I0_5

1I1_4

1I0_4

0026h ISPR2

Reset Valu e

AVD SCI TIMER B TIMER A

I1_11

1I0_11

1I1_10

1I0_10

1I1_9

1I0_9

1I1_8

1I0_8

0027h ISPR3

Reset Value1111

PWMART I2C

I1_13

1I0_13

1I1_12

1I0_12

0028h EICR

Reset Valu e IS11

0IS10

0IPB

0IS21

0IS20

0IPA

0TLIS

0TLIE

ST72F521, ST72521B

42/215

8 POWER SAVING MODES

8.1 INTRODUCTION

To give a large measure of flexibility to the applica-

tion in terms of power consumption, four main

power saving modes are implemented in the ST7

(see Figure 23): SLOW, WAIT (SLOW WAIT), AC-

TIVE HALT and HALT.

After a RESET the normal operating mode is se-

lected by default (RUN mode). This mode drives

the device (CPU and embedded peripherals) by

means of a master clock which is based on the

main oscillator frequency divided or multiplied by 2

(fOSC2).

From RUN mode, the different power saving

modes may be selected by setting the relevant

instruction whose action depends on the oscillator

status.

Figure 23. Power Saving Mode Transitions

8.2 SLOW MODE

This mode has two targets:

– To reduce power consumption by decreasing the

internal clock in the device,

– To adapt the internal clock frequency (fCPU) to

the available supply voltage.

SLOW mode is controlled by three bits in the

MCCSR register: the SMS bit which enables or

disables Slow mode and two CPx bits which select

the internal slow frequency (fCPU).

In this mode, the master clock frequency (fOSC2)

can be divided by 2, 4, 8 or 16. The CPU and pe-

ripherals are clocked at this lower frequency

(fCPU).

Note: SL OW-WAIT m ode is activat ed wh en ente r-

ing the WAIT mode while the device is already in

SLOW mode.

Figure 24. SLOW Mode Cloc k Transitions

POWER CONSUMPTION

WAIT

SLOW

RUN

ACTIVE HALT

High

Low

SLOW WAIT

HALT

00 01

SMS

CP1:0

fCPU

NEW SLOW NORMAL RUN MODE

MCCSR

FREQUENCY

REQUEST

fOSC2

fOSC2/2 fOSC2/4 fOSC2

ST72F521, ST72521B

43/215

POWER SAVING MODES (Cont’d)

8.3 WAIT MODE

WAIT mode places the MCU in a low power con-

sumption mode by stopping the CPU.

This power saving mode is selected by calling the

‘WFI’ instruction.

All peripherals remain active. During WAIT mode,

the I[1:0] bits of the CC register are forced to ‘10’,

to enable all interrupts. All other registers and

memory remain unchanged. The MCU remains in

WAIT mode until an interrupt or RESET occurs,

whereupon the Program Counter branches to the

starting address of the interrupt or Reset service

routine.

The MCU will remain in WAIT mode until a Reset

or an Interrupt occurs, causing it to wake up.

Refer to Figure 25.

Figure 25. WAIT Mode Flow-chart

Note:

1. Before servicing an interru pt, the CC regis ter is

pushed on the stack. The I[1 :0] bit s of the CC re g-

ister are set to the current software priority level of

the interrupt routine and recovered when the CC

WFI INSTRUCTION

RESET

INTERRUPT Y

CPU

OSCILLATOR

PERIPHERALS

I[1:0] BITS

OFF

FETCH RESET VECTOR

OR SERVICE INTERRUPT

CPU

OSCILLATOR

PERIPHERALS

I[1:0] BITS

OFF

CPU

OSCILLATOR

PERIPHERALS

I[1:0] BITS

XX 1)

256 OR 4096 CPU CLOCK

CYCLE DELAY

ST72F521, ST72521B

44/215

POWER SAVING MODES (Cont’d)

8.4 ACTIVE-HALT AND HALT MODES

ACTIVE-HALT and HALT modes are the two low-

est power consumption modes of the MCU. They

are both entered by executing the ‘HALT’ instruc-

tion. The decision to enter either in ACTIVE-HALT

or HALT mode is given by the MCC/RTC interrupt

enable flag (OIE bit in MCCSR register).

8.4.1 ACTIVE-HALT MODE

ACTIVE-HALT mode is the lowest power con-

sumption mode of the MCU with a real time clock

available. It is entered by executing the ‘HALT’ in-

struction when the OIE bit of the Main Clock Con-

troller Status register (MCCSR) is set (see section

10.2 on page 58 for more details on the MCCSR

The MCU can exit ACT IVE-HAL T mo de on recep -

tion of an MCC/RTC interrupt or a RESET. In ROM

devices, external interrupts can be used to wake-

up the MCU. When exiting ACTIVE-HALT mode

by means of an interrupt, no 256 or 4096 CPU cy-

cle delay occurs. The CPU resumes operation by

servicing the inter rupt or b y fetc hing th e reset ve c-

tor which woke it up (see Figure 27).

When entering ACTIVE-HALT mode, the I[1:0] bits

in the CC register are forced to ‘10b’ to enable in-

terrupts. Therefore, if an interrupt is pending, the

MCU wakes up immediately.

In ACTIVE-HALT mode, only the main oscillator

and its associated counter (MCC/RTC) are run-

ning to keep a wa ke-up time base. All other periph-

erals are not clocked except those which get their

clock supply from another clock generator (such

as external or auxiliary oscillator).

The safeguard against staying locked in ACTIVE-

HALT mode is provided by the oscillator interrupt.

Note: As soon as the interrupt capability of one of

the oscillators is selected (MCCSR.OIE bit set),

entering ACTIVE- HALT mode wh ile the Watch dog

is active does no t generate a RESET.

This means that the device cannot spend more

than a defined delay in this power saving mode.

CAUTION: When exiting ACTIVE-HALT mode fol-

lowing an MCC/RTC interrupt, OIE bit of MCC SR

the interrupt occurs (tDELAY = 256 or 4096 tCPU de-

lay depending on op tion byt e). Othe rwise, the ST7

enters HALT mode for the remaining tDELAY peri-

od.

Figure 26. ACTIVE-HALT Timing Ove rview

Figure 27. ACTIVE-HALT Mode Flow-chart

Notes:

1. This delay occurs only if the MCU exits ACTIVE-

HALT mode by means of a RESET.

2. Peripheral clocked with an external clock source

can still be active.

3. Before servicing an interru pt, the CC regis ter is

pushed on the stack. The I[1 :0] bit s of the CC re g-

ister are set to the current software priority level of

the interrupt routine and restored when the CC

4. In flash devices only the MCC/RTC interrupt can

exit the MCU from ACTIVE-HALT mode.

MCCSR

OIE bit Power Saving Mode entered when HALT

instruction is executed

0 HALT mode

1 ACTIVE-HALT mode

HALTRUN RUN

256 OR 4096 CPU

CYCLE DELAY 1)

RESET

INTERRUPT

HALT

INSTRUCTION FETCH

VECTOR

ACTIVE

[MCCSR.OIE=1]

HALT INSTRUCTION

RESET

CPU

OSCILLATOR

PERIPHERALS 2)

I[1:0] BITS

OFF

FETCH RESET VECTOR

OR SERVICE INTERRUPT

CPU

OSCILLATOR

PERIPHERALS

I[1:0] BITS

OFF

XX 3)

CPU

OSCILLATOR

PERIPHERALS

I[1:0] BITS

XX 3)

256OR4096CPUCLOCK

CYCLE DELAY

(MCCSR.OIE=1)

INTERRUPT 4)

ST72F521, ST72521B

45/215

POWER SAVING MODES (Cont’d)

8.4.2 HALT MODE

The HALT mode is the lowe st po we r co ns um p tio n

mode of the MCU. It is entered by executing the

‘HALT’ instruction when the OIE bit of the Main

Clock Controller Status register (MCCSR) is

cleared (see section 10.2 on page 58 for more de-

tails on the MCCSR register).

The MCU can exit HALT mode on reception of ei-

ther a specific interrupt (see Table 7, “Interrupt

Mapping,” on page 38) or a RESET. When exiting

HALT mode by means of a RESET o r an interrupt,

the oscillator is immediately turned on and the 256

or 4096 CPU cycle delay is used to stabilize the

oscillator. After the start up delay, the CPU

resumes operation by servicing the interrupt or by

fetching the reset ve ctor which woke it up (see Fig-

ure 29).

When entering HALT mode, the I[1:0] bits in the

CC register ar e fo rced to ‘10b’to e nable interrup ts.

Therefore, if an interrupt is pending, the MCU

wakes up immediately.

In HALT mode, the main oscillator is turned off

causing all internal processing to be stopped, in-

cluding the operation of the on-chip peripherals.

All peripherals are not clocked except the ones

which get their clock supply from another clock

generator (such as an external or auxiliary oscilla-

tor).

The compatibility of Watchdog operation with

HALT mode is configured by the “WDGHALT” op-

tion bit of the option byte. The HALT instruction

when executed while the Watchdog system is en-

abled, can generate a Watchdog RESET (see sec-

tion 14.1 on page 201 for more details).

Figure 28. HALT Timing Overview

Figure 29. HALT Mode Flow-chart

Notes:

1. WDGHALT is an option bit. See option byte sec-

tion for more details.

2. Peripheral clocked with an external clock source

can still be active.

3. Only some specific interrupts can exit the MCU

from HALT mode (such as external interrupt). Re-

fer to Tab le 7, “Inter rupt M apping,” o n pag e 38 for

more details.

4. Before servicing an interru pt, the CC regis ter is

pushed on the stack. The I[1 :0] bit s of the CC re g-

ister are set to the current software priority level of

the interrupt routine and recovered when the CC

HALTRUN RUN

256 OR 4096 CPU

CYCLE DELAY

RESET

INTERRUPT

HALT

INSTRUCTION FETCH

VECTOR

[MCCSR.OIE=0]

HALT INSTRUCTION

RESET

INTERRUPT 3) Y

CPU

OSCILLATOR

PERIPHERALS 2)

I[1:0] BITS

OFF

FETCH RESET VECTOR

OR SERVICE INTERRUPT

CPU

OSCILLATOR

PERIPHERALS

I[1:0] BITS

OFF

XX 4)

CPU

OSCILLATOR

PERIPHERALS

I[1:0] BITS

XX 4)

256 OR 4096 CPU CLOCK

DELAY

WATCHDOG

ENABLE

DISABLE

WDGHALT 1) 0

WATCHDOG

RESET

(MCCSR.OIE=0)

CYCLE

ST72F521, ST72521B

46/215

POWER SAVING MODES (Cont’d)

8.4.2.1 Halt Mode Recommendations

– Make sure that an external event is available to

wake up the microcontroller from Halt mode.

– When using an external interrupt to wake up the

microcontroller, reinitialize the corresponding I/O

as “Input Pull-up with Inter rupt” before executing

the HALT instruction. Th e main reason for this is

that the I/O may be wrongly configured due to ex-

ternal interferen ce or by an unforeseen logical

condition.

– For the same reason, reinitialize the level sensi-

tiveness of each external interrupt as a precau-

tionary measure.

– The opcode for the HALT instru ction is 0x8E. To

avoid an unexpected HALT instr uction due to a

program counter failure, it is advised to clear all

occurrences of the data value 0x8E from memo-

ry. For example, avoid defining a constant in

ROM with the value 0x8E.

– As the HALT instruction clears the interrupt mask

in the CC register to allow interrupts, the user

may choose to clear all pending interr upt bits be-

fore executing th e HALT instruction. This avo ids

entering other peripheral interrupt routines after

executing the external interrupt ro utine corre-

sponding to t he wake-up event (reset or exter nal

interrupt).

Related Documentation

AN 980: ST7 Keypad Decoding Techniques, Im-

plementing Wake-Up on Keystroke

AN1014: How to Minimize the ST7 Power Con-

sumption

AN1605: Using an active RC to wakeup the

ST7LITE0 from power saving mode

ST72F521, ST72521B

47/215

9 I/O PORTS

9.1 INTRODUCTION

The I/O ports offer different functional modes:

– transfer of data through digital inputs and outputs

and for specific pins:

– external interrupt generation

– alternate signal input/output for the on-chip pe-

ripherals.

An I/O port contains up to 8 pins. Each pin can be

progr ammed independently as digital input ( with or

without interrupt gener ation) or digital output.

9.2 FUNCTIONAL DESCRIPTION

Each port has 2 main registers:

– Data Register (DR)

– Data Direction Register (DDR)

and one optional register:

– Option Register (OR)

Each I/O pin may be pr ogrammed u sing the corr e-

sponding register bits in the DDR and OR regis-

ters: bit X corresponding to pin X of the port. The

same correspondence is used for the DR register.

The following description takes into account the

OR register, (for specific ports which do not pro-

vide this regis ter refe r to the I/ O Port Imp lementa -

tion section). The generic I/O block diagram is

shown in Figure 30

9.2.1 Input Modes

The input configuration is selected by clearing the

corresponding DDR reg ister bit.

In this case, reading the DR register returns the

digital value applied to the exter nal I/O pin.

Different input mode s ca n be select ed by soft ware

through the OR register.

Notes:

1. Writing the DR register modifies the latch value

but does not affect the pin status.

2. When sw itching from input to output mode, the

DR register has to be written first to drive the cor-

rect level on the pin as soon as the port is config-

ured as an output.

3. Do not use read/modify/write instructions (BSET

or BRES) to modify the DR re gist er

External interrupt function

When an I/O is configured as Input with Interrupt,

an event on this I/O ca n generate an external inter-

rupt request to the CPU.

Each pin can independently generate an interrupt

request. The interrupt sensitivity is independently

programmable using the sensitivity bits in the

EICR register.

Each external interrupt vector is linked to a dedi-

cated group of I/O port p ins (see pinout descr iption

and interrupt section). If several input pins are se-

lected simultaneously as interrupt sources, these

are first detected a ccording to the sensitivity bits in

the EICR register and then logically ORed.

The external interrupts are hardware interrupts,

which means that the request la tch (not accessible

directly by the applicati on) is automati cally cleared

when the corresponding interrupt vector is

fetched. To clear an unwanted pending interrupt

by software, the sensitivity bits in the EICR register

must be modified.

9.2.2 Output Modes

The output configuration is selected by setting the

corresponding DDR register bit. In this case, writ-

ing the DR register applies this digital value to the

I/O pin through the latch. Then reading the DR reg-

ister returns the previously st ored value.

Two different output modes can be selected by

software through the OR register: Output push-pull

and open-drain.

DR register value and output pin status:

9.2.3 Alternate Functions

When an on-chip peripheral is configured to use a

pin, the alternate function is automatically select-

ed. This alternate function takes priority over the

standard I/O programming.

When the signal is comin g from an on- chip periph-

eral, the I/O pin is automatically configured in out-

put mode (push-pull or open drain according to the

peripheral).

When the signal is going to an on-chip peripheral,

the I/O pin must be configured in input mode. In

this case, the pin state is also digi tally readab le by

addressing th e DR re gis te r.

Note: Input pull-up configuration can cause unex-

pected value at the input of the alternate peripheral

input. When an on- chip peripheral use a pin as in-

put and output, this pin has to be configured in in-

put floating mode.

DR Push-pull Open-drain

SS Vss

DD Floating

ST72F521, ST72521B

48/215

I/O PORTS (Cont’d)

Figure 30. I/O Port General Block Diagram

Table 9. I/O Port Mode Options

Legend: NI - not implemented

Off - implemented not activated

On - implemented and activated

Note: The diode to VDD is not implemented in th e

true open drain pads. A local protection between

the pad and VSS is implemented to protect t he de-

vice against positive stress.

Configuration Mode Pull-Up P-Buffer Diodes

to VDD to VSS

Input Floating with/without Interrupt Off Off On On

Pull-up with/without Interrupt On

Output Push-pull Off On

Open Drain (logic level) Off

True Open Drain NI NI NI (see note)

DDR

DATA BUS

PAD

VDD

ALTERNATE

ENABLE

ALTERNATE

OUTPUT 1

OR SEL

DDR SEL

DR SEL

PULL-UP

CONDITION

P-BUFFER

(see table below)

N-BUFFER

PULL-UP

(see table below)

ANALOG

INPUT

If implemented

ALTERNATE

INPUT

VDD

DIODES

(see table below)

EXTERNAL

SOURCE (eix)

INTERRUPT

CMOS

SCHMITT

TRIGGER

ACCESS

ST72F521, ST72521B

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I/O PORTS (Cont’d)

Table 10. I/O Port Configurations

Notes:

1. When the I/O po rt is in input configuration and t he associated alternate function is en abled as an output,

reading the DR register will read the alternate function output status.

2. When the I/O po rt is in output configuration and the associated alternate f unction is enabled as an input,

the alternate function reads the pin status given by the DR register content.

Hardware Configuration

INPUT 1)

OPEN-DRAIN OUTPUT 2)

PUSH-PULL OUTPUT 2)

CONDITION

PAD

VDD

RPU

EXTERNAL INTERRUPT

DATA BUS

PULL-UP

INTERRUPT

DR REGISTER ACCESS

SOURCE (eix)

CONDITION

ALTERNATE INPUT

NOT IMPLEMENTED IN

TRUE OPEN DRAIN

I/O PORTS

ANALOG INPUT

PAD

RPU

DATA BUS

DR REGISTER ACCESS

R/W

VDD

ALTERNATEALTERNATE

ENABLE OUTPUT

NOT IMPLEMENTED IN

TRUE OPEN DRAIN

I/O PORTS

PAD

RPU

DATA BUS

DR REGISTER ACCESS

R/W

VDD

ALTERNATEALTERNATE

ENABLE OUTPUT

NOT IMPLEMENTED IN

TRUE OPEN DRAIN

I/O PORTS

ST72F521, ST72521B

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I/O PORTS (Cont’d)

CAUTION: The alternate function must not be ac-

tivated as long as the pin is configured as input

with interrupt, in order to avoid generating spurious

interrupts.

Analog alternate function

When the pin is used as an ADC input, the I/O

must be configured as floating input. The analog

multiplexer (controlled by the ADC registers)

switches the analog voltage pr esent on th e select-

ed pin to the common an alog rail which is connect-

ed to the ADC input.

It is recommended not to change the voltage level

or loading on any port pin while conversion is in

progress. Furthermore it is recommended not to

have clocking pins located close to a selected an-

alog pin.

WARNING: The analog input voltage level must

be within the limits stated in the absolute maxi-

mum ratings.

9.3 I/O PORT IMPLEMENTATION

The hardware implementation o n each I/O port de-

pends on the settings in the DDR and OR registers

and specific feature of the I/O port such as ADC In-

put or true open drain.

Switching these I/O ports from one state to anoth-

er should be done in a sequence that prevents un-

wanted side effects. Recommended safe transi-

tions are illustrated in Figure 31 Other transitions

are potentially risky and should be avoided, since

they are likely to present unwanted side-effects

such as spurious interrupt generation.

Figure 31. Interrupt I/O Port State Transitions

9.4 LOW POWER MODES

9.5 INTERRUPTS

The external interrupt event generates an interrupt

if the corresponding configuration is selected with

DDR and OR registers and the interrupt mask in

the CC register is not active (RIM instruction).

Mode Description

WAIT No effect on I/O ports. External interrupts

cause the device to exit from WAIT mode.

HALT No effect on I/O ports. External interrupts

cause the device to exit from HALT mode.

Interrupt Event Event

Flag

Enable

Control

Bit

Exit

from

Wait

Exit

from

Halt

External interrupt on

selected external

event -DDRx

ORx Yes Yes

floating/pull-up

interrupt

INPUT

floating

(reset st ate)

INPUT

open-drain

OUTPUT

push-pull

OUTPUT

XX = DDR, OR

ST72F521, ST72521B

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I/O PORTS (Cont’d )

9.5.1 I/O Port Implementation

The I/O port register configurations are summa-

rised as follows.

Standard Ports

PA5:4, PC7:0, PD7:0, PE7:34,

PE1:0, PF7:3, PG7:0, PH7:0

Interrupt P o rts

PA2:0, PB6:5, PB4, PB2:0, PF1:0 (with pull-up)

PA3, PB7, PB3, PF2 (without pull-up)

True Open Drain Ports

PA7:6

Pull-up Inpu t Port (CANTX requirement)

PE2

Table 11. Port Configuration

* Note: when the CANTX alternate function is selected the I/O port operates in output push-pull mode.

MODE DDR OR

floating input 0 0

pull-up input 0 1

open drain output 1 0

push-pull output 1 1

MODE DDR OR

floating input 0 0

pull-up interrupt input 0 1

open drain output 1 0

push-pull output 1 1

MODE DDR OR

floating input 0 0

floating interrupt input 0 1

open drain output 1 0

push-pull output 1 1

MODE DDR

floating input 0

open drain (high sink ports) 1

MODE

pull-up input

Port Pin name Input Output

OR = 0 OR = 1 OR = 0 OR = 1

Port A

PA7:6 floating true open-drain

PA5:4 floating pull-up open drain push-pull

PA3 floating floating interrupt open drain push-pull

PA2:0 floating pull-up interrupt open drain push-pull

Port B PB7, PB3 floating floating interrupt open drain push-pull

PB6:5, PB4,

PB2:0 floating pull-up interrupt open drain push-pull

Port C PC7:0 floating pull-up open drain push-pull

Port D PD7:0 floating pull-up open drain push-pull

Port E PE7:3, PE1:0 floating pull-up open drain push-pull

PE2 pull-up input only *

Port F PF7:3 floating pull-up open drain push-pull

PF2 floating floating interrupt open drain push-pull

PF1:0 floating pull-up interrupt open drain push-pull

Port G PG7:0 floating pull-up open drain push-pull

Port H PH7:0 floating pull-up open drain push-pull

ST72F521, ST72521B

52/215

I/O PORTS (Cont’d)

Table 12. I/O Port Register Map and Reset Values

Related Doc u mentation

AN 970: SPI Communication between ST7 and

EEPROM

AN1045: S/W implementation of I2C bus master

AN1048: Software LCD driver

Address

(Hex.) Register

Label 76543210

Reset Value

of all I/O port registers 00000000

0000h PADR MSB LSB0001h PADDR

0002h PAOR

0003h PBDR MSB LSB0004h PBDDR

0005h PBOR

0006h PCDR MSB LSB0007h PCDDR

0008h PCOR

0009h PDDR MSB LSB000Ah PDDDR

000Bh PDOR

000Ch PEDR MSB LSB000Dh PEDDR

000Eh PEOR

000Fh PFDR MSB LSB0010h PFDDR

0011h PFOR

0012h PGDR MSB LSB0013h PGDDR

0014h PGOR

0015h PHDR MSB LSB0016h PHDDR

0017h PHOR

ST72F521, ST72521B

53/215

10 ON-CHIP PERIPHERALS

10.1 WATCHDOG TIMER (WDG)

10.1.1 Introduction

The Watchdog timer is used to detect the occur-

rence of a software f ault , usually ge ner at ed by e x-

ternal interference or by unforeseen logical condi-

tions, which causes the application program to

abandon its normal sequence. The Watchdog cir-

cuit generates an MCU reset on expiry of a pro-

grammed time period , unless the program refresh-

es the counter’s contents before the T6 bit be-

comes cleared.

10.1.2 Main Features

■Programmable free-running downcounter

■Programmable reset

■Reset (if watchdog activated) when the T6 bit

reaches zero

■Optional reset on HALT instruction

(configurable by optio n byte)

■Hardware Watchdog selectable by option byte

10.1.3 Functional Description

The counter value stored in the Watchdog Control

every 16384 fOSC2 cycles (approx.), and the

length of the timeout period can be programmed

by the user in 64 increments.

If the watchdog is activated (the WDGA bit is set)

and when the 7-bit timer (bits T[6:0]) rolls over

from 40h to 3Fh (T6 becomes cleared), it initiates

a reset cycle pulling low the reset pin for typically

500ns.

The application program must write in the

WDGCR register at regular intervals during normal

operation to prevent an MCU reset. This down-

counter is free-running: it counts down even if the

watchdog is disabled. Th e value to be stored in the

WDGCR register must be between FFh and C0h:

– The WDGA bit is set (watchdog enabled)

– The T6 bit is set to preve nt g enera tin g an im me-

diate reset

– The T[5:0] bits contain the number of increments

which represents the time delay before the

watchdog produces a reset (see Figure 33. Ap-

proximate Timeout Duration). The timing varies

between a minim um an d a ma xim u m valu e du e

to the unknown st atus of the prescaler when writ-

ing to the WDGCR register (see Figure 34).

Following a reset, the watchdog is disabled. Once

activated it cannot be disabled, except by a reset.

The T6 bit can be used to generate a software re-

set (the WDGA bit is set a nd the T6 bit is cleared) .

If the watchdog is activated, the HALT instruction

will generate a Reset.

Figure 32. Watchdog Block Diagram

RESET

WDGA

6-BIT DOWNCOUNTER (CNT)

fOSC2

T6 T0

WDG PRESCALER

WATCHDOG CONTROL REGISTER (WDGCR)

DIV 4

12-BIT MCC

RTC COUNTER

MSB LSB

DIV 64

MCC/RTC

TB[1:0] bits

(MCCSR

ST72F521, ST72521B

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WATCHDOG TIMER (Cont’d)

10.1.4 How to Program the Watchdog Timeout

Figure 33 shows the linear relationship between

the 6-bit value to be loaded in the Watchdog Coun-

ter (CNT) and the r esulting timeou t duration in mil-

liseconds. This can be used for a quick calculation

without taking the timing variations into account. If

more precision is need ed, use the f ormulae in Fig-

ure 34.

Caution: When writing to the WDGCR registe r, al-

ways write 1 in the T6 bit to avoid generating an

immediate reset.

Figure 33. Approximate Timeout Duration

CNT Value (hex.)

Watchdog timeout (ms) @ 8 MHz. fOSC2

128

1.5 65

503418 82 98 114

ST72F521, ST72521B

55/215

WATCHDOG TIMER (Cont’d)

Figure 34. Exact Timeout Duration (tmin and tmax)

WHERE:

tmin0 = (LSB + 128) x 64 x tOSC2

tmax0 = 16384 x tOSC2

tOSC2 = 125ns if fOSC2=8 MHz

CNT = Value of T[5:0] bits in the WDGCR register (6 bits)

MSB and LSB are values from the table below depending on the timebase selected by the TB[1:0] bits

in the MCCSR register

To calculate the minimum Watchdog Timeout (tmin):

IF THEN

ELSE

To calculate the maximum Watchdog Timeout (tmax):

IF THEN

ELSE

Note: In the above formulae, divisio n results must be rounded down to the next integer value.

Example:

With 2ms timeout selected in MCCSR register

TB1 Bit

(MCCSR Reg.) TB0 Bit

(MCCSR Reg.) Selected MCCSR

Timebase MSB LSB

0 0 2ms 4 59

0 1 4ms 8 53

1 0 10ms 20 35

1 1 25ms 49 54

Value of T[5:0] Bits in

WDGCR Register (Hex.)

Min. Watchdog

Timeout (ms)

tmin

Max. Watchdog

Timeout (ms)

tmax

00 1.496 2.048

3F 128 128.552

CNT MSB

-------------

<tmin tmin0 16384 CNT tosc2

××+

tmin tmin0 16384 CNT 4CNT

MSB

-----------------

–

⎝⎠

⎛⎞

×192 LSB+()64 4CNT

MSB

-----------------

××

+tosc2

×+=

CNT MSB

-------------

≤tmax tmax0 16384 CNT tosc2

××+=

tmax tmax0 16384 CNT 4CNT

MSB

-----------------

–

⎝⎠

⎛⎞

×192 LSB+()64 4CNT

MSB

-----------------

××

+tosc2

×+=

ST72F521, ST72521B

56/215

WATCHDOG TIMER (Cont’d)

10.1.5 Low Po wer Modes

10.1.6 Hardware Watchdog Option

If Hardware Watchdog is selected by option byte,

the watchdog is always active and the WDGA bit in

the WDGCR is not used. Refer to the Option Byte

description.

10.1.7 Using Halt Mode with the WDG

(WDGHALT option)

The following recommendation applies if Halt

mode is used when the watchdo g is enabled.

– Before executing the HALT instruction, refresh

the WDG counter , to avoid an unexp ected WDG

reset immediately after waking up the microcon-

troller.

10.1.8 Interrup ts

None.

10.1.9 Register Description

CONTROL REGISTER (WDGCR)

Read/Write

Reset Value: 0111 1111 (7Fh)

Bit 7 = WDGA Activation bit.

This bit is set by software and only cleared by

hardware after a reset. When WDGA = 1, the

watchdog can generate a reset.

0: Watchdog disabled

1: Watchdog enabled

Note: This bit is not used if the hardware watch-

dog option is enabled by op tion byte.

Bit 6:0 = T[6:0] 7-bit counter (MSB to LSB).

These bits contain the value of the watchdog

counter. It is decremented every 16384 fOSC2 cy-

cles (approx.). A reset is produced when it rolls

over from 40h to 3Fh (T6 becomes cleared).

Mode Description

SLOW No effect on Watchdog.

WAIT No effect on Watchdog.

HALT

OIE bit in

MCCSR

WDGHALT bit

in Option

Byte

No Watchdog reset is generated. The MCU enters Halt mode. The Watch-

dog counter is decremented once and then stops counting and is no longer

able to generate a watchdog reset until the MCU receives an external inter-

rupt or a reset.

If an external interrupt is received, the Watchdog restarts counting after 256

or 4096 CPU clocks. If a reset is generated, the Watchdog is disabled (reset

state) unless Hardware Watchdog is selected by option byte. For applica-

tion recommendations see Section 10.1.7 below.

0 1 A reset is generated.

No reset is generated. The MCU enters Active Halt mode. The Watchdog

counter is not decremented. It stop counting. When the MCU receives an

oscillator interrupt or external interrupt, the Watchdog restarts counting im-

mediately. When the MCU receives a reset the Watchdog restarts counting

after 256 or 4096 CPU clocks.

WDGA T6 T5 T4 T3 T2 T1 T0

ST72F521, ST72521B

57/215

Table 13. Watchdog Timer Register Map and Reset Values

Address

(Hex.) Register

Label 76543210

002Ah WDGCR

Reset Valu e WDGA

0T6

1T5

1T4

1T3

1T2

1T1

1T0

ST72F521, ST72521B

58/215

10.2 MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK AND BEEPER (MCC/RTC)

The Main Clock Controller consists of three differ-

ent functions:

■a programm ab le CPU clo ck pr es ca ler

■a clock-out signal to supply external devices

■a real time clock timer with interrupt capability

Each function can be used independently and si-

multaneously.

10.2.1 Programmable CPU Clock Prescaler

The programmable CPU clock prescaler supplies

the clock for the ST 7 CPU and its internal periph-

erals. It manages SLO W power saving mode (See

Section 8.2 SLOW MODE for more details).

The prescaler selects the fCPU main clock fre quen-

cy and is controlled by three bits in the MCCSR

10.2.2 Clock- out Capability

The clock-out capability is an alternate function of

an I/O port pin that outputs a fCPU clock to drive

external devices. It is controlled by the MCO bit in

the MCCSR register.

CAUTION: When selected, the clock out pin sus-

pends the clock during ACTIVE-HALT mode.

10.2.3 Real Time Clock Timer (RTC)

The counter of the real time clock timer allows an

interrupt to be generated based on an accurate

real time clock. Four different time bases depend-

ing directly on fOSC2 are available. The whole

functionality is controlled by four bits of the MCC-

SR register: TB[1:0], OIE and OIF.

When the RTC interrupt is enabled (OIE bit set),

the ST7 enters ACTIVE-HALT mode when the

HALT instruction is executed. See Se ction 8.4 AC-

TIVE-HALT AND HALT MODES for more details.

10.2.4 Beeper

The beep function is controlled by the MCCBCR

on the BEEP pin (I/O port alternate function).

Figure 35. Main Clock Controller (MCC/RTC) Block Diagram

DIV 2, 4, 8, 16

MCC/RTC INTERRUPT

SMSCP1 CP0 TB1 TB0 OIE OIF

CPU CLOCK

MCCSR

12-BIT MCC RTC

COUNTER

TO CPU AND

PERIPHERALS

fOSC2 fCPU

MCO

BC1 BC0

MCCBCR

BEEP

SELECTION

BEEP SIGNAL

WATCHDOG

TIMER

DIV 64

ST72F521, ST72521B

59/215

MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK (Cont’d)

10.2.5 Low Power Modes

10.2.6 Interrupts

The MCC/RTC interrupt event generates an inter-

rupt if the OIE bit of th e MCCSR register is set and

the interrupt mask in the CC register is not active

(RIM instruction).

Note:

The MCC/RTC interrupt wakes up the MCU from

ACTIVE-HALT mode, not from HALT mode.

10.2.7 Register Description

MCC CONTROL/STATUS REGISTER (MCCSR)

Read/Write

Reset Value: 0000 0000 (00h)

Bit 7 = MCO Main clock out selection

This bit enables the MCO alter nate function o n the

PF0 I/O port. It is set and cleared by software.

0: MCO alternate function disabled (I/O pin free for

general-purpose I/O)

1: MCO alternate function enabled (fCPU on I/O

port)

Note: To reduce power consumption, the MCO

function is not active in ACTIVE-HALT mode.

Bit 6:5 = CP[1:0] CPU clock prescaler

These bits select the CPU clock prescaler which is

applied in the different slow modes. Their action is

conditioned by the setting of the SMS bit. These

two bits are set and cleared by software

Bit 4 = SMS Slow mode select

This bit is set and cleared by software.

0: Normal mode. fCPU = fOSC2

1: Slow mode. fCPU is given by CP1, CP0

See Section 8.2 SLOW MODE and Section 10.2

MAIN CLOCK CONTROLLER WITH REAL TIME

CLOCK AND BEEPER (MCC/RTC) for more de-

tails.

Bit 3:2 = TB[1:0] Time base control

These bits select the programmable divider time

base. They are set and cleared by software.

A modification of the time base is taken into ac-

count at the end of the current period (previously

set) to avoid an unwanted time shift. This allows to

use this time base as a real time clock.

Bit 1 = OIE Oscillator interrupt enable

This bit set and cleared by software.

0: Oscillator interrupt disabled

1: Oscillator interrupt enabled

This interrupt can be used to exit from ACTIVE-

HALT mode.

When this bit is set, calling the ST7 software HALT

instruction enters the ACTIVE-HALT power saving

mode.

Mode Description

WAIT No effect on MCC/RTC peripheral.

MCC/RTC interrupt cause the device to exit

from WAIT mode.

ACTIVE-

HALT

No effect on MCC/RTC counter (OIE bit is

set), the registers are frozen.

MCC/RTC interrupt cause the device to exit

from ACTIVE-HALT mode.

HALT

MCC/RTC counter and registers are frozen.

MCC/RTC operation resumes when the

MCU is woken up by an interrupt with “exit

from HALT” capability.

Interrupt Event Event

Flag

Enable

Control

Bit

Exit

from

Wait

Exit

from

Halt

Time base overflow

event OIF OIE Yes No 1)

MCO CP1 CP0 SMS TB1 TB0 OIE OIF

fCPU in SLOW mode CP1 CP0

fOSC2 / 2 0 0

fOSC2 / 4 0 1

fOSC2 / 8 1 0

fOSC2 / 16 1 1

Counter

Prescaler

Time Base TB1 TB0

fOSC2 =4MHz fOSC2=8MHz

16000 4ms 2ms 0 0

32000 8ms 4ms 0 1

80000 20ms 10ms 1 0

200000 50ms 25ms 1 1

ST72F521, ST72521B

60/215

MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK (Cont’d)

Bit 0 = OIF Oscillator interrupt flag

This bit is set by hardware and clear ed by software

reading the MCCSR regi ster. It in dicates when set

that the main oscillator has reached the selected

elapsed time (TB1 :0).

0: Timeout no t re ached

1: Timeout reached

CAUTION: The BRES and BSET instructions

must not be used on the MCCSR register to avoid

unintentionally clearing the OIF bit.

MCC BEEP CONTROL REGISTER (MCCBCR)

Read/Write

Reset Value: 00 0 0 00 00 (0 0h )

Bit 7:2 = Reserved, must be kept cleared.

Bit 1:0 = BC[1:0] Beep control

These 2 bits select the PF1 pin beep capability.

The beep output signal is available in ACTIVE-

HALT mode but has to be disabled to reduce the

consumption.

Table 14. Main Clock Controller Register Map and Rese t Values

000000BC1BC0

BC1 BC0 Beep mode with fOSC2=8MHz

00 Off

01 ~2-KHz Output

Beep signal

~50% duty cycle

10 ~1-KHz

1 1 ~500-Hz

Address

(Hex.) Register

Label 76543210

002Bh SICSR

Reset Valu e AVDS

0AVDIE

0AVDF

0LVDRF

x000

WDGRF

002Ch MCCSR

Reset Valu e MCO

0CP1

0CP0

0SMS

0TB1

0TB0

0OIE

0OIF

002Dh MCCBCR

Reset Value000000

BC1

0BC0

ST72F521, ST72521B

61/215

10.3 PWM AUTO-RELOAD TIMER (ART)

10.3.1 Introduction

The Pulse Width Modulated Auto-Reload Timer

on-chip peripheral consists of an 8-bit auto reload

counter with compare/capture capabilities and of a

7-bit prescaler clock source.

These resources allow five possible operating

modes:

– Generation of up to 4 independe nt PWM sign als

– Output compare and Time base inter rupt

– Up to two input capture functions

– Exte rn al ev en t de te cto r

– Up to two external interrupt sources

The three first modes can be used together with a

single counter frequency.

The timer can be used to wake up the MCU from

WAIT and HALT modes.

Figure 36. PWM Auto-Reload Timer Block Diagram

OVF INTERRUPT

EXCL CC2 CC1 CC0 TCE FCRL OIE OVF ARTCSR

fINPUT

PWMx PORT

FUNCTION

ALTERNATE

OCRx

COMPARE

PROGRAMMABLE

PRESCALER

8-BIT COUNTER

(CAR REGISTER)

ARR

ICRx

LOAD

OPx

POLARITY

CONTROL

OEx

PWMCR

MUX

fCPU

DCRx

LOAD

fCOUNTER

ARTCLK fEXT

ARTICx

ICFxICSx ICCSR

LOAD

ICx INTERRUPT

ICIEx

INPUT CAPTURE

CONTROL

ST72F521, ST72521B

62/215

PWM AUTO-RELOAD TIMER (Cont’d)

10.3.2 Functional Description

Counter

The free runni ng 8- bit counte r is fe d by the out put

of the prescaler, and is incremented on every ris-

ing edge of the clock signal.

It is possible to read or write the contents of the

counter on the fly by re ading or writing the Counter

Access register (ARTCAR).

When a counter overflow occurs, the counter is

automatically reloaded with the contents of the

ARTARR register (the prescaler is not affected).

Counter clock and prescaler

The counter clock frequency is given by:

fCOUNTER = fINPUT / 2CC[2:0]

The timer counter’s input clock (fINPUT) feeds the

7-bit programmable prescaler, which selects one

of the 8 available taps of th e pr es ca ler , as de fin e d

by CC[2:0] bits in the Control/Status Register

(ARTCSR). Thus the division factor of the prescal-

er can be set to 2n (where n = 0, 1,..7).

This fINPUT frequency source is selected through

the EXCL bit of the ARTCSR register and can be

either the fCPU or an external input frequency fEXT.

The clock input to the counter is enabled by the

TCE (Timer Counter Enable) bit in the ARTCSR

stopped and the prescaler and counter contents

are frozen. When TCE is set, the counter runs at

the rate of the selected clock source.

Counter and Prescaler Initializat ion

After RESET, the counter and the prescaler are

cleared and fINPUT = fCPU.

The counter can be initialized by:

– Writing to the ARTARR register and then set ting

the FCRL (Force Counter Re-Load) and the TCE

(Timer Counter Enable) bits in the ARTCSR reg-

ister.

– Writing to the ARTCAR counter access register,

In both cases the 7-bit prescaler is also cleared,

whereupon counting will start from a known value.

Direct access to the prescaler is not possible.

Output compare control

The timer compare funct ion is based on four differ-

ent comparisons with the counter (one for each

PWMx output). Each comparison is made be-

tween the counter value and an output compare

be accessed directly, it is loaded from the du ty cy-

cle register (PWMDCRx) at each overflow of the

counter.

This double buffering method avoids glitch gener-

ation when changing the duty cycle on the fly.

Figure 37. Output compare control

COUNTER FDh FEh FFh FDh FEh FFh FDh FEh

ARTARR=FDh

fCOUNTER

OCRx

PWMDCRx FDh FEh

FDh FEh

FFh

PWMx

ST72F521, ST72521B

63/215

PWM AUTO-RELOAD TIMER (Cont’d)

Independent PWM signal generation

This mode allows up to four Pulse Width Modulat-

ed signals to be generated on the PWMx output

pins with minimum core processing overhead.

This function is stopped during HALT mode.

Each PWMx output signal can be selected inde-

pendently using the corresponding OEx bit in the

PWM Control register (PWMCR). When this bit is

set, the corr esponding I/O pin is configured as out-

put push-pull alternate function.

The PWM signals all have the same frequency

which is controlled by the counter period and the

ARTARR register value.

fPWM = fCOUNTER / (256 - ARTARR)

When a counter overflow occurs, the PWMx pin

level is changed depending on the corresponding

OPx (output polarity) bit in the PWMCR register.

When the counter reaches the value contained in

one of the output compare register (OCRx) the

corresponding PWMx pin le vel is restored.

It should be noted that the reload values will also

affect the value an d the resolution of the duty cycle

of the PWM output signal. To obtain a signal on a

PWMx pin, the contents of the OCRx registe r must

be greater than the contents of the ARTARR reg-

ister.

The maximum available resolution for the PWMx

duty cycle is:

Resolution = 1 / (256 - ARTARR)

Note: To get the maximum resolution (1/256), the

ARTARR register must be 0. With this maximum

resolution, 0% and 100% can be obtained by

changing the polarity.

Figure 38. PWM Auto-reload Time r Function

Figure 39. PWM Signal from 0% to 100% Duty Cycle

DUTY CYCLE

AUTO-RELOAD

PWMx OUTPUT

255

000

WITH OEx=1

AND OPx=0

(ARTARR)

(PWMDCRx)

WITH OEx=1

AND OPx=1

COUNTER

PWMx OUTPUT

WITH OEx=1

AND OPx=0

FDh FEh FFh FDh FEh FFh FDh FEh

OCRx=FCh

OCRx=FDh

OCRx=FEh

OCRx=FFh

ARTARR=FDh

fCOUNTER

ST72F521, ST72521B

64/215

PWM AUTO-RELOAD TIMER (Cont’d)

Output compare and Time base interrupt

On overflow, the OVF flag of the ARTCSR register

is set and an overf low interrupt request is gene rat-

ed if the overflow interrupt enable bit, OIE, in the

ARTCSR register, is set. The OVF f lag must be re-

set by the user software. This interrupt can be

used as a time base in the application.

External clock and event detector mode

Using the fEXT external prescaler input clock, the

auto-reload time r can be used as an external clock

event detector. In this mode, the ARTARR register

is used to select the nEVENT number of events to

be counted before setting the OVF flag.

nEVENT = 256 - ARTARR

Caution: The exte rn al cl ock f un ction is no t availa-

ble in HALT mode. If HALT mode is used in the ap-

plication, prior to executing the HALT instruction,

the counte r must be disabled by clearing the TCE

bit in the ARTCSR register to avoid spurio us coun-

ter increments.

Figure 40. External Event Detector Example (3 counts)

COUNTER

FDh FEh FFh FDh

OVF

ARTCSR READ

INTERRUPT

ARTARR=FDh

fEXT=fCOUNTER

FEh FFh FDh

IF OIE=1 INTERRUPT

IF OIE=1

ARTCSR READ

ST72F521, ST72521B

65/215

PWM AUTO-RELOAD TIMER (Cont’d)

Input capture function

This mode allows the measurement of external

signal pulse widths through ARTICRx registers.

Each input capt ure can generate an in terrupt inde-

pendently on a selected input signal transition.

This event is flagged by a set of the correspon ding

CFx bits of the Input Capture Control/Status regis-

ter (ARTICCSR).

These input capture interrupts are enabled

through the CIEx bits of th e ARTICCSR register.

The active transition (falling or ri sing edge) is soft-

ware programmable through the CSx bits of the

ARTICCSR register.

The read only input capture registers (ARTICRx)

are used to latch the auto-reload counter value

when a transition is detected on the ARTICx pin

(CFx bit set in ARTICCSR regist er). After fetching

the interrupt vector, the CFx flags can be read to

identify the interrupt source.

Note: After a capture detection, data transfer in

the ARTICRx register is inhibited until it is read

(clearing the CFx bit).

The timer interrupt remains pending while the CFx

flag is set when the interrupt is enabled (CIEx bit

set). This means, the ARTICRx register has to be

read at each capture eve nt to clear the CFx flag.

The timing resolutio n is given by auto-reloa d coun-

ter cycle time (1/fCOUNTER).

Note: During HALT mode, if both input capture

and external clock are enabled, the ARTICRx reg-

ister value is not guaranteed if the input capture

pin and the external cloc k change simultaneously.

External interrupt capability

This mode allows the Input capture capabilities to

be used as external interrupt sources. The inter-

rupts are generated on the edge of the ARTICx

signal.

The edge sensitivity of the external interrupts is

programmable (CSx bit of ARTICCSR register)

and they are independently enabled through CIEx

bits of the ARTICCSR register. After fetching the

interrupt vector, the CFx flag s can be read to iden-

tify the interrupt source.

During HALT mode, the external interrupts can be

used to wake up the micro (if the CIEx bit is set).

Figure 41. Input Capture Timin g Diagram

04h

COUNTER

01h

fCOUNTER

xxh

02h 03h 05h 06h 07h

04h

ARTICx PIN

CFx FLAG

ICRx REGISTER

INTERRUPT

ST72F521, ST72521B

66/215

PWM AUTO-RELOAD TIMER (Cont’d)

10.3.3 Register Description

CONTROL / STATUS REGISTER (ARTCSR)

Read/Write

Reset Value: 0000 0000 (00h)

Bit 7 = EXCL External Clock

This bit is set and cleared by software. It selects the

input clock for the 7-bit prescaler.

0: CPU clock.

1: External clock.

Bit 6:4 = CC[2:0] Counter Clo ck Control

These bits are set and cleared by software. They

determine the prescaler division ratio from fINPUT.

Bit 3 = TCE Timer Counter Enable

This bit is set and cleared by software. It puts the

timer in the lowest power consumption mode.

0: Counter stopped (prescaler and counter frozen).

1: Counter ru nn in g.

Bit 2 = FCRL Force Counter Re-Load

This bit is write-only and any attempt to read it will

yield a logical zero. When set, it causes the contents

of ARTARR register to be loaded into the counter,

and the content of the prescaler register to be

cleared in order to initialize the timer before starting

to count.

Bit 1 = OIE Overflow Interrupt Enable

This bit is set and cleared by software. It allows to

enable/disable the interrupt which is generated

when the OVF bit is set.

0: Overflow Interrupt disable.

1: Overflow Interrupt enable.

Bit 0 = OVF Overflow Flag

This bit is set by hardware and clear ed by software

reading the ARTCSR r egister. It indicate s the tran-

sition of the counter from FFh to the ARTARR val-

ue.

0: New transition not yet reached

1: Transition reached

COUNTER ACCESS REGISTER (ARTCAR)

Read/Write

Reset Value: 00 0 0 00 00 (0 0h )

Bit 7:0 = CA[7:0] Counter Access Data

These bits can be set and cleared either by hard-

ware or by software. Th e ARTCAR register is used

to read or write the aut o-reload co unter “on the fly”

(while it is counting).

AUTO-RELOAD REGISTER (ARTARR)

Read/Write

Reset Value: 00 0 0 00 00 (0 0h )

Bit 7:0 = AR[7:0] Counter Auto-Reload Data

These bits are set and cleared by software. They

are used to hold the auto- reload value which is au-

tomatically loaded in the counter when an over flow

occurs. At the same time, the PWM output levels

are changed according to the corresponding OPx

bit in the PWMCR register.

This register has two PWM management func-

tions:

– Adjusting the PWM frequency

– Setting the PWM duty cycle resolution

PWM Frequency vs. Resoluti on:

EXCL CC2 CC1 CC0 TCE FCRL OIE OVF

fCOUNTER With fINPUT=8 MHz CC2 CC1 CC0

fINPUT

fINPUT / 2

fINPUT / 4

fINPUT / 8

fINPUT / 16

fINPUT / 32

fINPUT / 64

fINPUT / 128

8 MHz

4 MHz

2 MHz

1 MHz

500 KHz

250 KHz

125 KHz

62.5 KHz

CA7 CA6 CA5 CA4 CA3 CA2 CA1 CA0

AR7 AR6 AR5 AR4 AR3 AR2 AR1 AR0

ARTARR

value Resolution fPWM

Min Max

0 8-bit ~0.244-KHz 31.25-KHz

[ 0..127 ] > 7-bit ~0.244-KHz 62.5-KHz

[ 128..191 ] > 6-bit ~0.488-KHz 125-KHz

[ 192..223 ] > 5-bit ~0.977-KHz 250-KHz

[ 224..239 ] > 4-bit ~1.953-KHz 500-KHz

ST72F521, ST72521B

67/215

PWM AUTO-RELOAD TIMER (Cont’d)

PWM CONTROL REGISTER (PWMCR)

Read/Write

Reset Value: 0000 0000 (00h)

Bit 7:4 = OE[3:0] PWM Output Enable

These bits are set and cleared by software. They

enable or disable the PWM output channels inde-

pendently acting on the corresponding I/O pin.

0: PWM output disabled.

1: PWM output enabled.

Bit 3:0 = OP[3:0] PWM Output Polarity

These bits are set and cleared by software. They

independently select the polarity of the four PWM

output signals.

Note: When an OPx bit is modified, the PWMx out-

put signal pola rity is imme d iately reversed .

DUTY CYCLE REGISTERS (PWMDCRx)

Read/Write

Reset Value: 00 0 0 00 00 (0 0h )

Bit 7:0 = DC[7:0] Duty Cycle Data

These bits are set and cleared by software.

A PWMDCRx register is associated with the OCRx

second edge location of the PWM signal (the first

edge location is common to all chan nels and given

by the ARTARR register). These PWMDCR regis-

ters allow the duty cycle to be set independently

for each PWM channel.

OE3 OE2 OE1 OE0 OP3 OP2 OP1 OP0

PWMx output level OPx

Counter <= OCRx Counter > OCRx

100

011

DC7 DC6 DC5 DC4 DC3 DC2 DC1 DC0

ST72F521, ST72521B

68/215

PWM AUTO-RELOAD TIMER (Cont’d)

INPUT CAPTURE

CONTROL / STATUS REGISTER (ARTICCSR)

Read/Write

Reset Value: 0000 0000 (00h)

Bit 7:6 = Reserved, always read as 0.

Bit 5:4 = CS[2:1] Capture Sensitivity

These bits are set and cleared by software. They

determine the trigger event polarity on the corre-

sponding input capture channel.

0: Falling edge triggers capture on channel x.

1: Rising edge triggers capture on channel x.

Bit 3:2 = CIE[2:1] Capture Interrupt Enable

These bits are set and cleared by software. They

enable or disable the Input capture channel inter-

rupts independently.

0: Input capture channel x interrupt disabled.

1: Input capture channel x interrupt enabled.

Bit 1:0 = CF[2:1] Capture F lag

These bits are set by hardware and cleared by

software reading t he corresponding ARTICRx r eg-

ister. Each CFx bit indicates that an input capture x

has occurred.

0: No input capture on channel x.

1: An input capture has occured on channel x.

INPUT CAPTURE REGISTERS (ARTICRx)

Read only

Reset Value: 00 0 0 00 00 (0 0h )

Bit 7:0 = IC[7:0] Input Captur e Data

These read only bits are set and cleared by hard-

ware. An ARTICRx register contains the 8-bit

auto-reload counter value transferred by the input

capture channel x event.

0 0 CS2 CS1 CIE2 CIE1 CF2 CF1

IC7 IC6 IC5 IC4 IC3 IC2 IC1 IC0

ST72F521, ST72521B

69/215

PWM AUTO-RELOAD TIMER (Cont’d)

Table 15. PWM Auto-Reload Timer Register Map and Reset Values

Address

(Hex.) Register

Label 76543210

0073h PWMDCR3

Reset Valu e DC7

0DC6

0DC5

0DC4

0DC3

0DC2

0DC1

0DC0

0074h PWMDCR2

Reset Valu e DC7

0DC6

0DC5

0DC4

0DC3

0DC2

0DC1

0DC0

0075h PWMDCR1

Reset Valu e DC7

0DC6

0DC5

0DC4

0DC3

0DC2

0DC1

0DC0

0076h PWMDCR0

Reset Valu e DC7

0DC6

0DC5

0DC4

0DC3

0DC2

0DC1

0DC0

0077h PWMCR

Reset Valu e OE3

0OE2

0OE1

0OE0

0OP3

0OP2

0OP1

0OP0

0078h ARTCSR

Reset Valu e EXCL

0CC2

0CC1

0CC0

0TCE

0FCRL

0RIE

0OVF

0079h ARTCAR

Reset Valu e CA7

0CA6

0CA5

0CA4

0CA3

0CA2

0CA1

0CA0

007Ah ARTARR

Reset Valu e AR7

0AR6

0AR5

0AR4

0AR3

0AR2

0AR1

0AR0

007Bh ARTICCSR

Reset Valu e 00

CS2

0CS1

0CIE2

0CIE1

0CF2

0CF1

007Ch ARTICR1

Reset Valu e IC7

0IC6

0IC5

0IC4

0IC3

0IC2

0IC1

0IC0

007Dh ARTICR2

Reset Valu e IC7

0IC6

0IC5

0IC4

0IC3

0IC2

0IC1

0IC0

ST72F521, ST72521B

70/215

10.4 16-BIT TIMER

10.4.1 Introduction

The timer consists of a 16- bit free -r unn ing count er

driven by a prog ra m m ab le presca le r.

It may be used for a variety of purposes, including

pulse length measurement of up to two input sig-

nals (input captur e) or ge neration of up to two out-

put waveforms (output compare and PWM).

Pulse lengths and waveform periods can be mod-

ulated from a few microseconds to several milli-

seconds using the timer prescaler and the CPU

clock prescaler.

Some ST7 devices have two on -chip 16-bit tim ers.

They are completely independent, and do not

share any resources. They are synchronized after

a MCU reset as long as the timer clock frequen-

cies are not modif ied.

This description cover s one or two 16- bit timers. In

ST7 devices with two timers, register names are

prefixed with TA (Timer A) or TB (Timer B).

10.4.2 Main Features

■Programmable prescaler: fCPU divided by 2, 4 or 8.

■Overflow status flag and maskable interrupt

■External clock input (must be at least 4 times

slower than the CPU clock speed) with the choice

of active edge

■1 or 2 Output Compare functions ea ch with:

– 2 dedicated 16-bit registers

– 2 dedicated programmable signals

– 2 dedicated status flags

– 1 dedicated maskable interrupt

■1 or 2 Input Capture functions each with:

– 2 dedicated 16-bit registers

– 2 dedicated active edge selection signals

– 2 dedicated status flags

– 1 dedicated maskable interrupt

■Pulse width modulation mode (PWM)

■One pulse mo de

■Reduced Power Mode

■5 alternate functions on I/O ports (ICAP1, ICAP2,

OCMP1, OCMP2, EXTCLK)*

The Block Diagram is shown in Figure 42.

*Note: Some tim er pins may not be av ailable (no t

bonded) in some ST7 devices. Refer t o the device

pin out description.

When reading an input signal on a non-bonded

pin, the value will always be ‘1’.

10.4.3 Functional Description

10.4.3.1 Counter

The main block of the Programmable Timer is a

16-bit free running upcounter and its associated

16-bit registers. The 16-bit registers are made up

of two 8-bit registers called high & low.

Counter Register (CR):

– Counter High Register (CHR) is the most sig-

nificant byte (MS Byte).

– Counter Low Register (CLR) is the least sig-

nificant byte (LS Byte).

Alternat e Co un te r Reg ist er (A CR)

– Alternate C ounter High Register (A CHR) is the

most significant byte (MS Byte).

– Alternate Counter Low Register (ACLR) is the

least significant byte (LS Byte).

These two read-only 16-bit registers contain the

same value but with the difference that reading the

ACLR register does not clear the TOF bit (Timer

overflow flag), located in the Status register, (SR),

(see note at the en d of paragraph t itled 16-bit r ead

sequence).

Writing in the CLR register or ACLR register resets

the free running counter to the FFFCh value.

Both counters have a reset value of FFFCh ( this is

the only value which is reloaded in the 16-bit tim-

er). The reset value of both counters is also

FFFCh in One Pulse mode and PWM mode.

The timer clock depends on the clock control bits

of the CR2 register, as illustrated in Table 16 Clock

Control Bits. The value in the counter register re-

peats every 131072, 262144 or 524288 CPU clock

cycles depending on the CC[1:0] bits.

The timer frequency can be fCPU/2, fCPU/4, fCPU/8

or an external frequency.

ST72F521, ST72521B

71/215

16-BIT TIMER (Cont’d)

Figure 42. Timer Block Diagram

MCU-PERIPHERAL INTERFACE

COUNTER

ALTERNATE

OUTPUT

COMPARE

OUTPUT COMPARE EDGE DETECT

OVERFLOW

DETECT

CIRCUIT

1/2

1/4

1/8

8-bit

buffer

ST7 INTERNAL BUS

LATCH1 OCMP1

ICAP1

EXTCLK

fCPU

TIMER INTERRUPT

ICF2ICF1 TIMD 00

OCF2OCF1 TOF

PWMOC1E EXEDG

IEDG2CC0CC1

OC2E OPMFOLV2ICIE OLVL1IEDG1OLVL2FOLV1OCIETOIE

ICAP2

LATCH2 OCMP2

8 low

8 high

16 16

(Control Register 1) CR1 (Control Register 2) CR2

(Control/Status Register)

8 8 8

88 8

high

low

high

low

EXEDG

TIMER INTERNAL BUS

CIRCUIT1

EDGE DETECT

CIRCUIT2

CIRCUIT

OUTPUT

COMPARE

INPUT

CAPTURE

INPUT

CAPTURE

CC[1:0]

COUNTER

Note: If IC, OC and TO interrupt requests have separate vectors

then the last OR is not present (See device Interrupt Vector Table)

(See note)

CSR

ST72F521, ST72521B

72/215

16-BIT TIMER (Cont’d)

16-bit read sequence: (from either the Counter

The user mus t rea d th e MS Byte f irst , the n the L S

Byte value is buffered automatically.

This buffered value remains unchanged until the

16-bit read sequence is completed, even if the

user reads the MS Byte several times.

After a complete reading sequence, if only the

CLR register or ACLR register are read, they re-

turn the LS Byte of the count value at the time of

the read.

Whatever the timer mode used (i nput capture, ou t-

put compare, one pulse mode or PWM mode) an

overflow occurs when the counter rolls over from

FFFFh to 0000h then:

– The TOF bit of the SR register is set.

– A timer interrupt is generated if:

– TOIE bit of the CR1 register is set and

– I bit of the CC register is cleared.

If one of these conditions is false, the interrupt re-

mains pending to be issued as soon as they are

both true.

Clearing the overflow interrupt request is done in

two steps:

1.Reading the SR register while the TOF bit is set.

2.An access (read or write) to the CLR register.

Notes: The TOF bit is not cleared by accesses to

ACLR register. The advantage of accessing the

ACLR register rather than the CLR register is that

it allows simultaneous use of th e overfl ow function

and reading the free running counter at random

times (for example, to measure elapsed time) with-

out the risk of clearing the TOF bit erroneously.

The timer is not affected by WAIT mode.

In HALT mode, the coun ter stops counting until the

mode is exited. Counting then resumes from the

previous count (MCU awakened by an interrupt) or

from the reset count (MCU awakened by a Reset).

10.4.3.2 External Clock

The external clock (where available) is selected if

CC0=1 and CC1=1 in the CR2 register.

The status of the EXEDG bit in the CR2 register

determines the type o f level transition on the exter-

nal clock pin EXTCLK that will trigger the free run-

ning counter.

The counter is synchronized with the falling edge

of the internal CPU clock.

A minimum of four falling edges of the CPU clock

must occur between two consecutive active edges

of the external clock; thus the external clock fre-

quency must be less than a quarter of the CPU

clock frequency.

is buffered

Read

At t0

Read Returns the buffered

LS Byte value at t0

At t0 +∆t

Other

instructions

Beginning of the sequence

Sequence completed

LS Byte

MS Byte

ST72F521, ST72521B

73/215

16-BIT TIMER (Cont’d)

Figure 43. Counter Timing Diagram, internal clock divided by 2

Figure 44. Counter Timing Diagram, internal clock divided by 4

Figure 45. Counter Timing Diagram, internal clock divided by 8

Note: The MCU is in reset state when the internal reset signal is high, when it is low the MCU is running.

CPU CLOCK

FFFD FFFE FFFF 0000 0001 0002 0003

INTERNAL RESET

TIMER CLOCK

COUNTER REGISTER

TIMER OVERFLOW FLAG (TOF)

FFFC FFFD 0000 0001

CPU CLOCK

INTERNAL RESET

TIMER CLOCK

COUNTER REGISTER

TIMER OVERFLOW FLAG (TOF)

CPU CLOCK

INTERNAL RESET

TIMER CLOCK

COUNTER REGISTER

TIMER OVERFLOW FLAG (TOF)

FFFC FFFD 0000

ST72F521, ST72521B

74/215

16-BIT TIMER (Cont’d)

10.4.3.3 Input Capture

In this section, the in dex, i, ma y be 1 or 2 because

there are 2 input capture functions in the 16-bit

timer.

The two 16-bit input capture registers (IC1R and

IC2R) are used to latch the value of the free run-

ning counter after a transition is detected on the

ICAPi pin (see figure 5).

ICiR register is a read-only register.

The active transition is software programmable

through the IEDGi bit of Control Registers (CRi).

Timing resolution is one count of the free running

counter: (fCPU/CC[1:0]).

Procedure:

To use the input capture functio n select the follo w-

ing in the CR2 register:

– Select the timer clock (CC[1:0]) (see Table 16

Clock Control Bits).

– Select the edge of the active transition on the

ICAP2 pin with the IEDG2 bit (the ICAP2 pin

must be configured as f loatin g input or input with

pull-up without interrupt if this configuration is

available).

And select the following in the CR1 register:

– Set the ICIE bit to generate an interrupt after an

input capture coming from either the ICAP1 pin

or the ICAP2 pin

– Select the edge of the active transition on the

ICAP1 pin with the IEDG1 bit (the ICAP1pin must

be configured as floating input or input with pull-

up without interrupt if this configuration is availa-

ble).

When an input capture occurs:

– ICFi bit is set.

– The ICiR register contains the value of the free

running counter on the active transition on the

ICAPi pin (see Figure 47).

– A timer interrupt is generated if the ICIE bit is set

and the I bit is cle ared in the CC regis ter. O ther -

wise, the interrupt remains pending until both

conditions become true.

Clearing the Input Capture interrupt request (i.e.

clearing the ICFi bit) is done in two steps:

1. Reading the SR register while the ICFi bit is set.

2. An access (read or write) to the IC iLR register.

Notes:

1. After reading the ICiHR register, transfer of

input capture data is inhibited and ICFi will

never be set until the ICiLR register is also

read.

2. The ICiR register contains the free running

counter value which corresponds to the most

recent input capture.

3. The 2 input capture functions can be used

together even if the timer also uses the 2 output

compare functions.

4. In One pulse Mode and PWM mode only Input

Capture 2 can be use d.

5. The alternate inputs (ICAP1 & ICAP2) are

always directly connected to the timer. So any

transitions on these pins activates the input

capture func tion .

Moreover if one of the ICAPi pins is configured

as an input and the second one as an output,

an interrupt can be generated if the user tog-

gles the output pin and if the ICIE bit is set.

This can be avoided if the input capture func-

tion i is disabl ed by read ing the IC iHR (see note

1).

6. The TOF bit can be used with interrupt genera-

tion in order to measure events that go beyond

the timer range (FFFFh).

MS Byte LS Byte

ICiR ICiHR ICiLR

ST72F521, ST72521B

75/215

16-BIT TIMER (Cont’d)

Figure 46. Input Capture Block Diagram

Figure 47. Input Capture Timin g Diagram

ICIE

CC0

CC1

16-BIT FREE RUNNING

COUNTER

IEDG1

(Control Register 1) CR1

(Control Register 2) CR2

ICF2ICF1 000

(Status Register) SR

IEDG2

ICAP1

ICAP2 EDGE DETECT

CIRCUIT2

16-BIT

IC1R Register

IC2R Register

EDGE DETECT

CIRCUIT1

FF01 FF02 FF03

FF03

TIMER CLOCK

COUNTER REGISTER

ICAPi PIN

ICAPi FLAG

ICAPi REGISTER

Note: The rising edge is the active edge.

ST72F521, ST72521B

76/215

16-BIT TIMER (Cont’d)

10.4.3.4 Output Compare

In this section, the in dex, i, ma y be 1 or 2 because

there are 2 output compare functions in the 16-bit

timer.

This function can be used to control an output

waveform or indicate when a period of time has

elapsed.

When a match is found between the Output Com-

pare register and th e free running counter, the ou t-

put compare function:

– Assigns pins with a prog rammable value if the

OCiE bit is set

– Sets a flag in the status register

– Generates an interru pt if enabled

Two 16-bit registers Output Compare Register 1

(OC1R) and Output Compare Register 2 (OC2R)

contain the value to be compared to the counter

These registers ar e reada ble and wr itable and are

not affected by the timer hardware. A reset event

changes the OCiR value to 8000h.

Timing resolution is one count of the free running

counter: (fCPU/CC[1:0]).

Procedure:

To use the output compare function, select the fol-

lowing in the CR2 register:

– Set the OCiE bit if an output is needed then the

OCMPi pin is dedicated to the output compare i

signal.

– Select the timer clock (CC[1:0]) (see Table 16

Clock Control Bits).

And select the following in the CR1 register:

– Select the OLVLi bit to applied to the OCMPi pins

after the match occur s.

– Set the OCIE bit to generate an interrupt if it is

needed.

When a match is found between OCRi register

and CR register:

– OCFi bit is set.

– The OCMPi pin ta kes OLVLi bit value (OCMPi

pin latch is forced low during reset).

– A timer interrupt is generated if the OCIE bit is

set in the CR1 register and the I bit is cleared in

the CC register (CC).

The OCiR register value required for a specific tim-

ing application can be calculated using the follow-

ing formula:

Where:

∆t = Output compare period (in seconds)

fCPU = CPU clock frequency (in hertz)

PRESC = Timer prescaler factor (2, 4 or 8 de-

pending on CC[1:0] bits, see Table 16

Clock Control Bits)

If the timer clock is an external clock, the formula

is:

Where:

∆t = Output compare period (in seconds)

fEXT = External timer clock frequency (in hertz)

Clearing the ou tp ut comp are int er ru pt re qu est ( i. e.

clearing the OCFi bit) is done by:

1. Reading the SR register while the OCFi bit is

set.

2. An acce ss (rea d or wr ite ) to t he OCiLR reg ist er .

The following procedure is recommended to pre-

vent the OC Fi bit from being set between the time

it is read and the write to the OC iR register:

– Write to the OCiHR register (further compares

are inhibited) .

– Read the SR register (first step of the clearance

of the OCFi bit, which may be already set).

– Write to the OCiLR registe r (e na ble s th e ou tp ut

compare function and clears the OCFi bit).

MS Byte LS Byte

OCiROCiHR OCiLR

∆ OCiR = ∆t * fCPU

PRESC

∆ OCiR = ∆t * fEXT

ST72F521, ST72521B

77/215

16-BIT TIMER (Cont’d)

Notes:

1. After a processor write cycle to the OCiHR reg-

ister, the output compare function is inhibited

until the OCiLR register is also written.

2. If the OCiE bit is not set, the OCMPi pin is a

general I/O port and the OLVLi bit will not

appear when a match is found but an interrupt

could be genera ted if the OCIE bit is set.

3. When the timer clock is fCPU/2, OCFi and

OCMPi are set while the counter value equals

the OCiR register value (see Figure 49 on page

78). This behaviour is the same in OPM or

PWM mode.

When the timer clock is fCPU/4, fCPU/8 or in

external clock mode, OCFi and OCMPi are set

while the counter value equals the OCiR regis-

ter value plus 1 (see Figure 50 on page 78).

4. T he output compare functions can be use d both

for generating external events on the OCMPi

pins even if the input capture mode is also

used.

5. The value in the 16-bit OCiR register and the

OLVi bit should be changed after each suc-

cessful comparison in ord er to cont rol an outp ut

waveform or establish a new elapsed timeout.

Forced Compare Output capability

When the FOLVi bit is set by software, the OLVLi

bit is copied to th e OCMPi pin. The OLVi bit has to

be toggled in order to toggle the OCMPi pin when

it is enabled (OCiE bit= 1). The OCFi b it is then not

set by hardware, and thus no interrupt request is

generated.

The FOLVLi bits have no effect in both one pulse

mode and PWM mode.

Figure 48. Output Compare Block Diagram

OUTPUT COMPARE

16-bit

CIRCUIT

OC1R Register

16 BIT FREE RUNNING

COUNTER OC1E CC0CC1

OC2E

OLVL1OLVL2OCIE

(Control Register 1) CR1

(Control Register 2) CR2

000OCF2OCF1

(Status Register ) SR

16-bit

OCMP1

OCMP2

Latch

OC2R Register

FOLV2 FOLV1

ST72F521, ST72521B

78/215

16-BIT TIMER (Cont’d)

Figure 49. Output Compare Timing Diagram, fTIMER =fCPU/2

Figure 50. Output Compare Timing Diagram, fTIMER =fCPU/4

INTERNAL CPU CLOCK

TIMER CLOCK

COUNTER REGISTER

OUTPUT COMPARE REGISTER i (OCRi)

OUTPUT COMPARE FLAG i (O CFi)

OCMPi PIN (OLVLi=1)

2ED3

2ED0 2ED1 2ED2 2ED3 2ED42ECF

INTERNAL CPU CLOCK

TIMER CLOCK

COUNTER REGISTER

OUTPUT COMPARE REGISTER i (OCRi)

COMPARE REGISTER i LATCH

2ED3

2ED0 2ED1 2ED2 2ED3 2ED42ECF

OCMPi PIN (OLVLi=1)

OUTPUT COMPARE FLAG i (OCFi)

ST72F521, ST72521B

79/215

16-BIT TIMER (Cont’d)

10.4.3.5 One Pulse Mode

One Pulse mode enables the generation of a

pulse when an external event occurs . This mode is

selected via the OPM bit in the CR2 register.

The one pulse mode uses the Input Capture1

function and the Output Compare1 functi on.

Procedure:

To use one pulse mode:

1. Load the OC1R register with the value corre-

sponding to the length of the pulse (see the for-

mula in the opposite column).

2. Select the following in the CR1 register:

– Using the OLVL1 bit, select the level to be ap-

plied to the OCMP1 pin after the pulse.

– Using the OLVL2 bit, select the level to be ap-

plied to the OCMP1 pin during the pulse.

– Select the edge of the active transition on the

ICAP1 pin with the IEDG1 bit (the ICAP1 pin

must be configured as floating input).

3. Select the following in the CR2 register:

– Set the OC1E bit, th e OCMP1 pin is then ded-

icated to the Output Compare 1 function.

– Set the OPM bit.

– Select the timer clock CC[1:0] (see Table 16

Clock Control Bits).

Then, on a valid eve nt on the ICAP1 pin, the coun-

ter is initialized to FFFCh and OLVL2 bit is loaded

on the OCMP1 pin , the ICF1 bit is set an d th e va l-

ue FFFDh is loaded in the IC1R register.

Because the ICF1 bit is set when an active edge

occurs, an interrupt can be generated if the ICIE

bit is set.

Clearing the Input Capture interrupt request (i.e.

clearing the ICFi bit) is done in two steps:

1. Reading the SR register while the ICFi bit is set.

2. An access (read or write) to the IC iLR register.

The OC1R register value required for a specific

timing application can be calculated using the fol-

lowing formula:

Where:

t = Pulse period (in seconds)

fCPU = CPU clock frequency (in hertz)

PRESC = Timer prescaler factor (2, 4 or 8 de pend-

ing on the CC[1:0] bits, see Table 16

Clock Control Bits)

If the timer clock is an external clock the formula is:

Where:

t = Pulse period (in seconds)

fEXT = External timer clock frequency (in hertz)

When the value of t he counter is equal to the value

of the contents of the OC1R register, the OLVL1

bit is output on the OCMP1 pin, (See Figure 51).

Notes:

1. T he OCF1 bit canno t be set b y ha rd wa re in one

pulse mode but the OCF2 bit can generate an

Output Compare interrupt.

2. When the Pulse Width Modulation (PWM) and

One Pulse Mode (OPM) bits are both set, the

PWM mode is the only active one.

3. If OLVL1=OLVL2 a continuous signal will be

seen on the OCMP1 pin.

4. T he ICAP1 pin can not be used to pe rform inp ut

capture. The ICAP2 pin can be used to perform

input capture ( ICF2 can be set a nd IC2R can be

loaded) but the user must take care that the

counter is reset each time a valid edge occurs

on the ICAP1 pin and ICF1 can also generates

interrupt if ICIE is set.

5. When one pulse mode is used OC1R is dedi-

cated to this mode. Nevertheless OC2R and

OCF2 can be used to indicate a period of time

has been elapsed but cannot generate an out-

put waveform because the level OLVL2 is dedi-

cated to the one pulse mode.

event occu rs

Counter

= OC1R OCMP1 = OLVL1

When

on ICAP1

One pulse mode cycle

OCMP1 = OLVL2

Counter is reset

to FFFCh

ICF1 bit is set

ICR1 = Counter

OCiR Value = t * fCPU

PRESC - 5

OCiR = t * fEXT -5

ST72F521, ST72521B

80/215

16-BIT TIMER (Cont’d)

Figure 51. One Pulse Mode Timing Example

Figure 52. Pulse Width Modulation Mode Timing Example with 2 Output Compare Functions

Note: O n timers with only 1 Output Com pare register, a fixed frequency PWM signal can be gene rated us-

ing the output compare and the counter overflow to define the pulse leng th.

COUNTER FFFC FFFD FFFE 2ED0 2ED1 2ED2

2ED3

FFFC FFFD

OLVL2 OLVL2OLVL1

ICAP1

OCMP1 compare1

Note: IEDG1=1, OC1R=2ED0h, OLVL1=0, OLVL2=1

01F8

01F8 2ED3

IC1R

COUNTER 34E2 34E2 FFFC

OLVL2 OLVL2

OLVL1

OCMP1 compare2 compare1 compare2

Note: OC1R=2ED0h, OC2R=34E2, OLVL1=0, OLVL2= 1

FFFC FFFD FFFE 2ED0 2ED1 2ED2

ST72F521, ST72521B

81/215

16-BIT TIMER (Cont’d)

10.4.3.6 Pulse Width Modulation Mode

Pulse Width Modulat ion ( PWM) m ode ena bles t he

generation of a signal with a frequency and pulse

length determined by the value of the OC1R and

OC2R registers.

Pulse Width Modulation mode uses the complete

Output Compare 1 function plus the OC2R regis-

ter, and so this functi onality ca n not be us ed when

PWM mode is activated.

In PWM mode, double buffering is implemented on

the output compare registers. Any new values writ-

ten in the OC1R and OC2R registers are taken

into account only at the end of the PWM period

(OC2) to avoid spikes on the PWM output pin

(OCMP1).

Procedure

To use pulse width modulat ion mode:

1. Load the OC2R register with the value corre-

sponding to the period of the signal using the

formula in the opposite column.

2. Load the OC1R register with the value corre-

sponding to the period of the pulse if (OLVL1=0

and OLVL2=1) using the formula in the oppo-

site column.

3. Select the following in the CR1 register:

– Using the OLVL1 bit, select the level to be ap-

plied to the OCMP1 pin after a successful

comparison with the OC1R register.

– Using the OLVL2 bit, select the level to be ap-

plied to the OCMP1 pin after a successful

comparison with the OC2R register.

4. Select the following in the CR2 register:

– Set OC1E bit: t he OCMP1 pin is then ded icat-

ed to the output compare 1 function.

– Set the PWM bit.

– Select the timer clock (CC[1:0]) (see T able 16

Clock Control Bits).

If OLVL1=1 and OLVL2=0 the length of the posi-

tive pulse is the d ifference between th e OC2R and

OC1R registers.

If OLVL1=OLVL2 a continuous signal will be seen

on the OCMP1 pin.

The OCiR register value required for a specific tim-

ing application can be calculated using the follow-

ing formula:

Where:

t = Signal or pulse period (in seconds)

fCPU = CPU clock frequency (in hertz)

PRESC = Timer prescaler factor (2, 4 or 8 de pend-

ing on CC[1 :0] b its, se e Table 16 Clock

Control Bits)

If the timer clock is an external clock the formula is:

Where:

t = Signal or pu lse period (in seconds)

fEXT = External timer clock frequency (in hertz)

The Output Compare 2 event causes the counter

to be initialized to FFFCh (See Figure 52)

Notes:

1. After a write instruction to the OCiHR register,

the output compar e function is inhibit ed until the

OCiLR register is also written.

2. The OCF1 and OCF2 bits cannot be set by

hardware in PWM mode therefore the Output

Compare interrupt is inhibited.

3. The ICF1 bit is set by hardware when the coun-

ter reaches the OC2R value and can produce a

timer interrupt if the ICIE bit is set and the I bit is

cleared.

4. In PWM mode the ICAP1 pin can not be used

to perform input capture because it is discon-

nected to the ti mer. The I CAP2 pin can be used

to perform input capture (ICF2 can be set and

IC2R can be loaded) but the user must take

care that the counter is reset each period and

ICF1 can also generates interrupt if ICIE is set.

5. When the Pulse Width Modulation (PWM) and

One Pulse Mode (OPM) bits are both set, the

PWM mode is the only active one.

Counter

OCMP1 = OLVL2

Counter

= OC2R

OCMP1 = OLVL1

When

= OC1R

Pulse Width Modulation cycle

Counter is reset

to FFFCh

ICF1 bit is set

OCiR Value = t * fCPU

PRESC - 5

OCiR = t * fEXT -5

ST72F521, ST72521B

82/215

16-BIT TIMER (Cont’d)

10.4.4 Low Po wer Modes

10.4.5 Interrup ts

Note: The 16-bit Timer interrupt events are connected to the same interrupt vector (see Interrupts chap-

ter). These events generate an interrupt if the corresponding Enable Control Bit is set and the interrupt

mask in the CC register is reset (RIM instruction).

10.4.6 Summary of Timer mode s

1) See note 4 in Section 10.4.3.5 One Pulse Mode

2) See note 5 in Section 10.4.3.5 One Pulse Mode

3) See note 4 in Section 10.4.3.6 Pulse Width Modulation Mode

Mode Description

WAIT No effect on 16-bit Timer.

Timer interrupts cause the device to exit from WAIT mode.

HALT

16-bit Timer registers are frozen.

In HALT mode, the counter stops counting until Halt mode is exited. Counting resumes from the previous

count when the MCU is woken up by an interrupt with “exit from HALT mode” capability o r from the counter

reset value when the MCU is woken up by a RESET.

If an input capture event occurs on the ICAPi pin, the input capture detection circuitry is armed. Consequent-

ly, when the MCU is woken up by an interrupt wi th “ex it from HALT mode” capability, the ICFi bit is set, and

the counter value present when exiting from HALT mode is captured into the ICiR register.

Interrupt Event Event

Flag

Enable

Control

Bit

Exit

from

Wait

Exit

from

Halt

Input Capture 1 event/Counter reset in PWM mode ICF1 ICIE Yes No

Input Capture 2 event ICF2 Y es No

Output Compare 1 event (not available in PWM mode) OCF1 OCIE Yes No

Output Compare 2 event (not available in PWM mode) OCF2 Yes No

Timer Overflow event TOF TOIE Yes No

MODES TIMER RESOURCES

Input Capture 1 Input Capture 2 Output Compare 1 Output Compare 2

Input Capture (1 and/or 2) Yes Yes Yes Yes

Output Compare (1 and/or 2) Yes Yes Yes Yes

One Pulse Mode No Not Recommended1) No Partially 2)

PWM Mode No Not Recommended 3) No No

ST72F521, ST72521B

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16-BIT TIMER (Cont’d)

10.4.7 Register Description

Each Timer is associated with three control and

status registers, and with six pair s of data registers

(16-bit values) relating to the two input captures,

the two output compares, the counter and the al-

ternate counter.

CONTROL RE GISTER 1 (CR1 )

Read/Write

Reset Value: 0000 0000 (00h)

Bit 7 = ICIE Input Capture Interrupt Enable.

0: Interrupt is inhibited.

1: A timer interrupt is generated whenever the

ICF1 or ICF2 bit of the SR register is set.

Bit 6 = OCIE Output Compare Interrupt Enable.

0: Interrupt is inhibited.

1: A timer interrupt is generated whenever the

OCF1 or OCF2 bit of the SR register is set.

Bit 5 = TOIE Timer Overflow Interrupt Enable.

0: Interrupt is inhibited.

1: A timer interrupt is enabled whenever the TOF

bit of the SR register is set.

Bit 4 = FOLV2 Forced Output Compare 2.

This bit is set and cleared by software.

0: No effect on the OCMP2 pin.

1:Forces the OLVL2 bit to be copied to the

OCMP2 pin, if the OC2E bit is set and even if

there is no successful comparison.

Bit 3 = FOLV1 Forced Output Compare 1.

This bit is set and cleared by software.

0: No effect on the OCMP1 pin.

1: Forces OLVL1 to be copied to the OCMP1 pin, if

the OC1E bit is set and even if there is no suc-

cessful comparison.

Bit 2 = OLVL2 Output Level 2.

This bit is copied to the OCMP2 pin whenever a

successful comparison occurs with the O C2R reg-

ister and OCxE is set in the CR2 register. This val-

ue is copied t o the OCMP1 pin in One Pulse Mode

and Pulse Width Modulation mode.

Bit 1 = IEDG1 Input Edg e 1.

This bit determines which type of level transition

on the ICAP1 pin will trigger the capture.

0: A falling edge triggers the capture.

1: A rising edge triggers the capture.

Bit 0 = OLVL1 Output Level 1.

The OLVL1 bit is copied to the OCMP1 pin when-

ever a successful comparison occurs with the

OC1R register and the OC1E bit is set in the CR2

ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1

ST72F521, ST72521B

84/215

16-BIT TIMER (Cont’d)

CONTROL RE GISTER 2 (CR2 )

Read/Write

Reset Value: 0000 0000 (00h)

Bit 7 = OC1E Output Compare 1 Pin Enable.

This bit is used only to output the signal from the

timer on the OCMP1 pin (OLV1 in Output Com-

pare mode, both OLV1 and OLV2 in PWM and

one-pulse mode). Whatever the value of the OC1E

bit, the Output Compare 1 function of the timer re-

mains active.

0: OCMP1 pin alternate function disabled (I/O pin

free for gene ral-purpose I/O).

1: OCMP1 pin alternate function enabled.

Bit 6 = OC2E Output Compare 2 Pin Enable.

This bit is used only to output the signal from the

timer on the OCMP2 pin (OLV2 in Output Com-

pare mode). Whatever the value of the OC2E bit,

the Output Compare 2 function of the timer re-

mains active.

0: OCMP2 pin alternate function disabled (I/O pin

free for gene ral-purpose I/O).

1: OCMP2 pin alternate function enabled.

Bit 5 = OPM One Pulse Mode.

0: One Pulse Mode is not active.

1: One Pulse Mode is active, the ICAP1 pin can be

used to trigge r one pulse on the OCMP1 pin; the

active transition is given by the IEDG1 bit. The

length of the generated pulse depends on the

contents of the OC1R register.

Bit 4 = PWM Pulse Width Modulation.

0: PWM mode is not active.

1: PWM mode is active, the OC MP 1 pin ou tput s a

programmable cyclic signal; the length of the

pulse depends on the value of OC1R register;

the period depend s on the value of OC2R regis-

ter.

Bit 3, 2 = CC[1:0] Clock Control.

The timer clock mode depends on these bits:

Table 16. Clock Control Bits

Note: If th e external clock pi n is not available , pro-

gramming the external clock configuration stops

the counter.

Bit 1 = IEDG2 Inpu t Edge 2.

This bit determines which type of level transition

on the ICAP2 pin will trigger the capture.

0: A falling edge triggers the capture.

1: A rising edge triggers the capture.

Bit 0 = EXEDG External Clock Edge.

This bit determines which type of level transition

on the external clock pin EXTCLK will trigger the

counter register.

0: A falling edge triggers the counter register.

1: A rising edge triggers the counter register.

OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG

Timer Clock CC1 CC0

fCPU / 4 0 0

fCPU / 2 0 1

fCPU / 8 1 0

External Clock (where

available) 11

ST72F521, ST72521B

85/215

16-BIT TIMER (Cont’d)

CONTROL/STATUS REGISTER (CSR)

Read/Write (bits 7:3 read only)

Reset Value: xxxx x0xx (xxh)

Bit 7 = ICF1 Inpu t Capture Flag 1.

0: No input capture (reset value).

1: An input capture has occurred on the ICAP1 pin

or the counter has reached the OC2R value in

PWM mode. To clear this bit, first read the SR

IC1R (IC1LR) register.

Bit 6 = OCF1 Output Compare Flag 1.

0: No match (reset value).

1: The content of the free running counter has

matched the content of the OC1R register. To

clear this bit, firs t read the SR register, then read

or write the low byte of the OC1R (OC1LR) reg-

ister.

Bit 5 = TOF Timer Overflow Flag.

0: No timer overflow (reset value).

1:The free running counter rolled over from FFFFh

to 0000h. To clear this bit, f irst read the SR reg-

ister, then read or write the low byte of the CR

(CLR) register.

Note: Reading or writing the ACLR register does

not clear TOF.

Bit 4 = ICF2 Input Capture Flag 2.

0: No input capture (reset value).

1: An input capture has occurred on the ICAP2

pin. To clear this bit, first read the SR register,

then read or write the low byte of the IC2R

(IC2LR) register.

Bit 3 = OCF2 Output Compare Flag 2.

0: No match (reset value).

1: The content of the free running counter has

matched the content of the OC2R register. To

clear this bit, firs t read the SR register, then read

or write the low byte of the OC2R (OC2LR) reg-

ister.

Bit 2 = TIMD Timer disable.

This bit is set and cleared by sof tware. When set, it

freezes th e timer presca ler and counter an d disa-

bled the output functions (OCMP1 and OCMP2

pins) to reduce power con s umption. Access to the

timer registers is still available, allowing the timer

configuration to be changed, or the counter reset,

while it is disabled.

0: Timer enabled

1: Timer prescaler, counter and outputs disabled

Bits 1:0 = Reserved, must be kept cleared.

ICF1 OCF1 TOF ICF2 OCF2 TIMD 0 0

ST72F521, ST72521B

86/215

16-BIT TIMER (Cont’d)

INPUT CAPTURE 1 HIGH REGISTER (IC1HR)

Read Only

Reset Value: Undefined

This is an 8-bit read only register that contains the

high part of the counter value (transferred by the

input capture 1 event).

INPUT CAPTURE 1 LOW REGISTER (IC1LR)

Read Only

Reset Value: Undefined

This is an 8-bit read only register that contains the

low part of the counter value (transferred by the in-

put capture 1 event).

OUTPUT COMPARE 1 HIGH REGISTER

(OC1HR)

Read/Write

Reset Value: 10 0 0 00 00 (8 0h )

This is an 8-bit register that contains the high part

of the value to be compared to the CHR register.

OUTPUT COMPARE 1 LOW REGISTER

(OC1LR)

Read/Write

Reset Value: 00 0 0 00 00 (0 0h )

This is an 8-bit register that contains the low part of

the value to be compared to the CLR register.

MSB LSB

ST72F521, ST72521B

87/215

16-BIT TIMER (Cont’d)

OUTPUT COMPARE 2 HIGH REGISTER

(OC2HR)

Read/Write

Reset Value: 1000 0000 (80h)

This is an 8-bit register that contains the high part

of the value to be compared t o the CHR register.

OUTPUT COMPARE 2 LOW REGISTER

(OC2LR)

Read/Write

Reset Value: 0000 0000 (00h)

This is an 8-bit register that contains the low part of

the value to be compared to the CLR register.

COUNTER HIGH REGISTER (CHR)

Read Only

Reset Value: 1111 1111 (FFh)

This is an 8-bit register that contains the high part

of the counter value.

COUNTER LOW RE GISTER (CLR)

Read Only

Reset Value: 1111 1100 (FCh)

This is an 8-bit register that contains the low part of

the counter value. A write to t his register resets the

counter. An access to this register after accessing

the CSR register clears the TOF bit.

ALTERNATE COUNTER HIGH REGISTER

(ACHR)

Read Only

Reset Value: 1111 1111 (FFh)

This is an 8-bit register that contains the high part

of the counte r va lue .

ALTERNATE COUNTER LOW REGISTER

(ACLR)

Read Only

Reset Value: 1111 1100 (FCh)

This is an 8-bit register that contains the low part of

the counter value. A write to this register resets the

counter. An access to this register after an access

to CSR register does not clear the TOF bit in the

CSR register.

INPUT CAPTURE 2 HIGH REGISTER (IC2HR)

Read Only

Reset Value: Undefined

This is an 8-bit read only register that contains the

high part of the counter value (transferred by the

Input Capture 2 event).

INPUT CAPTURE 2 LOW REGISTER (IC2LR)

Read Only

Reset Value: Undefined

This is an 8-bit read only register that contains the

low part of the counter value (transferred by the In-

put Capture 2 event).

MSB LSB

ST72F521, ST72521B

88/215

16-BIT TIMER (Cont’d)

Table 17. 16-Bit Timer Register Map and Reset Values

Related Doc u mentation

AN 973: SCI software communications using 16-

bit timer

AN 974: Real Time Clock with ST7 Timer Output

Compare

AN 976: Driving a buzzer through the ST7 Timer

PWM function

AN1041: Using ST7 PWM signal to generate ana-

log input (sinusoid)

AN1046: UART emulation software

AN1078: PWM duty cycle switch implementing

true 0 or 100 per cent duty cycle

AN1504: Starting a PWM signal directly at high

level using the ST7 16-Bit timer

Address

(Hex.) Register

Label 76543210

Timer A: 32

Timer B: 42 CR1

Reset Value ICIE

0OCIE

0TOIE

0FOLV2

0FOLV1

0OLVL2

0IEDG1

0OLVL1

Timer A: 31

Timer B: 41 CR2

Reset Value OC1E

0OC2E

0OPM

0PWM

0CC1

0CC0

0IEDG2

0EXEDG

Timer A: 33

Timer B: 43 CSR

Reset Value ICF1

xOCF1

xTOF

xICF2

xOCF2

xTIMD

Timer A: 34

Timer B: 44 IC1HR

Reset Value MSB

xxxxxxx

LSB

Timer A: 35

Timer B: 45 IC1LR

Reset Value MSB

xxxxxxx

LSB

Timer A: 36

Timer B: 46 OC1HR

Reset Value MSB

1000000

LSB

Timer A: 37

Timer B: 47 OC1LR

Reset Value MSB

0000000

LSB

Timer A: 3E

Timer B: 4E OC2HR

Reset Value MSB

1000000

LSB

Timer A: 3F

Timer B: 4F OC2LR

Reset Value MSB

0000000

LSB

Timer A: 38

Timer B: 48 CHR

Reset Value MSB

1111111

LSB

Timer A: 39

Timer B: 49 CLR

Reset Value MSB

1111110

LSB

Timer A: 3A

Timer B: 4A ACHR

Reset Value MSB

1111111

LSB

Timer A: 3B

Timer B: 4B ACLR

Reset Value MSB

1111110

LSB

Timer A: 3C

Timer B: 4C IC2HR

Reset Value MSB

xxxxxxx

LSB

Timer A: 3D

Timer B: 4D IC2LR

Reset Value MSB

xxxxxxx

LSB

ST72F521, ST72521B

89/215

10.5 SERIAL PERIPHERAL INTERFACE (SPI)

10.5.1 Introduction

The Serial Peripheral Interface (SPI) allows full-

duplex, synchronous, serial communication with

external devices. An SPI system may consist of a

master and one or more slaves however the SPI

interface can not be a master in a multi-master

system.

10.5.2 Main Features

■Full duplex synchronous transfers (on 3 lines)

■Simplex synchronous transfers (on 2 lines)

■Master or slave operation

■Six master mode frequencies (fCPU/4 max.)

■fCPU/2 max. slave mode frequency (see note)

■SS Management by software or hardware

■Programmabl e clock polarity and phase

■End of transfer interrupt flag

■Write collis ion, Mast er M ode Fault and Ove rru n

flags

Note: In slave mode, continuous transmission is

not possible at maximum frequency due to the

software ov erhead for clearin g status flags an d to

initiate the next transmission sequence.

10.5.3 General Description

Figure 53 shows the serial peripheral interface

(SPI) block diagram. There are 3 registers:

– SPI Control Register (SPICR)

– SPI Control/Status Register (SPICSR)

– SPI Data Register (SPIDR)

The SPI is connected to external devices through

4 pins:

– MISO: Master In / Slave Out data

– MOSI: Master Out / Slave In data

– SCK: Serial Clock out by SPI mast ers and in-

put by SPI slaves

Figure 53. Serial Peripheral Interface Block Diagram

SPIDR

Read Buffer

8-Bit Shift Register

Write

Read

Data/Address Bus

SPI

SPIE SPE MSTR CPHA SPR0

SPR1

CPOL

SERIAL CLOCK

GENERATOR

MOSI

MISO

SCK CONTROL

STATE

SPICR

SPICSR

Interrupt

request

MASTER

CONTROL

SPR2

SPIF WCOL MODF 0

OVR SSISSMSOD

SOD

bit SS 1

ST72F521, ST72521B

90/215

SERIAL PERIPHERAL INTERFACE (Cont’d)

–SS

: Slave select:

This input signal acts as a ‘chip select’ to let

the SPI master commu nicat e with sla ves indi-

vidually and to avoid contention on the data

lines. Slave SS inputs can be driven by stand-

ard I/O ports on the master MCU.

10.5.3.1 Funct ional Description

A basic example of interconnections between a

single master and a single slave is illustrated in

Figure 54.

The MOSI pins are connected together and the

MISO pins are connected together. In this way

data is transferred serially between master and

slave (most significant bit first).

The communication is always init iated by the mas-

ter. When the master device transmits data to a

slave device via MOSI pin, the slave device re-

sponds by sending data to the master device via

the MISO pin. Th is implies full duplex communica-

tion with both data out and data in synchronized

with the same clock signal (which is provided by

the master device via the SCK pin).

To use a single data line, the MISO and MOSI p ins

must be connected at ea ch node ( in this case only

simplex communication is possible).

Four possible data/clock timing relationships may

be chosen (see Figure 57) but master and slave

must be programmed with the same timing mode.

Figure 54. Single Master/ Single Slave Application

8-BIT SHIFT REGISTER

SPI

CLOCK

GENERATOR

8-BIT SHIFT REGISTER

MISO

MOSI MOSI

MISO

SCK SCK

SLAVE

MASTER

SS SS

+5V

MSBit LSBit MSBit LSBit

Not used i f SS is managed

by software

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SERIAL PERIPHERAL INTERFACE (Cont’d)

10.5.3.2 Slave Select Management

As an alternative to using the SS pin to contro l the

Slave Select signal, the application can choose to

manage the Slave Select signal by software. This

is configured by the SSM bit in the SPICSR regis-

ter (see Figure 56)

In software management, the external SS pin is

free for other applicat ion uses and the inte rnal SS

signal level is driven by writing to the SSI bit in the

SPICSR register.

In Master mode:

–SS

internal must be held high continuously

In Slave Mode:

There are two cases depending on the data/clock

timing relationship (see Figure 55):

If CPHA=1 (data latched on 2nd clock edge):

–SS

internal must be held low during the entire

transmission. This implies that in single slav e

applications the SS pin either can be tied to

VSS, or made fre e f or st an da rd I/ O by mana g-

ing the SS function by software (SSM= 1 and

SSI=0 in the in the SPICSR reg ister)

If CPHA=0 (data latched on 1st clock edge):

–SS

internal must be held low during byte

transmission and pulled high between each

byte to allow the slave to wr ite to the shift re g-

ister. If SS is not pulled high, a Write Collision

error will occur when the slave writes to the

shift register (see Section 10.5.5.3).

Figure 55. Generic SS Timing Diagram

Figure 56. Hardware/Software Slave Select Management

MOSI/MISO

Master SS

Slave SS

(if CPHA=0)

Slave SS

(if CPHA=1)

Byte 1 Byte 2 Byte 3

SS internal

SSM bit

SSI bit

SS external pin

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SERIAL PERIPHERAL INTERFACE (Cont’d)

10.5.3.3 Master Mode Operation

In master mode, the serial clock is output on the

SCK pin. The clock frequency, polarity and phase

are configured by software (refer to the description

of the SPICSR register).

Note: The idle state of SCK must correspond to

the polarity selected in the SPICSR register (by

pulling up SCK if CPOL=1 or pulling down SCK if

CPOL=0).

To operate the SPI in master mode, perform the

following steps in order (if the SPICSR register is

not written firs t, th e SPIC R re gis ter set tin g (M STR

bit) may be not take n into account):

1. Write to the SPICR register:

– Select the clock frequency by configuring the

SPR[2:0] bits.

– Select the clock polarity and clock phase by

configuring the CPOL and CPHA bits. Figure

57 shows the four possible configurations.

Note: The slave must have the same CPOL

and CPHA settings as the master.

2. Write to the SPICSR register:

– Either set the SSM bit and set the SSI bit or

clear the SSM bit and tie the SS pin high for

the complete byte transmit sequence.

3. Write to the SPICR register:

– Set the MSTR and SPE bits

Note: MSTR and SPE bits remain set only if

SS is high).

The transmit sequence begins when software

writes a byte in the SPID R register.

10.5.3.4 Master Mode Transmit Sequence

When software writes to the SPIDR register, the

data byte is loaded into the 8-bit shift register and

then shifted out serially to the MOSI pin most sig-

nificant bit first.

When data transfer is complete:

– The SPIF bit is set by hardware

– An interrupt request is generated if the SPIE

bit is set and the interrupt mask in the CCR

Clearing the SPIF bit is performed by the following

software sequence:

1. An access to the SPICSR register while the

SPIF bit is set

2. A read to the SPIDR register.

Note: While the SPIF bit is set, all writes to the

SPIDR register are inhib ited until the SPI CSR reg-

ister is read.

10.5.3.5 Slave Mode Operation

In slave mode, the serial clock is received on the

SCK pin from the master device.

To operate the SPI in slave mode:

1. Write to the SPICSR register to perform the fol-

lowing actions:

– Select the clock polarity and clock phase by

configuring the CPOL and CPHA bits (see

Figure 57).

Note: The slave must have the same CPOL

and CPHA settings as the master.

– Manage the SS pin as described in Section

10.5.3.2 and Figure 55. If CPHA=1 SS must

be held low continuously. If CPHA=0 SS must

be held low during byte transmission and

pulled up between each byte to let the slave

write in the shift register.

2. Write to the SPICR register to clear the MSTR

bit and set the SPE bit to enable the SPI I/O

functions.

10.5.3.6 Slave Mode Transmit Sequence

When software writes to the SPIDR register, the

data byte is loaded into the 8-bit shift register and

then shifted out serially to the MISO pin most sig-

nificant bit first.

The transmit se qu e nce begins when the slav e de-

vice receives the clock signal and the most signifi-

cant bit of the data on its MOSI pin.

When data transfer is complete:

– The SPIF bit is set by hardware

– An interrupt reque st is gener ated if SPIE bit is

set and interrupt mask in the CCR register is

cleared.

Clearing the SPIF bit is performed by the following

software sequence:

1. An access to the SPICSR register while the

SPIF bit is set.

2. A write or a read to the SPIDR register.

Notes: While the SPIF bit is set, all writes to the

SPIDR register are inhib ited until the SPI CSR reg-

ister is read.

The SPIF bit can be cleared during a second

transmission; however, it must be cleared before

the second SPIF bit in orde r to prevent an Overrun

condition (see Section 10.5.5.2).

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SERIAL PERIPHERAL INTERFACE (Cont’d)

10.5.4 Clock Phase and Clock Polarity

Four possible timing relationships may be chosen

by software, using the CPOL and CPHA bits (See

Figure 57).

Note: The idle state of SCK must correspond to

the polarity selected in the SPICSR register (by

pulling up SCK if CPOL=1 or pulling down SCK if

CPOL=0).

The combination of the CPOL clock polarity and

CPHA (clock phase) bits selects the data capture

clock edge

Figure 57, shows an SPI transfer with the four

combinations of the CPHA a nd CPOL bits. The di-

agram may be interpreted as a master or slave

timing diagram where the SCK pin, the MISO pin,

the MOSI pin are directly connected between the

master and the slave device.

Note: If CPOL is changed at the communication

byte boundaries, the SPI must be disabled by re-

setting the SPE bit.

Figure 57. Data Clock Timing Diagram

SCK

MSBit Bit 6 Bit 5 Bit 4 Bit3 Bit 2 Bit 1 LSBit

MSBit Bit 6 Bit 5 Bit 4Bit3Bit 2Bit 1LSBit

MISO

(from master)

MOSI

(from slave)

(to slave)

CAPTURE STROBE

CPHA =1

MSBit Bit 6 Bit 5 Bit 4 Bit3 Bit 2 Bit 1 LSBit

MISO

(from master)

MOSI

(to slave)

CAPTURE STROBE

CPHA =0

Note: This figure should not be used as a replacement for parametric information.

Refer to the Electrical Characteristics chapter.

(from slave)

(CPOL = 1)

SCK

(CPOL = 0)

SCK

(CPOL = 1)

SCK

(CPOL = 0)

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SERIAL PERIPHERAL INTERFACE (Cont’d)

10.5.5 Error Flags

10.5.5.1 Mast er Mode Fault (MODF)

Master mode fault occurs when the master device

has its SS pin pulled low.

When a Master mode fault occurs:

– The MODF bit is set and an SPI interrupt re-

quest is generated if the SPIE bit is set.

– The SPE bit is reset. This blocks all output

from the device and disables the SPI periph-

eral.

– The MSTR bit is reset, th us forcing the d evice

into slave mode.

Clearing the MODF bit is done through a software

sequence:

1. A read access to the SPICSR register while the

MODF bit is set.

2. A write to the SPICR register.

Notes: To avoid any conflicts in an application

with multiple slaves, the SS pin must be pulled

high during the MODF bit clearing sequence. The

SPE and MSTR bits may be restored to their orig-

inal state during or after this clearing sequence.

Hardware does not allow the user to set the SPE

and MSTR bits while the MODF bit is set except in

the MODF bit clearing sequence.

10.5.5.2 Overrun Condition (OVR)

An overrun condit ion occurs, when the master de-

vice has sent a data byte and the slave device has

not cleared the SPI F bit issued from the previously

transmitted byte.

When an Ov er ru n oc cu rs:

– The OVR bit is set and an interrupt request is

generated if the SPIE bit is set.

In this case, the receiver buffer contains the byte

sent after the SPIF bit was last cleared. A read to

the SPIDR register returns this byte. All other

bytes are lost.

The OVR bit is cleared by reading the SPICSR

10.5.5.3 Write Collision Error (WCOL)

A write collision occurs when the software tries to

write to the SPIDR register while a data transfer is

taking place with an external device. When this

happens, the transfer continues uninterrupted;

and the software write will be unsuccessful.

Write collisions can occur both in master and slave

mode. See also Section 10.5.3.2 Slave Select

Management.

Note: a "read collision" will never occur since the

received data byte is placed in a buffer in which

access is always synchronou s with the MCU oper-

ation.

The WCOL bit in the SPICSR register is set if a

write collision occurs.

No SPI interrupt is generated when the WCOL bit

is set (the WCOL bit is a status flag only).

Clearing the WCOL bit is done through a software

sequence (see Figure 58).

Figure 58. Clear ing the WCOL bit (Write Collision Flag) Software Sequence

Clearing sequence after SPIF = 1 (end of a data byte transfer)

1st Step Read SPICSR

Read SPIDR

2nd Step SPIF =0

WCOL=0

Clearing sequence before SPIF = 1 (during a data byte transfer)

1st Step

2nd Step WCOL=0

Read SPICSR

Read SPIDR

Note: Writing to the SPIDR regis-

ter instead of reading it does not

reset the WCOL bit

RESULT

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SERIAL PERIPHERAL INTERFACE (Cont’d)

10.5.5.4 Single Master Systems

A typical single master system ma y be configured,

using an MCU as the master and four MCUs as

slaves (see Figure 59).

The master device selects the individual slave de-

vices by using four pins o f a parallel po rt to contro l

the four SS pins of the slave devices.

The SS pins are pulled high during reset sin ce the

master device ports will be forced to be inputs at

that time, thus disabling the slave devices.

Note: To prevent a bus conflict on the MISO line

the master allows only one active slave device

during a transm ission.

For more security, the slave device may respond

to the master with t he received data byte. Then the

master will receive the previous byte back from the

slave device if all MISO and MOSI pins are con-

nected and the slave has not written to its SPIDR

Other transmission security methods can use

ports for handshake lines or data bytes with com-

mand fields.

Figure 59. Single Master / Multiple Slave Configuration

MISO

MOSI

MOSI MOSI MOSIMISO MISO MISOMISO

SS SS SS SS

SCK SCK

SCK

Ports

Slave

MCU

Slave

MCU

Slave

MCU

Slave

MCU

Master

MCU

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SERIAL PERIPHERAL INTERFACE (Cont’d)

10.5.6 Low Po wer Modes

10.5.6.1 Using t he SPI to wakeup the MCU from

Halt mode

In slave configuration, the SPI is able to wakeup

the ST7 device from HALT mode through a SPIF

interrupt. The data received is subsequently read

from the SPIDR register when the software is run-

ning (interrupt vector fetch). If multiple data trans-

fers have been performed before software clears

the SPIF bit, then the OVR bit is set by hardware.

Note: When waking up from Halt mode , if the SPI

remains in Slave mode, it is recommended to per-

form an extra communications cycle to bring the

SPI from Halt mode state to normal state. If the

SPI exits from Slave mode, it returns to normal

state immediately.

Caution: The SPI can wake up the ST7 from Halt

mode only if the Slave Select signal (external SS

pin or the SSI bit in the SPICSR register) is low

when the ST7 enters Halt mode. So if Slave selec-

tion is configured as external (see Section

10.5.3.2), make sure the master drives a low level

on the SS pin when the slave enters Halt mode.

10.5.7 Interrupts

Note: The SPI interrupt events are connected to

the same interrupt vector (see Interrupts chapter).

They generate an interrupt if the corresponding

Enable Control Bit is set and the interrupt mask in

Mode Description

WAIT No effect on SPI.

SPI interrupt events cause the device to exit

from WAIT mode.

HALT

SPI registers are frozen.

In HALT mode, the SPI is inactive. SPI oper-

ation resumes when the MCU is woken up by

an interrupt with “exit from HALT mode” ca-

pability. The data received is subsequently

read from the SPIDR register when the soft-

ware is running (interrupt vector fetching). If

several data are received before the wake-

up event, then an overrun error is generated.

This error can be detected after the fetch of

the interrupt routine that woke up the device. Interrupt Event Event

Flag

Enable

Control

Bit

Exit

from

Wait

Exit

from

Halt

SPI End of Transfer

Event SPIF

SPIE

Yes Yes

Master Mode Fault

Event MODF Yes No

Overrun Error OVR Yes No

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SERIAL PERIPHERAL INTERFACE (Cont’d)

10.5.8 Register Description

CONTROL REGISTER (SP I CR)

Read/Write

Reset Value: 0000 xxxx (0xh)

Bit 7 = SPIE Serial Peripheral Interrupt Enable.

This bit is set and cleared by software.

0: Interrupt is inhibited

1: An SPI interrupt is generated whenever

SPIF=1, MODF=1 or OVR=1 in the SPICSR

Bit 6 = SPE Serial Peripheral Output Enable.

This bit is set and cleared by software. It is also

cleared by hardware when, in m aster mode, SS=0

(see Section 10.5.5.1 Master Mode Fault

(MODF)). The SPE bit is cleared by reset, so the

SPI peripheral is not initially connected to the ex-

ternal pins.

0: I/O pins free for general purpose I/O

1: SPI I/O pin alternate functions enabled

Bit 5 = SPR2 Divider Enable.

This bit is set and cleared by software and is

cleared by reset. It is used with the SPR[1:0] bits to

set the baud rate. Refer to Table 18 SPI Master

mode SCK Frequency.

0: Divider by 2 enable d

1: Divider by 2 disabled

Note: This bit has no effect in slave mode.

Bit 4 = MSTR Master Mode.

This bit is set and cleared by software. It is also

cleared by hardware when, in m aster mode, SS=0

(see Section 10.5.5.1 Master Mode Fault

(MODF)).

0: Slave mode

1: Master mode. The function of the SCK pin

changes from an input to an output and the func-

tions of the MISO and MOSI pins are reversed.

Bit 3 = CPOL Clock Polarity.

This bit is set and clea red b y software. This bit d e-

termines the idle state of the serial Clock. The

CPOL bit affects both the master and slave

modes.

0: SCK pin has a low level idle state

1: SCK pin has a high level idle state

Note: If CPOL is changed at the communication

byte boundaries, the SPI must be disabled by re-

setting the SPE bit.

Bit 2 = CPHA Clock Phase.

This bit is set and cleared by software.

0: The first clock transition is the first data capture

edge.

1: The second clock transition is the first capture

edge.

Note: The slave must have the same CPOL and

CPHA settings as the master.

Bits 1:0 = SPR[1:0] Serial Clock Frequency.

These bits are set and cleared by software. Used

with the SPR2 bi t, they select the bau d rat e of th e

SPI serial clock SCK output by the SPI in master

mode.

Note: These 2 bits have no effect in slave mode.

Table 18. SPI Master mode SCK Frequency

SPIE SPE SPR2 MSTR CPOL CPHA SPR1 SPR0

Serial Clock SPR2 SPR1 SPR0

fCPU/4 1 0 0

fCPU/8 0 0 0

fCPU/16 0 0 1

fCPU/32 1 1 0

fCPU/64 0 1 0

fCPU/128 0 1 1

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SERIAL PERIPHERAL INTERFACE (Cont’d)

CONTROL/STATUS REGISTER (SPICSR)

Read/Write (some bits Read Only)

Reset Value: 0000 0000 (00h)

Bit 7 = SPIF Serial Peripheral Data Transfer Flag

(Read only).

This bit is set by hardware when a transfer has

been completed. An interrupt is generated if

SPIE=1 in the SPICR register. It is cleared by a

software sequence (an access to the SPICSR

SPIDR register).

0: Data transfer is in progress or the flag has been

cleared.

1: Data transfer between the device and an exter-

nal device has been completed.

Note: While the SPIF bit is set, all writes to the

SPIDR register are inh ibited until the SPICSR reg-

ister is read.

Bit 6 = WCOL Write Collision status (Read only).

This bit is set by hardware when a write to the

SPIDR register is done during a transmit se-

quence. It is cleared by a software sequence (see

Figure 58).

0: No write collision occurred

1: A write collision has been detected

Bit 5 = OVR SPI Overrun error (Read only).

This bit is set by hardware whe n the byte cu rrently

being received in the shift register is ready to be

transferred into the SPIDR register while SPIF = 1

(See Section 10.5.5.2). An interrupt is generated if

SPIE = 1 in SPICR register. The OVR bit is cleared

by software re ad in g th e S PICSR register.

0: No overrun error

1: Overrun error detect ed

Bit 4 = MODF Mode Fault flag (Read only).

This bit is set by hardware when the SS pin is

pulled low in master mode (see Section 10.5.5.1

Master Mode Fault (MODF)). An SPI interrupt can

be generated if SPIE=1 in the SPICSR register.

This bit is cleared by a software se que nce (An ac-

cess to the SPICR register while MODF=1 fol-

lowed by a write to the SPICR register).

0: No master mode fa ult detected

1: A fault in master mode has been detected

Bit 3 = Reserved, must be kept cleare d.

Bit 2 = SOD SPI Ou tput Disable.

This bit is set and cleared by sof tware. When set, it

disables the alternate function of the SPI output

(MOSI in master mode / MISO in slave mode)

0: SPI output enabled (if SPE=1)

1: SPI output disabled

Bit 1 = SSM SS Management.

This bit is set and cleared by sof tware. When set, it

disables the alternate function of the SPI SS pin

and uses the SSI bit value instead. See Section

10.5.3.2 Slave Sele ct Management.

0: Hardwa re man age ment (SS managed by exter-

nal pin)

1: Software management (internal SS signal con-

trolled by SSI bit. External SS pin fr ee for gener-

al-purpose I/O)

Bit 0 = SSI SS Internal Mode.

This bit is set and cleared by softwar e. It acts as a

‘chip select’ by controlling the level of the SS slave

select signal when the SSM bit is set.

0 : Slave selected

1 : Slave deselected

DATA I/O REGISTER (SPIDR)

Read/Write

Reset Value: Undefined

The SPIDR register is used to transmit and receive

data on the serial bus. In a master device, a write

to this register will initiate transmission/reception

of another byte.

Notes: During the last clock cycle the SPIF bit is

set, a copy of the received data byte in the shift

the serial peripheral data I/O register, the buffer is

actually being re ad .

While the SPIF bit is set, all writes to the SPIDR

read.

Warning: A write to the SPIDR register places

data directly into the shif t register for transmission.

A read to the SPIDR register returns the value lo-

cated in the buffer and not the content of the shift

SPIF WCOL OVR MODF - SOD SSM SSI

D7 D6 D5 D4 D3 D2 D1 D0

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SERIAL PERIPHERAL INTERFACE (Cont’d)

Table 19. SPI Register Map and Reset Values

Address

(Hex.) Register

Label 76543210

0021h SPIDR

Reset Value MSB

xxxxxxx

LSB

0022h SPICR

Reset Value SPIE

0SPE

0SPR2

0MSTR

0CPOL

xCPHA

xSPR1

xSPR0

0023h SPICSR

Reset Value SPIF

0WCOL

0OR

0MODF

SOD

0SSM

0SSI

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10.6 SERIAL COMMUNICATIONS INTERFACE (SCI)

10.6.1 Introduction

The Serial Communications Interface (SCI) offers

a flexible means of full-duplex data exchange with

external equipment requiring an industry standard

NRZ asynchronous serial data format . The SCI of-

fers a very wide range of baud rates using two

baud rate generator systems.

10.6.2 Main Features

■Full duplex, asynchronous communications

■NRZ standard format (Mark/Space)

■Dual baud rate generator systems

■Independently programmable transmit and

receive baud rates up to 500K baud.

■Programmable data word length (8 or 9 bits)

■Receive buffer full, Transmit buffer empty and

End of Transmission flags

■Two receiver wake-up modes:

– Address bit (MSB)

– Idle line

■Muting function for multiprocessor configurations

■Separate enable bits for Transmitter and

Receiver

■Four error detection flags:

– Overrun error

– Noise error

– Frame error

– Parity error

■Five interrupt sources with flags:

– Transmit data register empty

– Transmission complete

– Receive data register full

– Idle line received

– Overrun error detected

■Parity control:

– Transmits parity bit

– Checks parity of received data byte

■Reduced power consumption mode

10.6.3 General Description

The interface is externally connected to another

device by two pins (see Figure 61):

– TDO: Transmit Data Output. Whe n the tr an smit -

ter and the receiver are disabled, the output pin

returns to its I/O port configuration. When the

transmitter and/or the receiver are enabled and

nothing is to be transmitted, the TDO pin is at

high level.

– RDI: Receive Data Input is the serial da ta input .

Oversamplin g tec hn iq ue s ar e used for data re-

covery by discriminati ng between valid incoming

data and noise.

Through these pins, serial data is transmitted and

received as frames comprising:

– An Idle Line prior to transmission or reception

– A start bit

– A data word (8 or 9 bits) least significant bit first

– A Stop bit indicating that the frame is complete.

This interface uses two types of baud rate generator:

– A conventional type for commonly-used baud

rates,

– An extended type with a prescaler offering a very

wide range of baud rates even with non-standard

oscillator frequencies.

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SERIAL COMMUNICATIONS INTERFACE (Cont’d)

Figure 60. SCI Block Diagram

WAKE

UNIT RECEIVER

CONTROL

TRANSMIT

CONTROL

TDRE TC RDRF IDLE OR NF FE PE

SCI

CONTROL

INTERRUPT

CR1

R8 T8 SCID M WAKE PCE PS PIE

Received Data Register (RDR)

Received Shift Register

Read

Transmit Data Register (TDR)

Transmit Shift Register

Write

RDI

TDO

(DATA REGISTER) DR

TRANSMITTER

CLOCK

RECEIVER

CLOCK

RECEIVER RATE

TRANSMITTER RATE

BRR

SCP1

fCPU

CONTROL

SCP0SCT2 SCT1SCT0SCR2 SCR1SCR0

/PR

/16

CONVENTIONAL BAUD RATE GENERATOR

SBKRWURETEILIERIETCIETIE

CR2

ST72F521, ST72521B

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SERIAL COMMUNICATIONS INTERFACE (Cont’d)

10.6.4 Functional Description

The block diagram of the Serial Control Interface,

is shown in Figure 60. It contains 6 dedicated reg-

isters:

– Two control registers (SCICR1 & SCICR2)

– A status register (SCISR)

– A baud rate register (SCIBRR)

– An extended prescaler receiver r egister (SCIER-

PR)

– An extended prescaler transmitter register (SCI-

ETPR)

Refer to the register descriptions in Section

10.6.7for the definitions of each bit.

10.6.4.1 Serial Data Format

Word length may be selected as being either 8 or 9

bits by programming the M bit in the SCICR1 reg-

ister (see Figure 60).

The TDO pin is in low state during t he start bit.

The TDO pin is in high state during the stop bit.

An Idle character is interpreted as an entire frame

of “1”s followed by the start bit of the next frame

which contains data.

A Break cha racter is interprete d on receiving “0 ”s

for some multiple of the frame period. At the end of

the last break frame the transmitter inserts an ex-

tra “1” bit to acknowledge the start bit.

Transmission and reception are driven by their

own baud rate generator.

Figure 61. Word Length Programming

Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit8

Start

Bit Stop

Bit

Start

Bit

Idle Frame

Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7

Start

Bit Stop

Bit

Start

Bit

Start

Bit

Idle Frame Start

Bit

9-bit Word length (M bit is set)

8-bit Word length (M bit is reset)

Possible

Parity

Bit

Possible

Parity

Bit

Break Frame Start

Bit

Extra

’1’

Data Frame

Break Frame Start

Bit

Extra

’1’

Data Frame

Next Data Frame

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SERIAL COMMUNICATIONS INTERFACE (Cont’d)

10.6.4.2 Transmitter

The transmitter can send data words of eithe r 8 or

9 bits depending on the M bit status. When the M

bit is set, word length is 9 bits and the 9th bit (the

MSB) has to be st ored in the T8 bit in the SCICR1

Character Tran smission

During an SCI transmission, data shifts out least

significant bit first on the TDO pin. In this mode,

the SCIDR register consists of a buffer (TDR) be-

tween the interna l bus and th e tr ansm it shif t regi s-

ter (see Figure 60).

Procedure

– Select the M bit to define the word length.

– Select the desired baud rate using the SCIBRR

and the SCIETPR registers.

– Set the TE bit to assign the TDO pin to the alte r-

nate function and to send a idle frame as first

transmission.

– Access the SCISR register and write the dat a to

send in the SCIDR register (this sequence clears

the TDRE bit). Repe at this sequence for each

data to be transmitted.

Clearing th e TDRE bit is always perfor med by th e

following softw ar e sequ e nc e:

1. An access to the SCIS R regi st er

2. A write to the SCIDR register

The TDRE bit is set by hardware and it indicates:

– The TDR register is empty.

– The data transfer is beginning.

– The next data can be written in the SCIDR regis-

ter without overwriting the previous data.

This flag generates an interrupt if the TIE bit is set

and the I bit is cleared in the CCR register.

When a transmission is taking place, a write in-

struction to the SCIDR register stores the data in

the TDR register and which is copied in the shift

When no transmission is taking place, a write in-

struction to the SCIDR register places the data di-

rectly in the shift register, the data transmission

starts, and the TDRE bit is immediately set.

When a frame transmission is complete (after the

stop bit or after the break frame) the TC bit is set

and an interrupt is generated if the TCIE is se t and

the I bit is cleared in th e CCR register.

Clearing the TC bit is performed by the following

software sequence:

1. An access to the SCISR register

2. A write to the SCIDR register

Note: The TDRE and TC bits are cleared by the

same software sequence.

Break Characters

Setting the SBK bit loads the shift register with a

break character. The break frame length depends

on the M bit (see Figure 61).

As long as the SBK bit is set, the SCI send break

frames to the TDO pin. After clearing this bit by

software the SCI insert a logic 1 bit at the end of

the last break frame to guarantee the recognition

of the start bit of the next frame.

Idle Characters

Setting the TE bit drives the SCI to send an idle

frame before the first data frame.

Clearing and t hen setting the TE bit dur ing a trans-

mission sends an idle frame after the curren t word.

Note: Resetting and setting the TE bit causes the

data in the TDR register to be lost. Therefore the

best time to toggle the TE bit is when the TDRE bit

is set i.e. before writing the next byte in the SCIDR.

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SERIAL COMMUNICATIONS INTERFACE (Cont’d)

10.6.4.3 Recei ver

The SCI can receive data words of either 8 or 9

bits. When the M bit is set, word length is 9 bits

and the MSB is stored in the R8 bit in the SCICR1

Character reception

During a SCI reception, data shifts in least signifi-

cant bit first thro ugh the RDI pin . In this mo de, the

SCIDR register consists or a buffer (RDR) be-

tween the inte rnal bus and the received shift r egis-

ter (see Figure 60).

Procedure

– Select the M bit to define the word length.

– Select the desired baud rate using the SCIBRR

and the SCIERPR registers.

– Set the RE bit, this enables the receiver which

begins searching for a start bit.

When a character is received:

– The RDRF bit is set. It indicates that th e content

of the shift register is transferred to the RDR.

– An interrupt is generated if the RIE bit is set and

the I bit is cleared in the CCR register.

– The error flags can be set if a fr ame error , noise

or an overrun er r or has been de te cte d durin g r e-

ception.

Clearing the RDRF bit is performed by the following

software sequence done by:

1. An access to the SCIS R regi st er

2. A read to the SCIDR register.

The RDRF bit must be cleared before the end of the

reception of the next ch aracter to avo id an overrun

error.

Break Character

When a break character is received, the SPI han-

dles it as a framing error.

Idle Character

When a idle frame is detected, there is the same

procedure as a dat a received cha racter plus an in-

terrupt if the ILI E bit is set and the I bit is cleared in

the CCR register.

Overrun Error

An overrun error occurs when a character is re-

ceived when RDR F has not been reset. Data can

not be transferred from the shift register to the

RDR register as long as the RDRF bit is not

cleared.

When a overrun error occurs:

– The OR bit is set.

– The RDR content will not be lost.

– The shift register will be overwritten.

– An interrupt is generat ed if the RIE bi t is set a nd

the I bit is cleared in the CCR register.

The OR bit is reset by an access to the SCISR reg-

ister followed by a SCIDR register read operation.

Noise Error

Oversampling techniques are used for data recov-

ery by discriminating between valid incoming data

and noise. Normal data bit s are co nsidered va lid if

three consecutive samples (8th, 9th, 10th) have

the same bit value, other wise the NF flag is set. In

the case of start bit dete ction, the NF fla g is set on

the basis of an algorithm combining both valid

edge detectio n an d thr ee sam ples (8t h, 9th, 10t h).

Therefore, to prevent the NF flag gett ing set during

start bit recep tion, there should be a valid edge de-

tection as well as three valid samples.

When noise is detected in a frame:

– The NF flag is set at the rising edge of the RDRF

bit.

– Data is transferred from the Shift register to the

SCIDR register.

– No interrupt is generated. However this bit rises

at the same time as the RDRF bit which itself

generates an interr u pt.

The NF flag is reset by a SCISR register read op-

eration followed by a SCIDR register read opera-

tion.

During reception, if a false start bit is detected (e.g.

8th, 9th, 10th samples are 011,101,110), the

frame is discarded and the receiving sequence is

not started for this frame. There is no RDRF bit set

for this frame and the NF flag is set internally (not

accessible to the user). This NF flag is accessible

along with the RDRF bi t when a next valid fr ame is

received.

Note: If the ap plication Start Bit is not long enough

to match the above requirements, then the NF

Flag may get set due to the short Start Bit. In this

case, the NF flag may be ignored by the applica-

tion software when the first valid byte is received.

See also Section 10.6.4.10.

ST72F521, ST72521B

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SERIAL COMMUNICATIONS INTERFACE (Cont’d)

Figure 62. SCI Baud Rate and Extended Prescaler Bloc k Diagram

TRANSMITTER

RECEIVER

SCIETPR

SCIERPR

EXTENDED PRESCAL ER RECEIVER RATE CONTROL

EXTENDED PRESCALER TRANSMITTER RATE CONTROL

EXTENDED PRESCALER

CLOCK

RECEIVER RATE

TRANSMITTER RATE

SCIBRR

SCP1

fCPU

CONTROL

SCP0SCT2 SCT1SCT0SCR2 SCR1SCR0

/PR

/16

CONVENTIONAL BAUD RATE GENERATOR

EXTENDED RECEIVER PRESCALER REGISTER

EXTENDED TRANSMITTER PRESCALER REGISTER

ST72F521, ST72521B

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SERIAL COMMUNICATIONS INTERFACE (Cont’d)

Framing Error

A framing erro r is de te cte d wh en :

– The stop bit is not recognized on reception at the

expected time, following either a de-synchroni-

zation or excessive noise.

– A break is rec eiv ed .

When the fram in g error is detecte d:

– the FE bit is set by hardware

– Data is transferred from the Shift register to the

SCIDR register.

– No interrupt is generated . However this bit ri ses

at the same time as the RDRF bit which itself

generates an interrupt.

The FE bit is reset by a SCISR register read oper-

ation followed by a SCIDR registe r read operation.

10.6.4.4 Conventional Baud Rate Generation

The baud rate for the receiver and transmitter (Rx

and Tx) are set independently and calculated as

follows:

with:

PR = 1, 3, 4 or 13 (see SCP[1:0] bits)

TR = 1, 2, 4, 8, 16, 32, 64,12 8

(see SCT[2:0] bits)

RR = 1, 2, 4, 8, 16, 32, 64,128

(see SCR[2:0] bits)

All these bits are in the SCIBRR register.

Example: If fCPU is 8 MHz (normal mode) and if

PR=13 and TR=RR=1, the transmit and receive

baud rates are 38400 baud.

Note: the baud rate registers MUST NOT be

changed while the transmitter or the receiver is en-

abled.

10.6.4.5 Extended Baud Rate Generation

The extended prescaler option gives a very fine

tuning on the bau d rate, using a 255 value prescal-

er, whereas the conventional Baud Rate Genera-

tor retains industry standard software compatibili-

ty.

The extended baud rate generator block diagram

is described in the Figure 62.

The output clock rate sent to the transmitter or to

the receiver will be the output from the 16 divider

divided by a factor ran ging from 1 to 255 set in the

SCIERPR or the SCIE TPR reg iste r .

Note: the extended prescaler is activated by set-

ting the SCIETPR or SCIERPR register to a value

other than zero. The baud rates are calculated as

follows:

with:

ETPR = 1,..,255 (see SCIETPR register)

ERPR = 1,.. 255 (see SCIERPR register)

10.6.4.6 Receiver Muting and Wake-up Feature

In multiprocessor configurations it is often desira-

ble that only the intended message recipient

should actively receive the full message contents,

thus reducing redundant SCI service overhead for

all non addressed receivers.

The non addressed devices may be placed in

sleep mode by means of the mutin g function.

Setting the RWU bit by software puts the SCI in

sleep mode:

All the reception status bits can not be set.

All the receive interrupts are inhibited.

A muted receiver may be awakened by one of the

following two ways:

– by Idle Line detection if the WAKE bit is reset,

– by Address Mark detection if the WAKE bit is set.

Receiver wakes-up by Idle Line detection when

the Receive line has recognised an Idle Frame.

Then the RWU bit is reset by hardware but the

IDLE bit is not set.

Receiver wakes-up by Address Mark detection

when it received a “1” as the most signif icant bit of

a word, thus indicating that the message is an ad-

dress. The reception of this particular word wakes

up the receiver, resets the RWU bit and sets the

RDRF bit, which allows the receiver to receive this

word normally and to use it as an address word.

Caution: In Mute mode, do not write to the

SCICR2 register. If the SCI is in Mute mode during

the read operation (RWU=1) and a address mark

wake up event occurs (RWU is reset) before the

write operation, the RWU bit will be set again by

this write operation. Consequently the address

byte is lost and t he SCI is not woken up from Mute

mode.

Tx = (16*PR)*TR

fCPU Rx =

(16*PR)*RR

fCPU

Tx =

16*ETPR*(PR*TR)

fCPU Rx =

16*ERPR*(PR*RR)

fCPU

ST72F521, ST72521B

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SERIAL COMMUNICATIONS INTERFACE (Cont’d)

10.6.4.7 Parity Control

Parity control (generation of parity bit in transmis-

sion and parity checking in reception) can be ena-

bled by setting the PCE bit in the SCIC R1 register.

Depending on the frame length defined by the M

bit, the possible SCI frame formats are as list ed in

Table 20.

Table 20. Frame Formats

Legend: SB = Start Bit, STB = Stop Bit,

PB = Parity Bit

Note: In case of wake up by an address mark, the

MSB bit of the data is taken into account and not

the parity bit

Even parity: the parity bit is calculated to obtain

an even number of “1s” inside the frame made of

the 7 or 8 LSB bits (depending on whether M is

equal to 0 or 1) and the parity bit.

Ex: data=00110101; 4 bits set => parity bit will be

0 if even parity is selected (PS bit = 0).

Odd parity: the pa rity bit is calculat ed to obtain an

odd number of “1s” inside the fram e made of th e 7

or 8 LSB bits (depending on whethe r M is equal to

0 or 1) and the parity bit.

Ex: data=00110101; 4 bits set => parity bit will be

1 if odd parity is selected (PS bit = 1).

Transmission mode: If the PCE bit is set then the

MSB bit of the data written in the data register is

not transmit te d bu t is cha nge d by the parity bit.

Reception mode: If the PCE bit is set then the in-

terface checks if the received data byte has an

even number of “1s” if even parity is selected

(PS=0) or an odd number of “1s” if odd parity is se-

lected (PS=1). If the parity check fails, the PE flag

is set in the SCISR r egister and an interrupt is ge n-

erated if PIE is set in the SCICR1 register.

10.6.4.8 SCI Clock Tol erance

During reception, each bit is sampled 16 times.

The majority of the 8th, 9th and 10th samples is

considered as the bit value. For a valid bit detec-

tion, all the three samples should have the same

value otherwise the noise flag (NF) is set. For ex-

ample: if the 8th, 9th and 10th samples are 0, 1

and 1 respectively, then the bit value will be “1”,

but the Noise Flag bit is be set because the three

samples values are not the same.

Consequently, the bit length must be long enough

so that th e 8th, 9t h and 10t h samples have th e de-

sired bit value. This means the clock frequency

should not vary more than 6/ 16 (37.5%) within one

bit. The sampling clock is resynchronized at each

start bit, so that when receiving 10 bits (one start

bit, 1 data byte, 1 stop bit), the clock deviation

must not exceed 3.75%.

Note: The internal sampling clock of the microcon-

troller samples the pi n value on every fa lling edge.

Therefore, the internal sampling clock and the time

the application expect s the sampling to take place

may be out of sync. For example: If the baud rate

is 15.625 kbaud (bit length is 64µs), then the 8th,

9th and 10th samples will be at 28µs, 32µs & 36µs

respectively (the first sample starting ideally at

0µs). But if the falling edge of the internal clock oc-

curs just before the pin value changes, the sam-

ples would then be out of sync by ~4us. This

means the entire bit length must be at least 40µs

(36µs for the 10th sample + 4µs for synchroniza-

tion with the internal sampling clock).

M bit PCE bit SCI frame

0 0 | SB | 8 bit data | STB |

0 1 | SB | 7-bit data | PB | STB |

1 0 | SB | 9-bit data | STB |

1 1 | SB | 8-bit data PB | STB |

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SERIAL COMMUNICATIONS INTERFACE (Cont’d)

10.6.4.9 Clock Deviation Causes

The causes which contribute to the total deviation

are:

–D

TRA: Deviation due to transmitter error (Local

oscillator error of the transmitter or the trans-

mitter is transmitting at a different baud rate).

–D

QUANT: Error due to the baud rate quantisa-

tion of the receiver.

–D

REC: Deviation of the local oscillator of the

receiver: This deviation can occur during the

reception of one complete SCI message as-

suming that the deviation has been compen-

sated at the beginning of the message.

–D

TCL: Deviation due to the transmission line

(generally due to the transceivers)

All the deviations of the system should be added

and compared to the SCI clock tolerance:

DTRA + DQUANT + DREC + DTCL < 3.75%

10.6.4.10 Noise Error Causes

See also description of Noise error in Section

10.6.4.3.

Start bit

The noise flag (NF) is set durin g start bit recept ion

if one of the following conditions occurs:

1. A valid falling edge is not detected. A falling

edge is considered to be valid if the 3 consecu-

tive samples before the falling edge occurs are

detected as '1' and, after the falling edge

occurs, during the sampling of the 16 samples,

if one of the samples numbered 3, 5 or 7 is

detected as a “1”.

2. During samplin g of th e 16 sa mples, if o ne of the

samples numbered 8, 9 or 10 is detected as a

“1”.

Therefore, a valid Start Bit must satisfy both the

above conditions to pre vent the Noise Flag getting

set.

Data Bits

The noise flag (NF) is set during normal data bit re-

ception if the following condition occurs:

– During the sampling of 16 samples, if all three

samples numbered 8, 9 and10 are not the same.

The majority of the 8th, 9th and 10th samples is

considered as the bit value.

Therefore, a valid Data Bit must have samples 8, 9

and 10 at the same value to prevent the Noise

Flag getting set.

Figure 63. Bit Sampling in Receptio n Mode

RDI LINE

Sample

clock 1234567891011

12 13 14 15 16

sampled values

One bit time

6/16

7/16 7/16

ST72F521, ST72521B

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SERIAL COMMUNICATIONS INTERFACE (Cont’d)

10.6.5 Low Po wer Modes

10.6.6 Interrup ts

The SCI interrupt events are connected to the

same interrupt vector.

These events generate an interrupt if the corre-

sponding Enable Control Bit is set and the inter-

rupt mask in the CC register is reset (RIM instruc-

tion).

Mode Description

WAIT No effect on SCI.

SCI interrupts cause the device to exit

from Wait mode.

HALT

SCI registers are frozen.

In Halt mode, the SCI stops transmit-

ting/receiving until Halt mode is exit-

ed.

Interrupt Event Event

Flag

Enable

Control

Bit

Exit

from

Wait

Exit

from

Halt

Transmit Data Register

Empty TDRE TIE Yes No

Transmission Com-

plete TC TCIE Yes No

Received Data Ready

to be Read RDRF RIE Yes No

Overrun Error Detected OR Yes No

Idle Line Detected IDLE ILIE Yes No

Parity Error PE PIE Yes No

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SERIAL COMMUNICATIONS INTERFACE (Cont’d)

10.6.7 Register Description

STATUS REGISTER (SCISR)

Read Only

Reset Value: 1100 0000 (C0h)

Bit 7 = TDRE Transmit data register empty.

This bit is set by hardware when the content of the

TDR register has been transferred into the shift

in the SCICR2 register. It is cleared by a software

sequence (an access to the SCISR register fol-

lowed by a write to the SCIDR r egister).

0: Data is not tran sferred to the shift register

1: Data is transferred to the shift register

Note: Data will not be transfer red to the shift reg-

ister unless the TDRE bit is cleared.

Bit 6 = TC Transmission complete.

This bit is set by hardware when tra nsmission of a

frame contain ing Data is complete . An interrupt is

generated if TCIE=1 in the SCICR2 register. It is

cleared by a software sequence (an access to the

SCISR register followed by a write to the SCIDR

0: Transmission is not complete

1: Transmission is complete

Note: TC is no t set afte r the transmission of a Pre-

amble or a Break.

Bit 5 = RDRF Received data ready flag.

This bit is set by hardware when the content of the

RDR register has been transferred to the SCIDR

SCICR2 register. It is cleared by a software se-

quence (an access to the SCISR register followed

by a read to the SC ID R reg i st er ).

0: Data is not received

1: Received data is ready to be read

Bit 4 = IDLE Idle line detect.

This bit is set by hardware when a Idle Line is de-

tected. An interrupt is generated if the ILIE=1 in

the SCICR2 register. It is cleare d by a software se-

quence (an access to the SCISR register followed

by a read to the SC ID R reg i st er ).

0: No Idle Line is detected

1: Idle Line is detected

Note: The IDLE bit will not be set again until the

RDRF bit has been set itself (i.e. a new idle line oc-

curs).

Bit 3 = OR Overrun error.

This bit is set by hardware when the wo rd currently

being received in the shift register is ready to be

transferred into the RDR register while RDRF=1.

An interrupt is generated if RIE=1 in the SCICR2

access to the SCISR register followed by a read to

the SCIDR register).

0: No Overrun error

1: Overrun error is detected

Note: When this bit is set RDR register content will

not be lost but the shift register will be overwritten.

Bit 2 = NF Noise flag.

This bit is set by hardware when noise is detected

on a received frame . It is cleared by a so ftware se-

quence (an access to the SCISR register followed

by a read to the SCID R reg ist er ).

0: No noise is detect ed

1: Noise is detected

Note: This bit does not gen erate int errupt as it ap-

pears at the same time as the RDRF bit which it-

self generates an interrupt.

Bit 1 = FE Framin g error.

This bit is set by hardware when a de-synchroniza-

tion, excessive noise or a break character is de-

tected. It is cleared by a software sequence (an

access to the SCISR register followed by a read to

the SCIDR register).

0: No Framing error is detected

1: Framing erro r or break character is detected

Note: This bit does not gen erate int errupt as it ap-

pears at the same time as the RDRF bit which it-

self generates an interrupt. If the word currently

being transferred causes both frame error and

overrun error, it will be transferred and only the OR

bit will be set.

Bit 0 = PE Parity error.

This bit is set by hardware when a parity error oc-

curs in receiver mode. It is cleared by a software

sequence (a read to the sta tus register followed by

an access to the SCIDR data register). An inter-

rupt is generated if PIE=1 in the SCICR1 regist er.

0: No parity error

1: Parity error

TDRE TC RDRF IDLE OR NF FE PE

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SERIAL COMMUNICATIONS INTERFACE (Cont’d)

CONTROL RE GISTER 1 (SCICR1)

Read/Write

Reset Value: x000 0000 (x0h)

Bit 7 = R8 Receive data bit 8.

This bit is used to store the 9th bit of the received

word when M=1.

Bit 6 = T8 Transm it da ta bit 8.

This bit is used to store the 9th bit of the transmit-

ted word when M=1.

Bit 5 = SCID Disabled for low power consumption

When this bit is set the SCI pr escalers and outputs

are stopped and the end of the current byte trans-

fer in order to reduce power consumption.This bit

is set and cleared by so ftware.

0: SCI enabled

1: SCI prescaler and outputs disabled

Bit 4 = M Word length.

This bit determines the word length. It is set or

cleared by software.

0: 1 Start bit, 8 Data bits, 1 Stop bit

1: 1 Start bit, 9 Data bits, 1 Stop bit

Note: The M bit must not be modified during a data

transfer (both transmission and reception).

Bit 3 = WAKE Wake-Up method.

This bit determines the SCI Wake-Up method , it is

set or cleared by software.

0: Idle Line

1: Address Mark

Bit 2 = PCE Parity control enable.

This bit selects the hardwa re parity control (gene r-

ation and detection). Wh en the parity control is en-

abled, the computed parity is inserted at the MSB

position (9th bit if M=1; 8th bit if M=0) and parity is

checked on the received data. This bit is set and

cleared by software. Once it is set, PCE is active

after the curr ent byte (in reception and in tr ansmis-

sion).

0: Parity control disabled

1: Parity control enabled

Bit 1 = PS Parity selection.

This bit selects the odd or even parity when the

parity generation/detection is enabled (PCE bit

set). It is set and cleared by software. The parity

will be selected after the current byte.

0: Even parity

1: Odd parity

Bit 0 = PIE Parity interrupt enable.

This bit enables the interrupt capability of the hard-

ware parity control when a parity error is detected

(PE bit set). It is set and cleared by software.

0: Parity error interrupt disabled

1: Parity error int errupt enabled.

R8 T8 SCID M WAKE PCE PS PIE

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SERIAL COMMUNICATIONS INTERFACE (Cont’d)

CONTROL RE GISTER 2 (SCICR2)

Read/Write

Reset Value: 0000 0000 (00h)

Bit 7 = TIE Transmitter interrupt enable.

This bit is set and cleared by software.

0: Interrupt is inhibited

1: An SCI interrupt is generated whenever

TDRE=1 in the SCISR register

Bit 6 = TCIE Tran smission co mplete interr upt ena-

ble

This bit is set and cleared by software.

0: Interrupt is inhibited

1: An SCI interrupt is generated whenever TC=1 in

the SCISR register

Bit 5 = RIE Receiver interrupt enable.

This bit is set and cleared by software.

0: Interrupt is inhibited

1: An SCI interrupt is generated whenever OR=1

or RDRF=1 in the SCISR register

Bit 4 = ILIE Idle line interrupt enable.

This bit is set and cleared by software.

0: Interrupt is inhibited

1: An SCI interrupt is generated whenever IDLE=1

in the SCISR register.

Bit 3 = TE Transmitter enable.

This bit enables the transmitter. It is set and

cleared by software.

0: Transmitt er is disabled

1: Transmitter is enabled

Notes:

– During transmission, a “0” pulse on the TE bit

(“0” followed by “1” ) sends a preamble ( idle line)

after the current word.

– When TE is set there is a 1 bit-time delay before

the transmission starts.

Caution: The TDO pin is free for general purpose

I/O only when th e TE and RE b its are both cleared

(or if TE is never set).

Bit 2 = RE Receiver enable.

This bit enables the receiver. It is set and cleared

by softwar e.

0: Receiver is disabled

1: Receiver is enabled and be gins searching for a

start bit

Bit 1 = RWU Receiver wake-up.

This bit determines if the SCI is in mute mode or

not. It is set and cleared by software and can be

cleared by hardware when a wake- up sequence is

recognized.

0: Receiver in Active mode

1: Receiver in Mute mode

Note: Before selecting Mute mode (setting the

RWU bit), the SCI must receive some data first,

otherwise it cannot function in Mute mode with

wakeup by idle line detection.

Bit 0 = SBK Send break.

This bit set is used to send break characters. It is

set and cleared by software.

0: No break character is transmitted

1: Break characters are transmitted

Note: If the SBK bit is set to “1” and then to “0”, the

transmitter will send a BREAK word at the end of

the current word.

TIE TCIE RIE ILIE TE RE RWU SBK

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SERIAL COMMUNICATIONS INTERFACE (Cont’d)

DATA REGISTER (SCIDR)

Read/Write

Reset Value: Undefined

Contains the Received or Transmitted data char-

acter, depending on whet her it is read from or writ-

ten to.

The Data register performs a double function (read

and write) since it is composed of two registers,

one for transmission (TDR) and one for reception

(RDR).

The TDR register provides the parallel interface

between the internal bus and the output shift reg-

ister (see Figure 60).

The RDR register provides the parallel interface

between the input shift register and the internal

bus (see Figure 60).

BAUD RATE REGISTER (SCIBRR)

Read/Write

Reset Value: 0000 0000 (00h)

Bits 7:6= SCP[1:0] First SCI Prescaler

These 2 prescaling bits allow several standard

clock division ranges:

Bits 5:3 = SCT[2:0] SCI Transmitter rate divisor

These 3 bits, in conjunction with the SCP1 & SCP0

bits define the total division applied to the bus

clock to yield the transmit rate clock in convention-

al Baud Rate Generator mode.

Bits 2:0 = SCR[2:0] SCI Receiver rate divisor.

These 3 bits, in conjunction with the SCP[1:0] bits

define the total division applied to the bus clock to

yield the receive rate clock in conventional Baud

Rate Generator mode.

DR7 DR6 DR5 DR4 DR3 DR2 DR1 DR0

SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1 SCR0

PR Prescaling factor SCP1 SCP0

100

301

410

13 1 1

TR dividing factor SCT2 SC T1 SCT0

1000

2001

4010

8011

16 1 0 0

32 1 0 1

64 1 1 0

128 1 1 1

RR Dividing factor SCR2 SCR1 SCR0

1000

2001

4010

8011

16 1 0 0

32 1 0 1

64 1 1 0

128 1 1 1

ST72F521, ST72521B

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SERIAL COMMUNICATIONS INTERFACE (Cont’d)

EXTENDED RECEIVE PRESCALER DIVISION

Read/Write

Reset Value: 0000 0000 (00h)

Allows setting of the Extended Prescaler rate divi-

sion factor fo r the receive circuit.

Bits 7:0 = ERPR[7:0] 8-bit Extended Receive

Prescaler Register.

The extended Baud Rate Generator is activated

when a value different from 00h is stored in this

from the 16 divider (see Figure 62) is divided by

the binary factor set in the SCIERPR register (in

the range 1 to 255).

The extended baud rate generator is not used af-

ter a reset .

EXTENDED TRANSMIT PRESCA LER DIVISION

Read/Write

Reset Value:0000 0000 (00h)

Allows setting of the External Prescaler rate divi-

sion factor for the transmit circuit.

Bits 7:0 = ETPR[7:0] 8-bit Extended Transmit

Prescaler Register.

The extended Baud Rate Generator is activated

when a value different from 00h is stored in this

from the 16 divider (see Figure 62) is divided by

the binary factor set in the SCIETPR register (in

the range 1 to 255).

The extended baud rate generator is not used af-

ter a reset.

Table 21. Baudrat e Selection

ERPR

7ERPR

6ERPR

5ERPR

4ERPR

3ERPR

2ERPR

1ERPR

ETPR

7ETPR

6ETPR

5ETPR

4ETPR

3ETPR

2ETPR

1ETPR

Symbol Parameter Conditions Standard Baud

Rate Unit

fCPU Accuracy

vs. Standard Prescaler

fTx

fRx Communication frequency 8MHz

~0.16%

Conventional Mode

TR (or RR)=128, PR=13

TR (or RR)= 32, PR=13

TR (or RR)= 16, PR=13

TR (or RR)= 8, PR=13

TR (or RR)= 4, PR=13

TR (or RR)= 16, PR= 3

TR (or RR)= 2, PR=13

TR (or RR)= 1, PR=13

300

1200

2400

4800

9600

10400

19200

38400

~300.48

~1201.92

~2403.84

~4807.69

~9615.38

~10416.67

~19230.77

~38461.54

~0.79% Extended Mode

ETPR (or ERPR) = 35,

TR (or RR)= 1, PR=1 14400 ~14285.71

ST72F521, ST72521B

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SERIAL COMMUNICATION INTERFACE (Cont’d)

Table 22. SCI Register Map and Reset Values

Address

(Hex.) Register

Label 76543210

0050h SCISR

Reset Value TDRE

1TC

1RDRF

0IDLE

0OR

0NF

0FE

0PE

0051h SCIDR

Reset Value MSB

xxxxxxx

LSB

0052h SCIBRR

Reset Value SCP1

0SCP0

0SCT2

0SCT1

0SCT0

0SCR2

0SCR1

0SCR0

0053h SCICR1

Reset Value R8

xT8

0SCID

0WAKE

0PCE

0PS

0PIE

0054h SCICR2

Reset Value TIE

0TCIE

0RIE

0ILIE

0TE

0RE

0RWU

0SBK

0055h SCIERPR

Reset Value MSB

0000000

LSB

0057h SCIPETPR

Reset Value MSB

0000000

LSB

ST72F521, ST72521B

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10.7 I2C BUS INTERFACE (I2C)

10.7.1 Introduction

The I2C Bus Interface serves as an interface be-

tween the microcon trolle r and the ser ial I 2C b us . I t

provides both multimaster and slave functions,

and controls all I2C bus-specific sequencing, pro-

tocol, arbitration and timing. It supports fast I2C

mode (400kHz).

10.7.2 Main Features

■Parallel-bus/I2C protocol converter

■Multi-master capability

■7-bit/10-bit Addressing

■SMBus V1.1 Compliant

■Transmitter/Receiver flag

■End-of-byte transmission flag

■Transfer problem detection

I2C Master Features:

■Clock generation

■I2C bus busy flag

■Arbitration Lost Flag

■End of byte transmission flag

■Transmitter/Receiver Flag

■Start bit detection flag

■Start and Stop generation

I2C Slave Featur es:

■Stop bit detect ion

■I2C bus busy flag

■Detection of misplaced start or stop condition

■Programmable I2C Address detection

■Transfer problem detection

■End-of-byte transmission flag

■Transmitter/Receiver flag

10.7.3 General Description

In addition to receiving and transm itting data, this

interface converts it from serial to parallel format

and vice versa, using either an interrupt or polled

handshake. The interrupt s are enabled or disabled

by software. The interface is connected to the I2C

bus by a data pin (SDAI ) and by a clock pin (SCLI).

It can be connected both with a standard I2C bus

and a Fast I2C bus. This selection is made by soft-

ware.

Mode Selection

The interface can operate in the four following

modes:

– Slave transmitter/receiver

– Master transmitter/receiver

By default, it operates in slave mode.

The interface automat ically switches from slave to

master after it generates a START condition and

from master to sla ve in case of arbitratio n loss or a

STOP generation, allowing then Multi-Master ca-

pability.

Communication Flow

In Master mode, it initiates a data transfer and

generates the clock signal. A serial data transfer

always begins with a start condit ion and ends with

a stop condition . Both start and stop conditions are

generated in master mode by software.

In Slave mode, the interface is capable of recog-

nising its own address (7 or 10-bit), and the Gen-

eral Call address. The General Call address de-

tection may be enabled or disabled by software.

Data and addre sses are transferred a s 8-bit bytes,

MSB first. Th e first byte(s ) following the st art con-

dition contain the address (one in 7-bit mode, two

in 10-bit mode). The address is always transmitted

in Master mode.

A 9th clock pulse follows the 8 clock cycles of a

byte transfer, dur ing which t he rece ive r must send

an acknowledge bit to the tra nsmitter. Refer to Fig-

ure 64.

Figure 64. I2C BUS Protocol

SCL

SDA

12 89

MSB ACK

STOP

START CONDITION

CONDITION VR02119B

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I2C BUS INTERFACE (Cont’d)

Acknowledge may be enabled and disabled by

software.

The I2C interface address and/or general call ad-

dress can be selected by software.

The speed of the I2C interface may be selected

between Standard (up to 100KHz) and Fast I2C

(up to 400KHz).

SDA/SCL Line Control

Transmitter mode: the interface holds the clock

line low before transmission to wait for the micro-

controller to write t he byte in the Data Register.

Receiver mode: the interface holds the clock line

low after reception to wait for the micr ocontroller to

read the byte in the Data Register.

The SCL frequency (Fscl) is controlled by a pro-

grammable clock divider which depends on the

I2C bus mode.

When the I2C cell is enabled, the SDA and SCL

ports must be configured as floating inputs. In this

case, the value of the external pull-up resistor

used depends on the application.

When the I2C cell is disabled, the SDA and SCL

ports revert to being standard I/O port pins.

Figure 65. I2C Interface Block Diagram

DATA REGISTER (DR)

DATA SHIFT REGISTER

COMPARATOR

OWN ADDRESS REGIST ER 1 (OAR1)

CLOCK CONTROL REGISTER (CCR)

STATUS REGISTER 1 (SR1)

CONTROL REGISTER (CR)

CONTROL LOGIC

STATUS REGISTER 2 (SR2)

INTERRUPT

CLOCK CONTROL

DATA CONTROL

SCL or SCLI

SDA or SDAI

OWN ADDRESS REGIST ER 2 (OAR2)

ST72F521, ST72521B

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I2C BUS INTERFACE (Cont’d)

10.7.4 Functional Description

Refer to the CR, SR1 and SR2 registers in Section

10.7.7. for the bit definitions.

By default the I2C interface operates in Slave

mode (M/SL bit is cleared) except when it initiates

a transmit or receive sequence.

First the interface frequency must be configured

using the FRi bits in the OAR2 register.

10.7.4.1 Slave Mode

As soon as a start condition is detected, the

address is receiv ed from the SDA line an d sent to

the shift register; then it is compared with the

address of the interface or the General Call

address (if selected by software).

Note: In 10-bit addressing mode, the comparison

includes the hea der sequence (11110xx0) and t he

two most significant bits of the address.

Header matc hed (10-bit mode only): the interfa ce

generates an acknowledge pulse if the ACK bit is

set.

Address not matched: the interface ignores it

and waits for another Start condition.

Address matched: the interface generates in se-

quence:

– Acknowledge pulse if the ACK bit is set.

– EVF and ADSL bits are set with an interrupt if the

ITE bit is set.

Then the interface waits fo r a read of the SR1 reg-

ister, holding the SCL line low (see Figure 66

Transfer sequencing EV1).

Next, in 7-bit mode read the DR register to deter-

mine from the least significant bit (Data Direction

Bit) if the slave must enter Receiver or Transmitter

mode.

In 10-bit mode, after receiving the address se-

quence the slave is always in receive mode. It will

enter transmit mode on receiving a repeated Start

condition followed by the header sequence with

matching address bits and the least significant bit

set (11110xx1).

Slave Receiver

Following the address reception and after SR1

from the SDA line into t he DR register via the in ter-

nal shift register. After each byt e the interface gen-

erates in sequence:

– Acknowledge pulse if the ACK bit is set

– EVF and BTF bits are set with an interr upt if th e

ITE bit is set.

Then the inte rface wa its for a read of the SR1 reg-

ister followed by a read of the DR register, holding

the SCL line low (see Figure 66 Transfer se-

quencing EV2).

Slave Transmitter

Following the address reception and after SR1

the DR register to the SDA line via the internal shift

The slave waits for a read of the SR1 register fol-

lowed by a write in the DR register, holding the

SCL line low (see Figure 66 Transfer sequencing

EV3).

When the acknowledge pulse is received:

– The EVF and BTF bits are set by hardware with

an interrupt if the ITE bit is set.

Closing slave communication

After the last da ta byte is transferred a Sto p Con-

dition is generated by the master. The interface

detects this condition and sets:

– EVF and STOPF bits with an interrupt if the ITE

bit is set.

Then the inte rface wa its for a read of the SR2 reg-

ister (see Figure 66 Transfer sequencing EV4).

Error Cases

– BERR: Detection of a Stop or a Start condition

during a byte tr ansf er. In t his case, the EVF and

the BERR bits are set with an interrupt if the ITE

bit is set.

If it is a Stop then the interface discards the data,

released the lines and waits for another Start

condition.

If it is a Start the n the interface discards the data

and waits for the next slave address on the bus.

– AF: Detection of a non-acknowledge bit. In this

case, the EVF and AF bits are set with an inter-

rupt if the ITE bit is set.

The AF bit is clear ed by reading th e I2CSR2 reg-

ister. Howeve r, if re ad bef ore th e co mp le tio n of

the transmission, the AF flag will be set again,

thus possibly generating a new interrupt. Soft-

ware must ensure either that the SCL line is back

at 0 before reading the SR2 register, or be able

to correctly handle a second in terr upt dur ing t he

9th pulse of a transmitted byte.

Note: In case of errors, SCL line is not held low;

however, the SDA line can remain low if the last

bits transmitted are all 0. While AF=1, the SCL line

may be held low due to SB or BTF flags that are

set at the same time. It is then necessary to re-

lease both lines by software.

ST72F521, ST72521B

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I2C INTERFACE (Cont’d)

How to release the SDA / SCL lines

Set and subsequently clear the STOP bit while

BTF is set. The SDA/SCL lines are released after

the transfer of the current byte.

SMBus Co mpatibility

ST7 I2C is compatible with SMBus V1.1 protocol. It

supports all SMBus adre ssing m odes, SMBus bus

protocols and CRC-8 packet err or checking. Refer

to AN1713: SMBus Slave Driver For ST7 I2C Pe-

ripheral.

10.7.4.2 Mast er Mode

To switch from default Slave mode to Master

mode a Start condition generation is needed.

Start condition

Setting the START bit while the BUSY bit is

cleared causes the interface to switch to Master

mode (M/SL bit set) and generates a Start condi-

tion.

Once the Start condition is sent:

– The EVF and SB bits are set by hardware with

an interrupt if the ITE bit is set.

Then the master waits for a read of the SR1 regis-

ter followed by a write in the DR register with the

Slave address, holding the SCL line low (see

Figure 66 Transfer sequencing EV5).

Slave address transmission

Then the slave address is sent to the SDA line via

the internal shift register.

In 7-bit addressing mode, one address byte is

sent.

In 10-bit addressing mode, sending the first byte

including the header sequence causes the follow-

ing event:

– The EVF bit is set by hardware with interrupt

generation if the ITE bit is set.

Then the master waits for a read of the SR1 regis-

ter followed by a write in the DR register, holding

the SCL line low (see Figure 66 Transfer se-

quencing EV9).

Then the second a ddress byte is se nt by the inter-

face.

After completi on of this tran sfer (and ackno wledge

from the slave if the ACK bit is set):

– The EVF bit is set by hardware with interrupt

generation if the ITE bit is set.

Then the master wa its for a r ea d of the SR1 r egis-

ter followed by a write in the CR r egister (for exam-

ple set PE bit), holding the SCL line low (see Fig-

ure 66 Transfer sequencing EV6).

Next the master must enter Receiver or Transmit-

ter mode.

Note: In 10-bit addressing mode, to switch the

master to Receiver mo de, softwar e must genera te

a repeated Start condition and resend the header

sequence with the least significant bit set

(11110xx1).

Master Receiver

Following the address transmission and after SR1

and CR registers ha ve been accessed, the master

receives byt es from the SDA line into the DR reg-

ister via the internal shift register. After each byte

the interface generates in sequence:

– Acknowledge pulse if the ACK bit is set

– EVF and BTF bits are set by hardware with an in-

terrupt if the ITE bit is set.

Then the inte rface wa its for a read of the SR1 reg-

ister followed by a read of the DR register, holding

the SCL line low (see Figure 66 Transfer se-

quencing EV7).

To close the communication: before reading the

last byte from the DR register, set the STOP bit to

generate the Stop condition. The interface goes

automatically back to slave mode (M/SL bit

cleared).

Note: In order to generate the non-acknowledge

pulse after the last received data byte, the ACK bit

must be cleared just before reading the second

last data byte.

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I2C BUS INTERFACE (Cont’d)

Master Transmitter

Following the addre ss transmission and after SR1

from the DR register to the SDA line via the inter-

nal shift register.

The master waits f or a read of the SR1 reg ister fol-

lowed by a write in the DR register, holding the

SCL line low (see Figure 66 Transfer sequencing

EV8).

When the acknowledge bit is received, the

interface se ts:

– EVF and BTF bits with an interrupt if the ITE bit

is set.

To close the communication: after writing the last

byte to the DR regi ster, set th e STOP bit to gene r-

ate the Stop condition. The interface goes auto-

matically back to slave mode (M/SL bit cleared).

Error Cases

– BERR: Detection of a Stop or a Start condition

during a byte tran sfer. In this case, th e EVF and

BERR bits are set by hardware wit h an inter rupt

if ITE is set.

Note that BERR will not be set if an error is de-

tected during t he fi r st or secon d pu lse of ea ch 9-

bit transaction:

Single Mast er Mo de

If a Start or St op is issued duri ng t he fi r st or se c-

ond pulse of a 9-bit transaction, the BERR flag

will not be set and transfer will continue however

the BUSY flag will be reset. To work around this,

slave devices should issue a NACK when they

receive a misplaced Star t or Stop. The reception

of a NACK or BUSY by the master in the middle

of communication gives the possibility to reiniti-

ate transmission.

Multimaster Mode

Normally the BERR bit wo uld be set whenever

unauthorized transmission takes place while

transfer is already in p rogress. However, an is-

sue will arise if an external master generates an

unauthorized Start or Stop while the I2C master

is on the first or second pulse of a 9-bit transa c-

tion. It is possible to work around this by polling

the BUSY bit during I2C master mode transmis-

sion. The resetting of th e BUSY bit can th en be

handled in a similar manner as the BERR flag

being set.

– AF: Detection of a non-acknowledge bit. In this

case, the EVF and AF bits are set by hardware

with an interrupt if the ITE bit is set. To resume,

set the Start or Stop bit.

The AF bit is clear ed by reading th e I2CSR2 reg-

ister. Howeve r, if re ad bef ore th e co mp le tio n of

the transmission, the AF flag will be set again,

thus possibly generating a new interrupt. Soft-

ware must ensure either that the SCL line is back

at 0 before reading the SR2 register, or be able

to correctly handle a second in terr upt dur ing t he

9th pulse of a transmitted byte.

– ARLO: Detectio n of an arbitra tion lost co nditio n.

In this case the ARLO bit is set by hardware (with

an interrupt if the ITE bit is set and the interface

goes automatically back to slave mode (the M/SL

bit is cleared).

Note: In all these cases, the SCL line is not held

low; however, the SDA line can remain low due to

possible «0» bits transmit ted last. It is the n neces-

sary to release both lines by software.

ST72F521, ST72521B

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I2C BUS INTERFACE (Cont’d)

Figure 66. Transfer Sequencing

Legend: S=Start, Sr = Repeated Start, P=Stop, A=Acknowledge, NA=Non-acknowledge,

EVx=Event (with interrupt if ITE=1)

EV1: EVF=1, ADSL=1, cleared by reading SR1 register.

EV2: EVF=1, BTF=1, cleared by reading SR1 register followed by reading DR register.

EV3: EVF=1, BTF=1, cleared by reading SR1 register followed by writing DR register.

EV3-1: EVF=1, AF=1, BTF=1; AF is cleared by reading SR1 register. BTF is cleared by releasing the

lines (STOP=1, STOP=0) or by writing DR register (DR=FFh). Note: If lines are released by

STOP=1, STOP=0, the subsequent EV4 is not seen.

EV4: EVF=1, STOPF=1, cleared by reading SR2 register.

EV5: EVF=1, SB=1, cleared by reading SR1 register followed by writing DR register.

EV6: EVF=1, cleared by reading SR1 register followed by writing CR register (for example PE=1).

EV7: EVF=1, BTF=1, cleared by reading SR1 register followed by reading DR register.

EV8: EVF=1, BTF=1, cleared by reading SR1 register followed by writing DR register.

EV9: EVF=1, ADD10=1, cleared by reading SR1 register followed by writing DR register.

7-bit Slave recei ver:

7-bit Slave transmitter:

7-bit Master receiver:

7-bit Master transmitter:

10-bit Slave receiver:

10-bit Slave transmitter:

10-bit Master transmitter

10-bit Master receiver:

S Address A Data1 A Data2 A ..... DataN A P

EV1 EV2 EV2 EV2 EV4

S Address A Data1 A Data2 A ..... DataN NA P

EV1 EV3 EV3 EV3 EV3-1 EV4

S Address A Data1 A Data2 A ..... DataN NA P

EV5 EV6 EV7 EV7 EV7

S Address A Data1 A Data2 A ..... DataN A P

EV5 EV6 EV8 EV8 EV8 EV8

S Header A Address A Data1 A ..... DataN A P

EV1 EV2 EV2 EV4

SrHeader A Data1 A ....

.DataN A P

EV1 EV3 EV3 EV3-1 EV4

S Header A Address A Data1 A ..... DataN A P

EV5 EV9 EV6 EV8 EV8 EV8

SrHeader A Data1 A ..... DataN A P

EV5 EV6 EV7 EV7

ST72F521, ST72521B

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I2C BUS INTERFACE (Cont’d)

10.7.5 Low Po wer Modes

10.7.6 Interrup ts

Figure 67. Event Flags and Interrupt Generation

Note: The I2C interrupt events are connected to

the same interrupt vector (see Interrupts chapter).

They generate an interrupt if the corresponding

Enable Control Bit is set and the I-bit in the CC reg-

ister is reset (RIM instruction).

Mode Description

WAIT No effect on I2C interface.

I2C interrupts cause the device to exit from WAIT mode.

HALT I2C registers are frozen.

In HALT mode, the I2C interface is inactive and does not acknowledge data on the bus. The I2C interface

resumes operation when the MCU is woken up by an interrupt with “exit from HALT mode” capability.

Interrupt Event Event

Flag

Enable

Control

Bit

Exit

from

Wait

Exit

from

Halt

10-bit Address Sent Event (Master mode) ADD10

ITE

Yes No

End of Byte Transfer Event BTF Yes No

Address Matched Event (Slave mode) ADSEL Yes No

Start Bit Generation Event (Master mode) SB Yes No

Acknowledge Failure Event AF Yes No

Stop Detection Event (Slave mode) STOPF Yes No

Arbitration Lost Event (Multimaster configuration) ARLO Yes No

Bus Error Event BERR Yes No

BTF

ADSL

STOPF

ARLO

BERR EVF

INTERRUPT

ITE

* EVF can also be set by EV6 or an error from the SR2 register.

ADD10

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I2C BUS INTERFACE (Cont’d)

10.7.7 Register Description

I2C CONTROL REGISTER (CR)

Read / Write

Reset Value: 0000 0000 (00h)

Bit 7:6 = Reserved. Forced to 0 by hardware.

Bit 5 = PE Peripheral enable.

This bit is set and cleared by software.

0: Peripheral disabled

1: Master/Slave capability

Notes:

– When PE=0, all the bits of the CR register and

the SR register except the St op bit are re se t. All

outputs are released while PE=0

– When PE=1, the corresponding I/O pins are se-

lected by hardware as alternate functions.

– To enable the I2C interface, write the CR register

TWICE with PE=1 as the first write only activates

the interface (only PE is set).

Bit 4 = ENGC Enable General Call.

This bit is set and cleared by software. It is also

cleared by hardware when the interface is disa-

bled (PE=0). The 00h Gener al Call address is ac-

knowledged (01h ignored).

0: General Call disabled

1: General Call enabled

Note: In accordance with the I2C stand ar d , when

GCAL addressing is enable d, an I2C slave can

only receive data. It will not transmit data to the

master.

Bit 3 = START Generation of a Start condition.

This bit is set and cleared by software. It is also

cleared by hardware when the interface is disa-

bled (PE=0) or when the Start condition is sent

(with interrupt generation if ITE=1).

– In master mode:

0: No start generation

1: Repeated start generation

– In slave mode:

0: No start generation

1: Start generation when the bus is free

Bit 2 = ACK Acknowledge enable.

This bit is set and cleared by software. It is also

cleared by hardware when the interface is disa-

bled (PE=0).

0: No acknowledge returned

1: Acknowledge retu rned after an add ress byte or

a data byte is receiv ed

Bit 1 = STOP Generation of a Stop condition.

This bit is set and cleared by software. It is also

cleared by hardware in master mode. Note: This

bit is not cleared when the interface is disabled

(PE=0).

– In master mode:

0: No stop generation

1: Stop gener ation after the current byte transfer

or after the curren t S tar t co nd itio n is sen t. The

STOP bit is cleared by hardware when the Stop

condition is sent.

– In slave mode:

0: No stop generation

1: Release the SCL and SDA line s aft er the cur-

rent byte transfer (BTF=1). In this mode the

STOP bit has to be clear ed by sof twa re .

Bit 0 = ITE Interrupt enable.

This bit is set and clear ed by software and cleared

by hardware when the int erface is disabled

(PE=0).

0: Interrup ts disab l e d

1: Interrup ts ena ble d

Refer to Figure 67 for the relationship between the

events and the interrupt.

SCL is held low when the ADD10, SB, BTF or

ADSL flags or an EV6 event (See Figure 66) is de-

tected.

0 0 PE ENGC START ACK STOP ITE

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I2C BUS INTERFACE (Cont’d)

I2C STATUS REGISTER 1 (SR1)

Read Only

Reset Value: 0000 0000 (00h)

Bit 7 = EVF Event flag.

This bit is set by hardware as soon as an event oc-

curs. It is cleare d by software read ing SR2 register

in case of error ev ent or as described in Figur e 66.

It is also cleared by ha rdware when the interface is

disabled (PE=0).

0: No event

1: One of the following events has occurred:

– BTF=1 (Byte received or transmitted)

– ADSL=1 (Address matched in Slave mode

while ACK=1)

– SB=1 (Start condition generated in Master

mode)

– AF=1 (No acknowledge received after byte

transmission)

– STOPF=1 (Stop condition detected in Slave

mode)

– ARLO=1 (Arbitration lost in Master mode)

– BERR=1 (Bus error, misplaced Start or Stop

condition detect ed)

– ADD10=1 (Master has sent header byte)

– Address byte successfully transmitted in Mas-

ter mode.

Bit 6 = ADD10 10-bit addressing in Master mode.

This bit is set by hardware when the master has

sent the first byte in 10-bit address mode. It is

cleared by software reading SR2 register followed

by a write in the DR regist er of the second address

byte. It is also cleared by hardware when the pe-

ripheral is disabled (PE=0).

0: No ADD10 event occurred.

1: Master has sent first address byte (header)

Bit 5 = TRA Transmitter/Receiver.

When BTF is set, TRA=1 if a data byte has been

transmitted. It is cleared automatically when BTF

is cleared. It is also cleared by hardware after de-

tection of Stop condition (STOPF=1), loss of bus

arbitration (ARL O=1) or when the interface is disa-

bled (PE=0).

0: Data byte received (if BTF=1)

1: Data byte transmitted

Bit 4 = BUSY Bus busy.

This bit is set by hardware on detection of a Start

condition and cleared b y har dware on de te ct ion of

a Stop condition. It indicates a communication in

progress on the bus. The BUSY flag of the I2CSR1

0: No communication on the bus

1: Communication ongoing on the bus

Note:

– The BUSY flag is NOT updated when the inter-

face is disabled (PE=0). This can have conse-

quences when operating in Multimaster mode;

i.e. a second active I2C master commencing a

transfer with an unset BUSY bit can cau se a con-

flict resulting in lost data. A software wor karound

consists of checking that the I2C is not busy be-

fore enabling t he I2C Multimaster cell.

Bit 3 = BTF Byte transfer finished.

This bit is set by hardware as soon as a byte is cor-

rectly received or transmitted with interrupt gener-

ation if ITE=1. It is cleared by software reading

SR1 register follo wed by a read or write of DR reg-

ister. It is also cleared by hard ware when the inter-

face is disabled (PE=0).

– Following a byte transmission, this bit is set after

reception of the acknowledge clock pulse. In

case an address byte is sent, this bit is set only

after the EV6 event (See Figure 66). BTF is

cleared by reading SR1 register followed by writ-

ing the next byte in DR register.

– Following a byte reception, this bit is set after

transmission of the acknowledge clock pulse if

ACK=1. BTF is cleared by reading SR1 register

followed by reading the byte from DR register.

The SCL line is held low while BTF=1.

0: Byte transfe r no t do ne

1: Byte transfer succeeded

Bit 2 = ADSL Address matched (Slave mode).

This bit is set by hardware as soon as the received

slave address matched with the OAR register con-

tent or a general call is recognized. An interrupt is

generated if ITE=1. It is cleared by software read-

ing SR1 register or by hardware when the inter-

face is disabled (PE=0).

The SCL line is held low while ADSL=1.

0: Address mismatched or not received

1: Received addr e ss ma tc hed

EVF ADD10 TRA BUSY BTF ADSL M/SL SB

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I2C BUS INTERFACE (Cont’d)

Bit 1 = M/SL Master/Slave.

This bit is set by hardware a s soon as the interface

is in Master mode (writing START=1). It is cleared

by hardware after detecting a Stop condition on

the bus or a loss o f arbit ration ( ARLO=1) . It is also

cleared when the interface is disabled (PE=0).

0: Slave mode

1: Master mo de

Bit 0 = SB Start bit (Master mode).

This bit is set by hardware as soon as the Start

condition is generated (following a write

START=1). An int err upt is gen er at ed if IT E=1. I t is

cleared by software reading SR1 register followed

by writing the address b yte in DR register. It is also

cleared by hardware when the interface is disa-

bled (PE=0).

0: No Start condition

1: Start condition generated

I2C STATUS REGISTER 2 (SR2)

Read Only

Reset Value: 0000 0000 (00h)

Bit 7:5 = Reserved. Forced to 0 by hardware.

Bit 4 = AF Acknowledge failure.

This bit is set by hardware when no acknowledge

is returned. An interrupt is generated if ITE=1. It is

cleared by software reading SR2 register or by

hardware when the interface is disabled (PE=0) .

The SCL line is not held low while AF=1 but by oth-

er flags (SB or BTF) that are set at the sa me t ime.

0: No acknowledge failure

1: Acknowledge failure

Note:

– When an AF event occurs, the SCL line is not

held low; however, the SDA line can re main low

if the last bits transmitted are all 0. It is then nec-

essary to release both lines by software.

Bit 3 = STOPF Stop detection (Slave mode).

This bit is set by hardware when a Stop condition

is detected on the bus after an acknowledge (if

ACK=1). An interrupt is generated if ITE=1. It is

cleared by software reading SR2 register or by

hardware when the interface is disabled (PE=0) .

The SCL line is not held low while STOPF=1.

0: No Stop condition dete cted

1: Stop condition detected

Bit 2 = ARLO Arbitration lost.

This bit is set by hardware when the interface los-

es the arbitration of the bus to another master. An

interrupt is gener ated if ITE=1. It is cleared by soft-

ware reading SR2 register or by hardware when

the interface is disabled (PE=0).

After an ARLO event the interface switches back

automatically to Slave mode (M/SL=0).

The SCL line is not held low while ARLO=1.

0: No arbitration lost detected

1: Arbitration lost detected

Note:

– In a Multimaster environment, when the interface

is configured in Master Receive mode it does not

perform arbitration during the reception of the

Acknowledge Bit. Mishandling of the ARLO bit

from the I2CSR2 registe r may occur when a sec-

ond master si mu lta n eo us ly requests the same

data from the sam e sl ave an d the I 2C mast er

does not acknowledge the data. The ARLO bit is

then left at 0 in stead of being set.

Bit 1 = BERR Bus error.

This bit is set by hardware when the interface de-

tects a misplaced Start or Stop condition. An in ter-

rupt is gener ated if ITE=1. It is cleared by sof tware

reading SR2 register or by hardware when the in-

terface is disabled (PE=0).

The SCL line is not held low while BERR=1.

0: No misplaced Start or Stop cond ition

1: Misplaced Start or Stop condition

Note:

– If a Bus Error occurs, a Stop or a r epeated St art

condition should be generated by the Master to

re-synchronize communication, get the transmis-

sion acknowledged and the bus released for fur-

ther communication

Bit 0 = GCAL General Call (Slave mode).

This bit is set by hardware when a general call ad-

dress is detected on the bus while ENGC=1. It is

cleared by hardware detecting a Stop condition

(STOPF=1) or when the interface is disabled

(PE=0).

0: No general call address detected on bus

1: general call address detected on bus

0 0 0 AF STOPF ARLO BERR GCAL

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I2C BUS INTERFACE (Cont’d)

I2C CLOCK CONTROL REGISTER (CCR)

Read / Write

Reset Value: 0000 0000 (00h)

Bit 7 = FM/SM Fast/Standard I2C mode.

This bit is set and cleared by software. It is not

cleared when the interface is disabled (PE=0).

0: Standard I2C mode

1: Fast I2C mode

Bit 6:0 = CC[6:0] 7-bit clock divider.

These bits se lect the speed of the bus (FSCL) de-

pending on the I2C mode. They are not cleared

when the interf ace is disabled (PE=0).

Refer to the Electrical Characteristics section for

the table of values.

Note: The programmed FSCL assumes no load on

SCL and SDA lines.

I2C DATA REGISTER (DR)

Read / Write

Reset Value: 00 0 0 00 00 (0 0h )

Bit 7:0 = D[7:0] 8-bit Data Regist er.

These bits contain the byte to be received or trans-

mitted on the bus.

– Transmitter mode: Byte transmission start auto-

matically when the software writes in the DR reg-

ister.

– Receiver mode: the first data byte is received au-

tomatically in the DR register using the least sig-

nificant bit of the address.

Then, the follo wing data bytes are received one

by one after readin g th e DR re gister.

FM/SM CC6 CC5 CC4 CC3 CC2 CC1 CC0

D7 D6 D5 D4 D3 D2 D1 D0

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I2C BUS INTERFACE (Cont’d)

I2C OWN ADDRESS REGISTER (OAR1)

Read / Write

Reset Value: 0000 0000 (00h)

7-bit Addressing Mode

Bit 7:1 = ADD[7:1] Interface address.

These bits de fin e the I2C bus address of the inter-

face. They are not cleared when the interface is

disabled (PE=0).

Bit 0 = ADD0 Address direction bit.

This bit is don’t care, the interface acknowledges

either 0 or 1. It is not cleared when the interface is

disabled (PE=0).

Note: Address 01h is always ignored.

10-bit Addressing Mode

Bit 7:0 = ADD[7:0] Interface address.

These are the least significant bits of the I2C bus

address of the interface. They are not cleared

when the interf ace is disabled (PE=0).

I2C OWN ADDRESS REGISTER (OAR2)

Read / Write

Reset Value: 01 0 0 00 00 (4 0h )

Bit 7:6 = FR[1:0] Frequency bits.

These bits are set by software only when the in ter-

face is disa bled (PE=0). To co nfigure t he interfa ce

to I2C specified delays select the value corre-

sponding to the microcontroller frequency FCPU.

Bit 5:3 = Reserved

Bit 2:1 = ADD[9:8] Interface address.

These are the most significant bits of the I2C bus

address of the interface (10-bit mode only). They

are not cleared when the interface is disabled

(PE=0).

Bit 0 = Reserved.

ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0

FR1 FR0 0 0 0 ADD9 ADD8 0

fCPU FR1 FR0

< 6 MHz 0 0

6 to 8 MHz 0 1

ST72F521, ST72521B

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I²C BUS INTERFACE (Cont’d)

Table 23. I2C Register Map and Reset Values

Address

(Hex.) Register

Label 76543210

0018h I2CCR

Reset Value 0 0 PE

0ENGC

0START

0ACK

0STOP

0ITE

0019h I2CSR1

Reset Value EVF

0ADD10

0TRA

0BUSY

0BTF

0ADSL

0M/SL

0SB

001Ah I2CSR2

Reset Value000AF

0STOPF

0ARLO

0BERR

0GCAL

001Bh I2CCCR

Reset Value FM/SM

0CC6

0CC5

0CC4

0CC3

0CC2

0CC1

0CC0

001Ch I2COAR1

Reset Value ADD7

0ADD6

0ADD5

0ADD4

0ADD3

0ADD2

0ADD1

0ADD0

001Dh I2COAR2

Reset Value FR1

0FR0

1000

ADD9

0ADD8

001Eh I2CDR

Reset Value MSB

0000000

LSB

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10.8 CONTROLLER AREA NETWORK (CAN)

10.8.1 Introduction

This peripheral is designed to support serial data

exchanges using a multi-master contention based

priority scheme as described in CAN specification

Rev. 2.0 part A. It can also be connected to a 2.0 B

network without problems, since extended frames

are checked for correctness and acknowledged

accordingly although such frames cannot be trans-

mitted nor rece ived. The same applies t o overload

frames which are recognized but never initiated.

Figure 68. CAN Block Diagram

TX/RX

Buffer 1

10 Bytes

TX/RX

Buffer 2

10 Bytes

TX/RX

Buffer 3

10 Bytes

Filter 0

4 Bytes

Filter 1

4 Bytes

ST7 Interface

PSR

ICR

ISR

BRPR

CSR

TECR

RECR

CAN 2.0B passive Core

SHREG

BCDL

CRC

BTL

TX EML

ST7 Internal Bus

BTR

ST72F521, ST72521B

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CONTROLLER AREA NETWORK (Cont’d)

10.8.2 Main Features

– Support of CAN specification 2.0A and 2.0B pas-

sive

– Three prioritized 10-byte Transmit/Receive me s-

sage buffe rs

– Two programmable global 12-bit message ac-

ceptance filters

– Programmable baud rates up to 1 MBit/s

– Buffer flip-flopping capability in transmission

– Maskable interrupts for transmit, receive (one

per buffer), error and wake-up

– Automatic low-power mode after 20 recessive

bits or on demand (standby mode)

– Interrupt-driven wake-up from standby mode

upon reception of dominant pulse

– Optional dominant pulse transmission on leaving

standby mode

– Automatic message queuing for transmission

upon writing of data byte 7

– Programmable loop-back mode for self-test op-

eration

– Advanced error detection and diagno sis func-

tions

– Software-efficient buffer mapping at a unique ad-

dress space

– Scalable architecture.

10.8.3 Function al Descript io n

10.8.3.1 Frame Formats

A summary of all the CAN frame formats is given

in Figure 69 for reference. It covers only the stand-

ard frame format since the extended one is only

acknowledged.

A message begins with a start bit called Start Of

Frame (SOF). Th is bit is followed b y the arbitr ation

field which contains the 11-bit identifier (ID) and

the Remote Transmission Request bit (RTR). The

RTR bit indicates whet her it is a data frame or a re-

mote request fra me. A r emote request frame does

not have any data byte.

The control field contains the Identifier Extension

bit (IDE), which indicates standard or extended

format, a reserved bit (ro) and, in the last four bits,

a count of the data bytes (DLC). The data field

ranges from zero to eight bytes and is followed by

the Cyclic Redundancy Check (CRC) used as a

frame integrity check for detecting bit errors.

The acknowledgement (ACK) field comprises the

ACK slot and the ACK delimiter. The bit in the ACK

slot is placed on the bus by the tr ansmitter as a re-

cessive bit (logical 1). It is overwritten as a domi-

nant bit (logical 0) by those receivers which have

at this time received the data correctly. In this way,

the transmitting node can be assured that at least

one receiver has correctly received its message.

Note that messages are acknowledged by the re-

ceivers regardless of the outcome of the accept-

ance test.

The end of the message is indicated by the End Of

Frame (EOF). The intermission field defines the

minimum number of bit periods separating con-

secutive messages. If there is no subsequent bus

access by any station, the bus remains idle.

10.8.3.2 Hardware Blocks

The CAN controller contains the following func-

tional blocks (refer to Figure 68):

– ST7 Interface: buffering of the ST7 internal bus

and address decoding of the CAN registers.

– T X/RX Buffers: three 10 -b yt e bu ffers for trans-

mission and receptio n of maximum length mes-

sages.

– ID Filters: two 12-bit compare and don’t care

masks for message acceptance filtering.

– PSR: page selection register (see memory map).

– BR PR: clo ck divid e r fo r diff er en t data rat es .

– BTR: bit timing register.

– ICR: interrupt control register.

– ISR: interrupt status register.

– CS R: ge ne r al pu rp o se cont ro l/status registe r.

– TECR: transmit error counter register.

– RECR: receive error counter register.

– BTL: bit timing logic providing programmable bit

sampling and bit clock generation for synchroni-

zation of the contr o ller .

– BCDL: bit coding logic generating a NRZ-coded

datastream with stuff bits.

– SHREG: 8-bit shift register for serialization of

data to be transmitted and parallelisation of re-

ceived data.

– CRC: 15-bit CRC calculator and checker.

– EML: error detection and management logic.

– CAN Core: CAN 2.0B passive protocol control-

ler.

ST72F521, ST72521B

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CONTROLLER AREA NETWORK (Cont’d)

Figure 69. CAN Frames

Data Field

8 * N

Control Field

Arbitration Field

CRC Field

Ack Field

SOF

ID DLC CRC

Data Frame

44 + 8 * N

Arbitration Field

RTR

IDE

SOF

ID DLC

Remote Frame

CRC Field

16 7

CRC

Control Field

Overload Flag

Overload Delimiter

Overload Frame

Error Flag

Error Delimiter

Error Frame

Flag Echo

≤ 6

Bus Idle

Inter-Frame Space

Suspend

Intermission

3Transmission

ACK

Inter-Frame Space

or Overload Frame

Inter-Frame Space

or Overload Frame

Inter-Frame Space

or Overload Frame

Data Frame or

Remote Frame

Notes:

• 0 <= N <= 8

• SOF = Start Of Frame

• ID = Identifier

• RTR = Remote Transmission Request

• IDE = Identifier Extension Bit

• r0 = Reserved Bit

• DLC = Data Length Code

• CRC = Cyclic Redundancy Code

• Error flag: 6 dominant bits if node is error

active else 6 recessive bits.

• Suspend transmission: applies to error

passive nodes only.

• EOF = End of Frame

• ACK = Acknowledge bit

Data Frame or

Remote F rame

Any Frame

Inter-Frame Space

or Error Frame

End Of Frame or

Error Delimiter or

Overload Delimiter

Ack Field End Of Frame

RTR

IDE

EOF

ST72F521, ST72521B

132/215

CONTROLLER AREA NETWORK (Cont’d)

10.8.3.3 Modes of Operation

The CAN Core unit assumes one of the seven

states described below:

– STANDBY. Standby mode is entered either on a

chip reset or on resetting the RUN bit in the Con-

trol/Status Register (CSR). Any on-goi ng trans-

mission or reception op eration is no t interru pted

and completes normally before the Bit Time Log-

ic and the clock prescale r are tu rn ed off for mini-

mum power consumption. This state is signa lled

by the RUN bit being read-back as 0.

Once in standby, th e only event monitored is t he

reception of a dominant bit which causes a wake-

up interrupt if the SCIE bit of the Interrupt Control

The STANDBY mode is left by setting the RUN

bit. If the WKPS bit is set in the CSR register,

then the controller passes through WAKE-UP

otherwise it enters RESYNC directly.

It is important to note that the wake-up mecha-

nism is software-driven and theref or e ca rr ies a

significant time overhead. All messages received

after the wake -up b it and befor e the cont roller is

set to run and has completed synchr onization

are ignored.

Note: Standby mode is not entered on resetting

the RUN bit in the Control/Status register (CSR) if

the CANRX pin is short ed to GND.

– WAKE-UP. The CAN bus line is forced to domi-

nant for one bit time signalling the wake-up con-

dition to all othe r bus members.

Figure 70. CAN Controller State Diagram

STANDBY

RESYNC

WAKE-UP

RECEPTIONTRANSMISSION

ERROR

IDLE

ARESET

RUN RUN & WKPS

RUN & WKPS

FSYN & BOFF & 11 Recessi v e bits |

(FSYN | BOFF) & 128 * 11 Recessive bits

RUN

Write to D ATA7 |

TX Error & NRTX Start Of Frame

Arbitration lost

TX Error RX Error

TX OK RX OK

BOFF

ST72F521, ST72521B

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CONTROLLER AREA NETWORK (Cont’d)

– RESYNC. The resynchronization mode is used

to find the correct entry point for starting trans-

mission or reception after the node has gone

asynchronous either by going into the STANDBY

or bus-off states.

Resynchronization is ach ieved when 128 se-

quences of 11 recessive bits have been moni-

tored unless the no de is not bus-off and the

FSYN bit in the CSR register is set in which case

a single sequence of 11 recessive bits ne eds to

be monitored.

– IDLE. The CAN controller looks for one of the fol-

lowing events: the RUN bit is reset, a Start Of

Frame appears on the CAN bus or the DATA7

– TRANSMISSION. Once the LOCK bit of a Buffer

Control/Status Register (BCSRx) has been set

and read back as such, a transmit job can be

submitted by writing to the DATA7 register. The

message with the highest priority will be transmit-

ted as soon as the CAN bus becomes idle.

Among those messages with a pending trans-

mission request, the highest priority is given to

Buffer 3 then 2 and 1. If the transmission fails due

to a lost arbitration or to an error while t he NRTX

bit of the CSR register is reset, the n a new trans-

mission atte mpt is perf ormed . This goes on until

the transmission ends successfully or until the

job is cancelled by unlocking the buffer, by set-

ting the NRTX bit or if the node ever enters bus-

off or if a hig her priority message becomes pend-

ing. The RDY bit in the BCSRx register, which

was set since the job was submitted, gets reset.

When a transmission is in progress, the BUSY bit

in the BCSRx register is set. If it ends successful-

ly then the TXIF bit in the Interrupt Status Regis-

ter (ISR) is set, else the TEIF bit is set. An

interrupt is gener ated in either case provid ed the

TXIE and TEIE bits of the ICR register are set.

Note 1: Setting the SRTE bit of the CSR register

allows transmitted messages to be simultane-

ously received when they pass the acceptance

filtering. This is particularly useful for checking

the integrit y of the communication pat h.

RECEPTION. Once the CAN controller has syn-

chronized itself onto the bus activity, it is ready

for reception of new messages. Every incoming

message gets its identifier compared to the ac-

ceptance filters. If the bitwise comparison of the

selected bits ends up with a match for at least

one of the filt ers then th at message is electe d for

reception and a target buffer is searched for. This

buffer will be the first one - order is 1 to 3 - that

has the LOCK and RDY bits of its BCSRx regis-

ter rese t.

– When no such buffer exists then an overrun

interrupt is generated if the ORIE bit of the ICR

er of the last message is made available in the

Last Identif ier Register (LIDHR and LIDLR) at

least until it gets overwritten by a new identifi-

er picked-up from the bus.

– When a buffer does exist, the accepted mes-

sage gets written into it, the ACC bit in the

BCSRx register gets the number of the match-

ing filter, the RDY and RXIF bits get set and an

interrupt is generated if the RXIE bit in the ISR

Up to three messages can be automatically

received without intervention from the CPU

because each buffer has its own set of status

bits, greatly reducing the reactiveness require-

ments in the processing of the receive inter-

rupts.

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CONTROLLER AREA NETWORK (Cont’d)

– ERROR. The error management as described in

the CAN protocol is completely handled by har d-

ware using 2 erro r counters which get increment-

ed or decremented according to the error

condition. Bot h of them may be read by the a ppli-

cation to determ in e the stability of th e ne twork.

Moreover, as one of the node status bits (EPSV

or BOFF of the CSR register) changes, an inter-

rupt is generated if th e SCIE bit is set in the ICR

Figure 71. CAN Error Stat e Diagram

ERROR PASSIVE

When TECR or RECR > 127, the EPSV bit gets set

When TECR and RECR < 128,

and the EP SV bit gets cl eared

ERROR ACTIVE

BUS OFF

When TECR > 255 the BOFF bit gets setWhen 128 * 11 recessive bits occur:

- the BOFF bit gets cleared

- the TECR register gets cleared

- the RECR register gets cleared

the EPSV bit gets cleared

ST72F521, ST72521B

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CONTROLLER AREA NETWORK (Cont’d)

10.8.3.4 Bit Timing Logic

The bit timing logic monitors the serial bus-line and

performs sampling and adjustment of the sample

point by synchronizing on the start-bit edge and re-

synchronizing on following edges.

Its operation may be explained simply when the

nominal bit time is divided into three segments as

follows:

– Synchronisation segment (SYNC_SEG): a bit

change is expected to lie within this time seg-

ment. It has a fixe d length of one t ime quant a (1

x tCAN).

– Bit segment 1 (BS1): de fines the location of the

sample point. It includes the PROP_SEG and

PHASE_SEG1 of the CAN standard. Its duration

is programmable bet ween 1 and 16 time qu anta

but may be automatically le ngthened to compen-

sate for positive phase drifts due to differences in

the frequency of the various nodes of the net-

work.

– Bit segment 2 (BS2): de fines the location of the

transmit point. It represents the PHASE_SEG2

of the CAN standard . Its dur at ion is prog r am m a-

ble between 1 and 8 time quanta but may also be

automatically shortened to compensate for neg-

ative phase dr ift s .

– Resynchronization Jump Width (RJW): de-

fines an upper bound to the amount of lengthen-

ing or shorteni ng of the bit segments. It is

programmable between 1 and 4 time quanta.

To guarantee the correct behaviour of the CAN

controller, SYNC_SEG + BS1 + BS2 must be

greater than or equal to 5 time quanta.

The CAN controller resynchronizes on recessive

to dominant edges only.

For a detailed descri ption of t he CAN resynchro ni-

zation mechanism and other bit timing configura-

tion constraints, please refer to the Bosch CAN

standard 2.0.

As a safeguard against programming errors, the

configuration of the Bit Timing Register (BTR) is

only possible while the device is in STANDBY

mode.

Figure 72. Bit Timing

SYNC_SEG BIT SEGMENT 1 (BS1) BIT SEGMENT 2 (BS2)

NOMINAL BIT TIME

1 x tCAN tBS1 tBS2

SAMPLE POINT TRANSMIT POINT

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CONTROLLER AREA NETWORK (Cont’d)

10.8.4 Register Description

The CAN registers are organized a s 6 general pur-

pose registers plus 5 pages of 16 registers span-

ning the same address space and primarily used

for message and filter storage. The page actually

selected is define d by th e co nt en t of th e Pag e Se-

lection Register.

10.8.4.1 General Purpose Registers

INTERRUPT STATUS REGISTER (ISR)

Read/Write

Reset Value: 00h

Bit 7 = RXIF3 Receive Interrupt Flag for Buffer 3

− Read/Clear

Set by hardware to signal that a new error-free mes-

sage is available in buffer 3.

Cleared by software to release buffer 3.

Also cleared by resetting bit RDY of BCSR3.

Bit 6 = RXIF2 Receive Interrupt Flag for Buffer 2

− Read/Clear

Set by hardware to signal that a new error-free

message is available in buffer 2.

Cleared by software to release buffer 2.

Also cleared by resetting bit RDY of BCSR2.

Bit 5 = RXIF1 Receive Inte rrupt Flag for Buffer 1

− Read/Clear

Set by hardware to signal that a new error-free mes-

sage is available in buffer 1.

Cleared by software to release buffer 1.

Also cleared by resetting bit RDY of BCSR1.

Bit 4 = TXIF Transmit Interrupt Flag

− Read/Clear

Set by hardware to signal that the highest priority

message queued for transmission has been suc-

cessfully tran sm itte d .

Cleared by software.

Bit 3 = SCIF Status Change Interrupt Flag

− Read/Clear

Set by hardware to sig nal the reception of a domi-

nant bit while in standby mode. In Run mode this bit

is set when EPVS is set or reset (refer to Figure 71.

CAN Error State Diagram). This bit also signals any

receive error when ESCI=1.

Cleared by software.

Bit 2 = ORIF Overrun Interrupt Flag

− Read/Clear

Set by hardware to signal that a message could not

be stored because no receive buffer was available.

Cleared by software.

Bit 1 = TEIF Transmit Error Interrupt Flag

− Read/Clear

Set by hardware to signal that an error occurred dur-

ing the transmission of the highest priority message

queued for transmission.

Cleared by software.

Bit 0 = EPND Error Interrupt Pending

− Read Only

Set by hardware when at least one of the three error

interrupt flags SCIF, ORIF or TEIF is set.

Reset by hardware when all error interrupt flags

have been cleared.

Caution:

Interrupt flags are reset by writing a “0” to the cor-

responding bit position. T he appropriate way con-

sists in writing an immediate mask or the one’s com-

plement of the register content initially read by the

interrupt handler. Bit manipulation instruction

BRES should never be used due to its read-modify-

write nature .

RXIF3 RXIF2 RXIF1 TXIF SCIF ORIF TEIF EPND

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CONTROLLER AREA NETWORK (Cont’d)

INTERRUPT CONTROL REGISTER (ICR)

Read/Write

Reset Value: 00h

Bit 7 = Reserved.

Bit 6 = ESCI Extended Status Change Interrupt

− Read/Set/Clear

Set by software to specify that SCIF is to be set on

receive erro rs al so .

Cleared by software to set SCIF only on status

changes and wake-up but not on all receive errors.

Bit 5 = RXIE Receive Interrupt Enable

− Read/Set/Clear

Set by software to enable an interrupt request

whenever a message has been received free of er-

rors.

Cleared by software to disable receive interrupt r e-

quests.

Bit 4 = TXIE Transmit Interrupt Enable

− Read/Set/Clear

Set by software to enable an interrupt request

whenever a message has been successfully trans-

mitted.

Cleared by software to disable transmit interrupt

requests.

Bit 3 = SCIE Status Change Interrupt Enable

− Read/Set/Clear

Set by software to enable an interrupt request

whenever the node’s status changes in run mode or

whenever a domin ant p ulse is receive d in stand by

mode.

Cleared by software to disable status change inter-

rupt requests.

Bit 2 = ORIE Overrun Interrupt Enable

− Read/Set/Clear

Set by software to enable an interrupt request

whenever a message should be stored and no re-

ceive buffer is avala i ble .

Cleared by software to disable overrun interrupt re-

quests.

Bit 1 = TEIE Transmit Error Interrupt Enable

− Read/Set/Clear

Set by software to enable an interrupt whenever an

error has been detected during transmission of a

message.

Cleared by software to disabl e transmit err or inter-

rupts.

Bit 0 = Reserved.

0 ESCI RXIE TXIE SCIE ORIE TEIE 0

ST72F521, ST72521B

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CONTROLLER AREA NETWORK (Cont’d)

CONTROL/STATUS REGISTER (CSR)

Read/Write

Reset Value: 00h

Bit 6 = BOFF Bus-Off State

− Read Only

Set by hardware t o indicate that the node is in bus-

off state, i.e. the Transmit Error Counter exceeds

255.

Reset by hardware to indicate that the node is in-

volved in bus activities.

Bit 5 = EPSV Error Passive State

− Read Only

Set by hardware to indicate that the node is error

passive.

Reset by hardware to indicate that the node is either

error active (BOFF = 0) or bus-off.

Bit 4 = SRTE Simultaneous Receive/Transmit En-

able − Read/Set/Clear

Set by software to enable simultaneous transmis-

sion and reception of a message passing the ac-

ceptance filtering. Allows to check the integrity of

the communication path.

Reset by software to discard all messages trans-

mitted by the node. Allows remote and data frames

to share the sa me ide ntif ier .

Bit 3 = NRTX No Retransmission

− Read/Set/Clear

Set by software to disable the retransmission of un-

successful messages. It does not stop transmission

in case of Arbitration Lost.

Cleared by software to enable retransmission of

messages until success is met.

Bit 2 = FSYN Fast Synchronization

− Read/Set/Clear

Set by software to en able a f ast resynchro nizat ion

when leaving standby mode, i.e. wait for only 11 re-

cessive bits in a row.

Cleared by softwar e to en able t he st andard resyn-

chronization when leaving standby mode, i.e. wait

for 128 sequences of 11 recessive bits.

Bit 1 = WKPS Wake-up Pulse

− Read/Set/Clear

Set by software to generate a dominant pulse when

leaving standby mode.

Cleared by software for no dominant wake-up

pulse.

Bit 0 = RUN CAN Enable

− Read/Set/Clear

Set by software to leave standby mode after 128 se-

quences of 11 recessive bits or just 11 recessive

bits if FSYN is set.

Cleared by software to request a switch to the

standby or low-po wer mode as soon as any on-go-

ing transfer is complete. Read-back as 1 in the

meantime to enable proper signalling of the standby

state. The CPU clock may therefore be safely

switched OFF whenever RUN is read as 0.

0 BOFF EPSV SRTE NRTX FSYN WKPS RUN

ST72F521, ST72521B

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CONTROLLER AREA NETWORK (Cont’d)

BAUD RATE PRESCALER REGISTER (BRPR)

Read/Write in Standby mode

Reset Value: 00h

RJW[1:0] determine the ma ximum number of time

quanta by which a bit period may be shortened or

lengthened to achieve resynchronization.

tRJW = tCAN * (RJW + 1)

BRP[5:0] determine the CAN system clock cycle

time or time quanta which is used to build up the in-

dividual bit timing.

tCAN = tCPU * (BRP + 1)

Where tCPU = time period of the CPU clock.

The resulting baud rate can be computed by the for-

mula:

Note: Writing to this register is allowed only in

Standby mode to prevent any accidental CAN pr o-

tocol violation through programming errors.

BIT TIMING REGISTER (BTR)

Read/Write in Standby mode

Reset Value: 23h

BS2[2:0] determine the length of Bit Segm e nt 2.

tBS2 = tCAN * (BS2 + 1)

BS1[3:0] determine the length of Bit Segm e nt 1.

tBS1 = tCAN * (BS1 + 1)

Note: Writing to this register is allowed only in

Standby mode t o prevent any accidental CAN pr o-

tocol violation through programming errors.

PAGE SELECTION REGISTER (PSR)

Read/Write

Reset Value: 00h

PAGE[2:0] determine which buffer or filte r page is

mapped at addresses 0010h to 001Fh.

RJW1 RJW0 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0

BR 1

tCPU BRP 1+()×BS1 BS2 3++()×

----------------------------------------------------------------------------------------------------=

0 BS22 BS21 BS20 BS13 BS12 BS11 BS10

00000

PAGE

2PAGE

1PAGE

PAGE2 PAGE1 PAGE0 Page Title

0 0 0 Diagnosis

001Buffer 1

010Buffer 2

011Buffer 3

100Filters

1 0 1 Reserved

1 1 0 Reserved

1 1 1 Reserved

ST72F521, ST72521B

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CONTROLLER AREA NETWORK (Cont’d)

10.8.4.2 Paged Registers

LAST IDENTIFIER HIGH REGISTER (LIDHR)

Read/Write

Reset Value: Undefined

LID[10:3] are the most significant 8 bits of the last

Identifier read on the CAN bus.

LAST IDENTIFIER LOW REGISTER (LIDLR)

Read/Write

Reset Value: Undefined

LID[2:0] are the least significant 3 bits of the last

Identifier read on the CAN bus.

LRTR is the last Remote Transmission Request bit

read on the CAN bus.

LDLC[3:0] is the last Data Length Code read on the

CAN bus.

TRANSMIT ERROR COUNTER REG. (TECR)

Read Only

Reset Value: 00h

TEC[7:0] is the least significant byte of the 9-bit

Transmit Error Counter implementing part of the

fault confinement mecha nism of the CAN protocol.

In case of an error during transmission, this counter

is incremented by 8. It is decremented by 1 after

every successful transmission. When the counter

value exceeds 127, the CAN controller enters the

error passive state. When a value of 256 is reached,

the CAN controller is disconnected from the bu s.

RECEIVE ERROR COUNTER REG. (RECR)

Page: 00h — Read Only

Reset Value: 00h

REC[7:0] is the Receive Error Counter imple ment-

ing part of the fa ult co nfinem ent mech anism of t he

CAN protocol. In case of an error during reception,

this counter is incremente d by 1 or by 8 depending

on the error condition as defined by the CAN stand-

ard. After every successful reception the counter is

decremented by 1 or reset to 120 if its value was

higher than 128. When the counter value exceeds

127, the CAN controller enters the error passive

state.

IDENTIFIER HIGH REGISTERS (IDHRx)

Read/Write

Reset Value: Undefined

ID[10:3] are the most significant 8 bits of the 11-bit

message identifier.The identifier acts as the mes-

sage’s name, used for bus access arbitration and

acceptance filtering.

LID10 LID9 LID8 LID7 LID6 LID5 LID4 LID3

LID2 LID1 LID0 LRTR LDLC

3LDLC

2LDLC

1LDLC

TEC7 TEC6 TEC5 TEC4 TEC3 TEC2 TEC1 TEC0

REC7 REC6 REC5 REC4 REC3 REC2 REC1 REC0

ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3

ST72F521, ST72521B

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CONTROLLER AREA NETWORK (Cont’d)

IDENTIFIER LOW REGISTERS (IDLRx)

Read/Write

Reset Value: Undefined

ID[2:0] are the least significant 3 bits of the 11-bit

message identifier.

RTR is the Remote Transmission Requ est bit. It is

set to indicate a r emote frame and reset to indica te

a data frame.

DLC[3:0] is the Data Length Code. It gives the

number of bytes in the data field of the mes-

sage.The valid range is 0 to 8.

DATA REGISTERS (DATA0-7x)

Read/Write

Reset Value: Undefined

DATA[7:0] is a message data byte. Up to eight such

bytes may be part of a message. Writing to byte

DATA7 initiates a transmit request and should al-

ways be done even when DATA7 is not part of the

message.

BUFFER CONTROL/STATUS REGs. (B CSRx)

Read/Write

Reset Value: 00h

Bit 3 = ACC Acceptance Code

− Read Only

Set by hardware with the id of the highest priority

filter which accepted the message stored in the

buffer.

ACC = 0: Match for Filter/Mask0. Possible match

for Filter/Mas k1.

ACC = 1: No match for Filter/Mask0 and match for

Filter/Mask1.

Reset by hardware whe n either RDY or RXIF gets

reset.

Bit 2 = RDY Message Ready

− Read/Clear

Set by hardware to signal that a new error-free

message is available (LOCK = 0) or that a trans-

mission request is pending (LOCK = 1).

Cleared by software when LOCK = 0 to release

the buffer and to clear the corresponding RXIF bit

in the Interrupt Status Register.

Cleared by hardware when LOCK = 1 to indicate

that the transmission re quest has been serviced or

cancelled.

Bit 1 = BUSY Busy Buffer

− Read Only

Set by hardware when the buffer is being filled

(LOCK = 0) or emp tied (LO CK = 1) a nd reset af ter

the 2nd intermission bit.

Reset by hardware when the buffer is not ac-

cessed by the CAN core for transmission nor re-

ception purposes.

Bit 0 = LOCK Lock Buffer

− Read/Set/Clear

Set by software to lo ck a buffer. No more message

can be received into the buffer thus preserving its

content and making it availab le for transmission.

Cleared by software to make the buffer available

for reception. Cancels any pending transmission

request.

Cleared by hardware once a message has been

successfully transmitted provided the early trans-

mit interrupt mode is on. Left untouched othe rwise.

Note that in order to prevent any message corrup-

tion or loss of context, LOCK cannot be set nor re-

set while BUSY is set. Trying to do so will result in

LOCK not changing state.

ID2 ID1 ID0 RTR DLC3 DLC2 DLC1 DLC0

DATA

7DATA

6DATA

5DATA

4DATA

3DATA

2DATA

1DATA

0 0 0 0 ACC RDY BUSY LOCK

ST72F521, ST72521B

142/215

CONTROLLER AREA NETWORK (Cont’d)

FILTER HIGH REGISTERS (FHRx)

Read/Write

Reset Value: Undefined

FIL[11:3] are the most significant 8 bits of a 12-bit

message filter. The acceptance filter is compared

bit by bit with the identifier and the RTR bit of the

incoming message. If there is a match for the set

of bits specified by the acceptance mask then the

message is store d in a re ce ive bu ff er .

FILTER LOW REGISTERS (FLRx)

Read/Write

Reset Value: Undefined

FIL[3:0] are the least significant 4 bits of a 12-bit

message filter.

MASK HIGH REGISTERS (MHRx)

Read/Write

Reset Value: Undefined

MSK[11:3] are the most significant 8 bits of a 12-

bit message mask. The acceptance mask defines

which bits of the acceptance filter should match

the identifier an d the RTR bit of the incoming mes-

sage.

MSKi = 0: don’t care.

MSKi = 1: match required.

MASK LOW REGISTERS (MLRx)

Read/Write

Reset Value: Undefined

MSK[3:0] are the least significant 4 bits of a 12-bit

message mask.

FIL11 FIL10 FIL9 FIL8 FIL7 FIL6 FIL5 FlL4

FIL3 FIL2 FIL1 FIL0 0 0 0 0

MSK1

1MSK1

0MSK9 MSK8 MSK7 MSK6 MSK5 MSK4

MSK3 MSK2 MSK1 MSK0 0 0 0 0

ST72F521, ST72521B

143/215

CONTROLLER AREA NETWORK (Cont’d)

Figure 73. CAN Register Map

Interrupt Status

Interrupt Control

Control/Status

Baud Rate Prescaler

Page Selection

Paged Reg1

Paged Reg2

Paged Reg3

Paged Reg4

Paged Reg5

Paged Reg6

Paged Reg7

Paged Reg8

Paged Reg9

Paged Reg10

Paged Reg11

Paged Reg12

Paged Reg13

Paged Reg14

Paged Reg15

Paged Reg1

Paged Reg2

Paged Reg3

Paged Reg4

Paged Reg5

Paged Reg6

Paged Reg7

Paged Reg8

Paged Reg9

Paged Reg10

Paged Reg11

Paged Reg12

Paged Reg13

Paged Reg14

Paged Reg15

Paged Reg1

Paged Reg2

Paged Reg3

Paged Reg4

Paged Reg5

Paged Reg6

Paged Reg7

Paged Reg8

Paged Reg9

Paged Reg10

Paged Reg11

Paged Reg12

Paged Reg13

Paged Reg14

Paged Reg15

Paged Reg1

Paged Reg2

Paged Reg3

Paged Reg4

Paged Reg5

Paged Reg6

Paged Reg7

Paged Reg8

Paged Reg9

Paged Reg10

Paged Reg11

Paged Reg12

Paged Reg13

Paged Reg14

Paged Reg15

Paged Reg0

Paged Reg1

Paged Reg2

Paged Reg3

Paged Reg4

Paged Reg5

Paged Reg6

Paged Reg7

Paged Reg8

Paged Reg9

Paged Reg10

Paged Reg11

Paged Reg12

Paged Reg13

Paged Reg14

Paged Reg15

6Fh

5Ch

5Ah

5Bh

5Dh

5Fh

60h

Bit Timing

5Eh

ST72F521, ST72521B

144/215

CONTROLLER AREA NETWORK (Cont’d)

Figure 74. Page Maps

60h

61h

62h

63h

64h

65h

66h

67h

68h

69h

6Ah

6Bh

6Ch

6Dh

6Eh

6Fh

FHR0

FLR0

MHR0

MLR0

FHR1

FLR1

MHR1

MLR1

Reserved

IDHR1

IDLR1

DATA01

DATA11

DATA21

DATA31

DATA41

DATA51

DATA61

DATA71

Reserved

BCSR1

LIDHR

LIDLR

Reserved

TECR

RECR

IDHR2

IDLR2

DATA02

DATA12

DATA22

DATA32

DATA42

DATA52

DATA62

DATA72

Reserved

BCSR2

IDHR3

IDLR3

DATA03

DATA13

DATA23

DATA33

DATA43

DATA53

DATA63

DATA73

Reserved

BCSR3

PAGE 0 P AGE 1 PAGE 2 PAGE 3 PAGE 4

Diagnosis Buffer 1 Buffer 2 Buffer 3 Acceptance Filters

ST72F521, ST72521B

145/215

CONTROLLER AREA NETWORK (Cont’d)

Table 24. CAN Register Map and Reset Values

Address

(Hex.) Page Register

Label 76543210

5A CANISR

Reset Value RXIF3

0RXIF2

0RXIF1

0TXIF

0SCIF

0ORIF

0TEIF

0EPND

5B CANICR

Reset Value 0 ESCI

0RXIE

0TXIE

0SCIE

0ORIE

0TEIE

0ETX

5C CANCSR

Reset Value 0 BOFF

0EPSV

0SRTE

0NRTX

0FSYN

0WKPS

0RUN

5D CANBRPR

Reset Value RJW1

0RJW0

0BRP5

0BRP4

0BRP3

0BRP2

0BRP1

0BRP0

5E CANBTR

Reset Value 0 BS22

0BS21

1BS20

0BS13

0BS12

0BS11

1BS10

5F CANPSR

Reset Value 0 0 0 0 0 PAGE2

0PAGE1

0PAGE0

60 0CANLIDHR

Reset Value LID10

xLID9

xLID8

xLID7

xLID6

xLID5

xLID4

xLID3

1 to 3 CANIDHRx

Reset Value ID10

xID9

xID8

xID7

xID6

xID5

xID4

xID3

60, 64 4 CANFHRx

Reset Value FIL11

xFIL10

xFIL9

xFIL8

xFIL7

xFIL6

xFIL5

xFIL4

61 0CANLIDLR

Reset Value LID2

xLID1

xLID0

xLRTR

xLDLC3

xLDLC2

xLDLC1

xLDLC0

1 to 3 CANIDLRx

Reset Value ID2

xID1

xID0

xRTR

xDLC3

xDLC2

xDLC1

xDLC0

61, 65 4 CANFLRx

Reset Value FIL3

xFIL2

xFIL1

xFIL0

x0000

62 to 69 1 to 3 CANDRx

Reset Value MSB

xxxxxxx

LSB

62, 66 4 CANMHRx

Reset Value MSK11

xMSK10

xMSK9

xMSK8

xMSK7

xMSK6

xMSK5

xMSK4

63, 67 4 CANMLRx

Reset Value MSK3

xMSK2

xMSK1

xMSK0

x0000

6E 0 CANTECR

Reset Value MSB

0000000

LSB

CANRECR

Reset Value MSB

0000000

LSB

1 to 3 CANBCSRx

Reset Value 0 0 0 0 ACC

0RDY

0BUSY

0LOCK

ST72F521, ST72521B

146/215

CONTROLLER AREA NETWORK (Cont’d)

10.8.5 List of CAN Cell Limitations

10.8.5.1 Omitte d SOF bit

Symptom:

Start of Frame (SOF) bit is omitted if transmission

is requested in the last Intermission bit.

Test Case:

5.3.1 10-Kbit St ress Test

Details:

The IUT is request ed to start transm ission immedi-

ately after the com pletion of the previou s transmis-

sion. The LT also starts its transmission and as-

serts the SOF bit just after the 3rd Intermissi on bit.

The IUT also starts transmission but omits the

SOF bit. The IUT wins the arbitration and contin-

ues the transmission. The frame is sent correctly.

Impact On The Application:

As this effect only occurs when the IUT detects a

SOF bit on the CAN bus, the fact that it omits its

own SOF bit has no impact on the commun ication.

10.8.5.2 CAN: CPU Write Access (More Than

One Cycle) Corrupts CAN Frame

Symptoms:

For CAN received messages the identifier high

byte or last data byte can be corrupted.

For CAN transmitted messages the 2nd data byte

can be corrupted.

Details:

The CAN transmit and receive buffers are imple-

mented as dual ported RAM. During the reception

of a CAN frame the CAN core writes the received

identifier and the data byte-by-byte in the corre-

sponding buffer.

IF the CAN bit t iming co nfigu rat ion is tBS2 < 5 time

quanta

AND

IF concurrently with the pCAN, the CPU executes

a write access to the dual port ed RAM using an in-

struction with more than one cycle access, e.g.

CLR, BSET, BRES

THEN the access conflict can lead to the corrup-

tion described in the symptoms paragraph above.

Impact On The Ap plica tion :

Several CAN frames with erroneous data or iden-

tifier will be received/transmitted.

Software Workaround:

Program tBS2 > 4 time quanta or, when accessing

the receive or transmit buffers, do no t us e th e cr it-

ical instructions which are:

BSET, BRES, CLR, CPL, DEC, INC, NEG, RLC,

SLL, SRL, RRC, SRA, SWAP.

ST72F521, ST72521B

147/215

CONTROLLER AREA NETWORK (Cont’d)

10.8.5.3 Unexpec ted message trans mis si on

Symptom:

The prev ious messa ge rec eived b y pCAN, ev en if

this message did not pass the receive filter, will be

retransmitted by pCAN with a correct identif ier and

DLC but with corrupted data. The data bytes will

be a copy of the identifier bytes IDHR and IDLR in

the following repetitive pattern:

DATA_0 = IDHR

DATA_1 = IDLR

DATA_2 = IDHR

DATA_3 = IDLR

etc.

DATA_7 = IDLR

If no message has bee n re ceive d be fo re the pr ob-

lem occurs then identifier byte values are random

but the data bytes are in the same repetitive pat-

tern.

Details:

The buffers of the pCAN cell are configurable as

receive or transmit buffers. By default, all buffers

are configured in reception. To use a buffer to

transmit a CAN messag e the application has t o re-

serve this buffer for transmission by setting the

LOCK bit in the BCSR register. So the buffer is

then locked for a ny furt he r recept io n an d rese rved

for transmission.

Once a transmission has been requested by a

write access to data byte 7 of the buffer the appli-

cation might need to abort this transmission re-

quest. To do so, the application can reset the

LOCK bit in the BCSR register.

If the message is pending (RDY bit set) but not

currently being transmitted, then clearing the

LOCK bit will abort it immediately.

If the message is pending (RDY bit set) and cur-

rently being transmitted then the message will not

be interrupted but the CAN core will wait until the

end of this transmission attempt. Then software

must clear the LOCK bit again to abort the trans-

mission.

An unexpected transmis sio n ca n occ ur :

IF the application resets the LO CK bit

WHILE the CAN core is preparing the

transmission1) AND there is no other transm ission

pending in another buff er

THEN the LOCK bit is reset but the t ransmission is

not stopped. Instead the content of the page 0

buffer will be transmitted.

Impact On The Application:

pCAN will echo some messages sent by other

nodes. Identifier and DLC will be correct but data

are corrupted as described previously.

Note 1: The preparation lasts two bit times just be-

fore SOF, this is the critic al window during which

the LOCK bit must not be reset by the application.

ST72F521, ST72521B

148/215

CONTROLLER AREA NETWORK (Cont’d)

Software Work-around - Devices with Hard-

ware Fix (ST72F521 rev “R”):

To implement a transmission abort under safe

conditions, the LOCK bit must not be reset during

the critical window (2 bit times). A new function

has been implemented in the MCU allowing the

application to synchronize the reset of the LOCK

bit (abort request) with the reset of the TXRQST bit

(internal signal) in the pCAN core.

The synchronization is done using the WKPS bit in

the CANCSR register, the function of this bit has

been modified and n o mo re Wake- up Pulse (d om-

inant bit) is sent on the CAN_TX signal when the

WKPS bit is set. This means the functionality de-

scribed in the datasheet is no longer applicable

(see Section 10.8.5.4).

To abort the transmission, f irst the application sets

the WKPS bit and polls it until it is set. The maxi-

mum time needed to set this bit is two CAN bit

times. Once the application has read the WKPS bit

as one, it can reset the LOCK bit to stop the cur-

rent transmission.

The abort is completed wh en the LO CK bit is read

back as zero by the application. Once the abort

has been completed, the application must reset

the WKPS bit to be able to transmit again. Of

course the transmit buffer must be in LOCK state

as usual before any transmission attempt.

The “C” code sequence below sh ows the software

work-around usin g the WKPS bit.

CANCSR |= WKPS; // Set WKPS bit

while(!(CANCSR & WKPS) );// Wait until WKPS bit is set

while( CANBCSR & LOCK )// Wait until abort has been confirmed

{

CANBCSR &= ~LOCK;

}

CANCSR &= ~WKPS; // Allow transmission again

CANBCSR |= LOCK; //Alloc buffer for next transmission

ST72F521, ST72521B

149/215

CONTROLLER AREA NETWORK (Cont’d)

Software Work-a round - De vices with out Hard-

ware Fix:

To implement a transmission abort under safe

conditions, any reset of the LOCK bit during the

critical window (2 bit times) must be avoided. Two

different cases have to be considered, either the

pCAN enters standby mode after the abort, or the

abort is performed and pCAN keeps running.

Abort followed by STANDBY mode (RUN=0)

In this case, aborting the pending transmissions

can safely be done by first entering STANDBY

mode and then releasing the transmit buffers.

STANDBY mode is entered by resetting the RUN

bit in the CSR register and once the current trans-

mission attempt, even if it fails due to error or lost

arbitration, has been performed, pCAN enters

STANDBY mode (RUN=0). Once in STANDBY

mode the application can abort all pending trans-

missions by resetting the corresp onding LOCK bit.

Abort while staying in RUN mode (RUN=1)

Contrary to the STANDBY case described previ-

ously, in the RUN case the application has to han-

dle the error or arbitration lost conditions. In case

of transmission errors, causing the frame to be

transmitted again and again, the application must

set the NRTX bit in the CSR register. This will

cause pCAN to abort the transmission at the end

of the curren t att em p t.

In case of arbitration lost, setting the NRTX bit

does not abort the transmission, therefore the ap-

plication must reset the LOCK bit to abort the

transmission. To avoid r esetti ng the LO CK bit dur-

ing the critical t ime window, leading to th e problem

described at the start of this section, the applica-

tion must monitor the BUSY bit in the BCSR regis-

ter and reset the LOCK bit just after the falling

edge of the BUSY bit. The time between the falling

edge of the BUSY bit and the SOF of the next

transmission attempt is in any case long eno ugh to

guarantee that the LOCK bit is reset before the

critical time window.

The “C” code sequence below sh ows the software

work-around for both the error and arbitration lost

cases.

_asm("SIM\n"); // Mask interrupts

CANCSR |= NRTX; // Set non automatic retransmission bit

while(!(CANBCSR & BUSY) &&// Wait till BUSY bit is set

(CANBCSR & RDY) ); // or transmission done

while( CANBCSR & BUSY ); // Wait till BUSY bit is reset (falling edge)

if( CANBCSR & RDY )

{ // transmission still pending -> must be aborted

CANBCSR &= ~LOCK; //Arbitration lost => cancel transmission safe

while( CANBCSR & RDY );// Wait for unlock confirmed

CANCSR &= ~NRTX;// Reset NRTX bit once abort sequence done

_asm("RIM\n");

}

else

{ // No more abort required as RDY bit already reset

CANCSR &= ~NRTX;// Reset NRTX bit once abort sequence done

_asm("RIM\n"); // Enable interrupts

}

ST72F521, ST72521B

150/215

Figure 75. Work-around Flowchart

Application Requests

an Abort

READY == 1

BUSY == 0

SET NRTX

MASK INT

READY == 1

YES

YES NO

READY == 1

YES NO

AND

RESET LOCK

READY == 1

ENABLE INT

RESET NRTX

YES

Abort Done

SET LOCK

ST72F521, ST72521B

151/215

CONTROLLER AREA NETWORK (Cont’d)

The figures below sh ow th e ab ort be havio ur in the

four possible cases.

Figure 76. Abort and successful transmission

In this case the abort requ est performed during the

transmission has no effect, as the first transmis-

sion is successful.

Figure 77. Abort and trans m ission delayed by

busy CAN bus

In this case the NR TX bit is set to ab ort the trans -

mission aft er the first attemp t. As the first at tempt

is successful the READY and BUSY bits are reset

by pCAN and the transmit buffer becomes empty.

An abort is no longer required.

Figure 78. Abort and err or during transmiss ion

In this case NRTX (abort request ) is set before the

error, thus pCAN resets READY and BUSY after

the error (the first attempt). The abort has been

successful an d th e tra n sm i t bu ffe r is empty.

Figure 79. Abort and arbitration lost

In this case the NRTX bit is set but has no effect,

as the previous transmission attempt failed due to

an arbitration lost. The application waits for the

falling edge of BUSY bit and checks that READY is

still set. This is the case, this means pCAN has lost

the arbitration and LOCK bit can be safely reset.

Abort is immediate and pCAN resets the READY

and BUSY bits.

Timing Considerations

As no interrupt signals tha t an abort has been suc-

cessful, the application has to wait until the trans-

mit buffer is empty (transmission has been aborted

or transmitted successfully). This time can vary

depending on the case in which the abort is per-

formed (arbitration lost, error or successful trans-

mission). To show the impact of the software work-

around on this timing behaviour Figure 80 and Fig-

ure 81 compare the reference behaviour (worst

case when abort is done by LOCK only) with the

behaviour when NRTX, BUSY and LOCK bits are

used.

Figure 80. Abort by LOCK only - Reference

behaviour

CAN TX

CAN RX

LOCK

READY

BUSY

TX RQST

NRTX

ABORT RQST

CAN TX

CAN RX

LOCK

READY

BUSY

TX RQST

NRTX

ABORT RQST

CAN TX

CAN RX

LOCK

READY

BUSY

TX RQST

NRTX

ABORT RQST

Error

CAN TX

CAN RX

LOCK

READY

BUSY

TX RQST

NRTX

ABORT RQST

CAN TX

CAN RX

LOCK

READY

BUSY

TX RQST

NRTX

ABORT RQST

ST72F521, ST72521B

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CONTROLLER AREA NETWORK (Cont’d)

The worst case is when the abort request is done

when the transmission has just started. In this

case the LOCK bit cannot be reset as long as the

BUSY bit is set, this means until the end of the

frame. So the application will wait for READY to be

reset during the whole frame and in this case the

worst case will be the longest frame the applica-

tion is expected to transmit.

Figure 81. Abort with the software work-around

- by NRTX, BUSY and LOCK

Using the software work-around the worst case

occurs in the arbit ration lost case. If th e abort is re-

quested just after pCAN has lost the arbitration

then the application has to wait for the next falling

edge of the BUSY bit before the LOCK bit can be

reset. If the next arbitration is won by pCAN then

the BUSY bit will be reset by the end of the suc-

cessful transmission. The longest time the applica-

tion has to wait in this case is the tim e of the long -

est message expected on the bus (minus identifi-

er) plus the longest message expected to be trans-

mitted by the application. This roughly double the

time the application may have to wait before the

abort sequence is performed.

10.8.5.4 WKPS Functional it y

Due to a fix implemented to solve the “Unexpected

Message Transmission” issue (see Section

10.8.5.3) the WKPS functionality has been modi-

fied as follows in Flash ST72F521 devices:

CAN TX

CAN RX

LOCK

READY

BUSY

TX RQST

NRTX

ABORT RQST

Device Modification

Flash

ST72F521

Rev R

WKPS bit does not generate a wakeup

pulse. It is used to synchronize the re-

set of the LOCK bit (see “Software

Work-around - Devices with Hardware

Fix (ST72F521 rev “R”):” on page 148)

ROM

ST72521 All

revisions

WKPS bit functions according to the

datasheet description.

ST72F521, ST72521B

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CONTROLLER AREA NETWORK (Cont’d)

10.8.5.5 Bus- off state not entered

Symptom:

pCAN does not enter bus-off state under certain

conditions. This is fixed in FLASH version of

ST72F521 starting from silicon Rev R and in ROM

version ST72521B starting from silicon Rev Y.

Details:

According to the CAN stan dard, pCAN is expected

to enter bus-off state when TEC (Transmit Error

Counter) is greater than 255.

But if REC (Receive Error Count er) is greater t han

127 (Error Passive State) pCAN does not enter

bus-off and the BOFF bit of the CSR register is not

set. To enter bu s-off, REC must decrease to a val-

ue lower than 128 , this is the case with any corr ect

reception even if the message is f iltered out.

As bus-off state is not entered and pCAN still at-

tempts to transmit its message, after the overflow

the TEC register continue s to increment as long as

transmission errors occur.

Impact on the application:

The application will not stop attempting to transmit

CAN messages, even when t he bu s- of f co nd itio ns

have been reached, until the transmission has

been successful or the value of REC becomes

lower than 128. However the application will not

disturb the communication of the other nodes on

the CAN network as pCAN is in Error Passive

State.

Figure 82. CAN Error State Diagram showing “BUSOFF not entered” limitation

ERROR PASSIVE

When TECR or RECR > 127, the EPSV bit gets set

When TECR and RECR < 128,

ERROR ACTIVE

BUS OFF

When TECR > 255 and RECR < 128 the BOFF bit When 128 * 11 recessive bits occur:

- the BOFF bit gets cleared

- the TECR register gets cleared

- the RECR register gets cleared

the EPSV bit gets cleared

gets set a nd the EPSV bit gets cleared

ST72F521, ST72521B

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CONTROLLER AREA NETWORK (Cont’d)

Workaround Description

The bus-off entry works correct ly in almost all cas-

es, only when REC is greater than 127 a bus-off

will not be recognized by pCAN. Therefore the

pCAN bus-off signalling (BOFF) is still used but it

needs to be complemented by monitoring TEC by

software.

To detect the b us-off conditio n by soft ware the ap-

plication has to monitor the value of the TEC reg-

ister periodically. An overflow signals a bus-off

condition. When a bus-off condition has been de-

tected the application must execute the following

sequence to recover fr om bus-off prop erly: the ap-

plication stops pCAN by clearing the RUN bit in the

CANCSR register resets all pending transmission

by clearing the LOCK bit in the BCSR reg iste r and

starts it again by setting the RUN bit.

To detect the bus-off condition properly, the TEC

monitoring period must be lower than the time be-

tween two overflows. As the problem only occurs

when pCAN is in Error Passive St at e (R EC > 1 27)

pCAN will continuously try to send a SOF followed

by an Error Passive Flag and a Suspend Trans-

mission. This leads to 26 (1 + 6 + 8 + 3 + 8) bit

times. Each time TEC is incremented by 8, hence

to reach 256 the sequence must be executed 32

times. Under these conditions the shortest se-

quence leading to a TEC overflow lasts 832 bit

times.

Depending on the baudrate the application will

have to adapt the monitoring period, for example

at 500kbps the period must be less than 1600us.

The ‘C’ code below shows an implementation ex-

ample of the monitoring sequence. This code is

called periodically as described above.

To detect the overflow, the test condition must

take into account that TEC might also have been

decremented due to a successful transmission. So

an overflow condition is detected:

IF the current TEC value is lower than the previous

TEC value

AND the difference is greater than the number of

possible successful transmissions during the mon-

itoring period.

In the example above, one message can be sent,

therefore one is added t o CANTECR.

************************************************/

/* INITIALISATION

/************************************************/

unsigned char TECReg=0; //Previous value of TEC

unsigned char BusOffFlag=0; //Set to one if bus-off

/************************************************/

/* BUS-OFF MONITORING SEQUENCE

/************************************************/

if( (CANCSR & BOFF) || ( CANTECR+1 < TECReg) )

{

BusOffFlag = 1;

}

else

{

TECReg = CANTECR;

}

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10.9 10-BIT A/D CONVERTER (ADC)

10.9.1 Introduction

The on-chip Analog to Digit al Converter (ADC) pe-

ripheral is a 10-bit, successive approxima tion con-

verter with internal sample and hold circuitry. This

peripheral has up to 16 multiplexed analog input

channels (refer to device pin out description) that

allow the peripheral to convert the analog voltage

levels from up to 16 different sources.

The result of the conversion is stored in a 10-bit

Data Register. The A/D converter is controlled

through a Cont ro l/Sta tus Re gister.

10.9.2 Main Features

■10-bit conversio n

■Up to 16 channels with multiplexed input

■Linear successive approximation

■Data register (DR) which contains the results

■Conversion complete status flag

■On/off bit (to reduce consumption)

The block diagram is shown in Figure 83.

Figure 83. ADC Block Diagram

CH2 CH1EOC SPEEDADON 0 CH0 ADCCSR

AIN0

AIN1 ANALOG TO DIGITAL

CONVERTER

AINx

ANALOG

MUX

D4 D3D5D9 D8 D7 D6 D2

ADCDRH

DIV 4 fADC

fCPU

D1 D0

ADCDRL

000000

CH3

DIV 2

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10-BIT A/D CONVERTER (ADC) (Cont’d)

10.9.3 Functional Description

The conversion is mono tonic, meaning that the re-

sult never decreases if the analog input does not

and never increases if the analog input doe s not.

If the input voltage (VAIN) is greater than VAREF

(high-level voltage reference) then the conversion

result is FFh in the ADCDRH register and 03h in

the ADCDRL register (without overflow indication).

If the input vo ltage (VAIN) is lower than VSSA (low-

level voltage reference) t hen t he conver sio n result

in the ADCDRH and ADCDRL registers is 00 00h.

The A/D converter is linear and the dig ital result of

the conversion is stored in the ADCDRH and AD-

CDRL registers. The accuracy of the conversion is

described in the Electrical Characteristics Section.

RAIN is the maximum recommended impedance

for an analog input signal. If the impedance is too

high, this will result in a loss of accuracy due to

leakage and sampling not being completed in the

alloted time.

10.9.3.1 A/D Conve r ter Configuration

The analog input ports must be configured as in-

put, no pull-up, no interrupt. Refer to the «I/O

ports» chapter. Using these pins as analog inputs

does not affect the ability of the port to be read as

a logic input.

In the ADCCSR register :

– Select the CS[3:0] bits to assign the analog

channel to convert.

10.9.3.2 Starting the Conversion

In the ADCCSR register :

– Set the ADON bit to enable the A/D converter

and to start the conversion. From this time on,

the ADC performs a continuous conversion of

the selected channel.

When a conversion is complete:

– The EOC bit is set by hardware.

– The result is in the ADC DR re gist er s.

A read to the ADCDRH re se ts th e EOC bit.

To read the 10 bits, perform the following steps:

1. Poll the EOC bit

2. Read the ADCDRL register

3. Read the ADCDRH register. This clears EOC

automatically.

Note: The data is not la tche d, so bo th t he low and

the high data reg ister must be read before t he next

conversion is complete, so it is recommended to

disable inter ru p ts wh ile re ad in g th e co nv er sio n re -

sult.

To read only 8 bits, perform the following steps:

1. Poll the EOC bit

2. Read the ADCDRH register. This clears EOC

automatically.

10.9.3.3 Changing the conversion channel

The application can change channels during con-

version. When software modifies the CH[3:0] bits

in the ADCCSR re gister , the cur rent co nver sion is

stopped, the EOC bit is cleared, and the A/D con-

verter starts converting the newly selected chan-

nel.

10.9.4 Low Power Modes

Note: The A/D converter may be disabled by re-

setting the ADON bit. This feature allows reduced

power consumption when no conversion is need-

ed and between single shot conversions.

10.9.5 Interrupts

None.

Mode Description

WAIT No effect on A/D Converter

HALT

A/D Converter disabled.

After wakeup from Halt mode, the A/D

Converter requires a stabilization time

tSTAB (see Electrical Characteristics)

before accurate conversions can be

performed.

ST72F521, ST72521B

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10-BIT A/D CONVERTER (ADC) (Cont’d)

10.9.6 Register Description

CONTROL/STATUS REGISTER (ADCCSR)

Read/Write (Except bit 7 read only)

Reset Value: 0000 0000 (00h)

Bit 7 = EOC End of Conversion

This bit is set by hardware. It is cleared by hard-

ware when software reads the ADCDRH register

or writes to any bit of the ADCCSR register.

0: Conversion is not complete

1: Conversion com p le te

Bit 6 = SPEED ADC clock selection

This bit is set and cleared by software.

0: fADC = fCPU/4

1: fADC = fCPU/2

Bit 5 = ADON A/D Converter on

This bit is set and cleared by software.

0: Disable ADC and stop conversion

1: Enable ADC and start conversion

Bit 4 = Reserved. Must be kept cleared.

Bit 3:0 = CH[3:0] Channel Selection

These bits are set and cleared by software. They

select the analog input to convert.

*The number of channels is device dependent. Refer to

the device pinout description.

DATA REGISTER (ADCDRH)

Read Only

Reset Value: 0000 0000 (00h)

Bit 7:0 = D[9:2] MSB of Converte d Ana l o g Value

DATA REGISTER (ADCDRL)

Read Only

Reset Value: 0000 0000 (00h)

Bit 7:2 = Reserved. Forced by hardware to 0.

Bit 1:0 = D[1:0] LSB of Converted Analog Value

EOC SPEED ADON 0 CH3 CH2 CH1 CH0

Channel Pin* CH3 CH2 CH1 CH0

AIN0 0 0 0 0

AIN1 0 0 0 1

AIN2 0 0 1 0

AIN3 0 0 1 1

AIN4 0 1 0 0

AIN5 0 1 0 1

AIN6 0 1 1 0

AIN7 0 1 1 1

AIN8 1 0 0 0

AIN9 1 0 0 1

AIN10 1 0 1 0

AIN11 1 0 1 1

AIN12 1 1 0 0

AIN13 1 1 0 1

AIN14 1 1 1 0

AIN15 1 1 1 1

D9 D8 D7 D6 D5 D4 D3 D2

000000D1D0

ST72F521, ST72521B

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10-BIT A/D CONVERTER (Cont’d)

Table 25. ADC Register Map and Reset Values

Address

(Hex.) Register

Label 76543210

0070h ADCCSR

Reset Valu e EOC

0SPEED

0ADON

CH3

0CH2

0CH1

0CH0

0071h ADCDRH

Reset Valu e D9

0D8

0D7

0D6

0D5

0D4

0D3

0D2

0072h ADCDRL

Reset Value000000

0D0

ST72F521, ST72521B

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11 INSTRUCTION SET

11.1 CPU ADDRESSING MODES

The CPU features 17 different addressing modes

which can be classified in 7 main groups:

The CPU Instruction set is designed to minimize

the number of byte s required per instruction: To do

so, most of the addressing modes may be subdi-

vided in two sub-modes called long and short:

– Long addressing mode is more powerful be-

cause it can use the full 64 Kbyte address space,

however it uses more bytes and more CPU cy-

cles.

– Short addressing mode is less powerful because

it can generally only access page zero (0000h -

00FFh range), but the instruction size is more

compact, and faster. All memory to memory in-

structions use sh or t ad dres s ing mo d es only

(CLR, CPL, NEG, BSET, BRES, BTJT, BTJF,

INC, DEC, RLC, RRC, SLL, SRL, SRA, SWAP)

The ST7 Assembler optimizes the use of long and

short addressing modes.

Table 26. CPU Addressing Mode Overview

Addressing Mode Example

Inherent nop

Immediate ld A,#$55

Direct ld A,$55

Indexed ld A,($55,X)

Indirect ld A,([$55],X)

Relative jrne loop

Bit operation bset byte,#5

Mode Syntax Destination Pointer

Address

(Hex.)

Pointer Size

(Hex.) Length

(Bytes)

Inherent nop + 0

Immediate ld A,#$55 + 1

Short Direct ld A,$10 00..FF + 1

Long Direct ld A,$1000 0000..FFFF + 2

No Offset Direct Indexed ld A,(X) 00..FF + 0

Short Direct Indexed ld A,($10,X) 00..1FE + 1

Long Direct Indexed ld A,($1000,X) 0000..FFFF + 2

Short Indirect ld A,[$10] 00..FF 00..FF byte + 2

Long Indirect ld A,[$10.w] 0000..FFFF 00..FF word + 2

Short Indirect Indexed ld A,([$10],X) 00..1FE 00..FF byte + 2

Long Indirect Indexed ld A,([$10.w],X) 0000..FFFF 00..FF word + 2

Relative Direct jrne loop PC+/-127 + 1

Relative Indirect jrne [$10] PC+/-127 00..FF byte + 2

Bit Direct bset $10,#7 00..FF + 1

Bit Indirect bset [$10],#7 00..FF 00..FF byte + 2

Bit Direct Relative btjt $10,#7,skip 00..FF + 2

Bit Indirect Relative btjt [$10],#7,skip 00..FF 00..FF byte + 3

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INSTRUCTION SET OVERVIEW (Cont’d)

11.1.1 Inherent

All Inherent instructions consist of a single byte.

The opcode fully specifies all the required informa-

tion for the CPU to pr ocess the operation.

11.1.2 Immediate

Immediate instructions have two bytes, the first

byte contains the opcode, the second byte con-

tains the operand value.

11.1.3 Direct

In Direct instruction s, the oper ands are ref erenced

by their memory address.

The direct addressing mode consists of two sub-

modes:

Direct (short)

The address is a byte, t hus re quires only on e byte

after the opcode, but only allows 00 - FF address-

ing space.

Direct (long)

The address is a word, th us allowing 64 Kbyte ad-

dressing s pace, but requ ires 2 bytes a fter the op-

code.

11.1.4 Indexed (No Offset, Short, Long)

In this mode, the operand is referenced by its

memory address, which is defined by the un signed

addition of an index regist er (X or Y) with an offset.

The indirect addressing mode consists of three

sub-modes:

Indexed (No Offset)

There is no offset, (no extra byte after the opco de),

and allows 00 - FF addressing space.

Indexed (Short)

The offset is a byte , thus requires only one byt e af-

ter the opcode and allows 00 - 1FE addressing

space.

Indexed (long)

The offset is a word, thus allowing 64 Kbyte ad-

dressing space and requires 2 bytes after the op-

code.

11.1.5 Indirect (Short, Long)

The required data byt e to do the operation is found

by its memory address, located in memory (point-

er).

The pointer address follows the opcode. The indi-

rect addre ssin g mod e co ns ists of two sub-mode s:

Indirect (short)

The pointer address is a byte, the pointer size is a

byte, thus allowing 00 - FF addressing space, and

requires 1 byte after the opcode.

Indirect (long)

The pointer address is a byte, the pointer size is a

word, thus allowing 64 Kbyte addressing space,

and requir es 1 byte afte r th e opcode.

Inherent Instruction Function

NOP No operation

TRAP S/W Interrupt

WFI Wait For Interrupt (Low Pow-

er Mode)

HALT Halt Oscillator (Lowest Power

Mode)

RET Sub-routine Return

IRET Interrupt Sub-routine Return

SIM Set Interrupt Mask (level 3)

RIM Reset Interrupt Mask (level 0)

SCF Set Carry Flag

RCF Reset Carry Flag

RSP Reset Stack Pointer

LD Load

CLR Clear

PUSH/POP Push/Pop to/from the stack

INC/DEC Increment/Decrement

TNZ Test Negative or Zero

CPL, NEG 1 or 2 Complement

MUL Byte Multiplication

SLL, SRL, SRA, RLC,

RRC Shift and Rotate Operations

SWAP Swap Nibbles

Immediate Instruction Function

LD Load

CP Compare

BCP Bit Compare

AND, OR, XOR Logical Operations

ADC, ADD, SUB, SBC Arithmetic Operations

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INSTRUCTION SET OVERVIEW (Cont’d)

11.1.6 Indirect Indexed (Short, Long)

This is a combination of indirect a nd short in dexed

addressing modes. The operand is referenced by

its memory address, which is defined by the un-

signed addition of an index register value (X or Y)

with a pointer value located in memory. The point-

er address follows the opcode.

The indirect indexed addressing mode consists of

two sub-modes:

Indirect Ind exed (Short)

The pointer address is a byte, the pointer size is a

byte, thus allowing 00 - 1FE addressing space,

and require s 1 byte after the op co de .

Indirect Ind exed (Long)

The pointer address is a byte, the pointer size is a

word, thus allowing 64 Kbyte addressing space,

and require s 1 byte after the op co de .

Table 27. Instructions Supporting Direct,

Indexed, Indirect and Indirect Indexed

Addressing Modes

11.1.7 Relative mode (Direct, Indirect)

This addressing mode is used to modify the PC

it.

The relative addressing mode consists of two sub-

modes:

Relative (Direct)

The offset is following the opcode.

Relative (Indirect)

The offset is defined in memory, which address

follows the opcode.

Long and Short

Instructions Function

LD Load

CP Compare

AND, OR, XOR Logical Operations

ADC, ADD, SUB, SBC Arithmetic Additions/Sub-

stractions operations

BCP Bit Compare

Short Instructions

Only Function

CLR Clear

INC, DEC Increment/Decrement

TNZ Test Negative or Zero

CPL, NEG 1 or 2 Complement

BSET, BRES Bit Operations

BTJT, BTJF Bit Test and Jump Opera-

tions

SLL, SRL, SRA, RLC,

RRC Shift and Rotate Opera-

tions

SWAP Swap Nibbles

CALL, JP Call or Jump subroutine

Available Relative

Direct/Indirect

Instructions Function

JRxx Conditional Jump

CALLR Call Relative

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INSTRUCTION SET OVERVIEW (Cont’d)

11.2 INSTRUCTION GROUPS

The ST7 family devices use an Instruction Set

consisting of 63 instr uctions. The instructions may be subdivided into 13 main groups as illustrated in

the following table:

Using a pre-byte

The instructions are describ ed with one to fo ur op-

codes.

In order to extend the number of available op-

codes for an 8-bi t CPU (256 opcodes), three differ-

ent prebyte opcodes are defined. These prebytes

modify the meaning of the instruction they pre-

cede.

The whole instruction becomes:

PC-2 End of prev iou s ins tru ct ion

PC-1 Prebyte

PC opcode

PC+1 Additional word (0 to 2) according

to the number of byt es required to compute the ef-

fective address

These prebytes enable instruction in Y as well as

indirect addressing modes to be implemented.

They precede the opcode of th e instr uction in X or

the instruction using direct addressing mode. The

prebytes are:

PDY 90 Replace an X based instruction

using immediate, direct, indexed, or inherent ad-

dressing mode by a Y one.

PIX 92 Replace an instruction using di-

rect, direct bit, or direct relative addressing mode

to an instruction using the corresponding indirect

addressing mode.

It also changes an instruction using X indexed ad-

dressing mode to an instruction using ind irect X in-

dexed addressing mode.

PIY 91 Replace an instruction using X in-

direct indexed addressing mode by a Y one.

Load and Transfer LD CLR

Stack operation PUSH POP RSP

Increment/Decrement INC DEC

Compare and Tests CP TNZ BCP

Logical operations AND OR XOR CPL NEG

Bit Operation BSET BRES

Conditional Bit Test and Branch BTJT BTJF

Arithmetic operations ADC ADD SUB SBC MUL

Shift and Rotates SLL SRL SRA RLC RRC SWAP SLA

Unconditional Jump or Call JRA JRT JRF JP CALL CALLR NOP RET

Conditional Branch JRxx

Interruption management TRAP WFI HALT I RET

Condition Code Flag modification SIM RIM SCF RCF

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INSTRUCTION SET OVERVIEW (Cont’d)

Mnemo Description Function/Example Dst Src I1 H I0 N Z C

ADC Add with Carry A = A + M + C A M H N Z C

ADD Addition A = A + M A M H N Z C

AND Logical And A = A . M A M N Z

BCP Bit compare A, Memory tst (A . M) A M N Z

BRES Bit Reset bres Byte, #3 M

BSET Bit Set bset Byte, #3 M

BTJF Jump if bit is false (0) btjf Byte, #3, Jmp1 M C

BTJT Jump if bit is true (1) btjt Byte, #3, Jmp1 M C

CALL Call subroutine

CALLR Call subroutine relative

CLR Clear reg, M 0 1

CP Arithmetic Compare tst(Reg - M) reg M N Z C

CPL One Complement A = FFH-A reg, M N Z 1

DEC Decrement dec Y reg, M N Z

HALT Halt 1 0

IRET Interrupt routine return Pop CC, A, X, PC I1 H I0 N Z C

INC Increm ent inc X reg, M N Z

JP Absolute J ump jp [TBL.w]

JRA Jump relative always

JRT Jump relative

JRF Never jump jrf *

JRIH Jump if ext. INT pin = 1 ( ext. INT pin high)

JRIL Jump if ext. INT pin = 0 (ext. INT pin low)

JRH Jump if H = 1 H = 1 ?

JRNH Jump if H = 0 H = 0 ?

JRM Jump if I1:0 = 11 I1:0 = 11 ?

JRNM Jump if I1:0 <> 11 I1:0 <> 11 ?

JRMI Jump if N = 1 (minus) N = 1 ?

JRPL Jump if N = 0 (plus) N = 0 ?

JREQ Jump if Z = 1 (equal) Z = 1 ?

JRNE Jump if Z = 0 (not equal) Z = 0 ?

JRC Jump if C = 1 C = 1 ?

JRNC Jump if C = 0 C = 0 ?

JRULT Jump if C = 1 Unsigned <

JRUGE Jump if C = 0 J mp if unsigned >=

JRUGT Jump if (C + Z = 0) Unsigned >

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INSTRUCTION SET OVERVIEW (Cont’d)

Mnemo Description Function/Example Dst Src I1 H I0 N Z C

JRULE Jump if (C + Z = 1) Unsigned <=

LD Load dst <= src reg, M M, reg N Z

MUL Multiply X,A = X * A A, X, Y X, Y, A 0 0

NEG Negate (2's compl) neg $10 reg, M N Z C

NOP No Operation

OR OR operation A = A + M A M N Z

POP Pop from the Stack pop reg reg M

pop CC CC M I1 H I0 N Z C

PUSH Push onto the Stack push Y M reg, CC

RCF Reset carry flag C = 0 0

RET Subroutine Return

RIM Enable Interrupts I1:0 = 10 (level 0) 1 0

RLC Rotate left true C C <= A <= C reg, M N Z C

RRC Rotate right true C C => A => C reg, M N Z C

RSP Reset Stack Pointer S = Max allowed

SBC Substract with Carry A = A - M - C A M N Z C

SCF Set carry flag C = 1 1

SIM Disable Interrupts I1:0 = 11 (level 3) 1 1

SLA Shift left Arithmetic C <= A <= 0 reg, M N Z C

SLL Shift left Logic C <= A <= 0 reg, M N Z C

SRL Shift right Logic 0 => A => C reg, M 0 Z C

SRA Shift right Arithmetic A7 => A => C reg, M N Z C

SUB Substraction A = A - M A M N Z C

SWAP SWAP nibbles A7-A4 <=> A3-A0 reg, M N Z

TNZ Tes t for Neg & Zero tnz lbl1 N Z

TRAP S/W trap S/W interrupt 1 1

WFI Wait for Interrupt 1 0

XOR Exclusive OR A = A XOR M A M N Z

ST72F521, ST72521B

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12 ELECTRICAL CHARACTERISTICS

12.1 PARAMETE R CONDITIONS

Unless otherwise specified, all voltages are re-

ferred to VSS.

12.1.1 Minimum and Ma ximum values

Unless otherwise specified the minimum and max-

imum values are guaranteed in the worst condi-

tions of ambient temperature, supply voltage and

frequencies by tests in production on 100% of the

devices with an ambient temperature at TA=25°C

and TA=TAmax (given by t he selected temperature

range).

Data based on characterization results, design

simulation and/or technology characteristics are

indicated in the table footnotes and are not tested

in production. Based on characterization, the min-

imum and maximum values refer to sample tests

and represent the mean value plus or minus three

times the standard deviation (mean±3Σ).

12.1.2 Typical values

Unless otherwise specified, typi cal data are based

on TA=25°C, VDD=5V.They are given only as de-

sign guidelines and are not tested.

12.1.3 Typical curves

Unless otherwise specified, all typical curves are

given only as design guidelines and are no t tested.

12.1.4 Loading capacitor

The loading conditions used for pin parameter

measurement ar e shown in Figure 84.

Figure 84. Pin loading conditions

12.1.5 Pin input voltage

The input voltage mea surement on a pin of the de-

vice is described in Figur e 85 .

Figure 85. Pin input voltage

ST7 PIN

VIN

ST7 PIN

ST72F521, ST72521B

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12.2 ABSOLUTE MAXIMUM RATINGS

Stresses above those listed as “absolute maxi-

mum ratings” may cause permanent damage to

the device. This is a stress rating only and func-

tional operation of the device under these condi-

tions is not implied. Exposure to maximum rating

conditions for extended periods may affect device

reliability.

12.2.1 Voltage Characteristics

12.2.2 Current Characteristics

Notes:

1. Directly connecting the RESET and I/O pins to VDD or VSS could damage the device if an unintentional internal reset

is generated or an unexpected change of the I/O configuration occurs (for example, due to a corrupted program counter).

To guarantee safe operation, this connection has to be done through a pull-up or pull-down resistor (typical: 4.7kΩ for

RESET, 10kΩ for I/Os). For the same reason, unused I/O pins must not be directly tied to VDD or VSS.

2. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum cannot be

respected, the injection current must be limited externally to the IINJ(PIN) value. A positive injection is induced by VIN>VDD

while a negative injection is induced by V IN<VSS. For true open-drain pads, there is no positive injection current, and the

corresponding VIN maximum must always be respected

3. All power (VDD) and ground (VSS) lines must always be connected to the external supply.

4. Negative injection disturbs the analog performance of the device. See note in “ADC Accuracy” on page 196.

For best reliability, it is recommended to avoid negative injection of more than 1.6mA.

5. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the positive

and negative injected currents (instantaneous values). These results are based on characterisation with ΣIINJ(PIN) maxi-

mum current injection on four I/O port pins of the device.

6. True open drain I/O port pins do not accept positive injection.

Symbol Ratings Maximum value Unit

VDD - VSS Supply voltage 6.5

VPP - VSS Programming Voltage 13

VIN 1) & 2) Input Voltage on true open drain pin VSS-0.3 to 6.5

Input voltage on any other pin VSS-0.3 to VDD+0.3

|∆VDDx| and |∆VSSx| Variations between different digital power pins 50 mV

|VSSA - VSSx| Variations between digital and analog ground pins 50

VESD(HBM) Electro-static discharge voltage (Human Body Model) see section 12.7.3 on page 181

VESD(MM) Electro-static discharge voltage (Machine Model)

Symbol Ratings Maximum value Unit

IVDD Total current into VDD power lines (source) 3) 150 mA

IVSS Total current out of VSS ground lines (sink) 3) 150

IIO

Output current sunk by any standard I/O and control pin 25

Output current sunk by any high sink I/O pin 50

Output current source by any I/Os and control pin - 25

IINJ(PIN) 2) & 4)

Injected current on VPP pin ± 5

Injected current on RESET pin ± 5

Injected current on OSC1 and OSC2 pins ± 5

Injected current on PC6 (Flash devices only) + 5

Injected current on any other pin 5) & 6) ± 5

ΣIINJ(PIN) 2) Total injected current (sum of all I/O and control pins) 5) ± 25

ST72F521, ST72521B

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12.2.3 Thermal Characteristics

12.3 OPERATING CONDITIONS

12.3.1 General Operating Conditions

Figure 86. fCPU Max Versus VDD

Note: Some temperature ranges are only available with a specific package and memory size. Refer to Or-

dering Information.

Symbol Ratings Value Unit

TSTG Storage temperature range -65 to +150 °C

TJMaximum junction temperature (see Section 13.2 THERMAL CHARACTERISTICS)

Symbol Parameter Conditions Min Max Unit

fCPU Internal clock frequency 0 8 MHz

VDD

Standard voltage range (except Flash

Write/Erase) 3.8 5.5 V

Operating Voltage for Flash Write/Erase VPP = 11.4 to 12.6V 4.5 5.5

TAAmbient temperature range

1 Suffix Version 0 70

°C

5 Suffix Version -10 85

6 or A Suffix Versions -40 85

7 or B Suffix Versions -40 105

C Suffix Version -40 125

fCPU [MHz]

SUPPLY VOLTAGE [V]

03.5 4.0 4.5 5.5

FUNCTIONALITY FUNCTIONALITY

GUARANTEED

IN THIS AREA

NOT GUARANTEED

IN THIS AREA

3.8

(UNLESS

OTHERWISE

SPECIFIED

IN THE TABLES

OF PARAMETRIC

DATA)

ST72F521, ST72521B

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OPERATING CONDITIONS (Cont’d)

12.3.2 Operating Conditions with Low Voltage Detector (LVD)

Subject to general operating conditions for VDD, fCPU, and TA.

Notes:

1. Data based on characterization results, tested in production for ROM devices only.

2. When VtPOR is faster than 100 µs/V, the Reset signal is released after a delay of max. 42µs after VDD crosses the

VIT+(LVD) threshold.

3. If the medium or low thresholds are selected, the detection may occur outside the specified operating voltage range.

Below 3.8V, device operation is not guaranteed.

12.3.3 Auxiliary Voltage Detector (AVD) Thresholds

Subject to general operating conditions for VDD, fCPU, and TA.

1. Data based on characterization results, tested in production for ROM devices only.

12.3.4 External Voltage Detector (EVD) Thresholds

Subject to general operating conditions for VDD, fCPU, and TA.

1. Data based on characterization results, not tested in production.

Symbol Parameter Conditions Min Typ Max Unit

VIT+(LVD) Reset release threshold

(VDD rise)

VD level = High in option byte 4.0 1) 4.2 4.5

VD level = Med. in option byte3)

VD level = Low in option byte3) 3.55 1)

2.95 1) 3.75

3.15 4.01)

3.351)

VIT-(LVD) Reset generation threshold

(VDD fall)

VD level = High in option byte 3.8 4.0 4.25 1)

VD level = Med. in option byte3)

VD level = Low in option byte3) 3.351)

2.81) 3.55

3.0 3.751)

3.15 1)

Vhys(LVD) LVD voltage threshold hysteresis

1) VIT+(LVD)-VIT-(LVD) 150 200 250 mV

VtPOR VDD ri se time 1)2) Flash device, LVD enabled 6µs/V 20ms/V

ROM device, LVD enabled 6µs/V 100ms/V

tg(VDD) VDD glitches filtered (not detect-

ed) by LVD 1) 40 ns

Symbol Parameter Conditions Min Typ Max Unit

VIT+(AVD) 1⇒0 AVDF flag toggle threshold

(VDD rise)

VD level = High in option byte 4.4 1) 4.6 4.9

VD level = Med. in option byte

VD level = Low in option byte 3.95 1)

3.4 1) 4.15

3.6 4.41)

3.81)

VIT-(AVD) 0⇒1 AVDF flag toggle threshold

(VDD fall)

VD level = High in option byte 4.2 4.4 4.65 1)

VD level = Med. in option byte

VD level = Low in option byte 3.751)

3.21) 4.0

3.4 4.2 1)

3.6 1)

Vhys(AVD) AVD voltage threshold hysteresis VIT+(AVD)-VIT-(AVD) 200 mV

∆VIT- Voltage drop between AVD flag set

and LVD reset activated VIT-(AVD)-VIT-(LVD) 450 mV

Symbol Parameter Conditions Min Typ Max Unit

VIT+(EVD) 1⇒0 AVDF flag toggle threshold

(VDD rise)1) 1.15 1.26 1.35 V

VIT-(EVD) 0⇒1 AVDF flag toggle threshold

(VDD fall)1) 1.1 1.2 1.3

Vhys(EVD) EVD voltage threshold hysteresis VIT+(EVD)-VIT-(EVD) 200 mV

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12.4 SUPPLY CURRENT CHARACTERISTICS

The following current consumption specified for the ST7 functional operating modes over temperature

range does not t ake into account the clock source cur rent consump tion. To get t he total device con sump-

tion, the two current values must be added (except for HALT mode for which the clock is stopped).

12.4.1 CURRENT CONSUMPTION

Notes:

1. Data based on characterization results, tested in production at VDD max. and fCPU max.

2. Measurements are done in the following conditions:

- Program executed from RAM, CPU running with RAM access. The increase in consumption when executing from Flash

is 50%.

- All I/O pins in input mode with a static value at VDD or VSS (no load)

- All peripherals in reset state.

- LVD disabled.

- Clock input (OSC1) driven by external square wave.

- In SLOW and SLOW WAIT mode, fCPU is based on fOSC divided by 32.

To obtain the total current consumption of the device, add the clock source (Section 12.4.2) and the peripheral power

consumption (Section 12.4.3).

3. All I/O pins in push-pull 0 mode (when applicable) with a static value at VDD or VSS (no load), LVD disabled. Data

based on characterization results, tested in production at VDD max. and fCPU max.

4. Data based on characterisation results, not tested in production. All I/O pins in push-pull 0 mode (when applicable) with

a static value at VDD or VSS (no load); clock input (OSC1) driven by external square wave, LVD disabled. To obtain the

total current consumption of the device, add the clock source consumption (Section 12.4.2).

Symbol Parameter Conditions Flash Devices ROM Devices Unit

Typ Max

1) Typ Max

IDD

Supply current in RUN mode 2) fOSC=2MHz, fCPU=1MHz

fOSC=4MHz, fCPU=2MHz

fOSC=8MHz, fCPU=4MHz

fOSC=16MHz, fCPU=8MHz

1.3

2.0

3.6

7.1

3.0

5.0

8.0

15.0

1.3

2.0

3.6

7.1

2.0

3.0

5.0

10.0 mA

Supply current in SLOW mode 2) fOSC=2MHz, fCPU=62.5kHz

fOSC=4MHz, fCPU=125kHz

fOSC=8MHz, fCPU=250kHz

fOSC=16MHz, fCPU=500kHz

600

700

800

1100

2700

3000

3600

4000

600

700

800

1100

1800

2100

2400

3000

µA

Supply current in WAIT mode 2) fOSC=2MHz, fCPU=1MHz

fOSC=4MHz, fCPU=2MHz

fOSC=8MHz, fCPU=4MHz

fOSC=16MHz, fCPU=8MHz

1.0

1.5

2.5

4.5

3.0

4.0

5.0

7.0

1.0

1.5

2.5

4.5

1.3

2.0

3.3

6.0 mA

Supply current in SLOW WAIT mode 2) fOSC=2MHz, fCPU=62.5kHz

fOSC=4MHz, fCPU=125kHz

fOSC=8MHz, fCPU=250kHz

fOSC=16MHz, fCPU=500kHz

580

650

770

1050

1200

1300

1800

2000

100

200

350

200

300

600

1200

µA

Supply current in HALT mode 3) -40°C≤TA≤+85°C <1 10 <1 10 µA

-40°C≤TA≤+125°C <1 50 <1 50

IDD Supply current in ACTIVE-HALT mode

fOSC=2MHz

fOSC=4MHz

fOSC=8MHz

fOSC =16MHz

160

325

650

max.

guaran-

teed

120

100

200

µA

ST72F521, ST72521B

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SUPPLY CURRENT CHARACTERISTICS (Cont’d)

12.4.1.1 Power Consump tion vs fCPU: Flash Devices

Figure 87. Typical IDD in RUN mode

Figure 88. Typical IDD in SLOW mode

Figure 89. Typical IDD in WAIT mode

Figure 90. Typ. IDD in SLOW-WAIT mode

3.2 3.6 4 4.4 4.8 5.2 5.5

V dd (V )

Idd (mA)

8MHz

4MHz

2MHz

1MHz

0.00

0.20

0.40

0.60

0.80

1.00

1.20

3.2 3.6 4 4.4 4.8 5.2 5.5

Vdd (V)

Idd (mA)

500kHz

250kHz

125kHz

62.5kHz

3.2 3.6 4 4.4 4.8 5.2 5.5

V dd (V )

Idd (mA)

8MHz

4MHz

2MHz

1MHz

0.00

0.20

0.40

0.60

0.80

1.00

1.20

3.2 3.6 4 4.4 4.8 5.2 5.5

Vdd (V)

()

500kHz

250kHz

125kHz

62.5kHz

ST72F521, ST72521B

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SUPPLY CURRENT CHARACTERISTICS (Cont’d)

12.4.2 Supply and Clock Managers

The previous current consumption specified for the ST7 functional operating modes over temperature

range does not t ake into account the clock source cur rent consump tion. To get t he total device con sump-

tion, the two current values must be added (except for HALT mode).

Notes:

1.. Data based on characterization results done with the external components specified in Section 12.5.3, not tested in

production.

2. As the oscillator is based on a current source, the consumption does not depend on the voltage.

Symbol Parameter Conditions Typ Max Unit

IDD(RCINT) Supply current of internal RC oscillator 625

µA

IDD(RES) Supply current of resonator oscillator 1) & 2) see section

12.5.3 on page

174

IDD(PLL) PLL supply current VDD= 5V 360

IDD(LVD) LVD supply current VDD= 5V 150 300

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SUPPLY CURRENT CHARACTERISTICS (Cont’d)

12.4.3 On-Chip Peripherals

Measured on S72F521R9T3 on TQFP64 generic board TA = 25°C fCPU=4MHz.

Notes:

1. Data based on a differential IDD measurement between reset configuration (timer counter running at fCPU/4) and timer

counter stopped (only TIMD bit set). Data valid for one timer.

2. Data based on a differential IDD measurement between reset configuration (timer stopped) and timer counter enabled

(only TCE bit set).

3. Data based on a differential IDD measurement between reset configu ration (SPI disabled) and a permanent SPI master

communication at maximum speed (data sent equal to 55h).This measurement includes the pad toggling consumption.

4. Data based on a differential IDD measurement between SCI low power state (SCID=1) and a permanent SCI data trans-

mit sequence.

5. Data based on a differential IDD measurement between reset c onfiguration (I2C disabled) and a permanent I2C master

communication at 100kHz (data sent equal to 55h). This measurement include the pad toggling consumption (27kOhm

external pull-up on clock and data lines).

6. Data based on a differential IDD measurement between reset configuration and continuous A/D conversions.

7. Data based on a differential IDD measurement between reset configuration (CAN disabled) and a permanent CAN data

transmit sequence with RX and TX connected together. This measurement include the pad toggling consumption.

Symbol Parameter Conditions Typ Unit

IDD(TIM) 16-bit Timer supply current 1) VDD=5.0V 50 µA

IDD(ART) ART PWM supply current2) V

DD=5.0V 75 µA

IDD(SPI) SPI supply current 3) VDD=5.0V 400 µA

IDD(SCI) SCI supply current 4) VDD=5.0V 400 µA

IDD(I2C) I2C supply current 5) VDD=5.0V 175 µA

IDD(ADC) ADC supply current when converting 6) VDD=5.0V 400 µA

IDD(CAN) CAN supply current 5) VDD=5.0V 400 µA

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12.5 CLOCK AND TIMING CHARACTERISTICS

Subject to general operating conditions for VDD, fCPU, and TA.

12.5.1 General Timings

12.5.2 External Clock Source

Figure 91. Typical Application with an External Clock Source

Notes:

1. Data based on typical application software.

2. Time measured between interrupt event and interrupt vector fetch. ∆tc(INST) is the number of tCPU cycles needed to finish

the current instruction execution.

3. Data based on design simulation and/or technology characteristics, not tested in production.

Symbol Parameter Conditions Min Typ 1) Max Unit

tc(INST) Instruction cycle time 2312t

CPU

fCPU=8MHz 250 375 1500 ns

tv(IT) Interrupt reaction time 2)

tv(IT) = ∆tc(INST) + 10 10 22 tCPU

fCPU=8MHz 1.25 2.75 µs

Symbol Parameter Conditions Min Typ Max Unit

VOSC1H OSC1 input pin high level voltage

see Figure 91

VDD-1 VDD V

VOSC1L OSC1 input pin low level voltage VSS VSS+1

tw(OSC1H)

tw(OSC1L) OSC1 high or low time 3) 5ns

tr(OSC1)

tf(OSC1) OSC1 rise or fall time 3) 15

ILOSC1 Input leakage current VSS≤VIN≤VDD ±1 µA

OSC1

OSC2

fOSC

EXTERNAL

ST72XXX

CLOCK SOURCE

Not connected intern ally

VOSC1L

VOSC1H

tr(OSC1) tf(OSC1) tw(OSC1H) tw(OSC1L)

90%

10%

ST72F521, ST72521B

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CLOCK AND TIMING CHARACTERISTICS (Cont’d)

12.5.3 Crystal and Ceramic Resonator Oscillators

The ST7 internal clock can be supplied with four

different Crystal/Ceramic resonator oscillators. All

the information given in this paragraph are based

on characterization results with specified typical

external components. In the application, the reso-

nator and the loa d capacitors have to be placed as

close as possible to the oscillator pins in order to

minimize output distortion and start-up stabiliza-

tion time. Refer to the crystal/ceramic resonator

manufacturer for more details (frequency, pack-

age, accuracy...).

Figure 92. Typical Application with a Crystal or Ceramic Resonator

Notes:

1. The oscillator selection can be optimized in terms of supply current using an high quality resonator with small R S value.

Refer to crystal/ceramic resonator manufacturer for more details.

2. Data based on characterisation results, not tested in production.

Symbol Parameter Conditions Min Max Unit

fOSC Oscillator Frequency 1) LP: Low power oscillator

MP: Medium power oscillator

MS: Medium speed oscillator

HS: High speed oscillator

MHz

RFFeedback resistor2) 20 40 kΩ

CL1

CL2

Recommended load capacitance ver-

sus equivalent serial resistance of the

crystal or ceramic resonator (RS)

RS=200ΩLP oscillator

RS=200ΩMP oscillator

RS=200ΩMS oscillator

RS=100ΩHS oscillator

Symbol Parameter Conditions Typ Max Unit

i2OSC2 driving current

VDD=5V LP oscillator

VIN=VSS MP oscillator

MS oscillator

HS oscillator

160

310

610

150

250

460

910

µA

OSC2

OSC1 fOSC

CL1

CL2

ST72XXX

RESONATOR

WHEN RESONATOR WITH

INTEGRATED CAPACITORS

ST72F521, ST72521B

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CLOCK AND TIMING CHARACTERISTICS (Cont’d)

Notes:

1. Resonator characteristics given by the ceramic resonator manufacturer.

2. SMD = [-R0: Plastic tape package (∅ =180mm), -B0: Bulk]

LEAD = [-A0: Flat pack package (Radial taping Ho= 18mm), -B0: Bulk]

3. LP mode is not recommended for 2 MHz resonator because the peak to peak amplitude is too small (>0.8V)

For more information on these resonators, please consult www.murata.com

Supplier fOSC

(MHz)

Typical Ceramic Resonators

Reference2) Recommended OSCRANGE

Option bit configuration

Murata

2 CSTCC2M00G56A-R0 MP Mode3)

4CSTCR4M00G55B-R0 MS Mode

8CSTCE8M00G55A-R0 HS Mode

16 CSTCE16M0G53A-R0 HS Mode

ST72F521, ST72521B

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CLOCK CHARACTERISTICS (Cont’d)

12.5.4 RC Oscillator s

Figure 93. Typical fOSC(RCINT) vs TANote: To reduce disturbance to the RC oscillator,

it is recommended to place decoupling capacitors

between VDD and VSS as shown in Figure 113

Symbol Parameter Conditions Min Typ Max Unit

fOSC (RCINT) Internal RC oscillator frequency

See Figure 93 TA=25°C, VDD=5V 23.55.6MHz

3.2

3.4

3.6

3.8

-45 0 25 70 130

TA(°C)

fOSC(RCINT) (MHz)

Vdd = 5V

V dd = 5. 5V

ST72F521, ST72521B

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CLOCK CHARACTERISTICS (Cont’d)

12.5.5 PLL Characteristics

Note:

1. Data characterized but not tested.

The user must take the PLL jitter into account in the application (for example in serial communication or

sampling of high frequency signals). The PLL jitter is a periodic effect, which is integrated over several

CPU cycles. Therefore the longer the period of the application signal, the less it will be impacted by the

PLL jitter.

Figure 94 shows the PLL jitter integrated on application signals in th e range 125kHz to 4MHz. At frequen-

cies of less than 125KHz, the jitter is negligible.

Figure 94. Integrated PLL Jitter vs signal frequency1

Note 1: Measurement conditions: fCPU = 8MHz.

Symbol Parameter Conditions Min Typ Max Unit

fOSC PLL input frequency range 2 4 MHz

∆ fCPU/ fCPU Instantaneous PLL jitter 1)

ROM device,

fOSC = 4 MHz. 0.7 2

Flash device,

fOSC = 4 MHz. 1.0 2.5

Flash device,

fOSC = 2 MHz. 2.5 4.0

0.2

0.4

0.6

0.8

1.2

4 MHz 2 MHz 1 M Hz 500 kHz 250 kHz 125 kH z

Application Frequency

+/-Jitter (%)

FLASH typ

ROM max

ROM ty p

ST72F521, ST72521B

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12.6 MEMORY CHARACTERISTICS

12.6.1 RAM and Hardware Registers

12.6.2 FLASH Memory

Notes:

1. Minimum VDD supply voltage without losing data stored in RAM (in HALT mode or under RESET) or in hardware reg-

isters (only in HALT mode). Not tested in production.

2. Data based on characterization results, not tested in production.

3. VPP must be applied only during the programming or erasing operation and not permanently for reliability reasons.

4. Data based on simulation results, not tested in production.

Warning: Do not connect 12V to VPP before VDD is powered on, as this may damage the device.

Symbol Parameter Conditions Min Typ Max Unit

VRM Data retention mode 1) HALT mode (or RESET) 1.6 V

DUAL VOLTAGE HDFLASH MEMORY

Symbol Parameter Conditions Min 2) Typ Max 2) Unit

fCPU Operating frequency Read mode 0 8 MHz

Write / Erase mode 1 8

VPP Programming voltage 3) 4.5V ≤ VDD ≤ 5.5V 11.4 12.6 V

IDD Supply current4) RUN mode (fCPU = 4MHz) 3 mA

Write / Erase 0

Power down mode / HALT 1 10 µA

IPP VPP current4) Read (VPP=12V) 200

Write / Erase 30 mA

tVPP Internal VPP stabilization time 10 µs

tRET Data retention TA=55°C 20 years

NRW Write erase cycles TA=25°C 100 cycles

TPROG

TERASE

Programming or erasing tempera-

ture range -40 25 85 °C

ST72F521, ST72521B

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12.7 EMC CHARACTERISTICS

Susceptibility tests are performed on a sample ba-

sis during prod u ct ch ar ac te riza tio n .

12.7.1 Functional EMS (Electro Magnetic

Susceptibility)

Based on a simple running application on the

product (toggling 2 LEDs through I/O ports), the

product is stresse d by two electro magnetic events

until a failure occurs (indicated by the LEDs).

■ESD: Electro-Static Discharge (positive and

negative) is applied on all pins of the device until

a functional disturbance occurs. This test

conforms with the IEC 1000-4-2 standard.

■FTB: A Burst of Fast Tr ansient voltag e (positive

and negative) is applied to V DD and VSS through

a 100pF capacitor , until a functional disturban ce

occurs. This test confor ms wit h the IEC 1000- 4-

4 standard.

A device reset allows normal operations to be re-

sumed. The test results are given in the table be-

low based on the EMS levels and classes defined

in application note AN1709.

12.7.1.1 Designing hardened software to avoid

noise problems

EMC characterization and optimization are per-

formed at component level with a typical applica-

tion environment and simplified MCU software. It

should be noted that good EMC performance is

highly dependent on the user application and the

software in particular.

Therefore it is recommended that the user applies

EMC software optimization and prequalification

tests in relation with the EMC level requested for

his application.

Software recommendations:

The software flowchart must include the manage-

ment of runaway conditions such as:

– Corrupted program counter

– Unexpected reset

– Critic al Dat a co rr uptio n (c on tr ol re gisters...)

Prequal ifi ca ti o n tria ls :

Most of the common failures (unexpected reset

and program counter corruption) can be repro-

duced by manually forcing a low state on the RE-

SET pin or the Oscillator pins for 1 second.

To complete these trials, ESD stress can be ap-

plied directly on the device, over the range of

specification values. When unexpected behaviour

is detected, the software can be hardened to pre-

vent unrecoverable errors occurring (see applica-

tion note AN1015)

Symbol Parameter Conditions Level/

Class

VFESD Voltage limits to be applied on any I/O pin to induce a

functional disturbance

Flash device: VDD=5V, TA=+25°C,

fOSC=8MHz, conforms to IEC 1000-4-2 4B

ROM device: VDD=5V, TA=+25°C, fO-

SC=8MHz,conforms to IEC 1000-4-2 3B

VFFTB

Fast transient voltage burst limits to be applied

through 100pF on VDD and VDD pins to induce a func-

tional disturbance

Flash device: VDD=5V, TA=+25°C, fOSC=8

MHz, conforms to IEC 1000-4-4 3B

VFFTB

Fast transient voltage burst limits to be applied

through 100pF on VDD and VDD pins to induce a func-

tional disturbance

Flash device: VDD=5V, TA=+25°C, fOSC=8

MHz, conforms to IEC 1000-4-4 3B

ST72F521, ST72521B

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EMC CHARACTERISTICS (Cont’d)

12.7.2 Electro Ma gnetic Interference (EMI)

Based on a simple application running on the

product (toggling 2 LEDs through the I/O ports),

the product is monit ored in terms of emission. This

emission test is in line with the norm SAE J 1752/

3 which specifies the board and the loading of

each pin.

Notes:

1. Data based on characterization results, not tested in production.

2. Refer to Application Note AN1709 for data on other package types.

Symbol Parameter Conditions Monitored

Frequency Band Max vs. [f OSC/fCPU]Unit

8/4MHz 16/8MHz

SEMI Peak level VDD=5V, TA=+25°C,

TQFP64 14x14 package

conforming to SAE J 1752/3

0.1MHz to 30MHz 15 15 dBµV30MHz to 130MHz 20 27

130MHz to 1GHz 0 5

SAE EMI Level 2.5 3.0 -

ST72F521, ST72521B

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EMC CHARACTERISTICS (Cont’d)

12.7.3 Absolute Maximum Ratings (Electrical

Sensitivity)

Based on three dif fe rent tests (ESD, LU and DL U)

using specific measurement methods, the product

is stressed in order to determine its performance in

terms of electrical sensitivity. For more details, re-

fer to the application note AN1181.

12.7.3.1 Electro-Static Dischar g e (ESD)

Electro-Static Discharges (a positive then a nega-

tive pulse separated by 1 second) are applied to

the pins of each sample according to each pin

combination. The sample size depends on the

number of supply pins in the device (3 parts*(n+1)

supply pin). Two models can be simulated: Hu man

Body Model and Machine Model. This test con-

forms to the JESD22-A114A/A115A standard.

Absolute Maximum Ratings

Notes:

1. Data based on characterization results, not tested in production.

12.7.3.2 Static and Dynamic Latch-Up

■LU: 3 complementary static tests are required

on 10 parts to assess the latch-up p erformance.

A supply overvoltage (applied to each power

supply pin) and a current injection (applied to

each input, output and configurable I/O pin) are

performed on each sample. This test conforms

to the EIA/JESD 78 IC latch-up standard. For

more details, refer to the application note

AN1181.

■DLU: Electro-Static Discharges (one positive

then one negative test) are applied to each pin

of 3 samples when the micro is running to

assess the latch-up performance in dynamic

mode. Power supplies are set to the typical

values, the oscillator is connected as near as

possible to the pins of the micro and the

component is put in reset mode. This test

conforms to the IEC1000-4-2 and SAEJ1752/3

standards. For more details, refer to the

application note AN1181.

Electrical Sensit iv iti es

Notes:

1. Class description: A Class is an STMicroelectronic s internal specification. All its limits are higher than the JEDEC spec-

ifications, that means when a device belongs to Class A it exceeds the JEDEC standard. B Class strictly covers all the

JEDEC criteria (international standard).

Symbol Ratings Conditions Maximum value 1) Unit

VESD(HBM) Electro-static discharge voltage

(Human Body Model) TA=+25°C 2000 V

VESD(MM) Electro-static discharge voltage

(Machine Model) TA=+25°C 200

Symbol Parameter Conditions Class 1)

LU Static la tch-up class TA=+25°C

TA=+85°C

TA=+125°C

DLU Dynamic latch-up class VDD=5.5V, fOSC=4MHz, TA=+25°C A

ST72F521, ST72521B

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12.8 I/O PORT PIN CHARACTERISTICS

12.8.1 General Characteristics

Subject to general operating conditions for VDD, fOSC, and TA unless otherwise spec ifie d.

Figure 95. Unused I/O Pins configur ed as input Figure 96. Typical IPU vs. VDD with VIN=VSS

Notes:

1. Data based on characterization results, not tested in production.

2. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.

3. When the current limitation is not possible, the VIN maximum must be respected, otherwise refer to IINJ(PIN) specifica-

tion. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. Refer to section 12.2.2

on page 166 for more details.

4. Configuration not recommended, all unused pins must be kept at a fixed voltage: using the output mode of the I/O for

example and leaving the I/O unconnected on the board or an external pull-up or pull-down resistor (see Figure 95). Data

based on design simulation and/or technology characteristics, not tested in production.

5. The RPU pull-up equivalent resistor is based on a resistive transistor (corresponding IPU current characteristics de-

scribed in Figure 96).

6. To generate an external interrupt, a minimum pulse width has to be applied on an I/O port pin configured as an external

interrupt source.

Symbol Parameter Conditions Min Typ Max Unit

VIL Input low level voltage 1)

CMOS ports 0.3xVDD

VIH Input high level voltage 1) 0.7xVDD

Vhys Schmitt trigger voltage hysteresis 2) 0.7

VIL Input low level voltage 1)

TTL ports 0.8

VIH Input high level voltage 1) 2

Vhys Schmitt trigger voltage hysteresis 2) 1

IINJ(PIN)3) Injected Current on PC6 (Flash de-

vices only) VDD=5V

0+4

Injected Current on an I/O pin ± 4

ΣIINJ(PIN)3) Total injected current (sum of all I/O

and control pins) ± 25

ILInput leakage current VSS≤VIN≤VDD ±1 µA

ISStatic current consumption Floating input mode4) 400

RPU Weak pull-up equivalent resistor 5) VIN=VSS VDD=5V 50 120 250 kΩ

CIO I/O pin capacitance 5 pF

tf(IO)out Output high to low level fall time 1) CL=50pF

Between 10% and 90% 25 ns

tr(IO)out Output low to high level rise time 1) 25

tw(IT)in External interrupt pulse time 6) 1t

CPU

10kΩ

UNUSED I/O PORT

ST7XXX

10kΩUNUSED I/O PORT

ST7XXX

VDD

Note: I/O can be left unconnected if it is configured as output

greater EMC ro bu stness and lower cost.

(0 or 1) by the software. This has the advantage of

22.533.544.555.56

Vdd(V)

Ipu(uA)

Ta=140°C

Ta=95°C

Ta=25°C

Ta=-45°C

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I/O PORT PIN CHARACTERISTICS (Cont’d)

12.8.2 Output Driving Current

Subject to general operating conditions for VDD, fCPU, and TA unless otherwise specified.

Figure 97. Typical VOL at VDD=5V (standard)

Figure 98. Typical VOL at VDD=5V (high-sink)

Figure 99. Typical VOH at VDD=5V

Notes:

1. The IIO current sunk must always respect the absolute maximum rating specified in Secti on 12.2.2 and the sum of IIO

(I/O ports and control pins) must not exceed IVSS.

2. The IIO current sourced must always respect the absolute maximum rating specified in Section 12.2.2 and the sum of

IIO (I/O ports and control pins) must not exceed IVDD. True open drain I/O pins do not have VOH.

Symbol Parameter Conditions Min Max Unit

VOL 1)

Output low level voltage for a standard I/O pin

when 8 pins are sunk at same time

(see Figure 97)

VDD=5V

IIO=+5mA 1.2

IIO=+2mA 0.5

Output low level voltage for a high sink I/O pin

when 4 pins are sunk at same time

(see Figure 98 and Figure 100)

IIO=+20mA,TA≤85°C

TA≥85°C 1.3

1.5

IIO=+8mA 0.6

VOH 2) Output high level voltage for an I/O pin

when 4 pins are sourced at same time

(see Figure 99 and Figure 102)

IIO=-5mA, TA≤85°C

TA≥85°C VDD-1.4

VDD-1.6

IIO=-2mA VDD-0.7

0.2

0.4

0.6

0.8

1.2

1.4

0 0.005 0.01 0.015

Iio(A)

Vol (V) at Vdd= 5 V

Ta=140°C "

Ta=95°C

Ta=25°C

Ta=-45°C

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

0 0.01 0.02 0.03

Iio(A)

Vol(V) at Vdd=5V

Ta= 140 °C

Ta=95°C

Ta=25°C

Ta=-45°C

2.5

3.5

4.5

5.5

-0.01 -0.008 -0.006 -0.004 -0.002 0

Vdd-Voh (V) at Vdd=5V

Vdd=5V 1 40° C min

V dd=5v 95°C m in

V dd=5v 25°C m in

V dd=5v -4 5°C m i n

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I/O PORT PIN CHARACTERISTICS (Cont’d)

Figure 100. Typical VOL vs. VDD (standard)

Figure 101. Typical VOL vs. VDD (high-sink )

Figure 102. Typical VDD-VOH vs. VDD

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

2 2.5 3 3.5 4 4.5 5 5.5 6

Vdd(V)

Vol(V) at Iio=5mA

Ta=-45°C

Ta=25°C

Ta=95°C

Ta=140°C

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

0.45

2 2.5 3 3.5 4 4.5 5 5.5 6

Vdd

(

)

Vol(V) at Iio=2mA

Ta=-45°C

Ta=25°C

Ta=95°C

Ta=140°C

0.1

0.2

0.3

0.4

0.5

0.6

22.533.544.555.56

Vdd(V)

Vol(V ) at Iio=8m A

Ta= 140°C

Ta=9 5°C

Ta=25°C

Ta=-45°C

0.2

0.4

0.6

0.8

1.2

1.4

1.6

2 2.5 3 3.5 4 4.5 5 5.5 6

Vdd(V)

Vol(V ) at Iio=20m A

Ta = 140 °C

Ta=95°C

Ta=25°C

Ta=-45°C

2 2.5 3 3.5 4 4.5 5 5.5 6

Vdd(V)

Vdd - Voh(V) at I io = - 5m

Ta=-45°C

Ta=25°C

Ta=95°C

Ta=140°C

2.5

3.5

4.5

5.5

2 2.5 3 3.5 4 4.5 5 5.5 6

Vdd(V)

Vdd-Voh(V) at Iio=-2mA

Ta=-45°C

Ta=25°C

Ta=95°C

Ta=140°C

ST72F521, ST72521B

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12.9 CONTROL PIN CHARACTERISTICS

12.9.1 Asynchronous RESET Pin

Subject to general operating conditions for VDD, fCPU, and TA unless otherwise specified.

Notes:

1. Data based on characterization results, not tested in production.

2. Hysteresis voltage between Schmitt trigger switching levels.

3. The IIO current sunk must always respect the absolute maximum rating specified in Secti on 12.2.2 and the sum of IIO

(I/O ports and control pins) must not exceed IVSS.

4. To guarantee the reset of the device, a minimum pulse has to be applied to the RESET pin. All short pulses applied on

the RESET pin with a duration below th(RSTL)in can be ignored.

5. The reset network (the resistor and two capacitors) protects the device against parasitic resets, especially in noisy en-

vironments.

6. Data guaranteed by design, not tested in production.

Symbol Parameter Conditions Min Typ Max Unit

VIL Input low level voltage 1) 0.16xVDD V

VIH Input high level voltage 1) 0.85xVDD

Vhys Schmitt trigger voltage hysteresis 2) 2.5 V

VOL Output low level voltage 3) VDD=5V IIO=+2mA 0.2 0.5

IIO Input current on RESET pin 2 mA

RON Weak pull-up equivalent resistor 20 30 120 kΩ

tw(RSTL)out Generated reset pulse duration Stretch applied on

external pulse 042

6) µs

Internal reset sources 20 30 426) µs

th(RSTL)in External reset pulse hold time 4) 2.5 µs

tg(RSTL)in Filtered glitch duration 5) 200 ns

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CONTROL PIN CHARACTERISTICS (Cont’d)

Figure 103. RESET pin protection when LVD is enabled.1)2)3)4)

Figure 104. RESET pin protection when LVD is disabled.1)

Note 1:

– The reset network protects the device against parasitic resets.

– The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad. Otherwise the

device can be damaged when the ST7 generates an internal reset (LVD or watchdog).

– Whatever the reset source is (internal or external), the user must ensure that the level on the RESET pin can go

below the VIL max. level specified in section 12.9.1 on page 185. Otherwise the reset will not be taken into account

internally.

– Because the reset circuit is designed to allow the internal RESET to be output in the RESET pin, the user must en-

sure that the current sunk on the RESET pin is less than the absolute maximum value specified for IINJ(RESET) in

section 12.2.2 on page 166.

Note 2: When the LVD is enabled, it is recommended not to connect a pull-up resistor or capacitor. A 10nF pull-down

capacitor is required to filter noise on the reset line.

Note 3: In case a capacitive power supply is used, it is recommended to connect a 1MΩ pull-down resistor to the RESET

pin to discharge any residual voltage induced by the capacitive effect of the power supply (this will add 5µA to the power

consumption of the MCU).

Note 4: Tips when using the LVD:

– 1. Check that all recommendations related to reset circuit have been applied (see notes above).

– 2. Check that the power supply is properly decoupled (100nF + 10µF close to the MCU). Refer to AN1709 and

AN2017. If this cannot be done, it is recommended to put a 100nF + 1MΩ pull-down on the RESET pin.

– 3. The capacitors connected on the RESET pin and also the power supply are key to avoid any start-up marginality.

In most cases, steps 1 and 2 above are sufficient for a robust solution. Otherwise: replace 10nF pull-down on the

RESET pin with a 5µF to 20µF capacitor.

0.01µF

ST72XXX

PULSE

GENERATOR

Filter

RON

VDD

WATCHDOG

LVD RESET

INTERNAL

RESET

EXTERNAL

Required

1MΩ

Optional

(note 3)

0.01µF

VDD

EXTERNAL

RESET

CIRCUIT

USER

VDD

4.7kΩ

Required

Recommended for EMC ST72XXX

PULSE

GENERATOR

Filter

RON

VDD

WATCHDOG

INTERNAL

RESET

ST72F521, ST72521B

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CONTROL PIN CHARACTERISTICS (Cont’d)

12.9.2 ICCSEL/VPP Pin

Subject to general operating conditions for VDD, fCPU, and TA unless otherwise specified.

Figure 105. Two typical Applications with ICCSEL/VPP Pin 2)

Notes:

1. Data based on design simulation and/or technology characteristics, not tested in production.

2. When ICC mode is not required by the application ICCSEL/VPP pin must be tied to VSS.

Symbol Parameter Conditions Min Max Unit

VIL Input low level voltage 1) FLASH versions VSS 0.2

ROM versions VSS 0.3xVDD

VIH Input high level voltage 1) FLASH versions VDD-0.1 12.6

ROM versions 0.7xVDD VDD

ILInput leakage current VIN=VSS ±1 µA

ICCSEL/VPP

ST72XXX 10kΩ

PROGRAMMING

TOOL VPP

ST72XXX

ST72F521, ST72521B

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12.10 TIMER PERIPHERAL CHARACTERISTICS

Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified.

Refer to I/O por t characteristics for more de tails on the input/out put alternate fu nction characterist ics (out-

put compare, input capture, external clock, PWM output...).

12.10.1 8-Bit PWM-ART Auto-Reload Timer

12.10.2 16-Bit Timer

Symbol Parameter Conditions Min Typ Max Unit

tres(PWM) PWM resolution time 1t

CPU

fCPU=8MHz 125 ns

fEXT ART external clock frequency 0 fCPU/2 MHz

fPWM PWM repetition rate 0 fCPU/2

ResPWM PWM resolution 8bit

VOS PWM/DAC output step voltage VDD=5V, Res=8-bits 20 mV

Symbol Parameter Conditions Min Typ Max Unit

tw(ICAP)in Input capture pulse time 1 tCPU

tres(PWM) PWM resolution time 2t

CPU

fCPU=8MHz 250 ns

fEXT Timer external clock frequency 0 fCPU/4 MHz

fPWM PWM repetition rate 0 fCPU/4 MHz

ResPWM PWM resolution 16 bit

ST72F521, ST72521B

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12.11 COMMUNICATION INTERFACE CHARACTERISTICS

12.11.1 SPI - Serial Peripheral Interface

Subject to general operating conditions for VDD,

fCPU, and TA unless othe rwise specified.

Refer to I/O por t characteristics for more de tails on

the input/output alternate function characteristics

(SS, SCK, MOSI, MISO).

Figure 106. SPI Sla ve Timing Diagram with CPHA=0 3)

Notes:

1. Data based on design simulation and/or characterisation results, not tested in production.

2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has

its alternate function capability released. In this case, the pin status depends on the I/O port configuration.

3. Measurement points are done at CMOS levels: 0.3xVDD and 0.7xVDD.

Symbol Parameter Conditions Min Max Unit

fSCK

1/tc(SCK) SPI clock frequency

Master fCPU=8MHz fCPU/128

0.0625 fCPU/4

2MHz

Slave fCPU=8MHz 0fCPU/2

tr(SCK)

tf(SCK) SPI clock rise and fall time see I/O port pin description

tsu(SS)SS setup time Slave 120

th(SS)SS hold time Slave 120

tw(SCKH)

tw(SCKL) SCK high and low time Master

Slave 100

tsu(MI)

tsu(SI) Data input setup time Master

Slave 100

100

th(MI)

th(SI) Data input hold time Master

Slave 100

100

ta(SO) Data output access time Slave 0 120

tdis(SO) Data output disable time Slave 240

tv(SO) Data output valid time Slave (after enable edge) 90

th(SO) Data output hold time 0

tv(MO) Data output valid time M aster (before capture edge) 0.25 tCPU

th(MO) Data output hold time 0.25

SS INPUT

SCK INPUT

CPHA=0

MOSI INPUT

MISO OUTPUT

CPHA=0

tc(SCK)

tw(SCKH)

tw(SCKL) tr(SCK)

tf(SCK)

tv(SO)

ta(SO)

tsu(SI) th(SI)

MSB OUT

MSB IN

BIT6 OUT

LSB IN

LSB OUT

seenote2

CPOL=0

CPOL=1

tsu(SS)th(SS)

tdis(SO)

th(SO)

see

note 2

BIT1 IN

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COMMUNICATION INTERFACE CHARACTERISTICS (Cont’d)

Figure 107. SPI Slave Timing Diagram with CPHA=11)

Figure 108. SPI Master Timing Diagram 1)

Notes:

1. Measurement points are done at CMOS levels: 0.3xVDD and 0.7xVDD.

2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has

its alternate function capability released. In this case, the pin status depends of the I/O port configuration.

SS INPUT

SCK INPUT

CPHA=1

MOSI INPUT

MISO OUTPUT

CPHA=1

tw(SCKH)

tw(SCKL) tr(SCK)

tf(SCK)

ta(SO)

tsu(SI) th(SI)

MSB OUT BIT6 OUT LSB OUT

see

CPOL=0

CPOL=1

tsu(SS)th(SS)

tdis(SO)

th(SO)

see

note 2note 2

tc(SCK)

tv(SO)

MSB IN LSB IN

BIT1 IN

SS INPUT

SCK INPUT

CPHA=0

MOSI OUTPUT

MISO INPUT

CPHA=0

CPHA=1

tc(SCK)

tw(SCKH)

tw(SCKL)

th(MI)

tsu(MI)

tv(MO) th(MO)

MSB IN

MSB OUT

BIT6 IN

BIT6 OUT LSB OUT

LSB IN

seenote2 seenote2

CPOL=0

CPOL=1

CPOL=0

CPOL=1

tr(SCK)

tf(SCK)

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COMMUNICATION INTERFACE CHARACTERISTICS (Cont’d)

12.11.2 I2C - Inter IC Control Interface

Subject to general operating conditions for VDD,

fCPU, and TA unless othe rwise specified.

Refer to I/O por t characteristics for more de tails on

the input/output alternate function characteristics

(SDAI and SCLI). The ST7 I 2C interface meets the

requirements of the Standard I2C communication

protocol described in the following table.

Figure 109. Typical Application with I2C Bus and Timing Diagram 4)

Notes:

1. Data based on standard I2C protocol requirement, not tested in production.

2. The device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the undefined

region of the falling edge of SCL.

3. The maximum hold time of the S TART condition has only to be met if the interface does not stretch the low period of

SCL signal.

4. Measurement points are done at CMOS levels: 0.3xVDD and 0.7xVDD.

5. At 4MHz fCPU, max.I2C speed (400kHz) is not achievable. In this case, max. I2C speed will be approximately 260KHz.

Symbol Parameter Standard mode I2C Fast mode I2C5) Unit

Min 1) Max 1) Min 1) Max 1)

tw(SCLL) SCL clock low time 4.7 1.3 µs

tw(SCLH) SCL clock high time 4.0 0.6

tsu(SDA) SDA setup time 250 100

th(SDA) SDA data hold time 0 3) 0 2) 900 3)

tr(SDA)

tr(SCL) SDA and SCL rise time 1000 20+0.1Cb300

tf(SDA)

tf(SCL) SDA and SCL fall time 300 20+0.1Cb300

th(STA) START condition hold time 4.0 0.6 µs

tsu(STA) Repeated START condition setup time 4.7 0.6

tsu(STO) STOP condition setup time 4.0 0.6 µs

tw(STO:STA) STOP to START condition time (bus free) 4.7 1.3 µs

CbCapacitive load for each bus line 400 400 pF

REPEATED START

START

STOP

START

tf(SDA) tr(SDA) tsu(SDA) th(SDA)

tf(SCK)

tr(SCK)

tw(SCKL)

tw(SCKH)

th(STA) tsu(STO)

tsu(STA) tw(STO:STA)

SDA

SCK

4.7kΩSDAI

ST72XXX

SCLI

VDD

100Ω

VDD

4.7kΩ

I2CBUS

ST72F521, ST72521B

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COMMUNICATION INTERFACE CHARACTERISTICS (Cont’d)

The following table gives the values to be written in

the I2CCCR register to obtain the required I2C

SCL line frequency.

Table 28. SCL Frequency Table

Legend:

RP = External pull-up resistance

fSCL = I2C speed

NA = Not achievable

Note:

– For speeds around 200 kHz, achi eved speed can have ±5% tolerance

– For other speed ranges, achieved speed can have ±2% tolerance

The above variations depen d on the accuracy of the external components used.

12.11.3 CAN - Controller Area Network Interface

Subject to general operating condition for VDD, fOSC, and TA unless otherwise specified.

Refer to I/O port characteristics for more details on the input/output alternate function characteristics

(CANTX and CANRX).

Notes:

1. Data based on simulation results, not tested in production

fSCL

(kHz)

I2CCCR Value

fCPU=4 MHz. fCPU=8 MHz.

VDD = 4.1 V VDD = 5 V VDD = 4.1 V VDD = 5 V

RP=3.3kΩRP=4.7kΩRP=3.3kΩRP=4.7kΩRP=3.3kΩRP=4.7kΩRP=3.3kΩRP=4.7kΩ

400 NA NA NA NA 83h 83 83h 83h

300 NA NA NA NA 85h 85h 85h 85h

200 83h 83h 83h 83h 8Ah 89h 8Ah 8Ah

100 10h 10h 10h 10h 24h 23h 24h 23h

50 24h 24h 24h 24h 4Ch 4Ch 4Ch 4Ch

20 5Fh 5Fh 5Fh 5Fh FFh FFh FFh FFh

Symbol Parameter Conditions Min Typ Max Unit

tp(RX:TX) CAN controller propagation time1) 60 ns

ST72F521, ST72521B

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12.12 10-BIT ADC CHARACTERISTICS

Subject to general operating conditions for VDD, fCPU, and TA unless otherwise specified.

Notes:

1. Any added external serial resistor will downgrade the ADC accuracy (especially for resistance greater than 10kΩ). Dat a

based on characterization results, not tested in production.

2. For Flash devices: injecting negative current on any of the analog input pins significantly reduces the accuracy of any

conversion being performed on any analog input. Analog pins of flash devices can be protected against negative injection

by adding a Schottky diode (pin to ground). Injecting negative current on digital input pins degrades ADC accuracy espe-

cially if performed on a pin close to the analog input pins. Any positive injection current within the limits specified for

IINJ(PIN) and ΣIINJ(PIN) in Section 12.8 does not affect the ADC accuracy.

Symbol Parameter Conditions Min Typ Max Unit

fADC ADC clock frequency 0.4 2 MHz

VAREF Analog reference voltage 0.7*VDD ≤VAREF ≤VDD 3.8 VDD V

VAIN Conversion voltage range 1) VSSA VAREF

Ilkg

Positive input leakage current for analog

input -40°C≤TA≤85°C range ±250 nA

Other TA ranges ±1 µA

Negative input leakage current on ro-

bust analog pins (ROM devices only)2VIN<VSS, | IIN |< 400µA

on adjacent robust ana-

log pin 56µA

Ilkg

Positive input leakage current for analog

input -40°C≤TA≤85°C range ±250 nA

Other TA ranges ±1 µA

Negative input leakage current on ro-

bust analog pins (ROM devices only)2VIN<VSS, | IIN |< 400µA

on adjacent robust ana-

log pin 56µA

RAIN External input impedance see

Figure

110 and

Figure

1112)3)4)

kΩ

CAIN External capacitor on analog input pF

fAIN Variation freq. of analog input signal Hz

CADC Internal sample and hold capacitor 12 pF

tADC Conversion time (Sample+Hold)

fCPU=8MHz, SPEED=0 fADC=2MHz 7.5 µs

tADC - No of sample capacitor loading cycles

- No. of Hold conversion cycles 4

11 1/fADC

ST72F521, ST72521B

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ADC CHARACTERISTICS (Cont’d)

Figure 110. RAIN max. vs fADC wi th CAIN=0pF1) Figure 111. Recommended CAIN & RAIN values.2)

Figure 112. Typical A/D Converter Application

Notes:

1. CPARASITIC represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad ca-

pacitance (3pF). A high CPARASITIC value will downgrade conversion accuracy. To remedy this, fADC should b e reduced.

2. This graph shows that depending on the input signal variation (fAIN), CAIN can be increased for stabilization time and

decreased to allow the use of a larger serial resistor (RAIN).

0103070

CPARASITIC (pF)

Max. RAIN (Kohm)

2 MHz

1 MHz

0.1

100

1000

0.01 0.1 1 10

fAIN(KHz)

Max. RAIN (Kohm)

Cain 10 nF

Cain 22 nF

Cain 47 nF

AINx

ST72XXX

VDD

±1µA

0.6V

0.6V CADC

12pF

VAIN

RAIN 10-Bit A/D

Conversion

2kΩ(max)

CAIN

ST72F521, ST72521B

195/215

ADC CHARACTERISTICS (Cont’d)

12.12.1 Analog Power Supply and Reference

Pins

Depending on the MCU pin count, the package

may feature separate VAREF and VSSA analog

power supply pins. These pins supp ly power to the

A/D converter cell a nd function as the high and low

reference vo ltages for the conversion.

Separatio n of the digi tal and an alog powe r pins al-

low board designers to improve A/D performance.

Conversion accuracy can be impacted by voltage

drops and noise in the event of heavily loaded or

badly decoupled power supply lines (see Section

12.12.2 General PCB Design Guidelines).

12.12.2 General PCB Design Guidelines

To obtain best results, some general design and

layout rules should be followed when designing

the application PCB to shield the noise-sensitive,

analog physical interface from noise-generating

CMOS logic signals.

– Use separate digital and analog pl anes. The an-

alog ground plane should be connected to the

digital ground plane via a single point on the

PCB.

– Filter power to the analog powe r planes. It is rec-

ommended to connect capacitors, with good high

frequency characteristics, between the power

and ground lines, placing 0.1µF and option ally, if

needed 10pF capacito rs as close as possible to

the ST7 power supply pins and a 1 to 10µF ca-

pacitor close to the power source (see Figure

113).

– The analog and digital power supplies should be

connected in a sta r ne two r k. Do no t us e a re sis-

tor, as VAREF is used as a reference voltage by

the A/D converter and any resi stance would

cause a voltage dr o p an d a los s of acc ur a cy.

– Properly place components and rou te the signal

traces on the PCB to shield the analog inputs.

Analog signals p aths should run over the an alog

ground plane and be as short as possible. Isolate

analog signals from digital signals that may

switch while the analog inputs are being sampled

by the A/D converter. Do not toggle digital out-

puts on the same I/O port as the A/D input being

converted.

Figure 113. Power Supply Filtering

VSS

VDD

ST72XXX

VAREF

VSSA

POWER

SUPPLY

SOURCE

ST7

DIGITAL NOISE

FILTERING

EXTERNAL

NOISE

FILTERING

1 to 10µF0.1µF

0.1µF

ST72F521, ST72521B

196/215

10-BIT ADC CHARACTERISTICS (Cont’d)

12.12.3 ADC Accuracy

Conditions: VDD=5V 1)

Notes:

1. ADC Accuracy vs. Negative Injection Current: Injecting negative current may reduce the accuracy of the conversion

being performed on another analog input. The effect of negative injection current on robust pins is specified in Section

12.12.

Any positive injection current within the limits specified for I INJ(PIN) and ΣIINJ(PIN) in Section 12.8 does not affect the ADC

accuracy.

2. Data based on characterization results, monitored in production to guarantee 99.73% within ± max value from -40°C

to 125°C (± 3σ distribution limits).

Figure 114. ADC Accuracy Characteristics

Symbol Parameter Conditions Typ Max2) Unit

|ET| Total unadjusted error 1) 34

LSB

|EO| Offset error 1) 23

|EG| Gain Error 1) 0.5 3

|ED| Differential linearity error 1) CPU in run mode @ fADC 2 MHz. 12

|EL| Integral linearity error 1) CPU in run mode @ fADC 2 MHz. 12

1LSB

IDEAL

1LSBIDEAL VAREF VSSA

–

1024

--------------------------------------------=

Vin (LSBIDEAL)

(1) Example of an actual transfer curve

(2) The ideal transfer curve

(3) End point correlation lin e

ET=Total Unadjusted Error: maximum deviation

between the actual and the ideal transfer curves.

EO=Offset Err or : de viation between the first actual

transition and the first ideal one.

EG=Gain Error: deviation between the last ideal

transition and the last actual one.

ED=Differential Li nearity Error: maximum deviatio n

between actual steps and the ideal one.

EL=Integral Linearity Error: maximum deviation

between any actual transition and the end point

correlation lin e.

Digital Result ADCDR

1023

1022

1021

1234567 1021102210231024

(1)

(2)

(3)

VAREF

VSSA

ST72F521, ST72521B

197/215

13 PACKAGE CHARACTERISTICS

13.1 PACKAGE MECHANICAL DATA

Figure 115. 80-Pin Thin Quad Flat Package

Figure 116. 64-Pin Thin Quad Flat Package

Dim. mm inches

Min Typ Max Min Typ Max

A 1.60 0.063

A1 0.05 0.15 0.002 0.006

A2 1.35 1.40 1.45 0.053 0.055 0.057

b0.22 0.32 0.38 0.009 0.013 0.015

C0.09 0.20 0.004 0.008

D 16.00 0.630

D1 14.00 0.551

E 16.00 0.630

E1 14.00 0.551

e0.65 0.026

θ0° 3.5° 7° 0° 3.5° 7°

L0.45 0.60 0.75 0.018 0.024 0.030

L1 1.00 0.039

Number of Pins

N80

EE1

Dim. mm inches

Min Typ Max Min Typ Max

A 1.60 0.063

A1 0.05 0.15 0.002 0.006

A2 1.35 1.40 1.45 0.053 0.055 0.057

b0.30 0.37 0.45 0.012 0.015 0.018

c0.09 0.20 0.004 0.008

D 16.00 0.630

D1 14.00 0.551

E 16.00 0.630

E1 14.00 0.551

e0.80 0.031

θ0° 3.5° 7° 0° 3.5° 7°

L0.45 0.60 0.75 0.018 0.024 0.030

L1 1.00 0.039

Number of Pins

N64

ST72F521, ST72521B

198/215

PACKAGE MECHANICAL DATA (Cont’d)

Figure 117. 64-Pin Thin Quad Flat Package

Dim. mm inches

Min Typ Max Min Typ Max

A 1.60 0.063

A1 0.05 0.15 0.002 0.006

A2 1.35 1.40 1.45 0.053 0.055 0.057

b0.17 0.22 0.27 0.007 0.009 0.011

c0.09 0.20 0.004 0.008

D 12.00 0.472

D1 10.00 0.394

E 12.00 0.472

E1 10.00 0.394

e0.50 0.020

θ0° 3.5° 7° 0° 3.5° 7°

L0.45 0.60 0.75 0.018 0.024 0.030

L1 1.00 0.039

Number of Pins

N64

ST72F521, ST72521B

199/215

13.2 THERMAL CHARACTERISTICS

Notes:

1. The power dissipation is obtained from the formula PD=PINT+PPORT where PINT is the chip internal power (IDDxVDD)

and PPORT is the port power dissipation determined by the user.

2. The average chip-junction temperature can be obtained from the formula TJ = TA + PD x Rth J A.

Symbol Ratings Value Unit

RthJA

Package thermal resistance (junction to ambient)

TQFP80 14x14

TQFP64 14x14

TQFP64 10x10

50 °C/W

PDPower dissipation 1) 500 mW

TJmax Maximum junction temperature 2) 150 °C

ST72F521, ST72521B

200/215

13.3 SOLDERING INFORMATION

In accordance with the RoHS European directive,

all STMicroelectronics packages will be converted

in 2005 to lead-free technology, named ECO-

PACKTM (for a detailed roadmap, please refer to

PCN CRP/04/744 "Lead -free Conversion Prog ram

- Compliance with RoHS", issued November 18th,

2004).

■ECOPACKTM packages are qualified according

to the JEDEC STD-020B compliant soldering

profile.

■Detailed information on the STMicroelectronic

ECOPACKTM transition program is availa ble on

www.st.com/stonline/leadfree/, with specific

technical Application notes covering the main

technical aspects related to lead-free

conversion (AN2033, AN2034, AN2035,

AN2036).

Backward and forward compatibility:

The main difference between Pb and Pb-free sol-

dering process is the temperature range.

– ECOPACKTM TQFP packages are fully compat -

ible with Lead (Pb) con taining soldering process

(see application not e AN2034)

– TQFP Pb-packages are compatible with Lead-

free soldering process, nevertheless it's the cus-

tomer's duty to verify that the Pb-packages max-

imum temperature (mentioned on the Inner box

label) is compatible with their Lead-free soldering

temperature.

Table 29. Soldering Compatibility (wave and reflow soldering process)

* Assemblers must verify that the Pb-package maximum temperature (mentioned on the Inner box label)

is compatible with their Lead-free soldering process.

Package Plating material devices Pb solder paste Pb-free solder paste

TQFP NiPdAu (Nickel-palladium-Gold) Yes Yes *

ST72F521, ST72521B

201/215

14 ST72521 DEVICE CONFIGURATION AND ORDERING INFORMATION

Each device is available for productio n in user pro-

grammable version s (FLASH) as well as in fa ctory

coded versions (ROM/FASTROM).

ST72521B devices are ROM versions. ST72P521

devices are Factory Advanced Service Technique

ROM (FASTROM) versions: they are factory-pro-

grammed HDFlash devices. FLASH devices are

shipped to customers with a default content, while

ROM/FASTROM factory coded parts contain the

code supplied by the customer. This implies that

FLASH devices have to be configured by the cus-

tomer using the Option Bytes while the ROM/FAS-

TROM devices are factory-configured.

14.1 FLASH OPTION BYTES

The option bytes allow the hardware configuration

of the microcontrolle r to be selected. They have no

address in the memor y map an d can be acce ssed

only in programming mode (for example using a

standard ST7 prog ramming tool ). The default con-

tent of the FLASH is fixed to FFh. To program the

FLASH devices directly using ICP, FLASH devices

are shipped to customers with the internal RC

clock source. In masked ROM devices, the option

bytes are fixed in hard ware by the ROM code (see

option list).

OPTION BYTE 0

OPT7= WDG HALT Watchdog and HALT mode

This option bit determines if a RESET is generated

when entering HALT mode while the Watchdog is

active.

0: No Reset generation when ent ering Halt mode

1: Reset generation when entering Halt mode

OPT6= WDG SW Hardware or software watchdog

This option bit selects the watchdog type.

0: Hardware (watchdog always enabled)

1: Software (watchdog to be enabled by software)

OPT5 = Reserved, must be kept at default value.

OPT4:3= VD[1:0] Voltage detection

These option bits enable the voltage detection

block (LVD, and AVD) with a selected threshold for

the LVD and AVD (EVD+AVD).

Caution: If the medium or low thresholds are se-

lected, the detection may occur outside the speci-

fied operating voltage range. Below 3.8V, device

operation is not guaranteed. For details on the

AVD and LVD threshold levels refer to section

12.3.2 on page 168

STATIC OPTION BYTE 0

STATIC OPTION BYTE 1

WDG

Res.

Reserved

PKG0

FMP_R

PKG1

RSTC

OSCTYPE OSCRANGE

PLLOFF

HALT

10 10210

Default1110011111 101 1 11

Selected Low Voltage Detector VD1 VD0

LVD and AVD Off 1 1

Lowest Threshold: (VDD~3V) 1 0

Med. Threshold (VDD~3.5V) 0 1

Highest Threshold (VDD~4V) 0 0

ST72F521, ST72521B

202/215

ST72521 DEVICE CONFIGURATION AND ORDERING INFORMATION (Cont’d)

OPT2 = Reserved, must be kept at default value.

OPT1= PKG0 Package selec tio n bit 0

This option bit is used to select the package (see

table in PKG1 option bit description).

OPT0= FMP_R Flash memory read-out protection

Read-out protection, when selected, provides a

protection against Program Memory content ex-

traction and against write access to Flash memo-

ry.

Erasing the option bytes when the FMP_R option

is selected causes the whole user memory to be

erased first, and the device can be reprogrammed.

Refer to Section 4.3.1 and the ST7 Flash Pro-

gramming Reference Manual for more details.

Note: Readout protection is not supported if LVD

is enabled.

0: Read-out protection enabled

1: Read-out protection disabled

OPTION BYTE 1

OPT7= PKG1 Package selec tio n bit 1

This option bit, with the PKG0 bit, selects the pack-

age.

Note: O n the chip, each I/O port has 8 pads. Pads

that are not bonded to external pins are in input

pull-up configuration after reset. The configuration

of these pads must be kept at reset state to avoid

added current consumption.

OPT6 = RSTC RESET clock cycle selection

This option bit selects the number of CPU cycles

applied during the RESET phase and when exiting

HALT mode. For resonator oscillators, it is advised

to select 4096 due to the long crys tal stabilization

time.

0: Reset phase with 4096 CPU cycles

1: Reset phase with 256 CPU cycles

OPT5:4 = OSCTYPE[1:0] Oscillator Type

These option bits select the ST7 main clock

source type.

OPT3:1 = OSCRANGE[2:0] Oscillator range

When the resonator oscillator type is selected,

these option bits select the resonator oscillator

current source corresponding to the frequency

range of the used resona tor. O therwise, the se bits

are used to select the normal operating frequency

range.

OPT0 = PLLOFF PLL activation

This option bit activates the PLL which allows mul-

tiplication by two of the main input clock frequency.

The PLL must not b e used with the internal RC os-

cillator or with external clock source. The PLL is

guaranteed only with an input frequency between

2 and 4MHz.

0: PLL x2 enabled

1: PLL x2 disabled

CAUTION: the PLL can be enabled only if the

“OSC RANGE” (OPT3:1) bits are configured to

“MP - 2~4MHz”. Otherwise, the device functionali-

ty is not guaranteed.

Version Selected Package PKG 1 PKG 0

MTQFP8011

(A)R TQFP64 1 0

Clock Source OSCTYPE

Resonator Oscillator 0 0

Reserved 0 1

Internal RC Oscillator 1 0

External Source 1 1

Typ. Freq. Range OSCRANGE

210

LP 1~2MHz 0 0 0

MP 2~4MHz 0 0 1

MS 4~8MHz 0 1 0

HS 8~16MHz 0 1 1

ST72F521, ST72521B

203/215

ST72521 DEVICE CONFIGURATION AND ORDERING INFORMATION (Cont’d)

14.2 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE

Customer code is made up of the ROM/FAS-

TROM contents and the list of the select ed options

(if any). The ROM/FASTROM contents are to be

sent on diskette, or by electronic means, with the

S19 hexadecimal file generated by the develop-

ment tool. All unused bytes must be set to FFh.

The selected options are communicated to

STMicroelectronics using the correctly completed

OPTION LIST appended.

Refer to application note AN1635 for information

on the counter listing returned by ST after code

has been transferred.

The STMicroelectronics Sales Organization will be

pleased to provide detailed information on con-

tractual points.

14.2.1 Version-Specific Sales Conditions

To satisfy the different custome r requirements and

to ensure that ST Standard Microcontrollers will

consistently meet or exceed the expectations of

each Market Segment, the Codif ication System for

Standard Microcontrollers clearly distinguishes

products intended for use in automotive environ-

ments, from products intended for use in non-auto-

motive environment s.

It is the responsibility of the Customer to select the

appropriate product for his application.

Figure 118. ROM Fact ory Coded Device Types

DEVICE PACKAGE VERSION XXX

/Code name (defined by STMicroelectronics)

1 = Standard 0 to +70 °C

3 = Standard -40 to +125 °C

5 = Standard -10 to +85 °C

6 = Standard -40 to +85 °C

A = Automotive -40 to +85 °C

B = Automotive -40 to +105 °C

C = Automotive -40 to +125 °C

T= Plastic Thin Quad Flat Pack

ST72521BR9, ST72521BR6

ST72521BAR9, ST72521BAR6

ST72521BM9

ST72F521, ST72521B

204/215

ST72521 DEVICE CONFIGURATION AND ORDERING INFORMATION (Cont’d)

ST72521B MICROCONTROLLER OPTION LIST

(Last update: December 2004)

Customer: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Address: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Contact: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Phone No: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Reference/ROM Code* : . . . . . . . . . . . . . . . . . . . . . . .

*The ROM code name is assigned by STMicroelectronics.

ROM code must be sent in .S19 format. .Hex extension cannot be processed.

Device Type/Memory Size/Package (check only one option):

Conditioning (check only one option):

Version/ Temp. Range (do not check for die product). Please refer to datasheet for specific sales condition s:

Special Marking: [ ] No [ ] Yes "_ _ _ _ _ _ _ _ _ _ " (10 char. max)

Authorized characters are letters, digits, '.', '-', '/' and spaces only.

Clock Source Selection:

[ ] Resonator: [ ] LP: Low power resonator (1 to 2 MHz)

[ ] MP: Medium power resonator (2 to 4 MHz)

[ ] MS: Medium speed resonator (4 to 8 MHz)

[ ] HS: High speed resonator (8 to 16 MHz)

[ ] Internal RC:

[ ] External Clock

PLL [ ] Disabled [ ] Enabled

LVD Reset [ ] Disabled [ ] High threshold [ ] Med. threshold [ ] Low threshold

Reset Delay [ ] 256 Cycles [ ] 4096 Cycles

Watchdog Selection: [ ] Software Activation [ ] Hardware Activation

Watchdog Reset on Halt: [ ] Reset [ ] No Reset

Readout Protection: [ ] Disabled [ ] Enabled

Date . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Please download the latest version of this option list from:

http://www.st.com/mcu > downloads > ST7 microcontrollers > Option list

---------------------------------

ROM DEVICE:

---------------------------------|

|-------------------------------------

60K

------------------------------------- |

|-------------------------------------

32K

-------------------------------------

TQFP80: | [ ] ST72521BM9 |

TQFP64 14x14: | [ ] ST72521BR9 | [ ] ST72521BR6

TQFP64 10x10: | [ ] ST72521BAR9 | [ ] ST72521BAR6

---------------------------------

DIE FORM:

---------------------------------|

|--------------------------------------

60K

-------------------------------------- |

|-------------------------------------

32K

--------------------------------------

80-pin: | [ ] |

64-pin: | [ ] | [ ]

------------------------------------------------------------------------

Packaged Product

------------------------------------------------------------------------ |

|-----------------------------------------------------

Die Product (dice tested at 25°C only)

-----------------------------------------------------

[ ] Tape & Reel [ ] Tray | [ ] Tape & Reel

| [ ] Inked wafer

| [ ] Sawn wafer on sticky foil

-----------------------------

Standard

-----------------------------|

|-------------------------------------------

Automotive

------------------------------------------- |

|-------------------------------------------

Temp. Range

-------------------------------------------

[ ] | | [ ] 0°C to +70°C

[ ] | | [ ] -10°C to +85°C

[ ] | [ ] | [ ] -40°C to +85°C

| [ ] | [ ] -40°C to +105°C

| [ ] | [ ] -40°C to +125°C

ST72F521, ST72521B

205/215

DEVICE CONFIGURATION AND ORDERING INFORMATION (Cont’d)

Table 30. Orderable Flash Device Types

Part Number Version Package Flash

Memory

(Kbytes) Temp. Range

ST72F521AR6TC

Automotive

TQFP64 10 x 10 32

-40°C +125°C

ST72F521AR9TC 60

ST72F521R6TC TQFP64 14 x 14 32

ST72F521R9TC 60

ST72F521M9TC TQFP80 60

ST72F521AR6T3

Standard

TQFP64 10 x 10 32

-40°C +125°C

ST72F521AR9T3 60

ST72F521R6T3 TQFP64 14 x 14 32

ST72F521R9T3 60

ST72F521M9T3 TQFP80 60

ST72F521AR6T6

Standard

TQFP64 10 x 10 32

-40°C +85°C

ST72F521AR9T6 60

ST72F521R6T6 TQFP64 14 x 14 32

ST72F521R9T6 60

ST72F521M9T6 TQFP80 60

ST72F521, ST72521B

206/215

DEVICE CONFIGURATION AND ORDERING INFORMATION (Cont’d)

14.3 DEVELOPMENT TOOLS

STMicroelectronics offers a range of hardware

and software d evelopment tools for th e ST7 micro-

controller family. Full details of tools available for

the ST7 from thir d party manu fact urers ca n be ob-

tained from the STMicroelectronics Internet site:

http//www.st.com.

Tools from these manufacturers include C compli-

ers, evaluation t ools, emulators and progr ammers.

Emulators

Two types of emulators are available from ST for

the ST725 family :

■ST7 DVP3 entry-level emulator offers a flexible

and modular debugging and programming

solution. SDIP42 & SDIP32 probes/adapters

are included, other packages need a specific

connection kit (refer to Table 31)

■ST7 EMU3 high-end emulator is delivered with

everything (probes, TEB, a dapters etc.) needed

to start emulating the ST725. To configure it to

emulate other ST7 subf amily devices, the active

probe for the ST7EMU3 can be changed and

the ST7EMU3 probe is designed for easy

interchange of TEBs (Target Emulation Board).

See Table 31.

In-circuit Debugging Kit

Two configurations ar e available from ST:

■STXF521-IND/USB: Low-cost In-Circuit

Debugging kit from Softec Microsystems.

Includes STX-InDART/USB board (USB port)

and a specific demo board for ST72521

(TQFP64)

■STxF-INDART

Flash Programming tools

■ST7-STICK ST7 In-circuit Communication Kit, a

complete software/hardware package for

programming ST7 Flash devices. It connects to

a host PC parallel port and t o the target board or

socket board via ST7 ICC connector.

■ICC Socket Boards provide an easy to use and

flexible means of programming ST7 Flash

devices. They can be connected to any tool that

supports the ST7 ICC interface, such as ST7

EMU3, ST7-DVP3, inDART, ST7-STICK, or

many third-pa r ty de ve lop m en t to ols .

Evaluation boards

Three different Evaluation boards are available:

■ST7232x-EVAL ST72F321/325/521 evaluation

board, with ICC connector for programming

capability. Provides direct connection to ST7-

DVP3 emulator. Supplied with daughter boards

(core module) for ST72F321, ST72F324,

ST72325 & ST72F521 (the ST72F32x chips are

not included)

■ST7MDT20-EVC/xx1 with CAB TQFP64 14x14

socket

■ST7MDT20-EVY/xx1 with Yamaichi TQFP64

10x10 socket

Table 31. STMicroelectronics Development Tools

Note 1: Add suffix /EU, /UK, /US for the power supply of your region.

Supported

Products

Emulation Programming

ST7 DVP3 Series ST7 EMU3 series ICC Socket Board

Emulator Connection kit Emulator Active Probe &

T.E.B.

ST72521M,

ST72F521M

ST7MDT20-DVP3

ST7MDT20-T80/

DVP ST7MDT20M-

EMU3 ST7MDT20M-TEB ST7SB20M/xx1

ST72521AR,

ST72F521AR ST7MDT20-T6A/

DVP

ST72521R,

ST72F521R ST7MDT20-T64/

DVP

ST72F521, ST72521B

207/215

DEVICE CONFIGURATION AND ORDERING INFORMATION (Cont’d)

Table 32. Suggested List of Socket Types

14.3.1 Socket and Emulator Adapter

Information

For information on the type of socket that is sup-

plied with th e emulator, r efer to the sugg ested list

of sockets in Table 32.

Note: Before designing the board layout, it is rec-

ommended to check the overall dimensions of the

socket as they may be greater than the dimen-

sions of the de vic e.

For footprint and other mechanical information

about these sockets and adapters, refer to the

manufacturer’s datasheet (www.yamaichi.de for

TQFP64 10 x 10 and TQFP80 14 x 14 and

www.cabgmbh.com for TQFP64 14 x 14)

Related Documentation

AN 978: ST7 Visual Develop Software Key Debug-

ging Features

AN 1938: ST7 Visual Develop for ST7 Cosmic C

toolset us er s

AN 1939: ST7 Visual Develop for ST7 Metro works

C toolset users

AN 1940: ST7 Visual Develop for ST7 Assembler

Linker toolset users

Device Socket (supplied with ST7MDT20M-

EMU3) Emulator Adapter (supplied with

ST7MDT20M-EMU3)

TQFP64 14 x14 CAB 3303262 CAB 3303351

TQFP64 10 x10 YAMAICHI IC149-064-*75-*5 YAMA ICHI ICP-064-6

TQFP80 14 X 14 YAMAICHI IC149-080-*51-*5 YAMAICHI ICP-080-7

ST72F521, ST72521B

208/215

14.4 ST7 APPLICATION NOTES

Table 33. ST7 Application Notes

IDENTIFICATION DESCRIPTION

APPLICATION EXAMPLES

AN1658 SERIAL NUMBERING IMPLEMENTATION

AN1720 MANAGING THE READ-OUT PROTECTION IN FLASH MICROCONTROLLERS

AN1755 A HIGH RESOLUTION/PRECISION THERMOMETER USING ST7 AND NE555

AN1756 CHOOSING A DALI IMPLEMENTATION STRATEGY WITH ST7DALI

EXAMPLE DRIVERS

AN 969 SCI COMMUNICATION BETWEEN ST7 AND PC

AN 970 SPI COMMUNICATION BETWEEN ST7 AND EEPROM

AN 971 I²C COMMUNICATION BETWEEN ST7 AND M24CXX EEPROM

AN 972 ST7 SOFTWARE SPI MASTER COMMUNICATION

AN 973 SCI SOFTWARE COMMUNICATION WITH A PC USING ST72251 16-BIT TIMER

AN 974 REAL TIME CLOCK WITH ST7 TIMER OUTPUT COMPARE

AN 976 DRIVING A BUZZER THROUGH ST7 TIMER PWM FUNCTION

AN 979 DRIVING AN ANALOG KEYBOARD WITH THE ST7 ADC

AN 980 ST7 KEYPAD DECODING TECHNIQUES, IMPLEMENTING WAKE-UP ON KEYSTROKE

AN1017 USING THE ST7 UNIVERSAL SERIAL BUS MICR OCONTR OLLER

AN1041 USING ST7 PWM SIG NAL TO GENERATE ANALO G OUTPUT (SINUSOÏD)

AN1042 ST7 ROUTINE FOR I²C SLAVE MODE MANAGEMENT

AN1044 MULTIPLE INTERRUPT SOURCES MANAGEMENT FOR ST7 MCUS

AN1045 ST7 S/W IMPLEMENTATION OF I²C BUS MASTER

AN1046 UART EMULATION SOFTWARE

AN1047 M ANAGING RECEPTION ERRORS WITH THE ST7 SCI PERIPHERALS

AN1048 ST7 SOFTWARE LCD DRIVER

AN1078 PWM DUTY CYCLE SWITCH IMPLEMENTING TRUE 0% & 100% DUTY CYCLE

AN1082 DESCRIPTION OF THE ST72141 MOTOR CONTROL PERIPHERALS REGISTERS

AN1083 ST72141 BLDC MOTOR CONTROL SOFTWARE AND FLOWCHART EXAMPLE

AN1105 ST7 PCAN PERIPHERAL DRIVER

AN1129 PW M MANAGEMENT FOR BLDC MOTOR DRIVES USING THE ST72141

AN1130 AN INTRODUCTION TO SENSORLESS BRUSHLESS DC MOTOR DRIVE APPLICATIONS

WITH THE ST72141

AN1148 USING THE ST7263 FOR DESIGNING A USB MOUSE

AN1149 HANDLING SUSPEND MODE ON A USB MOUSE

AN1180 USING THE ST7263 KIT TO IMPLEMENT A USB GAME PAD

AN1276 BLDC MOTOR START ROUTINE FOR THE ST72141 MICROCONTROLLER

AN1321 USING THE ST72141 MOTOR CONTROL MCU IN SENSOR MODE

AN1325 USING THE ST7 USB LOW-SPEED FIRMWARE V4.X

AN1445 EMULATED 16 BIT SLAVE SPI

AN1475 DEVELOPING AN ST7265X MASS STORAGE APPLICATION

AN1504 STARTING A PWM SIGNAL DIRECTLY AT HIGH LE VEL USING THE ST7 16-BIT TIMER

AN1602 16-BIT TIMING OPERATIONS USING ST7262 OR ST7263B ST7 USB MCUS

AN1633 DEVICE FIRMWARE UPGRADE (DFU) IMPLEMENTATION IN ST7 NON-USB APPLICATIONS

AN1712 GENERATING A HIGH RESOLUTION SINEWAVE USING ST7 PWMART

AN1713 SMBUS SLAVE DRIVER FOR ST7 I2C PERIPHERALS

AN1753 SO FTWARE UART USING 12-BIT ART

AN1947 ST7MC PMAC SINE WAVE MOTOR CONTROL SOFTWARE LIBRARY

ST72F521, ST72521B

209/215

GENERAL PURPOSE

AN1476 LOW COST POWER SUPPLY FOR HOME APPLIANCES

AN1526 ST7FLITE0 QUICK REFER ENCE NOTE

AN1709 EMC DESIGN FOR ST MICROCONTROLLERS

AN1752 ST72324 QUICK REFERENCE NOTE

PRODUCT EVALUATION

AN 910 PERFORMANCE BENCHMARKING

AN 990 ST7 BENEFITS VERSUS INDUSTRY STANDARD

AN1077 OVERVIEW OF ENHANCED CAN CONTROLLERS FOR ST7 AND ST9 MCUS

AN1086 U435 CAN-DO SOLUTIONS FOR CAR MULTIPLEXING

AN1103 IMPROVED B-EMF DETECTION FOR LOW SPEED, LOW VOLTAGE WITH ST72141

AN1150 BENCHMARK ST72 VS PC16

AN1151 PERFORMANCE COMPARISON BETWEEN ST72254 & PC16F876

AN1278 LIN (LOCAL INTERCONNECT NETWORK) SOLUTIONS

PRODUCT MIGRATION

AN1131 MIGRATING APPLICATIONS FROM ST72511/311/214/124 TO ST72521/321/324

AN1322 MIGRATING AN APPLICATION FROM ST7263 REV.B TO ST7263B

AN1365 GUIDELINES FOR MIGRATING ST72C254 APPLICATIONS TO ST72F264

AN1604 HOW TO USE ST7MDT1-TRAIN WITH ST72F264

PRODUCT OPTIMIZATION

AN 982 USING ST7 WITH CERAMIC RESONATOR

AN1014 HOW TO MINIMIZE THE ST7 POWER CONSUMPTION

AN1015 SOFTWARE TECHNIQUES FOR IMPROVING MICROCONTROLLER EMC PERFORMANCE

AN1040 MONITORING THE VBUS SIGNAL FOR USB SELF-POWERED DEVICES

AN1070 ST7 CHECKSUM SELF-CHECKING CAPABILITY

AN1181 ELECTROSTATIC DISCHARGE SENSITIVE MEASUREMENT

AN1324 CALIBRATING THE RC OSCILLATOR OF THE ST7FLITE0 MCU USING THE MAINS

AN1502 EMULATED DATA EEPROM WITH ST7 HDFLASH MEMORY

AN1529 EXTENDING THE CURRENT & VOLTAGE CAPABILITY ON THE ST7265 VDDF SUPPLY

AN1530 ACCURATE TIMEBASE FOR LOW-COST ST7 APPLICATIONS WITH INTERNAL RC OSCILLA-

TOR

AN1605 USING AN ACTIVE RC TO WAKEUP THE ST7LITE0 FROM POWER SAVING MODE

AN1636 UNDERSTANDING AND MINIMIZING ADC CONVERSION ERRORS

AN1828 PIR (PASSIVE INFRARED) DETECTOR USING THE ST7FLITE05/09/SUPERLITE

AN1946 SENSORLESS BLDC MOTOR CONTROL AND BEMF SAMPLING METHODS WITH ST7MC

AN1971 ST7LITE0 MICROCONTROLLED BALLAST

PROGRAMMING AND TOOLS

AN 978 ST7 VISUAL DEVELOP SOFTWARE KEY DEBUGGING FEATURES

AN 983 KEY FEATURES OF THE COSMIC ST7 C-COMPILER PACKAGE

AN 985 EXECUTING CODE IN ST7 RAM

AN 986 USING THE INDIRECT ADDRESSING MODE WITH ST7

AN 987 ST7 SERIAL TEST CONTROLLER PROGRAMMING

AN 988 STARTING WITH ST7 ASSEMBLY TOOL CHAIN

AN 989 GETTING STARTED WITH THE ST7 HIWARE C TOOLCHAIN

AN1039 ST7 MATH UTILITY ROUTINES

AN1064 WRITING OPTIMIZED HIWARE C LANGUAGE FOR ST7

AN1071 HALF DUPLEX USB-TO-SERIAL BRIDGE USING THE ST72611 USB MICROCONTROLLER

Table 33. ST7 Application Notes

IDENTIFICATION DESCRIPTION

ST72F521, ST72521B

210/215

AN1106 TRANSLATING ASSEMBLY CODE FROM HC05 TO ST7

AN1179 PROGRAMMING ST7 FLASH MICROCONTROLLERS IN REMOTE ISP MODE (IN-SITU PRO-

GRAMMING)

AN1446 USING THE ST72521 EMULATOR TO DEBUG A ST72324 TARGET APPLICATION

AN1477 EM ULATED DATA EEPROM WITH XFLASH MEMORY

AN1478 PORTING AN ST7 PANTA PROJECT TO CODEWARRIOR IDE

AN1527 DEVELOPING A USB SMARTCARD READER WITH ST7SCR

AN1575 ON-BOARD PROGRAMMING METHODS FOR XFLASH AND HDFLASH ST7 MCUS

AN1576 IN-APPLICATION PROGRAMMING (IAP) DRIVERS FOR ST7 HDFLASH OR XFLASH MCUS

AN1577 DEVICE FIRMWARE UPGRADE (DFU) IMPLEMENTATION FOR ST7 USB APPLICATIONS

AN1601 SOFTWARE IMPLEMENTATION FOR ST7DALI-EVAL

AN1603 USING THE ST7 USB DEVICE FIRM WARE UPGRADE DEVELOPMENT KIT (DFU-DK)

AN1635 ST7 CUSTOMER ROM CODE RELEASE INFORMATION

AN1754 DATA LOGGING PROGRAM FOR TESTING ST7 APPLICATIONS VIA ICC

AN1796 FIELD UPDATES FOR FLASH BASED ST7 APPLICATIONS USING A PC COMM PORT

AN1900 HARDWARE IMPLEMENTATION FOR ST7DALI-EVAL

AN1904 ST7MC THREE-PHASE AC INDUCTION MOTOR CONTROL SOFTWARE LIBRARY

AN1905 ST7MC THREE-PHASE BLDC MOTOR CONTROL SOFTWARE LIBRARY

SYSTEM OPTIMIZATION

AN1711 SOFTWARE TECHNIQUES FOR COMPENSATING ST7 ADC ERRORS

AN1827 IMPLEMENTATION OF SIGMA-DELTA ADC WITH ST7FLITE05/09

AN2009 PWM MANAGEMENT FOR 3-PHASE BLDC MOTOR DRIVES USING THE ST7FMC

AN2030 BACK EMF DETECTION DURING PWM ON TIME BY ST7MC

Table 33. ST7 Application Notes

IDENTIFICATION DESCRIPTION

ST72F521, ST72521B

211/215

15 KNOWN LIMITATIONS

15.1 ALL FLASH AND ROM DEVICES

15.1.1 External RC option

The External RC clock source option described in

previous datasheet revisions is no longer support-

ed and has been removed from this specification.

15.1.2 Safe Connection of OSC1/OSC2 Pins

The OSC1 and/or OSC2 pins must not be left un-

connected otherwise the ST7 main oscillator may

start and, in this configuration, could generate an

fOSC clock frequency in excess of the allowed

maximum (>16MHz.), putting the ST7 in an un-

safe/undef ined st at e. Ref er t o sectio n 6. 2 on p age

25.

15.1.3 Reset pin protection with LVD Enabled

As mentioned in note 2 below Figure 103 on page

186, when the LVD is enabled, it is recommended

not to connect a pull-up resistor or capacitor. A

10nF pull-down capacitor is required to filter noise

on the reset line.

15.1.4 Unexpected Reset Fetch

If an interrupt request occurs wh ile a “POP CC” in-

struction is executed, the interrupt controller does

not recognise the source of the interrupt and, by

default, passes the RESET vector address to the

CPU.

Workaround

To solve this issue, a “POP CC” instruction must

always be preceded by a “SIM” instruction.

15.1.5 Clearing active interrupts outside

interrupt routine

When an active interrupt request occurs at the

same time as the related flag is being cleared, an

unwanted reset may occur.

Note: clearing the related interrupt mask will not

generate an unwanted reset

Concurrent interrupt context

The symptom does not occur when the interrupts

are handle d no rm a lly, i.e .

when:

– The interrupt flag is cleared within its own inter-

rupt routine

– The interrupt flag is cleared within any interrupt

routine

– The interrupt flag is cleared in any part of the

code while this interrupt is disabled

If these conditions are not met, the symptom can

be avoided by implementing the following se-

quence:

Perform SIM and RIM operation before and after

resetting an active interrupt request.

Example:

SIM

reset interrupt flag

RIM

Nested interrupt context:

The symptom does not occur when the interrupts

are handle d no rm a lly, i.e .

when:

– The interrupt flag is cleared within its own inter-

rupt routine

– The interrupt flag is cleared within any interrupt

routine with higher or identical priority level

– The interrupt flag is cleared in any part of the

code while this interrupt is disabled

If these conditions are not met, the symptom can

be avoided by implementing the following se-

quence:

PUSH CC

SIM

reset interrupt flag

POP CC

ST72F521, ST72521B

212/215

KNOWN LIMITATIONS (Cont’d)

15.1.6 SCI Wrong Break duration

Description

A single break ch aracte r is sent by sett ing and re-

setting the SBK bit in the SCICR2 register. In

some cases, the break character may have a long-

er duration than expecte d :

- 20 bits instead of 10 bits if M=0

- 22 bits instead of 11 bits if M=1.

In the same way, as long as the SBK bit is set,

break characters are sent to the TDO pin. This

may lead to g enerate one break more than expect-

ed.

Occurrence

The occurrence of the problem is r andom and pro-

portional to the baudrate. With a transmit frequen-

cy of 19200 baud (fCPU=8MHz and SCI-

BRR=0xC9), the wr ong break duration occurren ce

is around 1%.

Workaround

If this wrong duration is not compliant with the

communication protocol in the application, soft-

ware can request that an Idle line be generated

before the brea k character. In this case, the break

duration is always correct assuming the applica-

tion is not doing anythin g between the idle and the

break. This can be ensured by temporarily disa-

bling interrupts.

The exact sequence is:

- Disable interrupts

- Reset and Set TE (IDLE request )

- Set and Reset SBK (Break Request)

- Re-enable interrupts

15.1.7 16-bit Timer PWM Mode

In PWM mode, the first PWM pulse is missed after

writing the value FFFCh in the OC1R register

(OC1HR, OC1LR). It leads to either full or no PWM

during a period, depending on the OLVL1 and

OLVL2 settings.

15.1.8 CAN Cell Limitat ions

x=limitation pr es en t

1For details see section 10.8.5 on pa g e 14 6

2Software workaround possible using modified

WKPS bit.

3Functionality modified for Unexpected Message

Transmission workaround in Flash.

4Limitation present on ROM Rev W and Rev Z.

Not present in Flash and ROM Rev Y.

15.1.9 I2C Multimaster

In multimaster configurations, if the ST7 I2C re-

ceives a S TART condition from an other I2C mas-

ter after th e START bit is set in t he I2 CCR register

and before the START condition is generated by

the ST7 I2C, it may ignore the START condition

from the other I2C master. In this case, the ST7

master will receive a NACK from the other device.

On reception of the NACK, ST7 can send a re-start

and Slave address to re-initiate communication

Limitation1 Flash ROM

Omitted SOF bit x x

CPU write access

(more than one cycle)

corrupts CAN frame xx

Unexpected Mes-

sage transmission x2

Bus Off State Not En-

tered x4

WKPS Functionality x3

ST72F521, ST72521B

213/215

KNOWN LIMITATIONS (Cont’d)

15.2 ALL FLASH DEVICES

15.2.1 Internal RC Oscillator with LVD

The internal RC can only be used if LVD is ena-

bled.

15.2.2 I/O behaviour during ICC mode entry

sequence

Symptom

In 80-pin devices (Flash), both Port G and H are

forced to output push-pull during ICC mode entry

sequence. 80-pin ROM devices are not impacted

by this issue.

Details

To enable programming of all flash sectors, the

device must leave USER mode an d be co nfigu red

in ICC mode. Once in ICC mode, the ICC protocol

enables an ST7 microcontroller to communicate

with an external controller (such as a PC). ICC

mode is entered by applying 39 pulses on the IC-

CDATA signal during reset. To enter ICC mode,

the device goes through other modes, some

modes are critical because the I/Os PG[7:0] and

PH[7:0] are forced to output push-pull.

Impact on the Application

The PG and PH I/O ports are forced to output

push-pull during three pulses on ICCDATA. In cer-

tain circumstances, this behaviour can lead to a

short-circuit between t he I/O sign als and V DD, VSS

or an output signal of another application compo-

nent.

In addition, switching these I/Os to output mode

can cause the application t o leave reset state, dis-

turbing the ICC comm unication and preventi ng the

user from programming the flash.

15.2.3 Read-out protection with LVD

The LVD is not supported if Readout protection is

enabled.

ST72F521, ST72521B
214/215
16 REVISION HISTORY
Table 34. Revision History
 Date Revision  Description of Changes
7-Dec-2004 3
Added Figure 82 on page 153
Reinstated “I/O behaviour during ICC mode entry sequence” on page 213 
Reinstated “BUSOFF not entered” in “CAN Cell Limitations” on page 212
Added “flash only” to PC6 Iinj spec in Section 12.2 and Section 12.8
4-Mar-2005 4
Added Note on SMbus to Section 10.7
Static current consumption modified in section 12.8 on page 182
Updated footnote and Figure 103 and Figure 104 on page 186 
Modified VtPOR in section 12.3.2 on page 168 
Added note 4 below Table of “CAN Cell Limitations” on page 212
18-May-2005 5
Corrected MCO description in Table 1 and Section 10.2
Updated footnotes and Figure 103 and Figure 104 on page 186. 
Updated soldering information in section 13.3 on page 200
Added Suffix 3 to Figure 118 on page 203
Updated partnumbers in Table 30 on page 205
Added “Reset pin protection with LVD Enabled” on page 211

ST72F521, ST72521B

215/215

Notes:

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