HY5PS561621BFP 256Mb(16Mx16) DDR2 SDRAM HY5PS561621BFP This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 1.2/Aug. 2008 1 1HY5PS561621BFP Revision History Revision No. History Draft Date Remark 0.0 Initial Graphics Version Release Jan. 2007 Preliminary 0.1 Inserted the fixed speed bin and revised typos Jan. 2007 Preliminary 0.2 Added PKG information on page 78 Feb. 2007 Preliminary 0.3 Inserted the IDD value Mar. 2007 Preliminary 0.4 Revised tWR=15ns, tRCD=15ns and tRP=15ns on page 74 Apr. 2007 Preliminary 1.0 Added IDD value of (-16) Aug. 2007 1.1 1.2 1. Corrected the definition of rising & falling slew rate (P.58) 2. Inserted the thermal characteristics table (P.56) Input/Output leakage current rating inserted.(P.56) Mar. 2008 Aug. 2008 Note) The HY5PS561621BFP data sheet follows all of JEDEC DDR2 standard. Rev. 1.2/Aug. 2008 2 1HY5PS561621BFP Contents 1. Description 1.1 Device Features and Ordering Information 1.1.1 Key Feaures 1.1.2 Ordering Information 1.2 16Mx16 DDR2 Pin Configuration 1.3 Pin Description 2. Functioanal Description 2.1 Simplified State Diagram 2.2 Functional Block Diagram(16M x 16) 2.3 Basic Function & Operation of DDR2 SDRAM 2.3.1 Power up and Initialization 2.3.2 Programming the Mode and Extended Mode Registers 2.3.2.1 DDR2 SDRAM Mode Register Set(MRS) 2.3.2.2 DDR2 SDRAM Extended Mode Register Set 2.3.2.3 Off-Chip Driver(OCD) Impedance Adjustment 2.3.2.4 ODT(On Die Termination) 2.4 Bank Activate Command 2.5 Read and Write Command 2.5.1 Posted CAS 2.5.2 Burst Mode Operation 2.5.3 Burst Read Command 2.5.4 Burst Write Operation 2.5.5 Write Data Mask 2.6 Precharge Operation 2.7 Auto Precharge Operation 2.8 Refresh Commands 2.8.1 Auto Refresh Command 2.8.2 Self Refresh Command 2.9 Power Down 2.10 Asynchronous CKE Low Event 2.11 No Operation Command 2.12 Deselect Command 3. Truth Tables 3.1 Command Truth Table 3.2 Clock Enable(CKE) Truth Table for Synchronous Transistors 3.3 Data Mask Truth Table 4. Operating Conditions 4.1 Absolute Maximum DC Ratings 4.2 Operating Temperature Condition 4.3 Thermal Characteristics Rev. 1.2/Aug. 2008 3 1HY5PS561621BFP 5. AC & DC Operating Conditions 5.1 DC Operation Conditions 5.1.1 Recommended DC Operating Conditions(SSTL_1.8) 5.1.2 ODT DC Electrical Characteristics 5.2 DC & AC Logic Input Levels 5.2.1 Input DC Logic Level 5.2.2 Input AC Logic Level 5.2.3 AC Input Test Conditions 5.2.4 Differential Input AC Logic Level 5.2.5 Differential AC output parameters 5.2.6 Overshoot / Undershoot Specification 5.3 Output Buffer Levels 5.3.1 Output AC Test Conditions 5.3.2 Output DC Current Drive 5.3.3 OCD default chracteristics 5.4 Default Output V-I Characteristics 5.4.1 Full Strength Default Pulldown Driver Characteristics 5.4.2 Full Strength Default Pullup Driver Chracteristics 5.4.3 Calibrated Output Driver V-I Characteristics 5.5 Input/Output Capacitance 6. IDD Specifications & Measurement Conditions 7. AC Timing Specifications 7.1 Timing Parameters by Speed Grade 7.2 General Notes for all AC Parameters 7.3 Specific Notes for dedicated AC parameters. 8 Package Dimension(x16) Rev. 1.2/Aug. 2008 4 1HY5PS561621BFP 1. Description 1.1 Device Features & Ordering Information 1.1.1 Key Features * * * * * * * * * * * * * * * * * * * * * * * * * 2.0V VDD/VDDQ supports (600/500MHz) 1.8V VDD/VDDQ wide range max power supply supports(500/450/400/350MHz) All inputs and outputs are compatible with SSTL_18 interface Fully differential clock inputs (CK, /CK) operation Double data rate interface:two data transfers per clock cycle(tCK) Source synchronous-data transaction aligned to bidirectional data strobe (DQS, DQS) Differential Data Strobe (DQS, DQS) Data outputs on DQS, DQS edges when read (edged DQ) Data inputs on DQS centers when write(centered DQ) On chip DLL align DQ, DQS and DQS transition with CK transition DM mask write data-in at the both rising and falling edges of the data strobe All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock Programmable CAS latency 4, 5, 6 and 7 supported Programmable additive latency 0, 1, 2, 3, 4, 5 supported Programmable burst length 4/8 with both nibble sequential and interleave mode Internal four bank operations with single pulsed RAS Auto refresh and self refresh supported tRAS lockout supported 8K refresh cycles /64ms JEDEC standard 84ball FBGA(x16) Full strength driver option controlled by EMRS On Die Termination supported Off Chip Driver Impedance Adjustment supported Partial Array Self Refresh supported High Temperature Self Refresh rate supported 1.1.2 Ordering Information Part No. HY5PS561621BFP-16 HY5PS561621BFP-2 Power Supply VDD/VDDQ=2.0V HY5PS561621BFP-2L HY5PS561621BFP-22 HY5PS561621BFP-25 HY5PS561621BFP-28 VDD/VDDQ=1.8V Clock Frequency Max Data Rate 600MHz 1200Mbps/pin 500MHz 1000Mbps/pin 500MHz 1000Mbps/pin 450MHz 900Mbps/pin 400MHz 800Mbps/pin 350MHz 700Mbps/pin Interface Package SSTL_18 84Ball FBGA Note) Hynix supports Lead free parts for each speed grade with same specification, except Lead free materials. We'll add "P" character after "F" for Lead free product. For example, the part number of 350MHz Lead free product is HY5PS561621BFP-28. Rev. 1.2/Aug. 2008 5 1HY5PS561621BFP 1.2 16Mx16 DDR2 Pin Configuration 7 8 9 A VSSQ UDQS VDDQ UDM B UDQS VSSQ DQ15 DQ9 VDDQ C VDDQ DQ8 VDDQ DQ12 VSSQ DQ11 D DQ10 VSSQ DQ13 VDD NC VSS E VSSQ LDQS VDDQ DQ6 VSSQ LDM F LDQS VSSQ DQ7 VDDQ DQ1 VDDQ G VDDQ DQ0 VDDQ DQ4 VSSQ DQ3 H DQ2 VSSQ DQ5 VDDL VREF VSS J VSSDL CK VDD CKE WE K RAS CK ODT BA0 BA1 L CAS CS A10 A1 M A2 A0 A3 A5 N A6 A4 A7 A9 P A11 A8 A12 NC R NC NC 1 2 3 VDD NC VSS DQ14 VSSQ VDDQ NC VSS VDD VDD VSS ROW AND COLUMN ADDRESS TABLE Rev. 1.2/Aug. 2008 ITEMS 16Mx16 # of Bank 4 Bank Address BA0, BA1 Auto Precharge Flag A10/AP Row Address A0 - A12 Column Address A0-A8 Page size 1 KB 6 1HY5PS561621BFP 1.3 PIN DESCRIPTION PIN TYPE DESCRIPTION CK, CK Input Clock: CK and CK are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK. Output (read) data is referenced to the crossings of CK and CK (both directions of crossing). CKE Input Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER DOWN (row ACTIVE in any bank). CKE is synchronous for POWER DOWN entry and exit, and for SELF REFRESH entry and exit.. CKE must be maintained high throughout READ and WRITE accesses. Input buffers, excluding CK, CK ,CKE and ODT are disabled during POWER DOWN. Input buffers, excluding CKE are disabled during SELF REFRESH. CKE is an SSTL_18 input, but will detect an LVCMOS LOW level after Vdd is applied. CS Input Chip Select : Enables or disables all inputs except CK, CK, CKE, DQS and DM. All commands are masked when CS is registered high. CS provides for external bank selection on systems with multiple banks. CS is considered part of the command code. ODT Input On Die Termination Control : ODT enables on die termination resistance internal to the DDR2 SDRAM. When enabled, on die termination is only applied to DQ, LDQS, /LDQS, UDQS, /UDQS, LDM and UDM RAS, CAS, WE Input Command Inputs: RAS, CAS and WE (along with CS) define the command being entered. LDM, UDM Input Input Data Mask : DM is an input mask signal for write data. Input Data is masked when DM is sampled High coincident with that input data during a WRITE access. DM is sampled on both edges of DQS, Although DM pins are input only, the DM loading matches the DQ and DQS loading. BA0, BA1 Input Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE, Read, Write or PRECHARGE command is being applied. Bank address also determines if the mode register or extended mode register is to be accessed during a MRS or EMRS cycle. A0 ~ A12 Input Address Inputs: Provide the row address for ACTIVE commands, and the column address and AUTO PRECHARGE bit for READ/WRITE commands to select one location out of the memory array in the respective bank. A10 is sampled during a precharge command to determine whether the PRECHARGE applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by BA0, BA1. The address inputs also provide the op code during MODE REGISTER SET commands. DQ Input/Output Data input / output : Bi-directional data bus Input/Output Data Strobe : Output with read data, input with write data. Edge aligned with read data, centered in write data. For the x16, LDQS correspond to the data on DQ0~DQ7; UDQS corresponds to the data on DQ8~DQ15. The data strobes LDQS, UDQS may be used in single ended mode or paired with optional complementary signals LDQS, UDQS to provide differential pair signaling to the system during both reads and wirtes. An EMRS(1) control bit enables or disables all complementary data strobe signals. (UDQS),(UDQS) (LDQS),(LDQS) No Connect : No internal electrical connection is present. NC VDDQ Supply DQ Ground VDDL Supply DLL Power Supply VSSDL Supply DLL Ground VDD Supply Power Supply VSS Supply Ground VREF Supply Reference voltage for inputs for SSTL interface. In this data sheet, "differential DQS signals" refers to any of the following with A10 = 0 of EMRS(1) x16 LDQS/LDQS and UDQS/UDQS "single-ended DQS signals" refers to any of the following with A10 = 1 of EMRS(1) x16 LDQS and UDQS Rev. 1.2/Aug. 2008 7 1HY5PS561621BFP 2. Functional Description 2.1 Simplified State Diagram Initialization Sequence CKEL OCD calibration Self Refreshing SRF CKEH PR Setting MRS EMRS Idle MRS REF All banks precharged Refreshing CKEL ACT CKEL CKEH Precharge Power Down Activating CKEL CKEL CKEL Automatic Sequence Active Power Down Command Sequence CKEH CKEL Bank Active Read Write Write Read WRA Writing RDA Read Reading RDA WRA RDA Writing with Autoprecharge PR, PRA PR, PRA PR, PRA Precharging Reading with Autoprecharge CKEL = CKE low, enter Power Down CKEH = CKE high, exit Power Down, exit Self Refresh ACT = Activate WR(A) = Write (with Autoprecharge) RD(A) = Read (with Autoprecharge) PR(A) = Precharge (All) MRS = (Extended) Mode Register Set SRF = Enter Self Refresh REF = Refresh Note: Use caution with this diagram. It is indented to provide a floorplan of the possible state transitions and the commands to control them, not all details. In particular situations involving more than one bank, enabling/disabling on-die termination, Power Down enty/exit - among other things - are not captured in full detail. Rev. 1.2/Aug. 2008 8 1HY5PS561621BFP 2.2 Functional Block Diagram (16Mx16) 4Banks x 4Mbit x 16 I/O DDR2 SDRAM Self refresh logic & timer refresh Internal Row Counter CLK CLK CLK RAS CAS WE U/LDM ODT Row Pre Decoders control Row decoders CS Input Buffers & State Machine CKE Row Active refresh Column Active 4Mx16 Bank3 4Mx16 Bank2 4Mx16 Bank1 4Mx16 Bank0 DLL OCD ODT Memory Cell Array control 16 Column Active latch Additive Latency Column Add Counter&latch A0 A12 Address buffers A1 BA1 BA0 Rev. 1.2/Aug. 2008 DQ 0~15 4bit pre-fetch Write Data Register Column decoders bank select Output Buffers & ODT 4bit pre-fetch Read Data Register 64 Sense Amp & I/O Gate ODT DLL Clk Control 16 Column Pre Decoders Input Buffers DS ODT control Address Registers DS Mode Register DQS I/O Buffer &ODT DLL Clk DQS DQS OCD Control 9 1HY5PS561621BFP 2.3 Basic Function & Operation of DDR2 SDRAM Read and write accesses to the DDR2 SDRAM are burst oriented; accesses start at a selected location and continue for a burst length of four or eight in a programmed sequence. Accesses begin with the registration of an Active command, which is then followed by a Read or Write command. The address bits registered coincident with the active command are used to select the bank and row to be accessed (BA0-BA1 select the bank; A0-A12 select the row). The address bits registered coincident with the Read or Write command are used to select the starting column location for the burst access and to determine if the auto precharge command is to be issued. Prior to normal operation, the DDR2 SDRAM must be initialized. The following sections provide detailed information covering device initialization, register definition, command descriptions and device operation. 2.3.1 Power up and Initialization DDR2 SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. Power-up and Initialization Sequence The following sequence is required for POWER UP and Initialization. 1. Apply power and attempt to maintain CKE below 0.2*VDDQ and ODT*1 at a low state (all other inputs may be undefined.) - VDD, VDDL and VDDQ are driven from a single power converter output, AND - VTT is limited to 0.95 V max, AND - Vref tracks VDDQ/2. or - Apply VDD before or at the same time as VDDL. - Apply VDDL before or at the same time as VDDQ. - Apply VDDQ before or at the same time as VTT & Vref. at least one of these two sets of conditions must be met. 2. Start clock and maintain stable condition. 3. For the minimum of 200 us after stable power and clock(CK, CK), then apply NOP or deselect & take CKE high. 4. Wait minimum of 400ns then issue precharge all command. NOP or deselect applied during 400ns period. 5. Issue EMRS(2) command. (To issue EMRS(2) command, provide "Low" to BA0, "High" to BA1.)*2 6. Issue EMRS(3) command. (To issue EMRS(3) command, provide "High" to BA0 and BA1.)*2 7. Issue EMRS to enable DLL. (To issue "DLL Enable" command, provide "Low" to A0, "High" to BA0 and "Low" to BA1.) 8. Issue a Mode Register Set command for "DLL reset". (To issue DLL reset command, provide "High" to A8 and "Low" to BA0-1.) 9. Issue precharge all command. 10. Issue 2 or more auto-refresh commands. 11. Issue a mode register set command with low to A8 to initialize device operation. (i.e. to program operating parameters without resetting the DLL.) 12. At least 200 clocks after step 8, execute OCD Calibration ( Off Chip Driver impedance adjustment ). If OCD calibration is not used, EMRS OCD Default command (A9=A8= A7=1) followed by EMRS OCD Calibration Mode Exit command (A9=A8=A7=0) must be issued with other operating parameters of Rev. 1.2/Aug. 2008 10 1HY5PS561621BFP EMRS. 13. The DDR2 SDRAM is now ready for normal operation. *1) To guarantee ODT off, VREF must be valid and a low level must be applied to the ODT pin. *2) Sequence 5 and 6 may be performed between 8 and 9. Initialization Sequence after Power Up tCH tCL CK /CK tIS CKE ODT Command PRE ALL NOP 400ns tMRD tMRD tRP DLL ENABLE PRE ALL MRS EMRS DLL RESET REF tRP MRS REF tRFC tRFC EMRS tMRD ANY CMD EMRS Follow OCD Flowchart tOIT min. 200 Cycle OCD Default OCD CAL. MODE EXIT 2.3.2 Programming the Mode and Extended Mode Registers For application flexibility, burst length, burst type, CAS latency, DLL reset function, write recovery time(tWR) are user defined variables and must be programmed with a Mode Register Set (MRS) command. Additionally, DLL disable function, driver impedance, additive CAS latency, ODT(On Die Termination), single-ended strobe, and OCD(off chip driver impedance adjustment) are also user defined variables and must be programmed with an Extended Mode Register Set (EMRS) command. Contents of the Mode Register(MR) or Extended Mode Registers(EMR(#)) can be altered by re-executing the MRS and EMRS Commands. If the user chooses to modify only a subset of the MRS or EMRS variables, all variables must be redefined when the MRS or EMRS commands are issued. MRS, EMRS and Reset DLL do not affect array contents, which means reinitialization including those can be executed any time after power-up without affecting array contents. Rev. 1.2/Aug. 2008 11 1HY5PS561621BFP 2.3.2.1 DDR2 SDRAM Mode Register Set (MRS) The mode register stores the data for controlling the various operating modes of DDR2 SDRAM. It controls CAS latency, burst length, burst sequence, test mode, DLL reset, tWR and various vendor specific options to make DDR2 SDRAM useful for various applications. The default value of the mode register is not defined, therefore the mode register must be written after power-up for proper operation. The mode register is written by asserting low on CS, RAS, CAS, WE, BA0 and BA1, while controlling the state of address pins A0 ~ A15. The DDR2 SDRAM should be in all bank precharge with CKE already high prior to writing into the mode register. The mode register set command cycle time (tMRD) is required to complete the write operation to the mode register. The mode register contents can be changed using the same command and clock cycle requirements during normal operation as long as all banks are in the precharge state. The mode register is divided into various fields depending on functionality. Burst length is defined by A0 ~ A2 with options of 4 and 8 bit burst lengths. The burst length decodes are compatible with DDR SDRAM. Burst address sequence type is defined by A3, CAS latency is defined by A4 ~ A6. The DDR2 doesn't support half clock latency mode. A7 is used for test mode. A8 is used for DLL reset. A7 must be set to low for normal MRS operation. Write recovery time tWR is defined by A9 ~ A11. Refer to the table for specific codes. BA2 BA1 0*1 0 BA0 A15 ~ A13 0*1 0 A8 A12 A11 PD No 1 Yes Active power down exit time A9 WR DLL Reset 0 A12 A10 A8 A7 DLL TM A6 A5 A4 CAS Latency A3 BT A2 A1 A0 Burst Length Address Field Mode Register Burst Length A7 mode A3 Burst Type 0 Normal 0 Sequential A2 A1 A0 BL Test 1 Interleave 0 1 0 4 0 1 1 8 1 Write recovery for autoprecharge A11 A10 A9 CAS Latency WR(cycles)*2 A6 A5 A4 Latency 0 Fast exit(use tXARD) 0 0 0 Reserved 0 0 0 Reserved 1 Slow exit(use tXARDS) 0 0 1 2 0 0 1 Reserved 0 1 0 3 0 1 0 Reserved 0 1 1 4 0 1 1 Reserved 1 0 0 5 1 0 0 4 1 0 1 6 1 0 1 5 1 1 0 7 1 1 0 6 1 1 1 Reserved 1 1 1 7 BA1 MRS mode BA0 0 0 MRS 0 1 EMRS(1) 1 0 EMRS(2): Reserved 1 1 EMRS(3): Reserved *1: BA2 and A13~A15 are reserved for future use and must be programmed to 0 when setting the mode register. BA2 and A13~A15 are not used for 256Mb *2: WR(write recovery for autoprecharge) min is determined by tCK max and WR max is determined by tCK min. WR in clock cycles is calculated by dividing tWR (in ns) by tCK (in ns) and rounding up to the next integer (WR[cycles] = tWR(ns)/tCK(ns)). The mode register must be programmed to this value. This is also used with tRP to determine tDAL. Rev. 1.2/Aug. 2008 12 1HY5PS561621BFP 2.3.2.2 DDR2 SDRAM Extended Mode Register Set EMRS(1) The extended mode register(1) stores the data for enabling or disabling the DLL, output driver strength, additive latency, ODT, DQS disable, OCD program, RDQS enable. The default value of the extended mode register(1) is not defined, therefore the extended mode register(1) must be written after power-up for proper operation. The extended mode register(1) is written by asserting low on CS, RAS, CAS, WE, high on BA0 and low on BA1, while controlling the states of address pins A0 ~ A15. The DDR2 SDRAM should be in all bank precharge with CKE already high prior to writing into the extended mode register(1). The mode register set command cycle time (tMRD) must be satisfied to complete the write operation to the extended mode register(1). Mode register contents can be changed using the same command and clock cycle requirements during normal operation as long as all banks are in the precharge state. A0 is used for DLL enable or disable. A1 is used for enabling a half strength output driver. A3~A5 determines the additive latency, A7~A9 are used for OCD control, A10 is used for DQS disable. A2 and A6 are used for ODT setting. DLL Enable/Disable The DLL must be enabled for normal operation. DLL enable is required during power up initialization, and upon returning to normal operation after having the DLL disabled. The DLL is automatically disabled when entering self refresh operation and is automatically re-enabled upon exit of self refresh operation. Any time the DLL is enabled (and subsequently reset), 200 clock cycles must occur before a Read command can be issued to allow time for the internal clock to be synchronized with the external clock. Failing to wait for synchronization to occur may result in a violation of the tAC or tDQSCK parameters. Rev. 1.2/Aug. 2008 13 1HY5PS561621BFP EMRS(1) Programming BA2 BA1 BA0 A15 ~ A13 0*1 0 A12 A11 A10 0 0 DQS 0*1 1 BA1 A9 A8 A6 A5 Rtt OCD program MRS mode BA0 A7 A6 A2 A4 A2 A1 A0 Additive latency Rtt D.I.C DLL 0 MRS 0 0 ODT Disabled 0 1 EMRS(1) 0 1 75 ohm 1 0 EMRS(2): Reserved 1 0 150 ohm 1 1 EMRS(3): Reserved 1 1 50 ohm A8 A7 0 0 0 0 0 0 Extended Mode Register Rtt (NOMINAL) 0 A9 Address Field A3 OCD Calibration Program A0 DLL Enable 0 Enable 1 Disable A5 A4 A3 OCD Calibration mode exit; maintain setting 0 0 0 0 1 Drive(1) 0 0 1 1 1 0 Drive(0) 0 1 0 2 1 0 0 Adjust modea 0 1 1 3 1 1 1 OCD Calibration default b 1 0 0 4 1 0 1 5 1 1 0 Reserved 1 1 1 Reserved a: When Adjust mode is issued, AL from previously set value must be applied. b: After setting to default, OCD mode needs to be exited by setting A9-A7 to 000. Refer to the following 2.2.2.3 section for detailed information A12 Qoff (Optional)a Additive Latency Output Driver Impedence Control Driver Size 0 Output buffer enabled A1 1 Output buffer disabled 0 Normal 100% 1 Weak 60% a. Outputs disabled - DQs, DQSs, DQSs. This feature is used in conjunction with DIMM IDD meaurements when IDDQ is not desired to be included. A10 DQS 0 Enable 1 Disable *1 : BA2 and A13~A15 are reserved for future use and must be programmed to 0 when setting the mode register. Rev. 1.2/Aug. 2008 14 1HY5PS561621BFP EMRS(2) The extended mode register(2) controls refresh related features. The default value of the extended mode register(2) is not defined, therefore the extended mode register(2) must be written after power-up for proper operation. The extended mode register(2) is written by asserting low on /CS,/RAS,/CAS,/WE, high on BA1 and low on BA0, while controling the states of address pins A0~A15. The DDR2 SDRAM should be in all bank precharge with CKE already high prior to writing into the extended mode register(2). Mode register contents can be changed using the same command and clock cycle requirements during normal operation as long as all bank are in the precharge state. EMRS(2) Programming: BA2 BA1 BA0 A15 ~ A13 0*1 1 BA1 0 0 1 1 A12 A11 A10 A9 A8 0*1 0 A7 A6 A5 A4 BA0 MRS mode 0 MRS 1 EMRS(1) 0 EMRS(2) 1 EMRS(3):Reserved 1 0 A2 A1 0*1 SRF A7 A3 Hign Temp Self-refresh Rate Enable Enable Disable Address Field A0 Extended Mode Register(2) PASR A2 A1 A0 0 0 0 0 0 0 1 1 0 1 0 1 1 0 0 3/4 Quarter Array (BA[1:0] = 01, 10 & 11) 1 0 1 1 1 1 1 0 1 Half Array (BA[1:0] = 10 & 11) Quarter Array (BA[1:0] = 11) Not defined Bank Refresh @ PASR All Bank Half Array (BA[1:0] = 00 & 01) Quarter Array (BA[1:0] = 00) Not defined *1 : The rest bits in EMRS(2) is reserved for future use and all bits except A7, BA0 and BA1 must be programmed to 0 when setting the mode register during initialization. Due to the migration natural, user needs to ensure the DRAM part supports higher than 85 Tcase temperature self-refresh entry. JEDEC standard DDR2 SDRAM Module user can look at DDR2 SDRAM Module SPD fileld Byte 49 bit[0]. If the high temperature self-refresh mode is supported then controller can set the EMRS2 [A7] bit to enable the self-refresh rate in case of higher than 85 temperature self-refresh operation. For the lose part user, please refer to the Hynix web site(www.hynix.com) to check the high temperature self-refresh rate availability. In order to save power consumption, DDR2 DRAM has Partial Array Self Refresh (PASR) option. PASR includes 6 kinds of self refresh mode. EMRS(3) Programming: Reserved*1 BA2 BA1 BA0 A15 ~ A13 0*1 1 1 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 0*1 *1 : EMRS(3) is reserved for future use and all bits except BA0 and BA1 must be programmed to 0 when setting the mode register during initialization. Rev. 1.2/Aug. 2008 15 1HY5PS561621BFP 2.3.2.3 Off-Chip Driver (OCD) Impedance Adjustment DDR2 SDRAM supports driver calibration feature and the flow chart below is an example of sequence. Every calibration mode command should be followed by "OCD calibration mode exit" before any other command being issued. MRS should be set before entering OCD impedance adjustment and ODT (On Die Termiantion) should be carefully controlled depending on system environment. MRS shoud be set before entering OCD impedance adjustment and ODT should be carefully controlled depending on system environment Start EMRS: OCD calibration mode exit EMRS: Drive(1) DQ & DQS High; DQS Low EMRS: Drive(0) DQ & DQS Low; DQS High ALL OK ALL OK Test Test Need Calibration Need Calibration EMRS: OCD calibration mode exit EMRS: OCD calibration mode exit EMRS : Enter Adjust Mode EMRS : Enter Adjust Mode BL=4 code input to all DQs Inc, Dec, or NOP BL=4 code input to all DQs Inc, Dec, or NOP EMRS: OCD calibration mode exit EMRS: OCD calibration mode exit EMRS: OCD calibration mode exit End Rev. 1.2/Aug. 2008 16 1HY5PS561621BFP Extended Mode Register Set for OCD impedance adjustment OCD impedance adjustment can be done using the following EMRS mode. In drive mode all outputs are driven out by DDR2 SDRAM and drive of RDQS is depedent on EMRS bit enabling RDQS operation. In Drive(1) mode, all DQ, DQS (and RDQS) signals are driven high and all DQS signals are driven low. In drive(0) mode, all DQ, DQS (and RDQS) signals are driven low and all DQS signals are driven high. In adjust mode, BL = 4 of operation code data must be used. In case of OCD calibration default, output driver characteristics have a nominal impedance value of 18 ohms during nominal temperature and voltage conditions. Output driver characteristics for OCD calibration default are specified in Table x. OCD applies only to normal full strength output drive setting defined by EMRS(1) and if half strength is set, OCD default output driver characteristics are not applicable. When OCD calibration adjust mode is used, OCD default output driver characteristics are not applicable. After OCD calibration is completed or driver strength is set to default, subsequent EMRS commands not intended to adjust OCD characteristics must specify A9-A7 as '000' in order to maintain the default or calibrated value. Off- Chip-Driver program A9 A8 A7 Operation 0 0 0 OCD calibration mode exit 0 0 1 Drive(1) DQ, DQS, (RDQS) high and DQS low 0 1 0 Drive(0) DQ, DQS, (RDQS) low and DQS high 1 0 0 Adjust mode 1 1 1 OCD calibration default OCD impedance adjust To adjust output driver impedance, controllers must issue the ADJUST EMRS command along with a 4bit burst code to DDR2 SDRAM as in table X. For this operation, Burst Length has to be set to BL = 4 via MRS command before activating OCD and controllers must drive this burst code to all DQs at the same time. DT0 in table X means all DQ bits at bit time 0, DT1 at bit time 1, and so forth. The driver output impedance is adjusted for all DDR2 SDRAM DQs simultaneously and after OCD calibration, all DQs of a given DDR2 SDRAM will be adjusted to the same driver strength setting. The maximum step count for adjustment is 16 and when the limit is reached, further increment or decrement code has no effect. The default setting may be any step within the 16 step range. When Adjust mode command is issued, AL from previously set value must be applied Table X : Off- Chip-Driver Program 4bit burst code inputs to all DQs Operation DT0 DT1 DT2 DT3 0 0 0 0 NOP (No operation) NOP (No operation) 0 0 0 1 Increase by 1 step NOP 0 0 1 0 Decrease by 1 step NOP 0 1 0 0 NOP Increase by 1 step 1 0 0 0 NOP Decrease by 1 step 0 1 0 1 Increase by 1 step Increase by 1 step 0 1 1 0 Decrease by 1 step Increase by 1 step 1 0 0 1 Increase by 1 step Decrease by 1 step Rev. 1.2/Aug. 2008 Pull-up driver strength Pull-down driver strength 17 1HY5PS561621BFP 1 0 1 0 Decrease by 1 step Decrease by 1 step Other Combinations Reserved For proper operation of adjust mode, WL = RL - 1 = AL + CL - 1 clocks and tDS/tDH should be met as the following timing diagram. For input data pattern for adjustment, DT0 - DT3 is a fixed order and "not affected by MRS addressing mode (ie. sequential or interleave). OCD adjust mode CMD EMRS OCD calibration mode exit NOP NOP NOP NOP NOP EMRS NOP CK CK WL WR DQS DQS_in tDS DQ_in tDH DT0 DT1 DT2 DT3 DM Drive Mode Drive mode, both Drive(1) and Drive(0), is used for controllers to measure DDR2 SDRAM Driver impedance. In this mode, all outputs are driven out tOIT after "enter drive mode" command and all output drivers are turned-off tOIT after "OCD calibration mode exit" command as the following timing diagram. OCD calibration mode exit Enter Drive mode CMD EMRS NOP NOP NOP EMRS CK CK DQS DQS Hi-Z Hi-Z DQS high & DQS low for Drive(1), DQS low & DQS high for Drive(0) DQs high for Drive(1) DQ DQs low for Drive(0) tOIT Rev. 1.2/Aug. 2008 tOIT 18 1HY5PS561621BFP 2.3.2.4 ODT (On Die Termination) On Die Termination (ODT) is a feature that allows a DRAM to turn on/off termination resistance for each DQ, DQS/DQS, RDQS/RDQS, and DM signal for x4x8 configurations via the ODT control pin. For x16 configuration ODT is applied to each DQ, UDQS/UDQS, LDQS/LDQS, UDM, and LDM signal via the ODT control pin. The ODT feature is designed to improve signal integrity of the memory channel by allowing the DRAM controller to independently turn on/off termination resistance for any or all DRAM devices. The ODT function is supported for ACTIVE and STANDBY modes. ODT is turned off and not supported in SELF REFRESH mode. FUNCTIONAL REPRESENTATION OF ODT VDDQ sw1 Rval1 VDDQ sw2 Rval2 DRAM Input Buffer Input Pin Rval1 sw1 VSSQ Rval2 sw2 VSSQ Switch sw1 or sw2 is enabled by ODT pin. Selection between sw1 or sw2 is determined by "Rtt (nominal)" in EMRS Termination included on all DQs, DM, DQS, DQS, RDQS, and RDQS pins. Target Rtt (ohm) = (Rval1) / 2 or (Rval2) / 2 Rev. 1.2/Aug. 2008 19 1HY5PS561621BFP ODT timing for active/standby mode T0 T1 T2 T3 T4 T5 T6 CK CK CKE tIS tIS ODT tAOFD tAOND Internal Term Res. RTT tAOF,min tAON,max tAON,min tAOF,max ODT timing for powerdown mode T0 T1 T2 T3 T4 T5 T6 CK CK CKE tIS tIS ODT tAOFPD,max tAOFPD,min Internal Term Res. RTT tAONPD,min tAONPD,max Rev. 1.2/Aug. 2008 20 1HY5PS561621BFP ODT timing mode switch at entering power down mode T-5 T-4 T-3 T-2 CK CK T-1 T0 T2 T1 T3 T4 tANPD tIS CKE Entering Slow Exit Active Power Down Mode or Precharge Power Down Mode. tIS ODT Active & Standby mode timings to be applied. tAOFD Internal Term Res. RTT tIS ODT Power Down mode timings to be applied. tAOFPDmax Internal Term Res. RTT tIS ODT tAOND Internal Term Res. RTT Active & Standby mode timings to be applied. tIS ODT tAONPDmax Internal Term Res. Rev. 1.2/Aug. 2008 RTT Power Down mode timings to be applied. 21 1HY5PS561621BFP ODT timing mode switch at exiting power down mode T0 T1 T4 T5 T6 T7 T8 T9 T10 T11 CK CK tIS tAXPD CKE Exiting from Slow Active Power Down Mode or Precharge Power Down Mode. tIS Active & Standby mode timings to be applied. ODT tAOFD Internal Term Res. RTT tIS Power Down mode timings to be applied. ODT tAOFPDmax Internal Term Res. RTT tIS Active & Standby mode timings to be applied. ODT tAOND Internal Term Res. RTT tIS Power Down mode timings to be applied. ODT tAONPDmax Internal Term Res. Rev. 1.2/Aug. 2008 RTT 22 1HY5PS561621BFP 2.4 Bank Activate Command The Bank Activate command is issued by holding CAS and WE high with CS and RAS low at the rising edge of the clock. The bank addresses BA0 ~ BA1 are used to select the desired bank. The row address A0 through A15 is used to determine which row to activate in the selected bank. The Bank Activate command must be applied before any Read or Write operation can be executed. Immediately after the bank active command, the DDR2 SDRAM can accept a read or write command on the following clock cycle. If a R/W command is issued to a bank that has not satisfied the tRCDmin specification, then additive latency must be programmed into the device to delay when the R/W command is internally issued to the device. The additive latency value must be chosen to assure tRCDmin is satisfied. Additive latencies of 0, 1, 2, 3, 4 and 5 are supported. Once a bank has been activated it must be precharged before another Bank Activate command can be applied to the same bank. The bank active and precharge times are defined as tRAS and tRP, respectively. The minimum time interval between successive Bank Activate commands to the same bank is determined by the RAS cycle time of the device (tRC). The minimum time interval between Bank Activate commands is tRRD. Bank Activate Command Cycle: tRCD = 3, AL = 2, tRP = 3, tRRD = 2, tCCD = 2 T0 T1 T2 T3 Tn Tn+1 Tn+2 Tn+3 .......... CK / CK Internal RAS-CAS delay (>= tRCDmin) ADDRESS Bank A Row Addr. Bank B Bank B Col. Addr. Row Addr. CAS-CAS delay time (tCCD) additive latency delay (AL) Bank A Col. Addr. tRCD =1 A . . . . . . . . .Bank . Addr. Bank B Addr. Bank A Row Addr. Bank B Precharge Bank A Activate Read Begins RAS - RAS delay time (>= tRRD) COMMAND Bank A Activate : "H" or "L" Bank A Post CAS Read Bank B Activate Bank B Post CAS Read A . . . . . . . . Bank .. Precharge Bank Active (>= tRAS) Bank Precharge time (>= tRP) RAS Cycle time (>= tRC) Rev. 1.2/Aug. 2008 23 1HY5PS561621BFP 2.5 Read and Write Command After a bank has been activated, a read or write cycle can be executed. This is accomplished by setting RAS high, CS and CAS low at the clock's rising edge. WE must also be defined at this time to determine whether the access cycle is a read operation (WE high) or a write operation (WE low). The DDR2 SDRAM provides a fast column access operation. A single Read or Write Command will initiate a serial read or write operation on successive clock cycles. The boundary of the burst cycle is strictly restricted to specific segments of the page length. For example, the 32Mbit x 4 I/O x 4 Bank chip has a page length of 2048 bits (defined by CA0-CA9, CA11). The page length of 2048 is divided into 512 or 256 uniquely addressable boundary segments depending on burst length, 512 for 4 bit burst, 256 for 8 bit burst respectively. A 4bit or 8 bit burst operation will occur entirely within one of the 512 or 256 groups beginning with the column address supplied to the device during the Read or Write Command (CA0-CA9, CA11). The second, third and fourth access will also occur within this group segment, however, the burst order is a function of the starting address, and the burst sequence. A new burst access must not interrupt the previous 4 bit burst operation in case of BL = 4 setting. However, in case of BL = 8 setting, two cases of interrupt by a new burst access are allowed, one reads interrupted by a read, the other writes interrupted by a write with 4 bit burst boundry respectively. The minimum CAS to CAS delay is defined by tCCD, and is a minimum of 2 clocks for read or write cycles. Rev. 1.2/Aug. 2008 24 1HY5PS561621BFP 2.5.1 Posted CAS Posted CAS operation is supported to make command and data bus efficient for sustainable bandwidths in DDR2 SDRAM. In this operation, the DDR2 SDRAM allows a CAS read or write command to be issued immediately after the RAS bank activate command (or any time during the RAS-CAS-delay time, tRCD, period). The command is held for the time of the Additive Latency (AL) before it is issued inside the device. The Read Latency (RL) is controlled by the sum of AL and the CAS latency (CL). Therefore if a user chooses to issue a R/W command before the tRCDmin, then AL (greater than 0) must be written into the EMRS(1). The Write Latency (WL) is always defined as RL - 1 (read latency -1) where read latency is defined as the sum of additive latency plus CAS latency (RL=AL+CL). Read or Write operations using AL allow seamless bursts (refer to seamless operation timing diagram examples in Read burst and Wirte burst section) Examples of posted CAS operation Example 1 Read followed by a write to the same bank [AL = 2 and CL = 3, RL = (AL + CL) = 5, WL = (RL - 1) = 4, BL = 4] -1 0 1 2 3 4 5 6 7 8 9 10 11 12 11 12 CK/CK Active A-Bank CMD Write A-Bank Read A-Bank DQS/DQS > = tRCD DQ WL = RL -1 = 4 CL = 3 AL = 2 RL = AL + CL = 5 Dout0 Dout1 Dout2 Dout3 Din0 Din1 Din2 Din3 > = tRAC Example 2 Read followed by a write to the same bank [AL = 0 and CL = 3, RL = (AL + CL) = 3, WL = (RL - 1) = 2, BL = 4] -1 0 1 2 3 4 5 6 7 8 9 10 CK/CK AL = 0 CMD DQS/DQS DQ Rev. 1.2/Aug. 2008 Active A-Bank Write A-Bank Read A-Bank WL = RL -1 = 2 CL = 3 > = tRCD RL = AL + CL = 3 Dout0 Dout1 Dout2 Dout3 Din0 Din1 Din2 Din3 > = tRAC 25 1HY5PS561621BFP 2.5.2 Burst Mode Operation Burst mode operation is used to provide a constant flow of data to memory locations (write cycle), or from memory locations (read cycle). The parameters that define how the burst mode will operate are burst sequence and burst length. DDR2 SDRAM supports 4 bit burst and 8 bit burst modes only. For 8 bit burst mode, full interleave address ordering is supported, however, sequential address ordering is nibble based for ease of implementation. The burst type, either sequential or interleaved, is programmable and defined by the address bit 3 (A3) of the MRS, which is similar to the DDR SDRAM operation. Seamless burst read or write operations are supported. Unlike DDR devices, interruption of a burst read or write cycle during BL = 4 mode operation is prohibited. However in case of BL = 8 mode, interruption of a burst read or write operation is limited to two cases, reads interrupted by a read, or writes interrupted by a write. Therefore the Burst Stop command is not supported on DDR2 SDRAM devices. Burst Length and Sequence Burst Length Starting Address (A2 A1 A0) Sequential Addressing (decimal) Interleave Addressing (decimal) 000 0, 1, 2, 3 0, 1, 2, 3 001 1, 2, 3, 0 1, 0, 3, 2 010 2, 3, 0, 1 2, 3, 0, 1 011 3, 0, 1, 2 3, 2, 1, 0 000 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 001 1, 2, 3, 0, 5, 6, 7, 4 1, 0, 3, 2, 5, 4, 7, 6 010 2, 3, 0, 1, 6, 7, 4, 5 2, 3, 0, 1, 6, 7, 4, 5 011 3, 0, 1, 2, 7, 4, 5, 6 3, 2, 1, 0, 7, 6, 5, 4 100 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 101 5, 6, 7, 4, 1, 2, 3, 0 5, 4, 7, 6, 1, 0, 3, 2 110 6, 7, 4, 5, 2, 3, 0, 1 6, 7, 4, 5, 2, 3, 0, 1 111 7, 4, 5, 6, 3, 0, 1, 2 7, 6, 5, 4, 3, 2, 1, 0 4 8 Note: Page length is a function of I/O organization and column addressing Rev. 1.2/Aug. 2008 26 1HY5PS561621BFP 2.5.3 Burst Read Command The Burst Read command is initiated by having CS and CAS low while holding RAS and WE high at the rising edge of the clock. The address inputs determine the starting column address for the burst. The delay from the start of the command to when the data from the first cell appears on the outputs is equal to the value of the read latency (RL). The data strobe output (DQS) is driven low 1 clock cycle before valid data (DQ) is driven onto the data bus. The first bit of the burst is synchronized with the rising edge of the data strobe (DQS). Each subsequent data-out appears on the DQ pin in phase with the DQS signal in a source synchronous manner. The RL is equal to an additive latency (AL) plus CAS latency (CL). The CL is defined by the Mode Register Set (MRS), similar to the existing SDR and DDR SDRAMs. The AL is defined by the Extended Mode Register Set (1)(EMRS(1)). DDR2 SDRAM pin timings are specified for either single ended mode or differential mode depending on the setting of the EMRS(1) "Enable DQS" mode bit; timing advantages of differential mode are realized in system design. The method by which the DDR2 SDRAM pin timings are measured is mode dependent. In single ended mode, timing relationships are measured relative to the rising or falling edges of DQS crossing at VREF. In differential mode, these timing relationships are measured relative to the crosspoint of DQS and its complement, DQS. This distinction in timing methods is guaranteed by design and characterization. Note that when differential data strobe mode is disabled via the EMRS, the complementary pin, DQS, must be tied externally to VSS through a 20 ohm to 10 Kohm resistor to insure proper operation. tCH tCL CK CK CK DQS DQS/DQS DQS tRPRE tRPST DQ Q Q Q tDQSQmax Q tDQSQmax tQH tQH Figure YY-- Data output (read) timing Burst Read Operation: RL = 5 (AL = 2, CL = 3, BL = 4) T0 T1 T2 T3 T4 T5 T6 T7 T8 CK/CK CMD Posted CAS READ A NOP NOP NOP NOP NOP NOP NOP NOP =< tDQSCK DQS/DQS AL = 2 CL =3 RL = 5 DQs Rev. 1.2/Aug. 2008 DOUT A0 DOUT A1 DOUT A2 DOUT A3 27 1HY5PS561621BFP Burst Read Operation: RL = 3 (AL = 0 and CL = 3, BL = 8) T0 T1 T2 T3 T4 T5 T6 T7 T8 CK/CK READ A CMD NOP NOP NOP NOP NOP NOP NOP NOP =< tDQSCK DQS/DQS CL =3 RL = 3 DQs DOUT A0 DOUT A1 DOUT A2 DOUT A3 DOUT A4 DOUT A5 DOUT A6 DOUT A7 Burst Read followed by Burst Write: RL = 5, WL = (RL-1) = 4, BL = 4 T0 T1 Tn-1 Tn Tn+1 Tn+2 Tn+3 Tn+4 Tn+5 NOP NOP NOP NOP CK/CK CMD Post CAS READ A NOP Post CAS NOP WRITE A tRTW (Read to Write turn around time) NOP DQS/DQS RL =5 WL = RL - 1 = 4 DQ's DOUT A0 DOUT A1 DOUT A2 DOUT A3 DIN A0 DIN A1 DIN A2 DIN A3 The minimum time from the burst read command to the burst write command is defined by a read-to-writeturn-around-time, which is 4 clocks in case of BL = 4 operation, 6 clocks in case of BL = 8 operation. Rev. 1.2/Aug. 2008 28 1HY5PS561621BFP Seamless Burst Read Operation: RL = 5, AL = 2, and CL = 3, BL = 4 T0 T1 T2 T3 T4 T5 T6 T7 T8 CK/CK CMD Post CAS READ A NOP Post CAS READ B NOP NOP NOP NOP NOP NOP DQS/DQS CL =3 AL = 2 RL = 5 DQs DOUT A0 DOUT A1 DOUT A2 DOUT A3 DOUT B0 DOUT B1 DOUT B2 The seamless burst read operation is supported by enabling a read command at every other clock for BL = 4 operation, and every 4 clock for BL = 8 operation. This operation is allowed regardless of same or different banks as long as the banks are activated. Rev. 1.2/Aug. 2008 29 1HY5PS561621BFP Reads interrupted by a read Burst read can only be interrupted by another read with 4 bit burst boundary. Any other case of read interrupt is not allowed. Read Burst Interrupt Timing Example: (CL=3, AL=0, RL=3, BL=8) CK/CK CMD Read A NOP Read B NOP NOP NOP NOP NOP NOP NOP DQS/DQS DQs A0 A1 A2 A3 B0 B1 B2 B3 B4 B5 B6 B7 Note 1. Read burst interrupt function is only allowed on burst of 8. Burst interrupt of 4 is prohibited. 2. Read burst of 8 can only be interrupted by another Read command. Read burst interruption by Write command or Precharge command is prohibited. 3. Read burst interrupt must occur exactly two clocks after previous Read command. Any other Read burst interrupt timings are prohibited. 4. Read burst interruption is allowed to any bank inside DRAM. 5. Read burst with Auto Precharge enabled is not allowed to interrupt. 6. Read burst interruption is allowed by another Read with Auto Precharge command. 7. All command timings are referenced to burst length set in the mode register. They are not referenced to actual burst. For example, Minimum Read to Precharge timing is AL + BL/2 where BL is the burst length set in the mode register and not the actual burst (which is shorter because of interrupt). Rev. 1.2/Aug. 2008 30 1HY5PS561621BFP 2.5.4 Burst Write Operation The Burst Write command is initiated by having CS, CAS and WE low while holding RAS high at the rising edge of the clock. The address inputs determine the starting column address. Write latency (WL) is defined by a read latency (RL) minus one and is equal to (AL + CL -1). A data strobe signal (DQS) should be driven low (preamble) one clock prior to the WL. The first data bit of the burst cycle must be applied to the DQ pins at the first rising edge of the DQS following the preamble. The tDQSS specification must be satisfied for write cycles. The subsequent burst bit data are issued on successive edges of the DQS until the burst length is completed, which is 4 or 8 bit burst. When the burst has finished, any additional data supplied to the DQ pins will be ignored. The DQ Signal is ignored after the burst write operation is complete. The time from the completion of the burst write to bank precharge is the write recovery time (WR). DDR2 SDRAM pin timings are specified for either single ended mode or differential mode depending on the setting of the EMRS "Enable DQS" mode bit; timing advantages of differential mode are realized in system design. The method by which the DDR2 SDRAM pin timings are measured is mode dependent. In single ended mode, timing relationships are measured relative to the rising or falling edges of DQS crossing at VREF. In differential mode, these timing relationships are measured relative to the crosspoint of DQS and its complement, DQS. This distinction in timing methods is guaranteed by design and characterization. Note that when differential data strobe mode is disabled via the EMRS, the complementary pin, DQS, must be tied externally to VSS through a 20 ohm to 10 Kohm resistor to insure proper operation. tDQSH DQS DQS/ DQS tDQSL DQS tWPRE tWPST DQ D D tDS DM tDH tDS DMin D D DMin DMin tDH DMin Data input (write) timing Burst Write Operation: RL = 5, WL = 4, tWR = 3 (AL=2, CL=3), BL = 4 T0 T1 T2 T3 T4 T5 T6 T7 Tn CK/CK CMD Posted CAS WRITE A NOP NOP NOP NOP NOP NOP NOP Precharge Completion of the Burst Write < = tDQSS DQS/DQS WL = RL - 1 = 4 DQs Rev. 1.2/Aug. 2008 > = WR DIN A0 DIN A1 DIN A2 DIN A3 31 1HY5PS561621BFP Burst Write Operation: RL = 3, WL = 2, tWR = 2 (AL=0, CL=3), BL = 4 T0 T1 T2 T3 T4 T5 T6 T7 Tn CK/CK NOP WRITE A CMD NOP NOP NOP NOP Precharge NOP Bank A Activate Completion of the Burst Write < = tDQSS DQS/ DQS WL = RL - 1 = 2 > = tRP > = WR DQs DIN A0 DIN A1 DIN A2 DIN A3 Burst Write followed by Burst Read: RL = 5 (AL=2, CL=3), WL = 4, tWTR = 2, BL = 4 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 CK/CK Write to Read = CL - 1 + BL/2 + tWTR CMD NOP NOP NOP Post CAS READ A NOP NOP NOP NOP NOP DQS DQS/ DQS DQS CL = 3 AL = 2 WL = RL - 1 = 4 RL =5 > = tWTR DQ DIN A0 DIN A1 DIN A2 DOUT A0 DIN A3 The minimum number of clock from the burst write command to the burst read command is [CL - 1 + BL/2 + tWTR]. This tWTR is not a write recovery time (tWR) but the time required to transfer the 4bit write data from the input buffer into sense amplifiers in the array. tWTR is defined in AC spec table of this data sheet. Rev. 1.2/Aug. 2008 32 1HY5PS561621BFP Seamless Burst Write Operation: RL = 5, WL = 4, BL = 4 T0 T1 T2 T3 T4 T5 T6 T7 T8 CK/CK CMD Post CAS Write A NOP Post CAS Write B NOP NOP NOP NOP NOP NOP DQS DQS/ DQS DQS WL = RL - 1 = 4 DQ's DIN A0 DIN A1 DIN A2 DIN A3 DIN B0 DIN B1 DIN B2 DIN B3 The seamless burst write operation is supported by enabling a write command every other clock for BL = 4 operation, every four clocks for BL = 8 operation. This operation is allowed regardless of same or different banks as long as the banks are activated Rev. 1.2/Aug. 2008 33 1HY5PS561621BFP Writes interrupted by a write Burst write can only be interrupted by another write with 4 bit burst boundary. Any other case of write interrupt is not allowed. Write Burst Interrupt Timing Example: (CL=3, AL=0, RL=3, WL=2, BL=8) CK/CK CMD NOP Write A NOP NOP Write B NOP NOP NOP NOP NOP DQS/DQS DQs A0 A1 A2 A3 B0 B1 B2 B3 B4 B5 B6 B7 Notes: 1. Write burst interrupt function is only allowed on burst of 8. Burst interrupt of 4 is prohibited. 2. Write burst of 8 can only be interrupted by another Write command. Write burst interruption by Read command or Precharge command is prohibited. 3. Write burst interrupt must occur exactly two clocks after previous Write command. Any other Write burst interrupt timings are prohibited. 4. Write burst interruption is allowed to any bank inside DRAM. 5. Write burst with Auto Precharge enabled is not allowed to interrupt. 6. Write burst interruption is allowed by another Write with Auto Precharge command. 7. All command timings are referenced to burst length set in the mode register. They are not referenced to actual burst. For example, minimum Write to Precharge timing is WL+BL/2+tWR where tWR starts with the rising clock after the un-interrupted burst end and not from the end of actual burst end. Rev. 1.2/Aug. 2008 34 1HY5PS561621BFP 2.5.5 Write Data Mask One write data mask (DM) pin for each 8 data bits (DQ) will be supported on DDR2 SDRAMs, Consistent with the implementation on DDR SDRAMs. It has identical timings on write operations as the data bits, and though used in a uni-directional manner, is internally loaded identically to data bits to insure matched system timing. DM of x4 and x16 bit organization is not used during read cycles. However DM of x8 bit organization can be used as RDQS during read cycles by EMRS(1) settng. Data Mask Timing DQS/ DQS DQ DM tDS tDH tDS tDH Data Mask Function, WL=3, AL=0, BL = 4 shown Case 1 : min tDQSS CK CK COMMAND Write tDQSS tWR DQS/DQS DQ DM Case 2 : max tDQSS tDQSS DQS/DQS DQ DM Rev. 1.2/Aug. 2008 35 1HY5PS561621BFP 2.6 Precharge Operation The Precharge Command is used to precharge or close a bank that has been activated. The Precharge Command is triggered when CS, RAS and WE are low and CAS is high at the rising edge of the clock. The Precharge Command can be used to precharge each bank independently or all banks simultaneously. Three address bits A10, BA0 and BA1 for 256Mb are used to define which bank to precharge when the command is issued. Bank Selection for Precharge by Address Bits A10 BA1 BA0 Precharged Bank(s) LOW LOW LOW Bank 0 only LOW LOW HIGH Bank 1 only LOW HIGH LOW Bank 2 only LOW HIGH HIGH Bank 3 only HIGH DON'T CARE DON'T CARE All Banks Remarks Burst Read Operation Followed by Precharge Minium Read to precharge command spacing to the same bank = AL + BL/2 clocks For the earliest possible precharge, the precharge command may be issued on the rising edge which is "Additive latency(AL) + BL/2 clocks" after a Read command. A new bank active (command) may be issued to the same bank after the RAS precharge time (tRP). A precharge command cannot be issued until tRAS is satisfied. The minimum Read to Precharge spacing has also to satisfy a minimum analog time from the rising clock egde that initiates the last 4-bit prefetch of a Read to Precharge command. This time is called tRTP (Read to Precharge). For BL = 4 this is the time from the actual read (AL after the Read command) to Precharge command. For BL = 8 this is the time from AL + 2 clocks after the Read to the Precharge command. Rev. 1.2/Aug. 2008 36 1HY5PS561621BFP Example 1: Burst Read Operation Followed by Precharge: RL = 4, AL = 1, CL = 3, BL = 4, tRTP <= 2 clocks T0 T1 T2 T3 T4 T5 T6 T7 T8 NOP Bank A Active NOP T6 T7 T8 NOP NOP NOP CK/CK CMD Post CAS READ A NOP NOP Precharge NOP NOP AL + BL/2 clks DQS/DQS > = tRP CL = 3 AL = 1 RL =4 DQ's DOUT A0 > = tRAS DOUT A1 DOUT A2 DOUT A3 CL =3 > = tRTP Example 2: Burst Read Operation Followed by Precharge: RL = 4, AL = 1, CL = 3, BL = 8, tRTP <= 2 clocks T0 T1 T2 T3 T4 T5 CK/CK CMD Post CAS READ A NOP NOP NOP NOP Precharge A AL + BL/2 clks DQS/DQS CL = 3 AL = 1 RL =4 DQ's DOUT A0 DOUT A1 DOUT A2 DOUT A3 DOUT A4 DOUT A5 DOUT A6 DOUT A7 > = tRTP first 4-bit prefetch Rev. 1.2/Aug. 2008 second 4-bit prefetch 37 1HY5PS561621BFP Example 3: Burst Read Operation Followed by Precharge: RL = 5, AL = 2, CL = 3, BL = 4, tRTP <= 2 clocks T0 T1 T2 T3 T4 T5 T6 T7 T8 Bank A Activate NOP CK/CK CMD Posted CAS READ A NOP NOP NOP Precharge A NOP NOP AL + BL/2 clks DQS/DQS > = tRP AL = 2 CL =3 RL =5 DQ's DOUT A0 > = tRAS DOUT A1 DOUT A2 DOUT A3 CL =3 > = tRTP Example 4: Burst Read Operation Followed by Precharge: RL = 6, AL = 2, CL = 4, BL = 4, tRTP <= 2 clocks T0 T1 T2 T3 T4 T5 T6 T7 T8 Bank A Activate NOP CK/CK CMD Post CAS READ A NOP NOP NOP Precharge A NOP NOP AL + BL/2 Clks DQS/DQS > = tRP AL = 2 CL =4 RL = 6 DQ's DOUT A0 > = tRAS DOUT A1 DOUT A2 DOUT A3 CL =4 > = tRTP Rev. 1.2/Aug. 2008 38 1HY5PS561621BFP Example 5: Burst Read Operation Followed by Precharge: RL = 4, AL = 0, CL = 4, BL = 8, tRTP > 2 clocks T0 T1 T2 T3 T4 T5 T6 T7 T8 NOP Bank A Activate CK/CK CMD Post CAS READ A NOP NOP NOP NOP NOP Precharge A AL + 2 Clks + max{tRTP;2 tCK}* DQS/DQS AL = 0 > = tRP CL =4 RL = 4 DQ's DOUT A0 DOUT A1 DOUT A2 DOUT A3 DOUT A4 DOUT A5 DOUT A6 DOUT A7 > = tRAS > = tRTP first 4-bit prefetch second 4-bit prefetch * : rounded to next interger Rev. 1.2/Aug. 2008 39 1HY5PS561621BFP Burst Write followed by Precharge Minium Write to Precharge Command spacing to the same bank = WL + BL/2 clks + tWR For write cycles, a delay must be satisfied from the completion of the last burst write cycle until the Precharge Command can be issued. This delay is known as a write recovery time (tWR) referenced from the completion of the burst write to the precharge command. No Precharge command should be issued prior to the tWR delay. Example 1: Burst Write followed by Precharge: WL = (RL-1) =3 T0 T1 T2 T3 T4 T5 T6 T7 T8 CK/CK CMD Posted CAS WRITE A NOP NOP NOP NOP NOP NOP NOP Precharge A Completion of the Burst Write > = WR DQS/DQS WL = 3 DQs DIN A0 DIN A1 DIN A2 DIN A3 Example 2: Burst Write followed by Precharge: WL = (RL-1) = 4 T0 T1 T2 T3 T4 T5 T6 T7 T9 CK/CK CMD Posted CAS WRITE A NOP NOP NOP NOP NOP NOP NOP Precharge A Completion of the Burst Write > = tWR DQS/DQS WL = 4 DQs Rev. 1.2/Aug. 2008 DIN A0 DIN A1 DIN A2 DIN A3 40 1HY5PS561621BFP 2.7 Auto Precharge Operation Before a new row in an active bank can be opened, the active bank must be precharged using either the Precharge command or the auto-precharge function. When a Read or a Write command is given to the DDR2 SDRAM, the CAS timing accepts one extra address, column address A10, to allow the active bank to automatically begin precharge at the earliest possible moment during the burst read or write cycle. If A10 is low when the READ or WRITE command is issued, then normal Read or Write burst operation is executed and the bank remains active at the completion of the burst sequence. If A10 is high when the Read or Write command is issued, then the auto-precharge function is engaged. During auto-precharge, a Read command will execute as normal with the exception that the active bank will begin to precharge on the rising edge which is CAS latency (CL) clock cycles before the end of the read burst. Auto-precharge is also implemented during Write commands. The precharge operation engaged by the Auto precharge command will not begin until the last data of the burst write sequence is properly stored in the memory array. This feature allows the precharge operation to be partially or completely hidden during burst read cycles (dependent upon CAS latency) thus improving system performance for random data access. The RAS lockout circuit internally delays the Precharge operation until the array restore operation has been completed (tRAS satisfied) so that the auto precharge command may be issued with any read or write command. Burst Read with Auto Precharge If A10 is high when a Read Command is issued, the Read with Auto-Precharge function is engaged. The DDR2 SDRAM starts an Auto Precharge operation on the rising edge which is (AL + BL/2) cycles later than the read with AP command if tRAS(min) and tRTP are satisfied. If tRAS(min) is not satisfied at the edge, the start point of auto-precharge operation will be delayed until tRAS(min) is satisfied. If tRTP(min) is not satisfied at the edge, the start point of auto-precharge operation will be delayed until tRTP(min) is satisfied. In case the internal precharge is pushed out by tRTP, tRP starts at the point where the internal precharge happens (not at the next rising clock edge after this event). So for BL = 4 the minimum time from Read_AP to the next Activate command becomes AL + (tRTP + tRP)* (see example 2) for BL = 8 the time from Read_AP to the next Activate is AL + 2 + (tRTP + tRP)*, where "*" means: "rounded up to the next integer". In any event internal precharge does not start earlier than two clocks after the last 4-bit prefetch. A new bank activate (command) may be issued to the same bank if the following two conditions are satisfied simultaneously. (1) The RAS precharge time (tRP) has been satisfied from the clock at which the auto precharge begins. (2) The RAS cycle time (tRC) from the previous bank activation has been satisfied. Rev. 1.2/Aug. 2008 41 1HY5PS561621BFP Example 1: Burst Read Operation with Auto Precharge: RL = 4, AL = 1, CL = 3, BL = 8, tRTP <= 2 clocks T0 T1 T2 T3 T4 T5 T6 T7 NOP NOP NOP T8 CK/CK Post CAS CMD READ A NOP NOP NOP NOP Bank A Activate Autoprecharge AL + BL/2 clks > = tRP DQS/DQS CL = 3 AL = 1 RL =4 DQ's DOUT A0 DOUT A1 DOUT A2 DOUT A3 DOUT A4 DOUT A5 DOUT A6 DOUT A7 > = tRTP second 4-bit prefetch first 4-bit prefetch tRTP Precharge begins here Example 2: Burst Read Operation with Auto Precharge: RL = 4, AL = 1, CL = 3, BL = 4, tRTP > 2 clocks T0 T1 T2 T3 T4 T5 T6 T7 T8 NOP NOP Bank A Activate NOP CK/CK CMD Post CAS READ A NOP NOP NOP NOP Autoprecharge > = AL + tRTP + tRP DQS/DQS CL = 3 AL = 1 RL =4 DQ's DOUT A0 DOUT A1 DOUT A2 DOUT A3 4-bit prefetch tRTP Rev. 1.2/Aug. 2008 Precharge begins here tRP 42 1HY5PS561621BFP Example 3: Burst Read with Auto Precharge Followed by an activation to the Same Bank(tRC Limit): RL = 5 (AL = 2, CL = 3, internal tRCD = 3, BL = 4, tRTP <= 2 clocks) T0 T1 T2 T3 T4 T5 T6 T7 T8 CK/CK A10 = 1 CMD Post CAS READ A NOP NOP NOP > = tRAS(min) NOP NOP NOP NOP Bank A Activate Auto Precharge Begins DQS/DQS > = tRP AL = 2 CL =3 RL = 5 DQ's DOUT A0 DOUT A1 DOUT A2 DOUT A3 CL =3 > = tRC Example 4: Burst Read with Auto Precharge Followed by an Activation to the Same Bank(tRP Limit): RL = 5 (AL = 2, CL = 3, internal tRCD = 3, BL = 4, tRTP <= 2 clocks) T0 T1 T2 T3 T4 T5 T6 T7 T8 CK/CK A10 = 1 CMD Post CAS READ A NOP NOP NOP > = tRAS(min) NOP NOP Bank A Activate NOP NOP Auto Precharge Begins DQS/DQS > = tRP AL = 2 CL =3 RL = 5 DQ's DOUT A0 > = tRC Rev. 1.2/Aug. 2008 DOUT A1 DOUT A2 DOUT A3 CL =3 43 1HY5PS561621BFP Burst Write with Auto-Precharge If A10 is high when a Write Command is issued, the Write with Auto-Precharge function is engaged. The DDR2 SDRAM automatically begins precharge operation after the completion of the burst write plus write recovery time (tWR). The bank undergoing auto-precharge from the completion of the write burst may be reactivated if the following two conditions are satisfied. (1) The data-in to bank activate delay time (WR + tRP) has been satisfied. (2) The RAS cycle time (tRC) from the previous bank activation has been satisfied. Burst Write with Auto-Precharge (tRC Limit): WL = 2, tWR =2, BL = 4, tRP=3 T0 T1 T2 T3 T4 T5 T6 T7 Tm CK/CK A10 = 1 CMD Post CAS WRA BankA NOP NOP NOP NOP NOP Completion of the Burst Write NOP NOP Bank A Active Auto Precharge Begins DQS/DQS DQs > = tRP > = WR WL =RL - 1 = 2 DIN A0 DIN A1 DIN A2 DIN A3 > = tRC Burst Write with Auto-Precharge (tWR + tRP): WL = 4, tWR =2, BL = 4, tRP=3 T0 T3 T4 T5 T6 T7 T8 T9 T12 CK/CK A10 = 1 Post CAS CMD WRA Bank A NOP NOP NOP NOP NOP Completion of the Burst Write NOP NOP Bank A Active Auto Precharge Begins DQS/DQS > = WR WL =RL - 1 = 4 DQs DIN A0 DIN A1 DIN A2 > = tRP DIN A3 > = tRC Rev. 1.2/Aug. 2008 44 1HY5PS561621BFP 2.8 Refresh Commands DDR2 SDRAMs require a refresh of all rows in any rolling 64 ms interval. Each refresh is generated in one of two ways: by an explicit Auto-Refresh command, or by an internally timed event in SELF REFRESH mode. Dividing the number of device rows into the rolling 64ms interval, tREFI, which is a guideline to controllers for distributed refresh timing. For example, a 256Mb DDR2 SDRAM has 8192 rows resulting in a tREFI of 7.8. To avoid excessive interruptions to the memory controller, higher density DDR2 SDRAMS maintain 7.8 average refresh time and perform multiple internal refresh bursts. In these cases, the refresh recovery times, tRFC an tXSNR are extended to accomodate these internal operations. 2.8.1 Auto Refresh Command AUTO REFRESH is used during normal operation of the DDR2 SDRAM. This command is nonpersistent, so it must be issued each time a refresh is required. The refresh addressing is generated by the internal refresh controller. This makes the address bits "Don't Care" during an AUTO REFRESH command. When CS, RAS and CAS are held low and WE high at the rising edge of the clock, the chip enters the Refresh mode (REF). All banks of the DDR2 SDRAM must be precharged and idle for a minimum of the Precharge time (tRP) before the Refresh command (REF) can be applied. An address counter, internal to the device, supplies the bank address during the refresh cycle. No control of the external address bus is required once this cycle has started. When the refresh cycle has completed, all banks of the DDR2 SDRAM will be in the precharged (idle) state. A delay between the Refresh command (REF) and the next Activate command or subsequent Refresh command must be greater than or equal to the Refresh cycle time (tRFC). To allow for improved efficiency in scheduling andswitching between tasks, some flexibility in the absolute refresh interval is provided. A maximum of eight Refresh commands can be posted to any given DDR2 SDRAM, meaning that the maximum absolute interval between any Refresh command and the next Refresh command is 9 * tREFI. T0 T1 T2 T3 Tm Tn Tn + 1 CK/CK High CKE CMD Precharge NOP > = tRFC > = tRFC > = tRP NOP REF REF NOP ANY 2.8.2 Self Refresh Operation The Self Refresh command can be used to retain data in the DDR2 SDRAM, even if the rest of the system is powered down. When in the Self Refresh mod, the DDR2 SDRAM retains data without external clocking. The DDR2 SDRAM device has a built-in timer to accommodate Self Refresh operation. The Self Refresh Command is defined by having CS, RAS, CAS and CKE held low with WE high at the rising edge of the clock. ODT must be turned off before issuing Self Refresh command, by either driving ODT pin low or using EMRS command. Once the Command is registered, CKE must be held low to keep the device in Self Refresh mode. The DLL is automatically disabled upon entering Self Refresh and is automatically enabled upon existing Self Refresh. When the DDR2 SDRAM has entered Self Refresh mode all of the external signals except CKE, are "don't care". The DRAM initiates a minimum of one Auto Refresh command internally within tCKE period once it enters Self Refresh mode.The clock is internally disabled during Self Refresh Operation to save power. The minimum time that the DDR2 SDRAM must remain in Self Refresh mode is tCKE. The user may change the external clock frequency or halt the external clock one clock after Self-Refresh entry is registered, however, the clock must be restarted and stable before the device can exit Self Refresh operation. Rev. 1.2/Aug. 2008 45 1HY5PS561621BFP The procedure for existing Self Refresh requires a sequence of commands. First, the clock must be stable prior to CKE going back HIGH. Once Self Refresh Exit command is registered, a delay equal or longer than the tXSNR or tXSRD must be satisfied before a valid command can be issued to the device. CKE must remain high for the entire Self Refresh exit period tXSRD for proper operation. Upon exit from Self Refresh, the DDR2 SDRAM can be put back into Self Refresh mode after tXSRD expires.NOP or deselect commands must be registered on each positive clock edge during the Self Refresh exit interval. ODT should also be turned off during tXSRD. The Use of Self Refresh mode introduce the possibility that an internally timed refresh event can be missed when CKE is raised for exit from Self Refresh mode. Upon exit from Self Refresh, the DDR2 SDRAM requires a minimum of one extra auto refresh command before it is put back into Self Refresh mode. T0 T1 T2 T3 T4 T5 T6 Tm Tn tCK tCH tCL CK CK > = tXSNR tRP* > = tXSRD CKE tIS tIS tAOFD ODT tIS tIS tIH CMD Self Refresh NOP NOP NOP Valid - Device must be in the "All banks idle" state prior to entering Self Refresh mode. - ODT must be turned off tAOFD before entering Self Refresh mode, and can be turned on again when tXSRD timing is satisfied. - tXSRD is applied for a Read or a Read with autoprecharge command - tXSNR is applied for any command except a Read or a Read with autoprecharge command. Rev. 1.2/Aug. 2008 46 1HY5PS561621BFP 2.9 Power-Down Power-down is synchronously entered when CKE is registered low (along with Nop or Deselect command). CKE is not allowed to go low while mode register or extended mode register command time, or read or write operation is in progress. CKE is allowed to go low while any of other operations such as row activation, precharge or autoprecharge, or auto-refresh is in progress, but power-down IDD spec will not be applied until finishing those operations. Timing diagrams are shown in the following pages with details for entry into power down. The DLL should be in a locked state when power-down is entered. Otherwise DLL should be reset after exiting power-down mode for proper read operation. If power-down occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs when there is a row active in any bank, this mode is referred to as active power-down. Entering powerdown deactivates the input and output buffers, excluding CK, CK, ODT and CKE. Also the DLL is disabled upon entering precharge power-down or slow exit active power-down, but the DLL is kept enabled during fast exit active power-down. In power-down mode, CKE low and a stable clock signal must be maintained at the inputs of the DDR2 SDRAM, and ODT should be in a valid state but all other input signals are "Don't Care". CKE low must be maintained until tCKE has been satisfied. Power-down duration is limited by 9 times tREFI of the device. The power-down state is synchronously exited when CKE is registered high (along with a Nop or Deselect command). CKE high must be maintained until tCKE has been satisfied. A valid, executable command can be applied with power-down exit latency, tXP, tXARD, or tXARDS, after CKE goes high. Power-down exit latency is defined at AC spec table of this data sheet. Basic Power Down Entry and Exit timing diagram CK/CK tIS tIH tIH tIS tIH tIH tIS tIS tIH CKE Command VALID NOP tCKE NOP tCKE VALID VALID tXP, tXARD, tXARDS tCKE Enter Power-Down mode Exit Power-Down mode Rev. 1.2/Aug. 2008 VALID Don't Care 47 1HY5PS561621BFP Read to power down entry T0 T1 T2 Tx Tx+1 Tx+2 Tx+3 Tx+4 Tx+5 Tx+6 Tx+7 Tx+8 Tx+9 CK CK CMD Read operation starts with a read command and CKE should be kept high until the end of burst operation. RD BL=4 CKE AL + CL DQ Q Q Q Q DQS DQS T0 CMD T1 T2 Tx Tx+1 Tx+2 Tx+3 Tx+4 Tx+5 Tx+6 Tx+7 Tx+8 Tx+9 RD CKE should be kept high until the end of burst operation. BL=8 CKE AL + CL DQ Q Q Q Q Q Q Q Q DQS DQS Read with Autoprecharge to power down entry T0 T1 T2 Tx Tx+1 Tx+2 Tx+3 Tx+4 Tx+5 Tx+6 Tx+7 Tx+8 Tx+9 CK CK CMD RDA PRE BL=4 AL + BL/2 with tRTP = 7.5ns & tRAS min satisfied CKE CKE should be kept high until the end of burst operation. AL + CL DQ Q Q Q Q DQS DQS T0 T1 T2 Tx Tx+1 Tx+2 Tx+3 Tx+4 Tx+5 Tx+6 Tx+7 Tx+8 Tx+9 Start internal precharge CMD RDA BL=8 AL + BL/2 with tRTP = 7.5ns & tRAS min satisfied PRE CKE should be kept high until the end of burst operation. CKE AL + CL DQ Q Q Q Q Q Q Q Q DQS DQS Rev. 1.2/Aug. 2008 48 1HY5PS561621BFP Write to power down entry T0 T1 Tm Tm+1 Tm+2 Tm+3 Tx Tx+1 Tx+2 Ty Ty+1 Ty+2 Ty+3 Tm+5 Tx Tx+1 Tx+2 Tx+3 Tx+4 Tx+2 Tx+3 Tx+4 Tx+5 Tx+6 Tx Tx+1 Tx+2 Tx+3 Tx+4 CK CK CMD WR BL=4 CKE WL DQ D D D D tWTR DQS DQS T0 CMD T1 Tm Tm+1 Tm+2 Tm+3 Tm+4 D D D D WR BL=8 CKE WL DQ D D D D tWTR DQS DQS Write with Autoprecharge to power down entry T0 T1 Tm Tm+1 Tm+2 Tm+3 Tx Tx+1 CK CK CMD WRA PRE BL=4 CKE WL DQ D D D D WR*1 DQS DQS T0 T1 Tm Tm+1 Tm+2 Tm+3 Tm+4 Tm+5 CK CK CMD WRA PRE BL=8 CKE DQ WL D D D D D D D D WR*1 DQS DQS * 1: WR is programmed through MRS Rev. 1.2/Aug. 2008 49 1HY5PS561621BFP Refresh command to power down entry T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 CK CK CMD REF CKE can go to low one clock after an Auto-refresh command CKE Active command to power down entry CMD ACT CKE can go to low one clock after an Active command CKE Precharge/Precharge all command to power down entry CMD PR or PRA CKE can go to low one clock after a Precharge or Precharge all command CKE MRS/EMRS command to power down entry CMD MRS or EMRS CKE tMRD Rev. 1.2/Aug. 2008 50 1HY5PS561621BFP 2. 10 Asynchronous CKE Low Event DRAM requires CKE to be maintained "HIGH" for all valid operations as defined in this data sheet. If CKE asynchronously drops "LOW" during any valid operation DRAM is not guaranteed to preserve the contents of array. If this event occurs, memory controller must satisfy DRAM timing specification tDelay before turning off the clocks. Stable clocks must exist at the input of DRAM before CKE is raised "HIGH" again. DRAM must be fully re-initialized (steps 4 thru 13) as described in initializaliation sequence. DRAM is ready for normal operation after the initialization sequence. See AC timing parametric table for tDelay specification Stable clocks tCK CK# CK tDelay CKE CKE asynchronously drops low Rev. 1.2/Aug. 2008 Clocks can be turned off after this point 51 1HY5PS561621BFP Input Clock Frequency Change during Precharge Power Down DDR2 SDRAM input clock frequency can be changed under following condition: DDR2 SDRAM is in precharged power down mode. ODT must be turned off and CKE must be at logic LOW level. A minimum of 2 clocks must be waited after CKE goes LOW before clock frequency may change. SDRAM input clock frequency is allowed to change only within minimum and maximum operating frequency specified for the particular speed grade. During input clock frequency change, ODT and CKE must be held at stable LOW levels. Once input clock frequency is changed, stable new clocks must be provided to DRAM before precharge power down may be exited and DLL must be RESET via EMRS after precharge power down exit. Depending on new clock frequency an additional MRS command may need to be issued to appropriately set the WR, CL etc.. During DLL re-lock period, ODT must remain off. After the DLL lock time, the DRAM is ready to operate with new clock frequency. Clock Frequency Change in Precharge Power Down Mode T0 T1 T2 NOP NOP T4 Tx Tx+1 Ty Ty+1 Ty+2 Ty+3 Ty+4 Tz CK CK CMD CKE NOP NOP Frequency Change Occurs here DLL RESET NOP Valid 200 Clocks ODT tRP tXP ODT is off during DLL RESET tAOFD Minmum 2 clocks required before changing frequency Rev. 1.2/Aug. 2008 Stable new clock before power down exit 52 1HY5PS561621BFP 2.11 No Operation Command The No Operation command should be used in cases when the DDR2 SDRAM is in an idle or a wait state. The purpose of the No Operation command (NOP) is to prevent the DDR2 SDRAM from registering any unwanted commands between operations. A No Operation command is registered when CS is low with RAS, CAS, and WE held high at the rising edge of the clock. A No Operation command will not terminate a previous operation that is still executing, such as a burst read or write cycle. 2.12 Deselect Command The Deselect command performs the same function as a No Operation command. Deselect command occurs when CS is brought high at the rising edge of the clock, the RAS, CAS, and WE signals become don't cares. Rev. 1.2/Aug. 2008 53 1HY5PS561621BFP 3. Truth Tables 3.1 Command truth table. CKE CS RAS CAS WE BA0 BA1 H L L L L BA H H L L L H X X X X 1 Self Refresh Entry H L L L L H X X X X 1 H X X X Self Refresh Exit L H X X X X 1,7 L H H H Function Previous Cycle Current Cycle (Extended) Mode Register Set H Refresh (REF) A15-A11 A10 A9 - A0 OP Code Notes 1,2 Single Bank Precharge H H L L H L BA X L X 1,2 Precharge all Banks H H L L H L X X H X 1 Bank Activate H H L L H H BA Write H H L H L L BA Column L Column 1,2,3, Write with Auto Precharge H H L H L L BA Column H Column 1,2,3, Read H H L H L H BA Column L Column 1,2,3 Read with Auto-Precharge H H L H L H BA Column H Column 1,2,3 No Operation H X L H H H X X X X 1 Device Deselect H X H X X X X X X X 1 H X X X Power Down Entry H L X X X X 1,4 L H H H H X X X X X X X 1,4 L H H H Power Down Exit L H Row Address 1,2 1. All DDR2 SDRAM commands are defined by states of CS, RAS, CAS , WE and CKE at the rising edge of the clock. 2. Bank addesses BA0, BA1(BA) determine which bank is to be operated upon. For (E)MRS BA selects an (Extended) Mode Register. 3. Burst reads or writes at BL=4 cannot be terminated or interrupted. See sections "Reads interrupted by a Read" and "Writes interrupted by a Write" in section 2.2.4 for details. 4. The Power Down Mode does not perform any refresh operations. The duration of Power Down is therefore limited by the refresh requirements outlined in section 2.2.7. 5. The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh. See section 2.2.2.4. 6. "X" means "H or L (but a defined logic level)". 7. Self refresh exit is asynchronous. Rev. 1.2/Aug. 2008 54 1HY5PS561621BFP 3.2 Clock Enable (CKE) Truth Table for Synchronous Transitions CKE Current State 2 Previous Cycle (N-1) 1 Command (N) 3 Current Cycle (N) 1 Action (N) 3 Notes RAS, CAS, WE, CS L L X Maintain Power-Down 11, 13, 15 L H DESELECT or NOP Power Down Exit 4, 8, 11,13 L L X Maintain Self Refresh 11, 15 L H DESELECT or NOP Self Refresh Exit 4, 5,9 H L DESELECT or NOP Active Power Down Entry 4,8,10,11,13 H L DESELECT or NOP Precharge Power Down Entry 4, 8, 10,11,13 H L REFRESH Self Refresh Entry 6, 9, 11,13 H H Power Down Self Refresh Bank(s) Active All Banks Idle Refer to the Command Truth Table 7 Notes: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. CKE (N) is the logic state of CKE at clock edge N; CKE (N-1) was the state of CKE at the previous clock edge. Current state is the state of the DDR SDRAM immediately prior to clock edge N. COMMAND (N) is the command registered at clock edge N, and ACTION (N) is a result of COMMAND (N). All states and sequences not shown are illegal or reserved unless explicitely described elsewhere in this document. On Self Refresh Exit DESELECT or NOP commands must be issued on every clock edge occurring during the tXSNR period. Read commands may be issued only after tXSRD (200 clocks) is satisfied. Self Refresh mode can only be entered from the All Banks Idle state. Must be a legal command as defined in the Command Truth Table. Valid commands for Power Down Entry and Exit are NOP and DESELECT only. Valid commands for Self Refresh Exit are NOP and DESELECT only. Power Down and Self Refresh can not be entered while Read or Write operations, (Extended) Mode Register Set operations or Precharge operations are in progress. See section 2.2.9 "Power Down" and 2.2.8 "Self Refresh Command" for a detailed list of restrictions. Minimum CKE high time is three clocks.; minimum CKE low time is three clocks. The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh. See section 2.2.2.4. The Power Down does not perform any refresh operations. The duration of Power Down Mode is therefore limited by the refresh requirements outlined in section 2.2.7. CKE must be maintained high while the SDRAM is in OCD calibration mode . "X" means "don't care (including floating around VREF)" in Self Refresh and Power Down. However ODT must be driven high or low in Power Down if the ODT fucntion is enabled (Bit A2 or A6 set to "1" in EMRS(1) ). 3.3 Data Mask Truth Table Name (Functional) DM DQs Note Write enable L Valid 1 Write inhibit H X 1 1. Used to mask write data, provided coinsident with the corresponding data Rev. 1.2/Aug. 2008 55 1HY5PS561621BFP 4. Operating Conditions 4.1 Absolute Maximum DC Ratings Symbol Rating Units Notes Voltage on VDD pin relative to Vss - 1.0 V ~ 2.3 V V 1 VDDQ Voltage on VDDQ pin relative to Vss - 0.5 V ~ 2.3 V V 1 VDDL Voltage on VDDL pin relative to Vss - 0.5 V ~ 2.3 V V 1 Voltage on any pin relative to Vss - 0.5 V ~ 2.3 V V 1 -55 to +100 C 1 Input leakage current; any input 0V VIN VDD; all other balls not under test = 0V) -2 uA ~ 2 uA uA Output leakage current; 0V VOUT VDDQ; DQ and ODT disabled -5 uA ~ 5 uA VDD VIN, VOUT TSTG Storage Temperature II IOZ 1. Parameter Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 4.2 Operating Temperature Condition Symbol Toper Parameter Operating Temperature Rating Units Notes 0 to 85 C 1,2 1. Operating Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard. 2. The operatin temperature range are the temperature where all DRAM specification will be supported. Outside of this temperature rang, even it is still within the limit of stress condition, some deviation on portion of operation specification may be required. During operation, the DRAM case temperature must be maintained between 0 ~ 85C under all other specification parameters. However, in some applications, it is desirable to operate the DRAM up to 95C case temperature. Therefore 2 spec options may exist. 1) Supporting 0 - 85C with full JEDEC AC & DC specifications. This is the minimum requirements for all oprating temperature options. 2) Supporting 0 - 85C and being able to extend to 95C with doubling auto-refresh commands in frequency to a 32 ms period(tRFI=3.9). Note; Self-refresh period within the above DRAM is hard coded at 64ms(tREFI= 7.8). Therfore, it is imperative that the system ensures the DRAM is at or below 85C case temperature before initiating self-refresh operation. 4.3 Thermal Characteristics PARAMETER Description Value UNIT NOTES TC Case Temperature 115.0 C 7 TJ Junction Temperature 125.1 C 7 Theta_JA Thermal resistance junction to ambient 62.6 C/W 1,2,3,4,5,7 Theta_JC Thermal resistance junction to case 16.7 C/W 1,2,6,7 1. Measurement procedures for each parameter must follow standard procedures defined in the current JEDEC JESD-51 standared. 2. Theta_JA and Theta_JC must be measured with the high effective thermal conductivity test board defined in JESD51-7 3. Airflow information must be deocumented for Theta_JA. 4. Theta_JA should only be used for comparing the thermal performance of signle packages and not for system related junction. 5. Theta_JA is the natural convection junction-to-ambient air thermal resistance measured in one cubic foot sealed enclosure as described in JESD-51. The environment is sometimes referred to as "still-air" although natural convection causes the air to move. 6. Theta_JC case surface is defined as the "outside surface of the package (case) closest to the chip mounting area when that same surface is properly hear sunk" so as to minimize temperature variation across that surface. 7. Test condition : Voltage 2.1V(Maximum voltage) / Frequency : 500Mhz Rev. 1.2/Aug. 2008 56 1HY5PS561621BFP 5. AC & DC Operating Conditons 5.1 DC Operation Conditions 5.1.1 Recommended DC Operating Conditions (SSTL_1.8) Rating Symbol Parameter Min. Typ. Max. Units Notes VDD Supply Voltage 1.9 2.0 2.1 V 5 VDDL Supply Voltage for DLL 1.9 2.0 2.1 V 4, 5 VDD Supply Voltage 1.7 1.8 2.1 V 6 VDDL Supply Voltage for DLL 1.7 1.8 2.1 V 4, 6 VDDQ Supply Voltage for Output 1.9 2.0 2.1 V 4, 5 VDDQ Supply Voltage for Output 1.7 1.8 2.1 V 4, 6 VREF Input Reference Voltage 0.49*VDDQ 0.50*VDDQ 0.51*VDDQ mV 1, 2 Termination Voltage VREF-0.04 VREF VREF+0.04 V 3 VTT There is no specific device VDD supply voltage requirement for SSTL-1.8 compliance. However under all conditions VDDQ must be less than or equal to VDD. 1. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the value of VREF is expected to be about 0.5 x VDDQ of the transmitting device and VREF is expected to track variations in VDDQ. 2. Peak to peak ac noise on VREF may not exceed +/-2% VREF (dc). 3. VTT of transmitting device must track VREF of receiving device. 4. VDDQ tracks with VDD, VDDL tracks with VDD. AC parameters are measured with VDD, VDDQ and VDDL tied together 5. 600/500Mhz support 6. 500/450/400/350Mhz support 5.1.2 ODT DC electrical characteristics PARAMETER/CONDITION Rtt effective impedance value for EMRS(A6,A2)=0,1; 75 ohm Rtt effective impedance value for EMRS(A6,A2)=1,0; 150 ohm Rtt effective impedance value for EMRS(A6, A12)=1,1 ; 50ohm Deviation of VM with respect to VDDQ/2 SYMBOL MIN NOM MAX UNITS NOTES Rtt1(eff) Rtt2(eff) Rtt3(eff) delta VM 60 120 40 -6 75 150 50 90 180 60 6 ohm ohm ohm % 1 1 1 1 Note 1: Test condition for Rtt measurements Measurement Definition for Rtt(eff): Apply VIH (ac) and VIL (ac) to test pin separately, then measure current I(VIH (ac)) and I( VIL (ac)) respectively. VIH (ac), VIL (ac), and VDDQ values defined in SSTL_18 VIH (ac) - VIL (ac) Rtt(eff) = I(VIH (ac)) - I(VIL (ac)) Measurement Definition for VM : Measurement Voltage at test pin(mid point) with no load. 2 x Vm delta VM = Rev. 1.2/Aug. 2008 VDDQ -1 x 100% 57 1HY5PS561621BFP 5.2 DC & AC Logic Input Levels 5.2.1 Input DC Logic Level Symbol Parameter Min. Max. Units VIH(dc) dc input logic high VREF + 0.125 + 0.3 V VIL(dc) dc input logic low - 0.3 VREF - 0.125 V Notes 5.2.2 Input AC Logic Level Symbol Parameter Min. Max. Units Notes VIH (ac) ac input logic high VREF + 0.250 - V 1 VIL (ac) ac input logic low - VREF - 0.250 V 1 VIH (ac) ac input logic high VREF + 0.350 - V 2 VIL (ac) ac input logic low - VREF - 0.350 V 2 Notes : 1. Supports 500/450/400/350MHz at 1.8V 2. Supports 600/500MHz at 2.0V 5.2.3 AC Input Test Conditions Symbol Condition Value Units Notes VREF Input reference voltage 0.5 * VDDQ V 1 VSWING(MAX) Input signal maximum peak to peak swing 1.0 V 1 SLEW Input signal minimum slew rate 1.0 V/ns 2, 3 Notes: 1. Input waveform timing is referenced to the input signal crossing through the VREF level applied to the device under test. 2. The input signal minimum slew rate is to be maintained over the range from VREF to VIH(ac) min for rising edges and the range from VREF to VIL(ac) max for falling edges as shown in the below figure. 3. AC timings are referenced with input waveforms switching from VIL(ac) to VIH(ac) on the positive transitions and VIH(ac) to VIL(ac) on the negative transitions. VDDQ VIH(ac) min VIH(dc) min VREF VIL(dc) max VIL(ac) max VSS VSWING(MAX) delta TF Falling Slew = delta TR VREF - VIL(ac) max Rising Slew = delta TF VIH(ac) min - VREF delta TR < Figure : AC Input Test Signal Waveform > Rev. 1.2/Aug. 2008 58 1HY5PS561621BFP 5.2.4 Differential Input AC logic Level Symbol Parameter VID (ac) ac differential input voltage VIX (ac) ac differential cross point voltage Min. Max. Units Notes 0.5 VDDQ + 0.6 V 1 0.5 * VDDQ - 0.175 0.5 * VDDQ + 0.175 V 2 1. VIN(DC) specifies the allowable DC execution of each input of differential pair such as CK, CK, DQS, DQS, LDQS, LDQS, UDQS and UDQS. 2. VID(DC) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input (such as CK, DQS, LDQS or UDQS) level and VCP is the complementary input (such as CK, DQS, LDQS or UDQS) level. The minimum value is equal to VIH(DC) - V IL(DC). VDDQ VTR Crossing point VID VIX or VOX VCP VSSQ < Differential signal levels > Notes: 1. VID(AC) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input signal (such as CK, DQS, LDQS or UDQS) and VCP is the complementary input signal (such as CK, DQS, LDQS or UDQS). The minimum value is equal to V IH(AC) - V IL(AC). 2. The typical value of VIX(AC) is expected to be about 0.5 * VDDQ of the transmitting device and VIX(AC) is expected to track variations in VDDQ . VIX(AC) indicates the voltage at whitch differential input signals must cross. 5.2.5 Differential AC output parameters Symbol VOX (ac) Parameter ac differential cross point voltage Min. Max. Units Notes 0.5 * VDDQ - 0.125 0.5 * VDDQ + 0.125 V 1 Notes: 1. The typical value of VOX(AC) is expected to be about 0.5 * V DDQ of the transmitting device and VOX(AC) is expected to track variations in VDDQ . VOX(AC) indicates the voltage at whitch differential output signals must cross. Rev. 1.2/Aug. 2008 59 1HY5PS561621BFP 5.2.6 Overshoot/Undershoot Specification AC Overshoot/Undershoot Specification for Address and Control Pins A0-A15, BA0-BA1, CS, RAS, CAS, WE, CKE, ODT Parameter Specification Maximum peak amplitude allowed for overshoot area (See Figure 1): 0.9V Maximum peak amplitude allowed for undershoot area (See Figure 1): 0.9V Maximum overshoot area above VDD (See Figure1). 0.45 V-ns Maximum undershoot area below VSS (See Figure 1). 0.45 V-ns Maximum Amplitude Overshoot Area Volts (V) VDD VSS Undershoot Area Maximum Amplitude Time (ns) Figure 1: AC Overshoot and Undershoot Definition for Address and Control Pins AC Overshoot/Undershoot Specification for Clock, Data, Strobe, and Mask Pins DQ, DQS, DM, CK, CK Parameter Specification Maximum peak amplitude allowed for overshoot area (See Figure 2): Maximum peak amplitude allowed for undershoot area (See Figure 2): 0.9V 0.9V Maximum overshoot area above VDDQ (See Figure 2). 0.23 V-ns Maximum undershoot area below VSSQ (See Figure 2). 0.23 V-ns Maximum Amplitude Overshoot Area Volts (V) VDDQ VSSQ Undershoot Area Maximum Amplitude Time (ns) Figure 2: AC Overshoot and Undershoot Definition for Clock, Data, Strobe, and Mask Pins Rev. 1.2/Aug. 2008 60 1HY5PS561621BFP Power and ground clamps are required on the following input only pins: 1. BA0-BA1 2. A0-A15 3. RAS 4. CAS 5. WE 6. CS 7. ODT 8. CKE V-I Characteristics table for input only pins with clamps Minimum Ground Voltage across clamp(V) Minimum Power Clamp Current (mA) Clamp Current (mA) 0.0 0 0 0.1 0 0 0.2 0 0 0.3 0 0 0.4 0 0 0.5 0 0 0.6 0 0 0.7 0 0 0.8 0.1 0.1 0.9 1.0 1.0 1.0 2.5 2.5 1.1 4.7 4.7 1.2 6.8 6.8 1.3 9.1 9.1 1.4 11.0 11.0 1.5 13.5 13.5 1.6 16.0 16.0 1.7 18.2 18.2 1.8 21.0 21.0 Rev. 1.2/Aug. 2008 61 1HY5PS561621BFP 5.3 Output Buffer Levels 5.3.1 Output AC Test Conditions Symbol Parameter SSTL_18 Class II Units Notes VOH Minimum Required Output Pull-up under AC Test Load VTT + 0.603 V VOL Maximum Required Output Pull-down under AC Test Load VTT - 0.603 V VOTR Output Timing Measurement Reference Level 0.5 * VDDQ V SSTl_18 Class II Units Notes - 13.4 mA 1, 3, 4 13.4 mA 2, 3, 4 1 1. The VDDQ of the device under test is referenced. 5.3.2 Output DC Current Drive Symbol 1. 2. 3. 4. Parameter IOH(dc) Output Minimum Source DC Current IOL(dc) Output Minimum Sink DC Current VDDQ = 1.7 V; VOUT = 1420 mV. (VOUT - VDDQ)/IOH must be less than 21 ohm for values of VOUT between VDDQ and VDDQ - 280 mV. VDDQ = 1.7 V; VOUT = 280 mV. VOUT/IOL must be less than 21 ohm for values of VOUT between 0 V and 280 mV. The dc value of VREF applied to the receiving device is set to VTT The values of IOH(dc) and IOL(dc) are based on the conditions given in Notes 1 and 2. They are used to test device drive current capability to ensure VIH min plus a noise margin and VIL max minus a noise margin are delivered to an SSTL_18 receiver. The actual current values are derived by shifting the desired driver operating point (see Section 3.3) along a 21 ohm load line to define a convenient driver current for measurement. 5.3.3 OCD defalut characteristics Description Min Nom Max Unit Output impedance 12.6 18 23.4 ohms 1,2 Pull-up and pull-down mismatch 0 4 ohms 1,2,3 5 V/ns 1,4,5,6,7 Output slew rate Parameter Sout 1.5 - Notes Note 1: Absolute Specifications (0C TCASE +95C; VDD = +1.8V 0.1V, VDDQ = +1.8V 0.1V) 2: Impedance measurement condition for output source dc current: VDDQ = 1.7V; VOUT = 1420mV; (VOUT-VDDQ)/Ioh must be less than 23.4 ohms for values of VOUT between VDDQ and VDDQ280mV. Impedance measurement condition for output sink dc current: VDDQ = 1.7V; VOUT = 280mV; VOUT/Iol must be less than 23.4 ohms for values of VOUT between 0V and 280mV. 3: Mismatch is absolute value between pull-up and pull-dn, both are measured at same temperature and voltage. 4: Slew rate measured from vil(ac) to vih(ac). 5: The absolute value of the slew rate as measured from DC to DC is equal to or greater than the slew rate as measured from AC to AC. This is guaranteed by design and characterization. 6: DRAM output slew rate specification Table. Rev. 1.2/Aug. 2008 62 1HY5PS561621BFP 5.4 Default Output V-I characteristics DDR2 SDRAM output driver characteristics are defined for full strength default operation as selected by the EMRS1 bits A7-A9 = `111'. The above Figures show the driver characteristics graphically, and tables show the same data in tabular format suitable for input into simulation tools. 5.4.1 Full Strength Default Pulldown Driver Characteristics Pulldow n Current (mA) Voltage (V) Minimum (23.4 Ohms) 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 8.5 12.1 14.7 16.4 17.8 18.6 19.0 19.3 19.7 19.9 20.0 20.1 20.2 20.3 20.4 20.6 Nominal Default Low (18 ohms) Nominal Default High (18 ohms) 11.3 16.5 21.2 25.0 28.3 30.9 33.0 34.5 35.5 36.1 36.6 36.9 37.1 37.4 37.6 37.7 37.9 11.8 16.8 22.1 27.6 32.4 36.9 40.9 44.6 47.7 50.4 52.6 54.2 55.9 57.1 58.4 59.6 Maximum (12.6 Ohms) 60.9 15.9 23.8 31.8 39.7 47.7 55.0 62.3 69.4 75.3 80.5 84.6 87.7 90.8 92.9 94.9 97.0 99.1 101.1 120 Pulldown current (mA) 100 Maximum 80 Nominal Default High 60 Nominal Default Low 40 20 Minimum 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 VOUT to VSSQ (V) Rev. 1.2/Aug. 2008 63 1HY5PS561621BFP 5.4.2 Full Strength Default Pullup Driver Characteristics Pullup Current (mA) Voltage (V) Minimum (23.4 Ohms) 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 -8.5 -12.1 -14.7 -16.4 -17.8 -18.6 -19.0 -19.3 -19.7 -19.9 -20.0 -20.1 -20.2 -20.3 -20.4 -20.6 Nominal Default Low (18 ohms) Nominal Default High (18 ohms) -11.1 -16.0 -20.3 -24.0 -27.2 -29.8 -31.9 -33.4 -34.6 -35.5 -36.2 -36.8 -37.2 -37.7 -38.0 -38.4 -38.6 -11.8 -17.0 -22.2 -27.5 -32.4 -36.9 -40.8 -44.5 -47.7 -50.4 -52.5 -54.2 -55.9 -57.1 -58.4 -59.6 -60.8 Maximum (12.6 Ohms) -15.9 -23.8 -31.8 -39.7 -47.7 -55.0 -62.3 -69.4 -75.3 -80.5 -84.6 -87.7 -90.8 -92.9 -94.9 -97.0 -99.1 -101.1 DDR2 Default Pullup Characteristics for Full Strength Output Driver 0 Pullup current (mA) -20 Minimum -40 Nominal Default Low -60 Nominal Default High -80 -100 Maximum -120 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 VDDQ to VOUT (V) Rev. 1.2/Aug. 2008 64 1HY5PS561621BFP 5.4.3 Calibrated Output Driver V-I Characteristics DDR2 SDRAM output driver characteristics are defined for full strength calibrated operation as selected by the procedure in OCD impedance adjustment. The below Tables show the data in tabular format suitable for input into simulation tools. The nominal points represent a device at exactly 18 ohms. The nominal low and nominal high values represent the range that can be achieved with a maximum 1.5 ohm step size with no calibration error at the exact nominal conditions only (i.e. perfect calibration procedure, 1.5 ohm maximum step size guaranteed by specification). Real system calibration error needs to be added to these values. It must be understood that these V-I curves as represented here or in supplier IBIS models need to be adjusted to a wider range as a result of any system calibration error. Since this is a system specific phenomena, it cannot be quantified here. The values in the calibrated tables represent just the DRAM portion of uncertainty while looking at one DQ only. If the calibration procedure is used, it is possible to cause the device to operate outside the bounds of the default device characteristics tables and figures. In such a situation, the timing parameters in the specification cannot be guaranteed. It is solely up to the system application to ensure that the device is calibrated between the minimum and maximum default values at all times. If this can't be guaranteed by the system calibration procedure, re-calibration policy, and uncertainty with DQ to DQ variation, then it is recommended that only the default values be used. The nominal maximum and minimum values represent the change in impedance from nominal low and high as a result of voltage and temperature change from the nominal condition to the maximum and minimum conditions. If calibrated at an extreme condition, the amount of variation could be as much as from the nominal minimum to the nominal maximum or vice versa. The driver characteristics evaluation conditions are: Nominal 25 oC (T case), VDDQ = 1.8 V, typical process Nominal Low and Nominal High 25 oC (T case), VDDQ = 1.8 V, any process Nominal Minimum TBD oC (T case), VDDQ = 1.7 V, any process Nominal Maximum 0 oC (T case), VDDQ = 1.9 V, any process Full Strength Calibrated Pulldown Driver Characteristics Calibrated Pulldow n Current (mA) Voltage (V) Nominal Minimum Nominal Low (18.75 Nominal (18 ohms) (21 ohms) ohms) 0.2 0.3 0.4 9.5 14.3 18.7 10.7 16.0 21.0 Nominal High (17.25 Nominal Maximum (15 ohms) ohms) 11.5 16.6 21.6 11.8 17.4 23.0 13.3 20.0 27.0 Full Strength Calibrated Pullup Driver Characteristics Calibrated Pullup Current (mA) Voltage (V) 0.2 0.3 0.4 Rev. 1.2/Aug. 2008 Nominal Minimum Nominal Low (18.75 Nominal High (17.25 Nominal Maximum (15 Nominal (18 ohms) (21 ohms) ohms) ohms) ohms) -9.5 -14.3 -18.7 -10.7 -16.0 -21.0 -11.4 -16.5 -21.2 -11.8 -17.4 -23.0 -13.3 -20.0 -27.0 65 1HY5PS561621BFP 5.5 Input/Output Capacitance 300MHz / 400MHz Parameter Symbol Units Min Max 1.0 2.0 pF x 0.25 pF 1.0 2.0 pF Input capacitance, CK and CK CCK Input capacitance delta, CK and CK CDCK Input capacitance, all other input-only pins CI Input capacitance delta, all other input-only pins CDI x 0.25 pF Input/output capacitance, DQ, DM, DQS, DQS CIO 2.5 3.5 pF Input/output capacitance delta, DQ, DM, DQS, DQS CDIO x 0.5 pF Rev. 1.2/Aug. 2008 66 1HY5PS561621BFP 6. IDD Specifications & Measurement Conditions 6.1 IDD Specifications Symbol 16 2 22 25 28 Units IDD0 115 110 105 100 95 mA IDD1 125 120 115 110 105 mA IDD2P 8 8 8 8 8 mA IDD2N 60 55 53 50 45 mA F 40 35 33 30 25 mA S 25 25 25 25 25 mA IDD3N 80 70 65 60 55 mA IDD4W 300 250 225 200 175 mA IDD4R 275 250 225 200 175 mA IDD5 135 130 128 125 123 mA IDD6 8 8 8 8 8 mA IDD7 300 260 240 220 210 mA IDD3P Rev. 1.2/Aug. 2008 67 1HY5PS561621BFP 6.2 IDD Meauarement Conditions Symbol Conditions Units IDD0 Operating one bank active-precharge current; tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRASmin(IDD);CKE is HIGH, CS is HIGH between valid commands;Address bus inputs are SWITCHING;Data bus inputs are SWITCHING mA IDD1 Operating one bank active-read-precharge curren ; IOUT = 0mA;BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRC = tRC (IDD), tRAS = tRASmin(IDD), tRCD = tRCD(IDD) ; CKE is HIGH, CS is HIGH between valid commands ; Address bus inputs are SWITCHING ; Data pattern is same as IDD4W mA IDD2P Precharge power-down current ; All banks idle ; tCK = tCK(IDD) ; CKE is LOW ; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING mA IDD2N Precharge standby current; All banks idle; tCK = tCK(IDD); CKE is HIGH, CS is HIGH; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING mA IDD3P Active power-down current; All banks open; tCK = tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Fast PDN Exit MRS(12) = 0 mA Slow PDN Exit MRS(12) = 1 mA IDD3N Active standby current; All banks open; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP =tRP(IDD); CKE is HIGH, CS is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING mA IDD4W Operating burst write current; All banks open, Continuous burst writes; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING mA IDD4R Operating burst read current; All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are SWITCHING;; Data pattern is same as IDD4W mA IDD5B Burst refresh current; tCK = tCK(IDD); Refresh command at every tRFC(IDD) interval; CKE is HIGH, CS is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING mA IDD6 Self refresh current; CK and CK at 0V; CKE 0.2V; Other control and address bus inputs are FLOATING; Data bus inputs are FLOATING mA IDD7 Operating bank interleave read current; All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = tRCD(IDD)-1*tCK(IDD); tCK = tCK(IDD), tRC = tRC(IDD), tRRD = tRRD(IDD), tRCD = 1*tCK(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are STABLE during DESELECTs; Data pattern is same as IDD4R; - Refer to the following page for detailed timing conditions mA Note: 1. IDD specifications are tested after the device is properly initialized 2. Input slew rate is specified by AC Parametric Test Condition 3. IDD parameters are specified with ODT disabled. 4. Data bus consists of DQ, DM, DQS, DQS, RDQS, RDQS, LDQS, LDQS, UDQS, and UDQS. IDD values must be met with all combinations of EMRS bits 10 and 11. 5. Definitions for IDD LOW is defined as Vin VILAC(max) HIGH is defined as Vin VIHAC(min) STABLE is defined as inputs stable at a HIGH or LOW level FLOATING is defined as inputs at VREF = VDDQ/2 SWITCHING is defined as: inputs changing between HIGH and LOW every other clock cycle (once per two clocks) for address and control signals, and inputs changing between HIGH and LOW every other data transfer (once per clock) for DQ signals not including masks or strobes. Rev. 1.2/Aug. 2008 68 1HY5PS561621BFP For purposes of IDD testing, the following parameters are to be utilized Parameter 16 2(L) 22 25 28 Unit CL(IDD) 7 7 6 6 5 tCK tRCD(IDD) 16 16 15.4 15 16.8 ns tRC(IDD) 60 60 61.6 60 61.6 ns tRRD(IDD)-x16 8 8 8.8 7.5 8.4 ns tCK(IDD) 1.6 2 2.2 2.5 2.8 ns tRASmin(IDD) 44.8 44 46.2 45 44.8 ns tRASmax(IDD) 70K 70K 70K 70K 70K ns tRP(IDD) 16 16 15.4 15 16.8 ns tRFC(IDD)-256Mb 75 75 75 75 75 ns Detailed IDD7 The detailed timings are shown below for IDD7. Changes will be required if timing parameter changes are made to the specification. Legend: A = Active; RA = Read with Autoprecharge; D = Deselect IDD7: Operating Current: All Bank Interleave Read operation All banks are being interleaved at minimum tRC(IDD) without violating tRRD(IDD) using a burst length of 4. Control and address bus inputs are STABLE during DESELECTs. IOUT = 0mA Rev. 1.2/Aug. 2008 69 1HY5PS561621BFP 7. AC Timing Specifications 7.1 Timing Parameters by Speed Grade 16 Symbol Parameter DQ output access time from CK/CK DQS output access time from CK/CK 2(L) 22 Unit Note min max min max min max tAC -250 +250 -300 +300 -350 +350 ps tDQSCK -200 +200 -250 +250 -300 +300 ps CK high-level width tCH 0.45 0.55 0.45 0.55 0.45 0.55 tCK CK low-level width tCL 0.45 0.55 0.45 0.55 0.45 0.55 tCK tHP min (tCL,tCH) - min (tCL,tCH) - min (tCL,tCH) - ps 11,12 CL=7 tCK 1.6 8 2 8 - - ns 15 CL=6 tCK - - - - 2.2 8 ns 15 DQ and DM input hold time tDH 125 - 125 - 125 - ps 6,7,8 DQ and DM input setup time tDS 50 - 50 - 50 - ps 6,7,8 Control & Address input pulse width for each input tIPW 0.6 - 0.6 - 0.6 - tCK tDIPW 0.35 - 0.35 - 0.35 - tCK tHZ - tAC max - tAC max - tAC max ps tAC min tAC max tAC min tAC max tAC min tAC max ps 2*tAC min tAC max ps CK half period Clock cycle time DQ and DM input pulse width for each input Data-out high-impedance time from CK/CK DQS low-impedance time from CK/CK tLZ(DQS) DQ low-impedance time from CK/CK tLZ(DQ) DQS-DQ skew for DQS and associated DQ signals tDQSQ - 200 - 200 tQHS - 300 - DQ hold skew factor 2*tAC min tAC max - tHP - tQHS - 200 ps 13 300 - 300 ps 12 - tHP tQHS - ps DQ/DQS output hold time from DQS tQH Write command to first DQS latching transition tDQSS DQS input high pulse width tDQSH 0.35 - 0.35 - 0.35 - tCK DQS input low pulse width tDQSL 0.35 - 0.35 - 0.35 - tCK tDSS 0.2 - 0.2 - 0.2 - tCK DQS falling edge hold time from CK tDSH 0.2 - 0.2 - 0.2 - tCK Mode register set command cycle time tMRD 2 - 2 - 2 - tCK Write postamble tWPST 0.4 0.6 0.4 0.6 0.4 0.6 tCK Write preamble DQS falling edge to CK setup time tHP - tQHS 2*tAC min tAC max WL - 0.25 WL + 0.25 WL - 0.25 WL + 0.25 WL - 0.25 WL+0.25 tCK 10 tWPRE 0.35 - 0.35 - 0.35 - tCK Address and control input hold time tIH 300 - 300 - 350 - ps 5,7,9 Address and control input setup time tIS 300 - 300 - 350 - ps 5,7,9 Read preamble tRPRE 0.9 1.1 0.9 1.1 0.9 1.1 tCK Read postamble tRPST 0.4 0.6 0.4 0.6 0.4 0.6 tCK Active to precharge command tRAS 45 70K 45 70K 45 70K ns Active to Read or Write (with and without Auto-Precharge) delay tRCD 16 - 16 - 15.4 - ns Rev. 1.2/Aug. 2008 3 70 1HY5PS561621BFP Parameter 16 Symbol 2(L) 22 Unit Note min max min max min max tRFC 75 - 75 - 75 - ns Precharge Command Period tRP 16 - 16 - 15.4 - ns Active to Active/Auto-Refresh command period tRC 60 - 60 - 61.6 - ns Active to active command period tRRD 8 - 8 - 8.8 - CAS to CAS command delay tCCD 2 - 2 Write recovery time tWR 13 - 14 - 15 - ns Auto precharge write recovery + precharge time tDAL WR+tRP - WR+tRP - WR+tRP - tCK Internal write to read command delay tWTR 7.5 - 7.5 - 7.5 - ns Internal read to precharge command delay tRTP 7.5 - 7.5 - 7.5 - ns Exit self refresh to a non-read command tXSNR tRFC + 10 Exit self refresh to a read command tXSRD 200 - 200 - 200 - tCK tXP 2 - 2 - 2 - tCK tXARD 2 2 2 tCK 1 tXARDS 8 - AL 8 - AL 8 - AL tCK 1, 2 3 3 3 Auto-Refresh to Active/Auto-Refresh command period Exit precharge power down to any non-read command Exit active power down to read command Exit active power down to read command (Slow exit, Lower power) CKE minimum pulse width (high and low pulse width) t CKE Average periodic Refresh Interval AOND t ODT turn-on ODT turn-on(Power-Down mode) t AONPD t ODT turn-off delay AOFD t ODT turn-off ODT turn-off (Power-Down mode) AON AOF t AOFPD tRFC + 10 7.8 tREFI t ODT turn-on delay 2 tRFC + 10 7.8 2 2 2 tAC(min) tAC (max)+0.7 tAC(min) 2 2 ns 7.8 us 2 tCK 2tCK+ 2tCK+ tAC(min)+ 2tCK+tAC tAC(min)+ tAC(min)+ tAC(max)+ tAC(max)+ 2 (max)+1 2 2 1 1 ns 2.5 2.5 tCK tAC(min) tAC(max)+ 0.6 ns 4.5tCK+ 4.5tCK+ 4.5tCK+ tAC(min)+ tAC(min)+ tAC(min)+ tAC(max) tAC(max)+ tAC(max)+ 2 2 2 +1 1 1 ns 2.5 tAC(min) 2.5 2.5 tAC(min) tAC(max)+ 0.6 ODT to power down entry latency tANPD 3 3 3 tCK ODT power down exit latency tAXPD 8 8 8 tCK OCD drive mode output delay tOIT 0 tDelay tIS+tCK +tIH Minimum time clocks remains ON after CKE asynchronously drops LOW Rev. 1.2/Aug. 2008 12 0 tIS+tCK +tIH 12 0 tIS+tCK +tIH 3 tCK ns tAC(max)+ 0.6 14 ns tAC tAC tAC(min) (max)+0.7 (max)+0.7 2.5 4 tCK 12 16 17 ns ns 15 71 1HY5PS561621BFP 25 Symbol Parameter 28 Unit Note min max min max tAC -450 +450 -450 +450 ps tDQSCK -400 +400 -400 +400 ps CK high-level width tCH 0.45 0.55 0.45 0.55 tCK CK low-level width tCL 0.45 0.55 0.45 0.55 tCK CK half period tHP min (tCL,tCH) - min (tCL,tCH) - ps 11,12 CL=6 tCK 2.5 8 - - ns 15 CL=5 tCK - - 2.8 8 ns 15 CL=4 tCK - - - - ns 15 DQ and DM input hold time tDH 175 - 175 - ps 6,7,8 DQ and DM input setup time tDS 50 - 50 - ps 6,7,8 Control & Address input pulse width for each input tIPW 0.6 - 0.6 - tCK DQ and DM input pulse width for each input tDIPW 0.35 - 0.35 - tCK tHZ - tAC max - tAC max ps tLZ(DQS) tAC min tAC max tAC min tAC max ps DQ low-impedance time from CK/CK tLZ(DQ) 2*tAC min tAC max 2*tAC min tAC max ps DQS-DQ skew for DQS and associated DQ signals tDQSQ - 200 - 250 ps 13 tQHS - 350 - 350 ps 12 DQ/DQS output hold time from DQS tQH tHP - tQHS - tHP - tQHS - ps Write command to first DQS latching transition tDQSS WL - 0.25 WL + 0.25 WL - 0.25 WL + 0.25 tCK DQS input high pulse width tDQSH 0.35 - 0.35 - tCK DQS input low pulse width tDQSL 0.35 - 0.35 - tCK DQS falling edge to CK setup time tDSS 0.2 - 0.2 - tCK DQS falling edge hold time from CK tDSH 0.2 - 0.2 - tCK Mode register set command cycle time tMRD 2 - 2 - tCK Write postamble tWPST 0.4 0.6 0.4 0.6 tCK Write preamble tWPRE 0.35 - 0.35 - tCK Address and control input hold time tIH 400 - 400 - ps 5,7,9 Address and control input setup time tIS 400 - 400 - ps 5,7,9 Read preamble tRPRE 0.9 1.1 0.9 1.1 tCK Read postamble tRPST 0.4 0.6 0.4 0.6 tCK Active to precharge command tRAS 45 70K 45 70K ns Active to Read or Write (with and without Auto-Precharge) delay tRCD 16.8 - 16.8 - ns DQ output access time from CK/CK DQS output access time from CK/CK Clock cycle time Data-out high-impedance time from CK/CK DQS low-impedance time from CK/CK DQ hold skew factor Rev. 1.2/Aug. 2008 10 3 72 1HY5PS561621BFP Parameter 25 Symbol 28 Unit min max min max - 16.8 - ns Note Active to Read or Write (with and without Auto-Precharge) delay tRCD 15 Auto-Refresh to Active/Auto-Refresh command period tRFC 75 75 - ns Precharge Command Period tRP 15 16.8 - ns Active to Active/Auto-Refresh command period tRC 60 61.6 - ns Active to active command period tRRD 8 8.4 - ns CAS to CAS command delay tCCD 3 2 Write recovery time tWR 15 15 - ns Auto precharge write recovery + precharge time tDAL WR+tRP - WR+tRP - tCK Internal write to read command delay tWTR 3 - 3 - tCK Internal read to precharge command delay tRTP 3 - 3 - tCK Exit self refresh to a non-read command tXSNR tRFC + 10 Exit self refresh to a read command tXSRD 200 - 200 - tCK tXP 2 - 2 - tCK tXARD 2 2 tCK 1 tXARDS 8 - AL 7 - AL tCK 1, 2 tCKE 3 3 tCK Exit precharge power down to any non-read command Exit active power down to read command Exit active power down to read command (Slow exit, Lower power) CKE minimum pulse width (high and low pulse width) Average periodic Refresh Interval ODT turn-on delay t 7.8 us 2 2 2 tCK AON tAC(min) tAC (max)+0.7 tAC(min) tAC (max)+0.7 ns AONPD tAC(min)+2 2tCK+tAC( max)+1 ns t t 2tCK+tAC(ma tAC(min)+2 x)+1 2.5 2.5 2.5 2.5 tCK AOF tAC(min) tAC(max)+ 0.6 tAC(min) tAC(max)+ 0.6 ns tAOFPD tAC(min)+2 3.5tCK+tAC( max)+1 tAC(min)+2 3.5tCK+tAC (max)+1 ns ODT to power down entry latency tANPD 3 3 tCK ODT power down exit latency tAXPD 8 8 tCK OCD drive mode output delay tOIT 0 tDelay tIS+tCK+tIH ODT turn-off delay ODT turn-off ODT turn-off (Power-Down mode) Minimum time clocks remains ON after CKE asynchronously drops LOW Rev. 1.2/Aug. 2008 AOFD t 12 0 tIS+tCK+tIH 14 3 ns 2 ODT turn-on ODT turn-on(Power-Down mode) tCK tRFC + 10 7.8 tREFI tAOND 4 12 16 17 ns ns 15 73 1HY5PS561621BFP 7.2 General notes, which may apply for all AC parameters 1. Slew Rate Measurement Levels a. Output slew rate for falling and rising edges is measured between VTT - 250 mV and VTT + 250 mV for single ended signals. For differential signals (e.g. DQS - DQS) output slew rate is measured between DQS - DQS = -500 mV and DQS - DQS = +500mV. Output slew rate is guaranteed by design, but is not necessarily tested on each device. b. Input slew rate for single ended signals is measured from dc-level to ac-level: from VREF - 125 mV to VREF + 250 mV for rising edges and from VREF + 125 mV and VREF - 250 mV for falling edges. For differential signals (e.g. CK - CK) slew rate for rising edges is measured from CK - CK = -250 mV to (250mV to -500 mV for falling egdes). CK - CK = +500 mV c. VID is the magnitude of the difference between the input voltage on CK and the input voltage on CK, or between DQS and DQS for differential strobe. 2. DDR2 SDRAM AC timing reference load The following fiture represents the timing reference load used in defining the relevant timing parameters of the part. It is not intended to be either a precise representation of the typical system environment nor a depiction of the actual load presented by a production tester. System designers will use IBIS or other simulation tools to correlate the timing reference load to a system environment. Manufacturers will correlate to their production test conditions (generally a coaxial transmission line terminated at the tester electronics). VDDQ DUT DQ DQS DQS RDQS RDQS Output Timing reference point VTT = VDDQ/2 25 AC Timing Reference Load The output timing reference voltage level for single ended signals is the crosspoint with VTT. The output timing reference voltage level for differential signals is the crosspoint of the true (e.g. DQS) and the complement (e.g. DQS) signal. 3. DDR2 SDRAM output slew rate test load Output slew rate is characterized under the test conditions as shown below. VDDQ DUT DQ DQS, DQS RDQS, RDQS Output Test point VTT = VDDQ/2 25 Slew Rate Test Load 4. Differential data strobe DDR2 SDRAM pin timings are specified for either single ended mode or differential mode depending on the setting of the EMRS "Enable DQS" mode bit; timing advantages of differential mode are realized in system design. The method by which the DDR2 SDRAM pin timings are measured is mode dependent. In single Rev. 1.2/Aug. 2008 74 1HY5PS561621BFP VREF. In differential mode, these timing relationships are measured relative to the crosspoint of DQS and its complement, DQS. This distinction in timing methods is guaranteed by design and characterization. Note that when differential data strobe mode is disabled via the EMRS, the complementary pin, DQS, must be tied externally to VSS through a 20 ohm to 10 K ohm resistor to insure proper operation. tDQSH DQS DQS/ DQS tDQSL DQS tWPRE tWPST DQ D D tDS DM tDH tDS DMin D D DMin DMin tDH DMin Figure -- Data input (write) timing tCH tCL CK CK/CK CK DQS DQS/DQS DQS tRPRE tRPST DQ Q Q tDQSQmax Q Q tDQSQmax tQH tQH Figure -- Data output (read) timing 5. AC timings are for linear signal transitions. See System Derating for other signal transitions. 6. These parameters guarantee device behavior, but they are not necessarily tested on each device. They may be guaranteed by device design or tester correlation. 7. All voltages referenced to VSS. 8. Tests for AC timing, IDD, and electrical (AC and DC) characteristics, may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. Rev. 1.2/Aug. 2008 75 1HY5PS561621BFP 7.3 Specific Notes for dedicated AC parameters 1. User can choose which active power down exit timing to use via MRS(bit 12). tXARD is expected to be used for fast active power down exit timing. tXARDS is expected to be used for slow active power down exit timing where a lower power value is defined by each vendor data sheet. 2. AL = Additive Latency 3. This is a minimum requirement. Minimum read to precharge timing is AL + BL/2 providing the tRTP and tRAS(min) have been satisfied. 4. A minimum of two clocks (2 * tCK) is required irrespective of operating frequency 5. Timings are guaranteed with command/address input slew rate of 1.0 V/ns. See System Derating for other slew rate values. 6. Timings are guaranteed with data, mask, and (DQS/RDQS in singled ended mode) input slew rate of 1.0 V/ns. See System Derating for other slew rate values. 7. Timings are guaranteed with CK/CK differential slew rate of 2.0 V/ns. Timings are guaranteed for DQS signals with a differential slew rate of 2.0 V/ns in differential strobe mode and a slew rate of 1V/ns in single ended mode. See System Derating for other slew rate values. 8. tDS and tDH (data setup and hold) derating tbd 9. tIS and tIH (input setup and hold) derating tbd 10. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but system performance (bus turnaround) will degrade accordingly. 11. MIN ( t CL, t CH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limits for t CL and t CH). For example, t CL and t CH are = 50% of the period, less the half period jitter ( t JIT(HP)) of the clock source, and less the half period jitter due to crosstalk ( t JIT(crosstalk)) into the clock traces. 12. t QH = t HP - t QHS, where: tHP = minimum half clock period for any given cycle and is defined by clock high or clock low ( tCH, tCL). tQHS accounts for: 1) The pulse duration distortion of on-chip clock circuits; and 2) The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next transition, both of which are, separately, due to data pin skew and output pattern effects, and pchannel to n-channel variation of the output drivers. 13. tDQSQ: Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers for any given cycle. 14. t DAL = (nWR) + ( tRP/tCK): For each of the terms above, if not already an integer, round to the next highest integer. tCK refers to the Rev. 1.2/Aug. 2008 76 1HY5PS561621BFP application clock period. nWR refers to the t WR parameter stored in the MRS. 15. The clock frequency is allowed to change during self-refresh mode or precharge power-down mode. In case of clock frequency change during precharge power-down, a specific procedure is required as described in section 2.9. 16. ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when the ODT resistance is fully on. Both are measured from tAOND. 17. ODT turn off time min is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance. Both are measured from tAOFD. Rev. 1.2/Aug. 2008 77 1HY5PS561621BFP 8 Package Dimension(x16) 84Ball Fine Pitch Ball Grid Array Outline 8 +/- 0.10 13 +/- 0.10 A1 Ball Mark 2-R 0.15 MAX 0.19 30o 0.15+/-0.05 <Top View> 0.325 1.10 +/-0.10 2.10+/-0.10 R L M N P 0.50+/0.025 K A B C D E F G H J 0.80 0.8 x 14 = 11.2 0.90 0.34 +/- 0.05 A1 Ball Mark 0.80 1 2 3 1.60 1.60 7 8 9 84 - 0.50 +/- 0.05 0.80 x 8 = 6.40 <Bottom View> Note: All dimension units are Millimeters. Rev. 1.2/Aug. 2008 78