W29C011A 128K x 8 CMOS FLASH MEMORY GENERAL DESCRIPTION The W29C011A is a 1-megabit, 5-volt only CMOS flash memory organized as 128K x 8 bits. The device can be programmed and erased in-system with a standard 5V power supply. A 12-volt VPP is not required. The unique cell architecture of the W29C011A results in fast program/erase operations with extremely low current consumption (compared to other comparable 5-volt flash memory products). The device can also be programmed and erased using standard EPROM programmers. FEATURES * * Single 5-volt program and erase operations * Fast page-write operations - Active current: 25 mA (typ.) - 128 bytes per page - Standby current: 20 A (typ.) - Page program cycle: 10 mS (max.) - Effective byte-program cycle time: 39 S - Software-protected data write * Fast chip-erase operation: 50 mS * Read access time: 150 nS * Page program/erase cycles: 1,000 * Ten-year data retention * Software and hardware data protection Low power consumption * Automatic program timing with internal VPP generation * End of program detection - Toggle bit - Data polling * Latched address and data * TTL compatible I/O * JEDEC standard byte-wide pinouts * Available packages: 32-pin 600 mil DIP, 450 mil SOP and PLCC -1- Publication Release Date: January 31, 2002 Revision A3 W29C011A PIN CONFIGURATIONS BLOCK DIAGRAM NC 1 32 VDD #WE NC A16 2 31 A15 3 30 A12 4 29 #CE #OE A14 A7 5 28 A13 A6 6 27 A8 A5 7 26 A9 A4 A3 8 32-pin DIP VDD VSS 25 A11 9 24 A2 10 23 #OE A10 A1 11 22 A0 12 21 #CE DQ7 DQ0 DQ1 13 20 DQ6 14 19 DQ5 DQ2 15 18 DQ4 GND 16 17 DQ3 CONTROL OUTPUT BUFFER #WE A0 . DECODER . CORE ARRAY A16 V # A A A 1 1 1 N D W N 2 5 6 C D E C 4 3 2 PIN DESCRIPTION 1 32 31 30 A7 5 29 A14 A6 6 28 A13 A5 7 27 A8 A4 8 A3 9 A2 A1 26 A9 25 A11 10 24 11 23 #O E A10 A0 12 22 DQ0 13 21 32-pin PLCC SYMBOL A0 - A16 DQ0 - DQ7 #CE DQ7 14 15 16 17 18 19 20 D D G D D D D Q Q N Q Q Q Q 1 2 D 3 4 5 6 Address Inputs Data Inputs/Outputs #CE Chip Enable #OE Output Enable #WE Write Enable VDD Power Supply GND Ground NC -2- PIN NAME No Connection DQ0 . . DQ7 W29C011A FUNCTIONAL DESCRIPTION Read Mode The read operation of the W29C011A is controlled by #CE and #OE, both of which have to be low for the host to obtain data from the outputs. #CE is used for device selection. When #CE is high, the chip is de-selected and only standby power will be consumed. #OE is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either #CE or #OE is high. Refer to the timing waveforms for further details. Page Write Mode The W29C011A is programmed on a page basis. Every page contains 128 bytes of data. If a byte of data within a page is to be changed, data for the entire page must be loaded into the device. Any byte that is not loaded will be erased to "FFh" during programming of the page. The write operation is initiated by forcing #CE and #WE low and #OE high. The write procedure consists of two steps. Step 1 is the byte-load cycle, in which the host writes to the page buffer of the device. Step 2 is an internal programming cycle, during which the data in the page buffers are simultaneously written into the memory array for non-volatile storage. During the byte-load cycle, the addresses are latched by the falling edge of either #CE or #WE, whichever occurs last. The data are latched by the rising edge of either #CE or #WE, whichever occurs first. If the host loads a second byte into the page buffer within a byte-load cycle time (TBLC) of 200 S, after the initial byte-load cycle, the W29C011A will stay in the page load cycle. Additional bytes can then be loaded consecutively. The page load cycle will be terminated and the internal programming cycle will start if no additional byte is loaded into the page buffer within 300 S (TBLCO) from the last byte-load cycle, i.e., there is no subsequent #WE high-to-low transition after the last rising edge of #WE. A7 to A16 specify the page address. All bytes that are loaded into the page buffer must have the same page address. A0 to A6 specify the byte address within the page. The bytes may be loaded in any order; sequential loading is not required. In the internal programming cycle, all data in the page buffers, i.e., 128 bytes of data, are written simultaneously into the memory array. Before the completion of the internal programming cycle, the host is free to perform other tasks such as fetching data from other locations in the system to prepare to write the next page. Software-protected Data Write The device provides a JEDEC-approved software-protected data write. Once this scheme is enabled, any write operation requires a series of three-byte program commands (with specific data to a specific address) to be performed before the data load operation. The three-byte load command sequence begins the page load cycle, without which the write operation will not be activated. This write scheme provides optimal protection against inadvertent write cycles, such as cycles triggered by noise during system power-up and power-down. The W29C011A is shipped with the software data protection enabled. To enable the software data protection scheme, perform the three-byte command cycle at the beginning of a page load cycle. The device will then enter the software data protection mode, and any subsequent write operation must be preceded by the three-byte program command cycle. -3- Publication Release Date: January 31, 2002 Revision A3 W29C011A Hardware Data Protection The integrity of the data stored in the W29C011A is also hardware protected in the following ways: (1) Noise/Glitch Protection: A #WE pulse of less than 15 nS in duration will not initiate a write cycle. (2) VDD Power Up/Down Detection: The programming and read operation are inhibited when VDD is less than 3.8V. (3) Write Inhibit Mode: Forcing #OE low, #CE high, or #WE high will inhibit the write operation. This prevents inadvertent writes during power-up or power-down periods. Data Polling (DQ7)-Write Status Detection The W29C011A includes a data polling feature to indicate the end of a programming cycle. When the W29C011A is in the internal programming cycle, any attempt to read DQ7 of the last byte loaded during the page/byte-load cycle will receive the complement of the true data. Once the programming cycle is completed. DQ7 will show the true data. Toggle Bit (DQ6)-Write Status Detection In addition to data polling, the W29C011A provides another method for determining the end of a program cycle. During the internal programming cycle, any consecutive attempts to read DQ6 will produce alternating 0's and 1's. When the programming cycle is completed, this toggling between 0's and 1's will stop. The device is then ready for the next operation. 5-Volt-Only Software Chip Erase The chip-erase mode can be initiated by a six-byte command sequence. After the command loading cycles, the device enters the internal chip erase mode, which is automatically timed and will be completed in 50 mS. The host system is not required to provide any control or timing during this operation. Product Identification The product ID operation outputs the manufacturer code and device code. Programming equipment automatically matches the device with its proper erase and programming algorithms. The manufacturer and device codes can be accessed by software or hardware operation. In the software access mode, a six-byte command sequence can be used to access the product ID. A read from address 0000H outputs the manufacturer code (DAh). A read from address 0001H outputs the device code (C1h). The product ID operation can be terminated by a three-byte command sequence. In the hardware access mode, access to the product ID is activated by forcing #CE and #OE low, #WE high, and raising A9 to 12 volts. Note: The hardware SID read function is not included in all parts; please refer to Ordering Information for details. -4- W29C011A TABLE OF OPERATING MODES Operating Mode Selection Operating Range = 0 to 70 C (Ambient Temperature), VDD = 5V 10 %, VSS = 0V, VHH = 12V MODE PINS #CE #OE #WE Read VIL VIL VIH AIN Dout Write VIL VIH VIL AIN Din Standby VIH X X X High Z X VIL X X High Z/DOUT X X VIH X High Z/DOUT X VIH X X High Z 5-Volt Software Chip Erase VIL VIH VIL AIN DIN Product ID VIL VIL VIH A0 = VIL; A1 - A16 = VIL; A9 = VHH Manufacturer Code DA (Hex) VIL VIL VIH A0 = VIH; A1 - A16 = VIL; A9 = VHH Device Code C1 (Hex) Write Inhibit Output Disable ADDRESS -5- DQ. Publication Release Date: January 31, 2002 Revision A3 W29C011A Command Codes for Software Data Protection Write BYTE SEQUENCE ADDRESS DATA 0 Write 5555H AAH 1 Write 2AAAH 55H 2 Write 5555H A0H Software Data Protection Acquisition Flow Software Data Protection Write Flow Load data AA to address 5555 Load data 55 to address 2AAA Load data A0 to address 5555 Load 0 to 128 bytes of page data Pause 10 mS Exit Notes for software program code: Data Format: DQ7 - DQ0 (Hex) Address Format: A14 - A0 (Hex) -6- W29C011A COMMAND CODES FOR SOFTWARE CHIP ERASE BYTE SEQUENCE 0 Write 1 Write 2 Write 3 Write 4 Write 5 Write ADDRESS 5555H 2AAAH 5555H 5555H 2AAAH 5555H DATA AAH 55H 80H AAH 55H 10H Software Chip Erase Acquisition Flow Load data AA to address 5555 Load data 55 to address 2AAA Load data 80 to address 5555 Load data AA to address 5555 Load data 55 to address 2AAA Load data 10 to address 5555 Pause 50 mS Exit Notes for software chip erase: Data Format: DQ7 - DQ0 (Hex) Address Format: A14 - A0 (Hex) -7- Publication Release Date: January 31, 2002 Revision A3 W29C011A Command Codes for Product Identification BYTE SEQUENCE 0 Write 1 Write 2 Write 3 Write 4 Write 5 Write SOFTWARE PRODUCT IDENTIFICATION ENTRY ADDRESS DATA 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 60H Pause 10 S SOFTWARE PRODUCT IDENTIFICATION EXIT ADDRESS DATA 5555H AAH 2AAAH 55H 5555H F0H Pause 10 S Software Product Identification Acquisition Flow Product Identification Entry(1) Product Identification Mode(2,3) Product Identification Exit(1) Load data AA to address 5555 Load data 55 to address 2AAA Load data 80 to address 5555 Load data AA to address 5555 Read address = 0 data = DA Load data AA to address 5555 Load data 55 to address 2AAA Load data 55 to address 2AAA Load data FO to address 5555 Read address = 1 data = C1 m Pause 10 S (4) Load data 60 to address 5555 Normal Mode Pause 10 S Notes for software product identification: (1) Data format: DQ7 - DQ0 (Hex); address format: A14 - A0 (Hex). (2) A1 - A16 = VIL; manufacture code is read for A0 = VIL; device code is read for A0 = VIH. (3) The device does not remain in identification mode if power down. (4) The device returns to standard operation mode. -8- W29C011A DC CHARACTERISTICS Absolute Maximum Ratings PARAMETER RATING UNIT -0.5 to +7.0 V 0 to +70 C -65 to +150 C D.C. Voltage on Any Pin to Ground Potential except #OE -0.5 to VDD +1.0 V Transient Voltage (20 nS) on Any Pin to Ground Potential -1.0 to VDD +1.0 V -0.5 to 12.5 V Power Supply Voltage to Vss Potential Operating Temperature Storage Temperature Voltage on #OE Pin to Ground Potential Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device. Operating Characteristics (VDD = 5.0V 10%, VSS = 0V, TA = 0 to 70 C) PARAMETER SYM. TEST CONDITIONS LIMITS UNIT MIN. TYP. MAX. Power Supply Current ICC #CE = #OE = VIL, #WE = VIH, all I/Os open Address inputs = VIL/VIH, at f = 5 MHz - - 50 mA Standby VDD Current (TTL input) ISB1 #CE = VIH, all I/Os open Other inputs = VIL/VIH - 2 3 mA Standby VDD Current (CMOS input) ISB2 #CE = VDD -0.3V, all I/Os open Other inputs = VDD -0.3V/GND - 20 100 A Input Leakage Current ILI VIN = GND to VDD - - 1 A Output Leakage Current ILO VIN = GND to VDD - - 10 A Input Low Voltage VIL - -0.3 - 0.8 V Input High Voltage VIH - 2.0 - VDD +0.5 V Output Low Voltage VOL IOL = 2.1 mA - - 0.45 V Output High Voltage VOH IOH = -0.4 mA 2.4 - - V Power-up Timing PARAMETER SYMBOL TYPICAL UNIT Power-up to Read Operation TPU.READ 100 S Power-up to Write Operation TPU.WRITE 5 mS -9- Publication Release Date: January 31, 2002 Revision A3 W29C011A CAPACITANCE (VDD = 5.0V, TA = 25 C, f = 1 MHz) PARAMETER SYMBOL CONDITIONS MAX. UNIT I/O Pin Capacitance CI/O VI/O = 0V 12 pF Input Capacitance CIN VIN = 0V 6 pF AC CHARACTERISTICS AC Test Conditions (VDD = 5V 10%) PARAMETER CONDITIONS Input Pulse Levels 0V/3V Input Rise/Fall Time 10 nS Input/Output Timing Level 1.5V/1.5V Output Load 1 TTL Gate and CL = 100 pF AC Test Load and Waveforms +5V 1.8K ohm DOUT 100 pF 1.3K ohm Output Input 3V 1.5V 1.5V 0V Test Point Test Point - 10 - W29C011A Read Cycle Timing Parameters (VDD = 5.0V 10%, VSS = 0V, TA = 0 to 70 C) PARAMETER SYMBOL W29C011A-15 MIN. MAX. UNIT Read Cycle Time TRC 150 - nS Chip Enable Access Time TCE - 150 nS Address Access Time TAA - 150 nS Output Enable Access Time TOE - 70 nS #CE Low to Active Output TCLZ 0 - nS #OE Low to Active Output TOLZ 0 - nS #CE High to High-Z Output TCHZ - 45 nS #OE High to High-Z Output TOHZ - 45 nS Output Hold from Address change TOH 0 - nS Byte/Page-Write Cycle Timing Parameters PARAMETER SYMBOL MIN. TYP. MAX. UNIT Write Cycle (erase and program) TWC - - 10 mS Address Setup Time TAS 0 - - nS Address Hold Time TAH 50 - - nS #WE and #CE Setup Time TCS 0 - - nS #WE and #CE Hold Time TCH 0 - - nS #OE High Setup Time TOES 10 - - nS #OE High Hold Time TOEH 10 - - nS #CE Pulse Width TCP 70 - - nS #WE Pulse Width TWP 70 - - nS #WE High Width TWPH 150 - - nS Data Setup Time TDS 50 - - nS Data Hold Time TDH 10 - - nS Byte Load Cycle Time TBLC 0.22 - 200 S Byte Load Cycle Time-out TBLCO 300 - - S Note: All AC timing signals observe the following guidelines for determining setup and hold times: (a) High level signal's reference level is VIH and (b) low level signal's reference level is VIL. - 11 - Publication Release Date: January 31, 2002 Revision A3 W29C011A Data Polling and Toggle Bit Timing Parameters PARAMETER SYMBOL W29C011A-15 UNIT MIN. MAX. #OE to Data Polling Output Delay TOEP - 70 nS #CE to Data Polling Output Delay TCEP - 150 nS #OE to Toggle Bit Output Delay TOET - 70 nS #CE to Toggle Bit Output Delay TCET - 150 nS TIMING WAVEFORMS Read Cycle Timing Diagram TRC Address A16-0 TCE #CE TOE #OE #W E VIH T OHZ TOLZ TCLZ DQ7-0 TOH T CHZ High-Z High-Z Data Valid Data Valid TAA - 12 - W29C011A Timing Waveforms, continued Page Write Timing Diagram Address A16-0 DQ6 2AAA 5555 AA 55 TWC Byte/page load cycle starts Three-byte sequence for software data protection mode 5555 A0 #CE #OE TBLC TWP #WE TBLCO TWPH SW1 SW0 SW2 Byte 0 Byte N-1 Byte N (last byte) Internal write starts Note Notes: Refer to "#CE (#WE) Controlled Write Cycle Timing Diagram" for a detailed timing diagram. #WE Controlled Write Cycle Timing Diagram TBLCO TAS T WC TAH Address A16-0 #CE TCS TCH TOES T OEH #OE #WE TWP TWPH TDS DQ7-0 Data Valid TDH Internal write starts - 13 - Publication Release Date: January 31, 2002 Revision A3 W29C011A Timing Waveforms, continued #CE Controlled Write Cycle Timing Diagram TBLCO TAS T WC T AH Address A16-0 T CPH T CP #CE T OES T OEH #OE #WE T DS High Z DQ7-0 Data Valid T DH Internal Write Starts #DATA Polling Timing Diagram Address A16-0 #WE TCEP #CE TOES TOEH #OE TOEP DQ7-0 X X X TWC - 14 - X W29C011A Timing Waveforms, continued Toggle Bit Timing Diagram Address A16-0 #WE #CE TOES TOEH #OE DQ6 TWC 5 Volt-Only Software Chip Erase Timing Diagram Six-byte code for 5V-only software chip erase Address A16-0 DQ7-0 5555 2AAA 55 AA 5555 5555 80 AA 2AAA 55 TWC 5555 10 #CE #OE TWP TBLC TBLCO #WE TWPH SW0 SW1 SW2 SW3 SW4 SW5 Internal programming starts - 15 - Publication Release Date: January 31, 2002 Revision A3 W29C011A ORDERING INFORMATION PART NO. ACCESS TIME (nS) POWER SUPPLY CURRENT MAX. (mA) STANDBY VDD CURRENT MAX. (A) PACKAGE HARDWARE SID READ FUNCTION W29C011A-15 150 50 100 600 mil DIP Y W29C011AS-15 150 50 100 450 mil SOP Y W29C011AP-15 150 50 100 32-pin PLCC Y W29C011A-15N 150 50 100 600 mil DIP N W29C011AP15N 150 50 100 32-pin PLCC N Notes: 1. Winbond reserves the right to make changes to its products without prior notice. 2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure. 3. In Hardware SID Read column: Y = with SID read function; N = without SID read function. HOW TO READ THE TOP MARKING Example: The top marking of 32L-PLCC W29C011AP-15 W29C011AP-15 2138977A-A12 149OBRA st 1 line: winbond logo nd 2 line: the part number: W29C011AP-15 rd 3 line: the lot number th 4 line: the tracking code: 149 O B RA 149: Packages made in '01, week 49 O: Assembly house ID: A means ASE, O means OSE, ...etc. B: IC revision; A means version A, B means version B, ...etc. RA: Process code - 16 - W29C011A PACKAGE DIMENSIONS 32-pin P-DIP Symbol A A1 A2 B D 17 E1 0.160 3.81 3.94 4.06 0.018 0.022 0.41 0.46 0.56 1 0.048 0.050 0.054 1.22 1.27 1.37 c D E E1 e1 L 0.008 0.010 0.014 0.20 0.25 S c A 2 A1 L Base Plane Seating Plane B e1 eA a B1 0.36 1.650 1.660 41.91 42.16 0.600 0.610 15.49 14.99 15.24 0.545 0.550 0.555 13.84 13.97 14.10 0.090 0.100 0.110 2.29 2.54 2.79 0.120 0.130 0.140 3.05 3.30 3.56 15 0 0.670 16.00 16.51 17.02 0.590 0 0.630 0.650 15 0.085 S Notes: E A 0.25 0.155 eA 16 5.33 0.210 0.010 0.016 a 1 Dimension in mm Min. Nom. Max. Min. Nom. Max. 0.150 B 32 Dimension in inches 2.16 1.Dimensions D Max. & S include mold flash or tie bar burrs. 2.Dimension E1 does not include interlead flash. 3.Dimensions D & E1. include mold mismatch and are determined at the mold parting line. 4.Dimension B1 does not include dambar protrusion/intrusion. 5.Controlling dimension: Inches. 6.General appearance spec. should be based on final visual inspection spec. 32-pin SO Wide Body Symbol 17 32 e1 A A1 A2 b c D E e HE L LE S y E HE L Detail F 1 b 16 c A2 S y A e LE A1 See Detail F Seating Plane - 17 - Min. Nom. Max. Dimension in mm Min. Nom. 0.004 Max. 3.00 0.118 0.10 0.101 0.106 0.111 2.57 2.69 0.014 0.016 0.020 0.36 0.41 0.51 0.006 0.008 0.012 0.15 0.20 0.31 0.805 0.817 20.45 20.75 0.440 0.445 0.450 11.18 11.30 11.43 0.044 0.050 0.056 1.12 1.27 1.42 0.546 0.556 0.556 13.87 14.12 14.38 0.023 0.031 0.039 0.58 0.79 0.99 0.047 0.055 0.063 1.19 1.40 1.60 0.036 0.91 0.10 0.004 0 10 2.82 0 10 Notes: e1 D Dimension in Inches 1. Dimensions D Max. & S include mold flash or tie bar burrs. 2. Dimension b does not include dambar protrusion/intrusion. 3. Dimensions D & E include mismatch . moldmold and determined at the parting line. 4. Controlling dimension: Inches. 5. General appearance spec should be based on final visual inspection spec. Publication Release Date: January 31, 2002 Revision A3 W29C011A Package Dimensions, continued 32-pin PLCC Symbol H E E 4 1 32 30 5 29 G D H D D 21 13 A A1 A2 b1 b c D E e GD GE HD HE L y Dimension in Inches Min. Nom. Dimension in mm Max. Min. Nom. 0.140 0.020 Max. 3.56 0.50 0.105 0.110 0.115 2.67 2.80 2.93 0.026 0.028 0.032 0.66 0.71 0.81 0.016 0.018 0.022 0.41 0.46 0.008 0.010 0.014 0.20 0.25 0.35 0.547 0.550 0.553 13.89 13.97 14.05 0.447 0.450 0.453 11.35 11.43 11.51 0.044 0.050 0.056 1.12 1.27 1.42 0.490 0.510 0.530 12.45 12.95 13.46 0.390 0.410 0.430 9.91 10.41 10.92 0.585 0.590 0.595 14.86 14.99 15.11 0.485 0.490 0.495 12.32 12.45 12.57 0.075 0.090 0.095 1.91 2.29 2.41 0.10 0.004 0 10 0.56 0 10 Notes: 14 1. Dimensions D & E do not include interlead flash. 2. Dimension b1 does not include dambar protrusion/intrusion. 3. Controlling dimension: Inches. 4. General appearance spec. should be based on final visual inspection sepc. c 20 L A2 e b b Seating Plane G A A1 1 y E - 18 - W29C011A VERSION HISTORY VERSION DATE A1 Dec. 1997 A2 Jan. 2001 PAGE Initial Issued 10 4, 16 A3 Jan. 31, 2002 DESCRIPTION Modify VIH/VIL = 0V/3V and VOH/VOL = 1.5V/1.5V Add in Hardware SID Read function note 4 Modify VCC Power Up/Down Detection in Hardware Data Protection 16 Add HOW TO READ THE TOP MARKING Headquarters Winbond Electronics Corporation America Winbond Electronics (Shanghai) Ltd. No. 4, Creation Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5665577 http://www.winbond.com.tw/ 2727 North First Street, San Jose, CA 95134, U.S.A. TEL: 1-408-9436666 FAX: 1-408-5441798 27F, 2299 Yan An W. Rd. Shanghai, 200336 China TEL: 86-21-62365999 FAX: 86-21-62365998 Taipei Office Winbond Electronics Corporation Japan Winbond Electronics (H.K.) Ltd. 9F, No.480, Rueiguang Rd., Neihu Chiu, Taipei, 114, Taiwan, R.O.C. TEL: 886-2-8177-7168 FAX: 886-2-8751-3579 7F Daini-ueno BLDG, 3-7-18 Shinyokohama Kohoku-ku, Yokohama, 222-0033 TEL: 81-45-4781881 FAX: 81-45-4781800 Unit 9-15, 22F, Millennium City, No. 378 Kwun Tong Rd., Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064 Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. - 19 - Publication Release Date: January 31, 2002 Revision A3