256K x 4 Static RAM
CY7C106BN
CY7C1006BN
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document #: 001-06429 Rev. ** Revised February 1, 2006
Features
•High speed
—t
AA = 15 ns
• CMOS for optimum speed/powe r
• Low active power
—495 mW
• Low standby power
—275 mW
• 2.0V data retention (optional)
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
Functional Description
The CY7C106BN and CY7C1006BN are high-performance
CMOS static RAMs organized as 262,144 words by 4 bits.
Easy memory expansion is provided by an active LOW Chip
Enable (CE), an active LOW Output Enable (OE), and
three-state drivers. These devices have an automatic
power-down feature that reduces power consumption by more
than 65% when th e de vi ce s ar e de sel e c te d .
Writing to the devices is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. Data on the four I/O
pins (I/O0 through I/O3) is then written into the location
specified on the address pins (A0 through A17).
Reading from the devices is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the four I/O pins.
The four input/output pins (I/O0 through I/O3) are placed in a
high-impedance state when the devices are deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a wri te
operation (CE and WE LOW).
The CY7C106BN is available in a standard 400-mil-wide SOJ;
the CY7C1006BN is available in a standard 300-mil-wide SOJ.
LogicBlockDiagram Pin Configuration
512 x 512 x4
ARRAY
A
1
A
0
A
10
A
12
A
11
A
13
A
14
COLUMN
DECODER
ROW DECODER
SENSE AMPS
POWER
DOWN
OE
INPUTBUFFER
A
15
A
16
A
17
1
2
3
4
5
6
7
8
9
10
11
14 15
16
20
19
18
17
21
24
23
22
Top View
SOJ
12
13
25
28
27
26
GND
A1
A2
A3
A4
A5
A6
A7
A8
A17
VCC
A16
A15
A14
A13
I/O3
I/O2
I/O1
I/O0
A9
A0
A10
CE
OE
NC
A12
A11
WE
WE
CE
I/O
0
I/O
1
I/O
2
I/O
3
A
2
A
3
A
4
A
6
A
7
A
8
A
9
A
5
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CY7C106BN
CY7C1006BN
Document #: 001-06429 Rev. ** Page 2 of 8
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ......................... .. ... ..–65×C to +150×C
Ambient Temperature with
Power Applied............................................–55×C to +125×C
Supply Voltage on VCC Relative to GND[1] ....–0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State[1] ....................................–0.5V to VCC + 0.5V
DC Input V oltage[1].................................–0.5V to VCC + 0.5V
Current into Outputs (LOW).........................................20 mA
Static Discharge Voltage ...........................................>2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current.....................................................>200 mA
Selection Guide
7C106BN-15
7C1006BN-15 7C106BN-20
7C1006BN-20
Maximum Access Time (ns) 15 20
Maximum Operating Current (mA) 80 75
Maximum Standby Current (mA) 30 30
Operating Range
Range Ambient
Temperature[2] VCC
Commercial 0°C to +70°C 5V ± 10%
Industrial –45°C to +85°C
Electrical Characteristics Over the Operating Range
Parameter Description Test Conditions
7C106BN-15
7C1006BN-15 7C106BN-20
7C1006BN-20
Min. Max. Min. Max. Unit
VOH Output HIGH Voltage VCC = Min., IOH = –4.0 mA 2.4 2.4 V
VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA 0.4 0.4 V
VIH Input HIGH Voltage 2.2 VCC + 0.3 2.2 VCC + 0.3 V
VIL Input LOW Voltage[1] –0.3 0.8 –0.3 0.8 V
IIX Input Leakage Current GND < VI < VCC –1 +1 –1 +1 mA
IOZ Output Leakage Current GND < VI < VCC, Output
Disabled –5 +5 –5 +5 mA
IOS Output Short
Circuit Current[3] VCC = Max., VOUT = GND –300 –300 mA
ICC VCC Operating Supply
Current VCC = Max., IOUT = 0 mA,
f = fMAX = 1/tRC 80 75 mA
ISB1 Automatic CE Power-Down
Current —TTL Inputs Max. VCC, CE > VIH, VIN > VIH or
VIN < VIL, f = fMAX
30 30 mA
ISB2 Automatic CE Power-Down
Current —CMOS Inputs Max. VCC,
CE > VCC – 0.3V,
VIN > VCC – 0.3V
or VIN < 0.3V, f=0
Com’l 10 10 mA
Capacitance[4]
Parameter Description Test Co nditions Max. Unit
CIN: Addresses Input Capacitance TA = 25×C, f = 1 MHz,
VCC = 5.0V 7pF
CIN: Controls 10 pF
COUT Output Capacitance 10 pF
Notes:
1. VIL (min.) = –2.0V for pulse durations of less than 20 ns.
2. TA is the “instant on” case temperature.
3. Not more than 1 output sh ould be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
4. Tested initially and after any design or process change s that may affect these parameters.
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CY7C1006BN
Document #: 001-06429 Rev. ** Page 3 of 8
AC Test Loads and Waveforms
Switching Characteristics Over the Operating Range[5]
7C106B-15
7C1006B-15 7C106B-20
7C1006B-20
Parameter Description Min. Max. Min. Max. Unit
READ CYCLE
tRC Read Cycle Time 15 20 ns
tAA Address to Data Valid 15 20 ns
tOHA Data Hold from Address Change 3 3 ns
tACE CE LOW to Data Valid 15 20 ns
tDOE OE LOW to Data Valid 7 8 ns
tLZOE OE LOW to Low Z 0 0 ns
tHZOE OE HIGH to High Z[6, 7] 78ns
tLZCE CE LOW to Low Z[7] 33ns
tHZCE CE HIGH to High Z [6, 7] 78ns
tPU CE LOW to Power-Up 0 0 ns
tPD CE HIGH to Power-Down 15 20 ns
WRITE CYCLE[8, 9]
tWC Write Cycle Time 15 20 ns
tSCE CE LOW to Write End 12 15 ns
tAW Address Set-Up to Write End 12 15 ns
tHA Address Hold from Write End 0 0 ns
tSA Address Set-Up to Write Start 0 0 ns
tPWE WE Pulse Width 12 15 ns
tSD Data Set-Up to Write End 8 10 ns
tHD Data Hold from Write End 0 0 ns
tLZWE WE HIGH to Low Z[7] 33ns
tHZWE WE LOW to High Z[6, 7] 78ns
Notes:
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 30–pF load capacitance.
6. tHZOE, tHZCE, and tHZWE are specified with a load cap acitance of 5 pF as in p art (b) of AC Test Loads. T ransition is measured ±500 mV f rom steady-state volta ge.
7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
8. The internal write time of the memory is defined by the overlap of CE and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either of
these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the si gnal that terminates the write.
9. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
90%
10%
3.0V
GND
90%
10%
ALL INPUT PULSES
5V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
5V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
(a) (b)
OUTPUT
R1 480ΩR1 480Ω
R2
255ΩR2
255Ω
167Ω
Equivalent to: THÉ VENIN EQUIVALENT
1.73V
Rise Time < 1V/ns Fall Time < 1V/n
s
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CY7C106BN
CY7C1006BN
Document #: 001-06429 Rev. ** Page 4 of 8
Data Retention Characteristics Over the Operating Range
Parameter Description Conditions[10] Min. Max. Unit
VDR VCC for Data Retention 2.0 V
ICCDR Data Retention Current VCC = VDR = 2.0V,
CE > VCC – 0.3V,
VIN > VCC – 0.3V or
VIN < 0.3V
250 µA
tCDR[4] Chip Deselect to Data Retention Time 0ns
tR[4] Operation Recovery Time 200 ms
Data Retention Waveform
4.5V4.5V
CE
VCC tCDR
VDR >2V
DATA RETENTION MODE
tR
Switching Waveforms
Read Cycle No.1[11, 12]
Read Cycle No. 2 (OE Controlled)[12, 13]
Notes:
10.No input may exceed VCC +0.5V.
11.Device is continuously selected, OE and CE = VIL.
12.WE is HIGH for read cycle.
13.Address valid prior to or coincident with CE transition LO W.
1
PREVIOUS DATA VALID DATA VALID
tRC
tAA
tOHA
ADDRESS
DATA OUT
50%
50%
DATA VALID
tRC
tACE
tDOE
tLZOE
tLZCE
tPU
HIGH IMPEDANCE IMPEDANCE
ICC
ISB
tHZOE tHZCE
tPD
HIGH
ADDRESS
CE
DATA OUT
VCC
SUPPLY
CURRENT
OE
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CY7C106BN
CY7C1006BN
Document #: 001-06429 Rev. ** Page 5 of 8
Write Cycle No. 1 (CE Controlled)[14, 15]
Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[14, 15]
Notes:
14.If CE goes HIGH simultaneously with WE going HI GH, the output remains in a high-impedance state.
15.Data I/O is high impedance if OE = VIH.
Switching Waveforms (continued)
tWC
DATA VALID
tAW
tSA
tPWE
tHA
tHD
tSD
tSCE
ADDRESS
CE
DATA I/O
WE
DATA VALID
tHD
tSD
tPWE
tSA
tHA
tAW
tSCE
tWC
tHZOE
ADDRESS
CE
WE
DATA I/O
OE
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CY7C106BN
CY7C1006BN
Document #: 001-06429 Rev. ** Page 6 of 8
Write Cycle No. 3 (WE Controlled, OE LOW)[9, 15]
Switching Waveforms (continued)
DATA VALID
tHD
tSD
tLZWE
tPWE
tSA
tHA
tAW
tSCE
tWC
tHZWE
ADDRESS
CE
WE
DATA I/O
Truth Table
CE OE WE Input/Output Mode Power
H X X High Z Power-Down Standby (ISB)
L L H Data Out Read Active (ICC)
L X L Data In Write Active (ICC)
L H H High Z Selected, Outputs Disabled Active (ICC)
Ordering Information
Speed
(ns) Ordering Code Package
Diagram Package Typ e Operating
Range
15 CY7C106BN-15VC 51-85032 28-Lead (400-Mil) Molded SOJ Commercial
CY7C1006BN-15VC 51-85031 28-Lead (300-Mil) Molded SOJ
20 CY7C106BN-20VC 51-85032 28-Lead (400-Mil) Molded SOJ Commercial
Please contact local sales repre se ntative regarding availability of these parts.
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CY7C1006BN
Document #: 001-06429 Rev. ** Page 7 of 8
© Cypress Semi con duct or Cor po rati on , 20 06 . The information con t a in ed he re i n is su bject to change without notice. C ypr ess S em icon ductor Corporation assumes no resp onsib ility for the u se
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypres s. Furthermore, Cypress does no t authorize i ts
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant inju ry to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
All product or company names mentioned in this document may be the trademarks of their respective holders.
Package Diagrams
MIN.
MAX.
PIN 1 ID
0.291
0.300
0.050
TYP.
0.007
0.013
0.330
0.350
0.120
0.140
0.025 MIN.
0.262
0.272
0.697
0.713
0.013
0.019 0.014
0.020
0.032
0.026
A
A
DETAIL
EXTERNAL LEAD DESIGN
OPTION 1 OPTION 2
114
15 28
0.004
SEATING PLANE
NOTE :
1. JEDEC STD REF MO088
2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH
MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.006 in (0.152 mm) PER SIDE
3. DIMENSIONS IN INCHES
51-85031-*C
28-pin (300-Mil) Molded SOJ (51-85031)
PIN 1 I.D
.435
.395 .445
.405
.128
.148
.360
.380
.026
.015
.032
.020
DIMENSIONS IN INCHES MIN.
MAX.
.025 MIN.
.007
.013
.050
TYP.
.720
.730
114
15 28
0.004
SEATING PLANE
51-85032.*B
28-Lead (400-Mil) Molded SOJ (51-8503 2)
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