ANALOG CMOS 12-Bit DEVICES Buffered Multiplying DAC AD7545A REV. A 1.1 Scope. This specification covers the detail requirements for a monolithic CMOS multiplying digital-to-analog converter with on-board data latches. It is loaded by a single 12-bit wide word and interfaces directly to 12- and 16-bit microprocessor based systems. The AD7545A is an improved version of the AD7545 and will operate with any supply voltage from +5 V to +15 V. 1.2 Part Number. The complete part numbers per Tables 1 and 2 of this specification are as follows: Device Part Number -1 AD7S45AT(X)/883B -2 AD7545AU(X/883B NOTE To compiete the part number substitute the package identifier as shown in paragraph 1.2.3. 1.2.3 Case Outline. See Appendix 1 of General Specification ADI-M-1000: package outline: (X) Package Description Q Q20 20-Pin Cerdip E E-20A 20-Contact LCC 1.3 Absolute Maximum Ratings. (T,=+25C unless otherwise noted) Vpp t0 DGND .. 0... cee eee cence tenance ne te penne -0.3.V,+17V Digital Input Voltage to DGND ....... 0.0... ec cece eee ees 0.3 V, Vpp +0.3 V Vargo Vrerp tO DGND ... 1... ec ee nee teen ence et ee nev eteeene +25 V Vprm tO DGND 0... ce tence neem e en eeeteeee ~0.3 V, Vpp +0.3 V AGND to DGND ... 0... eee een ene te te neaee ~0.3 V, Vpp +0.3 V Power Dissipation to +75C 0... me cette eet eee seca rtesenes 450 mW Derates above +75C by 2.0... 0. ccc cence ee eee eee e een eeneenanes 6 mW/C Operating Temperature Range ... 0.0... ccc cece eee eet ne eeees 55C to + 125C Storage Temperature 2.0.1... eee eee nen ee ee newee 65C to + 150C Lead Temperature (Soldering, 10 sec) . 2... 0. cece cece eee tee eee eteeneeas +300C 1.5 Thermal Characteristics. Thermal Resistance 6;- = 30C/W for Q-20 and E-20A 8y4 = 120C/W for Q-20 and E-20A DIGITAL-TO-ANALOG CONVERTERS 8-149 DIGITAL-TO-ANALOG CONVERTERS aAD7545A SPECIFICATIONS Table 1. Design Sub Sub Limit Group | Group | Test Conditions/Comments Test Symbol | Device | Tiin/Tmax | 1 2,3 Vop = +5 V Units Resolution RES -1,2 12 Bits Relative Accuracy RA -1,2 v2 1/2 1/2 +LSB max Differential Nonlinearity DNL -1,2 1 1 1 12-Bit Monotonic T pain tO T inex +LSB max Gain Error Ag -1 4 3 4 DAC Register Loaded with 1111 1111 1111 +LSB max -2 2 1 2 Gain Tempco TCye -1,2 5 +ppovC max Power Supply Rejection PSRR -1,2 0.004 0.002 0.004 Vopp = +5% +%/% max Output Leakage Current OUT] | -1,2 | 200 10 200 DBO-DBI1 = 0 V; WR, CS =0V +nA max Output Current Settling Time tr -1,2 1 To +1/2 LSB; OUT] Load = 1009, DAC | ps max Output Measured from Falling Edge of WR. CS =0V Feedthrough Error FT ~1,2 10 mV p-p max Reference Input Resistance Rw -1,2 10 10 10 k min Pin 19 to Ground 20 20 20 k max Digital Input High Voltage Vin -1,2 2.4 2.4 2.4 V min Digital Input Low Voltage Viv ~1,2 0.8 0.8 0.8 V max Digital Input Leakage Current Iw ~1,2 10 1 10 Vin = 0 Vor Vpp pA max Digital Input Capacitance Cw ~1,2 8 DBO-DB11; WR, CS pF max 15 Output Capacitance Cour: | ~1.2 | 70 DBO-DB11 = 0 V, WR, CS = 0V pF max 150 DBO-DB11 = Vpp; WR, CS = OV Chip Select to Write Setup Time? | t.-; ~1,2 170 ns min Chip Select to Write Hold Time? | ty; ~1,2 0 Write Pulse Width? twr ~1,2 | 170 lesZtwr ten 20 Data Setup Time? tps ~1,2 150 Data Hold Time? ton ~1,2 5 Supply Current from Vopp Ipp -1,2 2 2 2 All Digital Inputs Vi, or Vi mA max 100 100 100 All Digital Inputs 0 or Vpp pA max NOTES Your = 0V, Vac = +10 V, AGND = ?Measured using internal feedback resistor. Timing per Figure 1. 8-150 DIGITAL-TO-ANALOG CONVERTERS DGND unless otherwise stated. REV. AAD7545A Table 2. Design Sub Sub Limit Group | Group | Test Conditions/Comments Test Symbol | Device | Toun/Tmex | 1 2,3 Vop = +15V Units Resolution RES 71,2 12 Bits Relative Accuracy RA -1,2 2 1/2 4/2 +LSB max Differential Nonlinearity DNL -1,.2 1 1 1 12-Bit Monotonic T,,,,, [0 Tmax ~LSB max Gain Error? AE =1 4 3 4 DAC Register Loaded with IMI TIL ILI |) =LSB max ~2 2 1 2 Gain Tempco TCyse -1,2 5 ~ppm/C max Power Supply Rejection PSRR -1,2 0.004 0.002 0.004 Vop = =5% =%/% max Output Leakage Current OUT -1,2 200 10 200 DBO-DB11 = 0 V; WR,CS = 0V nA max Output Current Settling Time tsp -1,2 1 To +1/2 LSB; OUT1 Load = 100, DAC | ys max Output Measured from Falling Edge of WR. Feedthrough Error FT -1,2 10 mV p-p max Reference Input Resistance Rw -1,2 10 10 10 k min Pin 19 to Ground 20 20 20 k max Digital Input High Voltage Vin ~-1,2 13.5 13.5 13.5 V min Digital Input Low Voltage Vir -1,2 1.5 1.5 1.5 V max Digital Input Leakage Current ly 1,2 | 10 \ 10 Vix = 0 Vor Vpp *pA max Digital Input Capacitance Cw ~1,2 8 DBO-DB11; WR, CS pF max Output Capacitance Coun -1,2 70 DBO-DB11 = 0 V, WR, CS = 0V pF max 150 DBO-DB!1 = Vpp; WR, CS = 0V Chip Select to Write Setup Time? | tc -1,2 95 ns min Chip Select to Write Hold Time | tc; -1,2 4 0 Write Pulse Width? twr -1,2 95 lesZtwro te Z0 Data Setup Time? tps -1,2 80 Data Hold Time? ton ~1,2 5 Supply Current from Vpp Ipp -1,2 2 2 2 All Digital Inputs V), or Vie mA max 100 100 100 Ail Digital Inputs 0 or Vop pA max NOTES 'Vour: = 0 V, Vrer = +10 V, AGND = DGND unless otherwise stated. ?Measured using internal feedback resistor. Timing per Figure 1. | t tcu { v MODE SELECTION cs oD CHIP \ Ye WRITE MODE: HOLD MODE: SELECT 0 CS and WR low, DAC responds Either CS or WR high, data bus : to data bus (OBO-D811) inputs. (DBO-D611) is locked out; DAC ty | Vop holds jast data present when q YS WR or CS assumed high state. WRITE . YW Sf ton 0 NOTES: t Vop = +5V; t = ty = 20ns - OS v Vop = +15V; t= y= 40n DATA IN Dns ; oo onan rise and fail times measured from 10% to (DB0-DB11} vi AVALID 0 Timing meesurement reference level ix Mitd* Vin Figure 1. Write Cycle Timing Diagram DIGITAL-TO-ANALOG CONVERTERS 8-157 DIGITAL-TO-ANALOG CONVERTERS aAD7545A 3.2.1 Functional Block Diagram and Terminal Assignments. AD7545A Vaer __ 12-BIT MULTIPLYING DAC aE WR 47) cs INPUT DATA LATCHES Pin Assignments Cerdip (Q) Res out: [7] [20] Are Gd AGND Ea a] Vaer OGNOD E va) Voo oettiwas) [e] [7] wR ouTi on fF sores Fa) (2) AGNO pee [6] tnotte Scale) [75] neo tus Des CG 4) pet 69 Voo 087 a a pez Des | % 12] Des DGND OBE | 10 tt! oes Os hd 0811-DBo (PINS 4-15) 0B11 (MSB) DBI ose Cas oOs7 TOP VIEW iNot To Scale} 9 10 11 12 13 BEER s 3.2.4 Microcircuit Technology Group. This microcircuit is covered by technology group (80). 4.2.1 Life Test/Burn-In Circuit. Steady state life test is per MIL-STD-883, Method 1005. Burn-in is per MIL-STD-883 Method 1015, Test Condition (B). ouT1 Res outz Vase GNO Voo pB11 WR B10 cs DB9 DBO pss OB1 087 DB2 DBS DBs pes DBe DATAO 100k ONE PERBOARD ara 0 ~~ Vegre = +10V = CS= GND 8-152 DIGITAL-TO-ANALOG CONVERTERS REV. A