2SC4306S-TL-E - SANYO - Datasheet.Live

1. General description

The PTN3392 is a DisplayPort to VGA adapter IC designed to connect a DisplayPort

source to a VGA sink. The PTN3392 integrates a DisplayPort receiver and a high-speed

triple video digital-to-analog converter that supports display resolutions from VGA to

WUXGA (see Table 4). The PTN3392 supports either one or two DisplayPort v1.1a lanes

operating at either 2.7 Gbit/s or 1.62 Gbit/s per lane. The PTN3392 has ‘Flash -ove r-AUX’

capability enabling simple firmware upgradability in the field.

The PTN3392 supports I2C-bus over AUX per DisplayPort v1.1a specification (Ref. 1),

and bridges the VESA DDC channel to the DisplayPort Interface.

The PTN3392 is designed for single supply and minimizes application costs. It can be

powered directly from the DisplayPort source side 3.3 V supply without a need for

additional core voltag e regulator. The VGA output is powered down when there is no valid

DisplayPort source data being transmitted. The PTN3392 also aids in monitor detection

by performing load sensing and reporting sink connection status to the source.

2. Features and benefits

2.1 VESA compliant DisplayPort v1.1a converter

Main Link: 1-lane and 2-lane modes supported

HBR (High Bit Rate) at 2.7 Gbit/s per lane

RBR (Reduced Bit Rate) at 1.62 Gbit/s per lane

BER (Bit Error Rate) better than 109

Down-spreading SSC (Spread Spectrum Clocking) supported

1 MHz AUX channel

Supports native AUX CH syntax

Supports I2C-bus over AUX CH syntax

Hot Plug Detect (HPD) signal to the source

Cost-effective design optimized fo r VGA ap plic at ion

2.2 DDC channel output

Supports 100 kbit/s I2C-bus speed, declared in DPCD register

Support of I2C-bus speed control by DisplayPort source via DPCD registers,

facilitating use of longer VGA cables

I2C Over Aux feature facilitates full support of MCCS, DDC-CI, and DDC protocols

(see Ref. 2)

PTN3392

2-lane DisplayPort to VGA adapter IC

Rev. 4 — 8 October 2012 Product data sheet

Product data sheet Rev. 4 — 8 Oct ober 2012 2 of 30

NXP Semiconductors PTN3392

2-lane DisplayPort to VGA adapter IC

2.3 Analog video output

VSIS 1.2 compliance (Ref. 3) for all supported video output modes

Analog RGB current-source outputs

VSYNC and HSYNC outputs

Pixel clock up to 240 MHz

Triple 8-bit Digital-to-Analog Converter (DAC)

Direct drive of double terminated 75  load with standard 700 mV (peak-to-peak)

signals

2.4 General features

Supports ‘Flash-over-AUX’ field upgradability

Monitor presence detection. Connection/disconnection reported via HPD IRQ and

DPCD update.

All display resolutions from VGA to WUXGA are supported1, including e.g.:

WUXGA: 6 bits, 1920 1200, 60 Hz, 193 MHz pixel clock rate

WUXGA: 1920 1200, 60 Hz, reduced blanking, 154 MHz pixel clock rate

UXGA: 1600 1200, 60 Hz, 162 MHz pixel clock rate

SXGA: 1280 1024, 60 Hz, 108 MHz pixel clock rate

XGA: 1024 768, 60 Hz, 65 MHz pixel clock rate

SVGA: 800 60 0, 60 Hz, 40 M Hz pixel clock rate

VGA: 640 480, 60 Hz, 25 MHz pixel clock rate

Any resolution and refresh rates are supported up to 8 bit color

Bits per color (bpc) supporte d 1

6, 8 bits supported

10, 12, 16 bits supported by truncation to 8 MSBs

All VGA colorimetry formats (RGB) supported

Power modes

Active-mode power consumption:

~600 mW at UXGA / 162 MHz pixel clock

~500 mW at SXGA / 108 MHz pixel cloc k

~40 mW at Low-power mode or before link training started

On-board crystal oscillator for use with external 27 MHz crystal

ESD protection

7 kV ESD HBM JEDEC

8 kV ESD HBM IEC 61000-4-2 (Ref. 4)

3.3 V 10 % power supply

Commercial temperature range: 0 C to 85 C

48-pin HVQFN, 7 mm 7mm0.85 mm (nominal); 0.5 mm pitch; lead-free package

1. Except for color depth beyond 8 bits, display resolutions and refresh rates are only limited to those which a standard 2-lane

DisplayPort configuration is able to support.

Product data sheet Rev. 4 — 8 Oct ober 2012 3 of 30

NXP Semiconductors PTN3392

2-lane DisplayPort to VGA adapter IC

3. Applications

Dongle PC accessory

Dongle connected to PC DisplayPort output and connected to RGB monitor via

VGA cable

PTN3392 is powered by the DP_PWR pin on the DisplayPort connector

Desktop and notebook computers

Notebook docking stations

4. Ordering information

[1] PTN3392BS uses latest firmware version.

[2] PTN3392BS/FX uses specific firmware version (‘X’ = 1, 2, 3, etc., and changes according to firmware version).

5. Functional diagram

Table 1. Ordering information

Type number Topside mark Package

Name Description Version

PTN3392BS[1] PTN3392BS HVQFN48 plastic thermal enhanced very thin quad flat package;

no leads; 48 terminals; 7 70.85 mm SOT619-1

PTN3392BS/FX[2] PTN3392BS HVQFN48 plastic thermal enhanced very thin quad flat package;

no leads; 48 terminals; 7 70.85 mm SOT619-1

Fig 1. Functional di agram

002aae032

DIFF

RCV CDR,

S2P

RX PHY

ANALOG

SUBSYSTEM

DIFF

RCV CDR,

S2P

RCV

PTN3392

DRV

MANCHESTER

CODEC

RX DIGITAL SUBSYSTEM

10b/8b

DE-SCRAM

INTERFACE DE-SKEWING

10b/8b

DE-SCRAM

RX PHY DIGITAL

AUX COMMAND

LEVEL MODULE

RX ACLI

DPCD

REGISTERS

I2C-BUS

MASTER

FLASH MCU

CONTROL

TIME

CONV.

ISOCHRONOUS LINK

TIMING RECOVERY

MAIN

STREAM

DAC

R[7:0]

G[7:0]

B[7:0]

VGA

OUTPUT

H, V

sync

VIDEO DAC SUBSYSTEM

HSYNC

VSYNC

SCL

SDA

Vbias

MONITOR

PRESENCE

DETECT

lane 0

lane 1

AUX

Product data sheet Rev. 4 — 8 Oct ober 2012 4 of 30

NXP Semiconductors PTN3392

2-lane DisplayPort to VGA adapter IC

6. Pinning information

6.1 Pinning

6.2 Pin description

Fig 2. Pin configuration for HVQFN48

002aae033

PTN3392BS

RED

SCL

VDD_IO

OSC_IN

TDI OSC_OUT

TRST_N GNDD

TMS GNDD

GND_IO LDOCAP_CORE

TDO VDDD

TCK VDDD

VDDA_DP S0

HPD S1

CLK_O S2

RESET_N S3

SDA

VSYNC

HSYNC

BLU

VDD_DAC

BLU_N

GRN_N

GRN

RSET

GND_DAC

RED_N

GNDA_DP1

ML1_N

ML1_P

GNDA_DP0

ML0_N

ML0_P

RRX

GNDA

AUX_N

AUX_P

LDOCAP_AUX

VDDA

12 25

11 26

10 27

9 28

8 29

7 30

6 31

5 32

4 33

3 34

2 35

1 36

terminal 1

index area

Transparent top view

Table 2. Pin description

Symbol Pin Type Description

VDDD 32, 31 power digital core 3.3 V supply

VDDA 37 power analog AUX, bias and PLL 3.3 V supply

voltage

VDDA_DP 4 power analog 3.3 V supply for DisplayPort receiver

module

VDD_IO 12 power I/O 3.3 V supply voltage

VDD_DAC 17, 18 power analog 3.3 V supply for DAC

GND_IO[1] 7 power I/O supply ground

GND_DAC[1] 23 power analog ground for DAC

GNDA_DP0[1] 45 power analog ground for DisplayPort Lane0

GNDA_DP1[1] 48 power analog ground for DisplayPort Lane1

GNDA[1] 41 power analog AUX, bias and PLL supply ground

GNDD[1] 28, 29 power digital core supply ground

Product data sheet Rev. 4 — 8 Oct ober 2012 5 of 30

NXP Semiconductors PTN3392

2-lane DisplayPort to VGA adapter IC

DisplayPort

ML0_P 43 self-biasing

differential input DisplayPort main lane signal lane 0, positive

ML0_N 44 self-biasing

differential input DisplayPort main lane signal lane 0, negative

ML1_P 46 self-biasing

differential input DisplayPort main lane signal lane 1, positive

ML1_N 47 self-biasing

differential input DisplayPort main lane signal lane 1, negative

AUX_P 39 self-biasing

differential

input/output

DisplayPort auxiliary channel signal, positive

AUX_N 40 self-biasing

differential

input/output

DisplayPort auxiliary channel signal, negative

HPD 3 3.3 V TTL

single-ended output Hot-plug detect

RGB DAC outputs

BLU 16 analog output ‘blue’ current analog output

BLU_N 19 analog output ‘blue’ current complementary analog output

GRN 21 analog output ‘green’ current analog output

GRN_N 20 analog output ‘green’ current complementary analog output

RED 25 analog output ‘red’ current analog output

RED_N 24 analog output ‘red’ current complementary analog output

RSET 22 analog input/outp ut DAC full-scale current control resistor.

Pull down to ground by an external

1.2 k1 % resistor.

DDC

SCL 11 single-ended 5 V

open-drain DDC I/O 5 V sink-side DDC clock I/O. Pulled up by

1.2 k external resistor to 5 V.

SDA 13 single-ended 5 V

open-drain DDC I/O 5 V sink-side DDC data I/O. Pulled up by

1.2 k external resistor to 5 V.

Monitor-side sync

HSYNC 15 single-ended 3.3 V

TTL output horizontal sync signal to monitor; serial

resistance of 36  is recommended.

VSYNC 14 single-ended 3.3 V

TTL output vertical sync signal to monitor; serial

resistance of 36  is recommended.

JTAG

TCK 5 input JTAG clock input

TDO 6 output JTAG data output

TMS 8 input JTAG mode select input

TRST_N 9 input JTAG reset (active LOW) input

TDI 10 input JTAG data input

Table 2. Pin description …continued

Symbol Pin Type Description

Product data sheet Rev. 4 — 8 Oct ober 2012 6 of 30

NXP Semiconductors PTN3392

2-lane DisplayPort to VGA adapter IC

[1] HVQFN48 package die supply ground is connected to both GND pins and exposed center pad. GND pins

7, 23, 28, 29, 41, 45, 48, and exposed center pad must be connected to supply ground for proper device

operation. For enhanced thermal, electrical, and board level performance, the exposed pad needs to be

soldered to the board using a corresponding thermal pad on the board and for proper heat conduction

through the board, thermal vias need to be incorporated in the PCB in the thermal pad region.

Stra p pins, S[3:0]

S0 33 input Open (internal pull-down) = logic 0:

Implement VGA-side monitor detect

according to VESA DisplayPort Standard

v1.1a sections 7 and 8 (Ref. 1). Refer to

Section 7.4.1 for S0 = 0 behavior.

HIGH (external pull-up) = logic 1:

Set HPD HIGH upon VGA monitor

detection; set HPD LOW upon VGA monitor

detachment. Refer to Section 7.4.2 for

S0 = 1 behavior.

Default S0 = 0 for standard compliance.

S1 34 input reserved; leave open-circuit (default internal

pull-down)

S2 35 input Open (internal pull-down) = logic 0 to set

default I2C speed to 50 kbit/s for

PTN3392BS/F3, 100 kbit/s for

PTN3392BS/F1, PTN3392BS/F2.

HIGH (external pull-up) = logic 1, to se t

default I2C speed to 10 kbit/s.

This pin may be left open-circuit (internal

pull-down) or tied to VDD according to the

desired default I2C speed. See more

explanation in Table 3 about S2 pin setting

and DPCD register 00109h.

S3 36 input reserved; leave open-circuit (default internal

pull-down)

Miscellaneous

RESET_N 1 input Hardware reset input (active LOW); internal

pull-up. A capacitor must be connected

between this pin and ground. A 1 F capacitor

is recommended.

CLK_O 2 output DisplayPort receiver test clock output

LDOCAP_CORE 30 power 1.8 V digital core supply decoupling

OSC_IN 26 input crystal oscillator input

OSC_OUT 27 output crystal oscillator output

LDOCAP_AUX 38 power 1.8 V AUX supply decoupling

RRX 42 input Receiver termination resistance control. A

12 k resistor must be connected between

this pin and LDOCAP_AUX (pin 38).

Table 2. Pin description …continued

Symbol Pin Type Description

Product data sheet Rev. 4 — 8 Oct ober 2012 7 of 30

NXP Semiconductors PTN3392

2-lane DisplayPort to VGA adapter IC

7. Functional description

Referring to Figure 1 “Functional diagram”, the PTN3392 converts the DisplayPort

AC-coupled high speed differential signaling protocol into a VESA VSIS 1.2 compliant

analog VGA signaling. The PTN3392 integrates a DisplayPort receiver (according to

VESA DisplayPort v1.1a specification, Ref. 1) and a high-speed triple 8-bit video

digital-to-analog converter that supports display resolution from VGA to WUXGA (see

Table 4 “Display resolution and pixe l clock ra te ”), up to a pixel clo ck rate of 24 0 MHz. The

PTN3392 supports one or two DisplayPort v1.1a Main Link lanes operating at either in

2.7 Gbit/s or 1.62 Gbit/s per lane. The PTN3392 can dr ive up to 100 feet of analog video

cable.

The DisplayPort receiver comprises the following functional blocks:

•Main Link

•AUX CH (Auxiliary Channel)

•DPCD (DisplayPort Configuration Data)

•Monitor detection

•EDID handling

•Video DAC

The RGB video data with corresponding synchronization references is extracted from the

main stream video data. Main stream video attribute information is also extracted. This

information is inserted once per video frame during the vertical blanking period by the

DisplayPort source. The attributes describe the main video stream format in terms of

geometry, timing, and color format. The original clock and video stream are derived from

these main link data.

The PTN3392 internal DPCD registers can be accessed by the source via the auxiliary

channel. The monitor’s DDC control bus may also be controlled via the auxiliary channel.

A bridging conversion block translates the input DisplayPort auxiliary channel signals from

the source side to the DDC signals on the sink side. The PTN3392 passes through

sink-side status change ( e.g., hot- plug e vents) to the so ur ce side, thr ou gh HPD in te rr upts

and DPCD registers.

7.1 DisplayPort Main Link

The DisplayPort main link consist s of doub ly terminated, AC-coupled differential pair . The

50  internally calibrated termination resistors are integrated inside PTN3392.

The PTN3392 supports HBR at 2.7 Gbit/s and RBR at 1. 62 G bit/s per lane.

7.2 DisplayPort auxiliary channel

The AUX CH is a half-duplex, bidirectional channel between DisplayPort transmitter and

receiver. It consists of one differential pair transporting self-clocked da ta at 1 Mbit/s. The

PTN3392 integrates the AUX CH replier (or slave), and responds to transactions initiated

by the DisplayPort so ur ce AUX CH requ e ste r (o r ma ste r ).

The AUX CH uses the Manchester-II code for the self-clocked transmission of signals;

every ‘zero’ is represented by LOW-to-HIGH transition, and ‘one’ represented by

HIGH-to-LOW transition, in the middle of the bit time.

Product data sheet Rev. 4 — 8 Oct ober 2012 8 of 30

NXP Semiconductors PTN3392

2-lane DisplayPort to VGA adapter IC

7.3 DPCD registers

DPCD registers that are part of the VESA DisplayPort v1.1a are described in detail in

Ref. 1. The following paragraphs only describe the specific implementation by PTN3392.

The PTN3392 DisplayPort receiver capability and status information about the link are

reported by DisplayPort Configuration Data (DPCD) registers, when a DisplayPort source

issues a read command on the AUX CH. The DisplayPort source device can also write to

the link configuration field of DPCD to configure and initialize the link. The DPCD is

DisplayPort v1.1a compliant.

It is the responsibility of the host to only issue commands within the capability of the

PTN3392 as defined in the ‘Receiver Capability Field’ in order to prevent undefined

behavior. PTN3392 specific DPCD registers are listed in Table 3.

7.3.1 PTN3392 specific DPCD register settings

Table 3. PTN3392 specific DPCD registers

DPCD

Reset value Read/write

over AUX CH

Receiver Capability Field

0000Bh RECEIVE_PORT1_CAP_1. ReceiverPort1 Capability_1. 00h read only

0000Ch I2C-bus speed control capabilities bit map. The bit values in this register are

assigned to I2C-bus speeds as follows:

Bits 7:0

0000 0001b = 1 kbit/s; supported by PTN3392

0000 0010b = 3 kbit/s; supported by PTN3392

0000 0100b = 10 kbit/s; supported by PTN3392

0000 1000b = 100 kbit/s; supported by PTN3392

0001 0000b = 400 kbit/s; not supported by PTN3392

0010 0000b = 1 Mbit/s; not supported by PTN3392

0100 0000b = reserved

1000 0000b = 50 kbit/s; supported by PTN3392BS/F3

1000 0000b = reserved in PTN3392BS/F1, PTN3392BS/F2

8Fh read only

Product data sheet Rev. 4 — 8 Oct ober 2012 9 of 30

NXP Semiconductors PTN3392

2-lane DisplayPort to VGA adapter IC

[1] Byte fields that are not explicitly listed are by definition reserved (‘RES’) and their default value is 0h.

Link Configuration Field

00109h I2C-bus speed control/status bit map. Bit values in this register are assigned to

I2C-bus speeds as follows:

Bits 7:0

0000 0001b = 1 kbit/s; supported by PTN3392

0000 0010b = 3 kbit/s; supported by PTN3392

0000 0100b = 10 kbit/s; supported by PTN3392

0000 1000b = 100 kbit/s; supported by PTN3392

0001 0000b = 400 kbit/s; not supported by PTN3392

0010 0000b = 1 Mbit/s; not supported by PTN3392

0100 0000b = reserved

1000 0000b = 50 kbit/s; supported by PTN3392BS/F3

1000 0000b = reserved in PTN3392BS/F1, PTN3392BS/F2

Default value: 1000 0000b (50 kbit/s) for PTN3392BS/F3

Default value: 0000 1000b (100 kbit/s) for PT N3392BS/F1, PTN3392BS/F2

See also behavior of pin S2 in Table 2.

S2 setting read/write

Automated testing sub-field (optional)

00218h to

0027Fh Not supp orted.

Branch device specific field

00500h BRANCH_IEEE_OUI 7:0

Branch vendor 24-bit IEEE OUI.

NXP OUI = 00

00h read only

00501h BRANCH_IEEE_OUI 15:8

NXP OUI = 60 60h read only

00502h BRANCH_IEEE_OUI 23:16

NXP OUI = 37 37h read only

00503h ID string = 3392N2 33h re ad only

00504h 33h read only

00505h 39h read only

00506h 32h read only

00507h 4Eh re ad only

00508h 32h read only

00509h Hardware revision level v1.2 12h re ad only

0050Ah,

0050Bh Major revision level (example: v1.38),

Minor revision level (example: v1.38)01h,

26h read only

0050Ch to

005FFh RESERVED read only

Table 3. PTN3392 specific DPCD registers …continued

DPCD

Reset value Read/write

over AUX CH

Product data sheet Rev. 4 — 8 Oct ober 2012 10 of 30

NXP Semiconductors PTN3392

2-lane DisplayPort to VGA adapter IC

7.3.2 I2C over AUX CH registers

7.3.2.1 I2C-bus speed control register (read only, 0000Ch)

Bit or bits are set to indicate I2C-bus speed control capabilities.

DisplayPort source reads register 0000Ch and sets the I2C-bus speed according to the

DPCD register 00109h setting. The PTN3392 then ad apts it s I2C-bus bit rate to the speed

set by the DisplayPort source.

7.3.2.2 I2C-bus speed control/status register (read/write, 00109h)

Bit values in this register are assigned to I2C-bus speeds.

Prior to software writing to this register, PTN3392 defaults to the I2C-bus speed (either

50 kbit/s or 10 kbit/s) selected by the S2 pin (Table 2).

On read, the PTN3392 returns a value set to indicate the speed currently in use.

On write, software provides a mask to limit the speeds to be enabled:

•The PTN3392 uses the slowest speed ena ble d by the mask and th e PTN3392 sp ee d

capabilities.

•If the result of the mask with the speed capabilities is 0000 0000b, then the PTN3392

keeps the S2 setting I2C-bus speed that it is using before the software write (i.e., no

change).

Some specific examples are listed below for clarification purposes:

•If the source writes 11111111b, the PTN3392 uses the lowest speed of 1 kbit/s.

•If the source writes 0000 1100b, the PTN3392 uses the lower of 10 kbit/s and

100 kbit/s, i.e., 10 kbit/s.

•If the source writes 0011 0000b, the PTN3392 would stay using the same I2C-bus

speed that it is using before the software write (i.e., no change).

For DDC communicat ion, the PTN3392 generates defer responses to the source while the

I2C-bus transfer is taking place as specified in the DisplayPort standard v1.1a. Note that

when the I2C-bus bit rate is set to 1 kbit/s, each bit takes 1 ms. One byte including

I2C_ACK takes 9 ms. Given this, the DisplayPort source should expect over

20 I2C_DEFER’s wh en requesting to read a byte over I2C-bus at the slowes t rate.

Product data sheet Rev. 4 — 8 Oct ober 2012 11 of 30

NXP Semiconductors PTN3392

2-lane DisplayPort to VGA adapter IC

7.4 Monitor detection

The PTN3392 assumes 75  double termination, as shown in Figure 6. The load sensing

circuit of the PTN3392 senses a 37.5  or 75  termination respectively, when the

monitor is connected or disconnected. The load-sensing ci rcuit is active during the vertical

blanking period (never during the horizontal retrace period), so that there will be no

disturbance to the screen image caused by the load-sensing circuit.

Upon detection of an RGB monitor being connected, the PTN3392 dynamically updates

DPCD register 00200h and 00204h, to indicate the presence of a sink device being

connected (s ee Section 7.3). After updating the DPCD register 00200h, the PTN3392

generates an IRQ request on HPD.

The PTN3392 implements two different ways to handle the HPD signal. The HPD

behavior is governed by the S0 pin’s value after the reset and initialization sequence is

completed (see Figure 3).

•If S0 is tied LOW, HPD is driven HIGH irrespective of whether a VGA monitor is

detected.

•If S0 pin is tied HIGH, HPD is only driven HIGH when a monitor is detected.

Fig 3. Pin S0 behavior

002aaf365

HPD = 0;

initialize

Power-up

HPD = 1

monitor

detected?

yes

SINK_COUNT = 0

S0 = LOW

HPD = 0;

initialize

Power-up

S0 = HIGH

monitor

detected?

SINK_COUNT = 1

monitor

detected

changed?

yes

generate IRQ_HPD pulse

yes

SINK_COUNT = 0

HPD = 0

SINK_COUNT = 1

HPD = 1

monitor

detected

changed?

no yes

Product data sheet Rev. 4 — 8 Oct ober 2012 12 of 30

NXP Semiconductors PTN3392

2-lane DisplayPort to VGA adapter IC

7.4.1 S0 = logic 0

If S0 is left open-circuit (internal pull-down) (DisplayPort v1.1a compliant behavior),

PTN3392 behav es as stated in VESA DisplayPort v1.1a, sections 7 and 8. PTN3392 will

keep HPD LOW during its internal initialization sequence after power-up. It will then

update DPCD register SINK_COUNT to the expected value, depending if a VGA monitor

is detected or not, and will then assert HPD HIGH whatever is the value of SINK_COUNT

will update the SINK_COUNT register accordingly, set

DOWNSTREAM_PORT_STATUS_CHANGED register bit to 1 and generate IRQ_HPD

pulse to signal the source about the status change. Refer to Figure 3, S0 = LOW

flowchart.

7.4.2 S0 = logic 1

If S1 is tied to HIGH with external pull-up (best interoperability behavior), the PTN3392 will

keep HPD LOW during its internal initialization sequence after power-up. It will then wait

for a VGA monitor to be connected downstream before asserting HPD HIGH to force

source waiting for a VGA monitor before startin g protocol negotiations. If a VGA monitor is

disconnected during normal operations, PTN3392 will assert HPD LOW so that the source

will consider that no sink device is connected anymore. Refer to Figure 3, S0 = HIGH

flowchart.

7.5 EDID handling

Figure 4 shows a DisplayPort-to-analog video converter (or dongle) situated between the

DisplayPort source and a VGA monitor. The PTN3392 co nverts a DP I2C Over AUX

request to I2C on the monitor's DDC bus. The monitor's EDID read dat a is then returned to

the DP source via an I2C Over AUX response issued by the PTN3392.

It is the responsibility of th e sou rce to only choo se video mo de s wh ich ar e decla red in the

EDID and to adjust the DisplayPort link capabilities (link rate and lane count) to provide

the necessary video bandwidth. The PTN3392 does not cache or modify the EDID to

match the capabilities of the DisplayPort link data.

If the DisplayPort source drives display modes that are not sp ecified in the EDID mode

list, the PTN3392 will not detect such conditions, and will display at its output what it is

presented by the DisplayPort source.

Fig 4. DisplayPort to VGA adapter IC (dongle) sits between the DisplayPort source and a

VGA monitor with EDID

DP Tx

002aae039

box-to-box

DisplayPort

source device

DP Rx

with DPCD VIDEO DAC

DisplayPort to VGA adapter IC

box-to-box

legacy VGA DISPLAY

WITH EDID

sink device

Product data sheet Rev. 4 — 8 Oct ober 2012 13 of 30

NXP Semiconductors PTN3392

2-lane DisplayPort to VGA adapter IC

7.6 Triple 8-bit video DACs and VGA outputs

The triple 8-bit video DACs output a 700 mV (peak-to-peak) analog video output signal

into 37.5  load, as is the case of a doub ly te rminated 7 5  cable. The DAC is cap able of

supporting the maximum pixel rate supported by a two-lane DP link (240 MHz).

The PTN3392 generates the RGB video timing and synchr oniza tion signals, RGB signa ls

are then sent to the DACs for conversion to analog signals.

7.6.1 DAC reference resistor

An external reference resistor must be connecte d be twe en p in RSET an d a nalo g g ro und .

This resistor sets the reference current which determines the analog output level, and is

specified as 1.2 k with a 1 % tolerance. This value allows a 0.7 V (peak-to-peak) output

into a 37.5  load, such as a double-terminated 75  coaxial cable.

8. Power-up and reset

PTN3392 has built- in po we r- on res et cir cuit ry wh ich autom at ica lly seq ue n ce s the part

through reset and initialization.

For proper behavior , a capacitor should be connected from the RESET_N pin to ground to

slow down the internal reset pulse; 1 F capacitance is recommended.

Before link is established, the PTN3392 holds VSYNC and HSYNC signals LOW and

blanks the RGB signals.

While the PTN3392 performs initialization,

•The HPD signal is driven LOW, to indicate to the DisplayPort source that the

PTN3392 is not ready for link communication

•The RED, GRN, BLU and complementary outpu ts (RED_N , GRN_N, BLU_N) are

disabled

•The VSYNC and HSYNC outputs are driven LOW

xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x xxxxxxxxxxxxxx xxxxxxxxxx xxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx

xxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxx

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Product data sheet Rev. 4 — 8 October 2012 14 of 30

NXP Semiconductors PTN3392

2-lane DisplayPort to VGA adapter IC

9. Application design-in information

(1) 1 F is recommended.

(2) Example of external DC-to-DC regulator.

Fig 5. Application dia gram

002aae252

PTN3392

1.2 kΩ

1 %

RED_N

GND_DAC

RSET

GRN

GRN_N

BLU_N

VDD_DAC

BLU

HSYNC

VSYNC

SDA

VDDD

GNDD

OSC_OUT

OSC_IN

RED

VDDA

LDOCAP_AUX

AUX_P

AUX_N

GNDA

RRX

ML0_P

ML0_N

GNDA_DP

ML1_P

ML1_N

GNDA_DP

VDD(3V3)AUX

27 MHz

0.1 μF

RESET_N

CLK_O

HPD

VDDA_DP

TCK

TDO

GND_IO

TMS

TRST_N

TDI

SCL

VDD_IO

100 kΩ

LANE0p

GND

LANE0n

LANE1p

GND

LANE1n

LANE2p

GND

LANE2n

LANE3p

GND

LANE3n

GND_DOWN1

GND_DOWN2

AUXp

GND

AUXn

HPD

RTN

DP_PWR

1 MΩ

VDD(3V3)

0.1 μF

VDD(3V3)

10 μF

6.3 V

1.2 kΩ

VDD(5V)

SDA

GRN

BLUE_RTN

BLUE

VDD(5V)

n.c.

GND

SCL

GND

RED_RTN

n.c.

RED

GRN_RTN

VGA connector

VDD_CONN_5V

VDD(3V3)

2.2 μF

IN 5

SHDN 3

GND

OUT

CNEG

CPOS

DC/DC

0.22 μF

2.2 μF

VDD(5V)

VDD_CONN_5V

(2)

10 μF

6.3 V

GND_C

DP CONN

1 μF

0.1 μF

VDD(3V3)AUX

VDD(3V3)

(1)

VDD(3V3)

20 pF

LDOCAP_CORE

VDD(3V3)

12 kΩ 47 nH

3.3 pF

75 Ω

47 nH

3.3 pF

75 Ω

47 nH

3.3 pF

75 Ω

10 pF

2.2 μF

0.1 μF

VDD(3V3)

0.1 μF

36 Ω

47 Ω at

100 MHz

47 Ω at

100 MHz

47 Ω at

100 MHz

VDD(3V3)

Product data sheet Rev. 4 — 8 Oct ober 2012 15 of 30

NXP Semiconductors PTN3392

2-lane DisplayPort to VGA adapter IC

9.1 Display resolution

Table 4 lists some example display resolutions and clock rates that PTN3392 supports.

(Refer to Footnote 1 on page 2.)

The available bandwidth over a 2-lane HBR DisplayPort v1.1a link limits pixel clock rate

support to:

•240 MHz at 6 bpc

•180 MHz at 8 bpc

9.2 Power supply filter

All supply pins can be tied to a single 3.3 V power source. Sufficient decoupling

capacitance to ground should be connected from each VDD pin directl y to ground to filter

supply noise. (Refer to Figure 5 “Application diagram”.)

Table 4. Display resolution and pixel clock rate

Display

type Active video Total frame Bits per

pixel Frame rate

(Hz) Pixel clock

(MHz) Dat a rate

(Gbit/s)

Horizontal Vertical Horizontal Vertical

VGA 640 480 800 525 24 59.94 25.175 0.8

SVGA 800 600 1056 628 24 60.32 40.002 1.2

XGA 1024 768 1344 806 24 60 64.996 1.9

XGA+ 1152 864 1520 806 24 60 81.806 2.45

WXGA 1280 768 1664 897 24 60 79.672 2.39

WXGA+ 1400 900 1848 934 24 60 103.562 3.11

XGA+ 1152 864 1520 806 24 60 81.806 2.45

1366 768 1792 798 24 60 85.801 2.57

SXGA 1280 1024 1688 1066 24 60.02 108.000 3.2

SXGA 1280 1024 1728 1072 24 85 157.455 4.72

SXGA+ 1400 1050 1864 1089 24 60 121.794 3.65

1600 900 2112 934 24 60 118.356 3.55

WSXGA+ 1680 1050 2240 1089 24 60 146.362 4.39

UXGA 1600 1200 2160 1250 24 60 162.000 3.9

UXGA 1600 1200 1760 1243 24 75 164.076 4.92

UXGA 1600 1200 2160 1250 18 85 229.500 5.16

FHD 1920 1080 2200 1125 24 60 148.500 4.46

WUXGA 1920 1200 2592 1245 18 59.885 193.251 4.35

WUXGA 1920 1200 2080 1235 24 59.95 154.000 4.62

QXGA 2048 1536 2144 1555 24 49.266 164.249 4.9

QWXGA 2048 1152 2720 1188 24 49.979 161.500 4.84

QWXGA 2048 1152 2208 1185 24 59.909 156.751 4.7

Product data sheet Rev. 4 — 8 Oct ober 2012 16 of 30

NXP Semiconductors PTN3392

2-lane DisplayPort to VGA adapter IC

9.3 DAC terminations

We recommend the DAC outputs to use 75  double termination. Figure 6 shows an

example of VGA dongle application. A 75  termination is used to terminate inside the

dongle, and another 75  termination is typically used inside the RGB monitor. The load

sensing mechanism assumes this double termination.

10. Limiting values

[1] Human Body Model: ANSI/EOS/ESD-S5.1-1994, standard for ESD sensitivity testing, Human Body Model - Component level;

Electrostatic Discharge Association, Rome, NY, USA.

[2] Charged Device Model: ANSI/EOS/ESD-S5.3-1-1999, standard for ESD sensitivity testing, Charged Device Model - Component level;

Electrostatic Discharge Association, Rome, NY, USA

[3] IEC 61000-4-2, Level 4 (Ref. 4).

Fig 6. Recommended DAC terminations for PTN3392

002aae044

DAC RED, GRN, BLU

RED_N, GRN_N, BLU_N

DONGLE

PCB

EMI filter

75 Ω

VGA cable

double-ended

termination

MONITOR

75 Ω

Table 5. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

VDDA analog supply voltage 0.3 +3.8 V

VDDD digital supply voltage 0.3 +4.6 V

VIinput voltage 3.3 V CMOS inputs 0.3 VDD +0.5 V

Tstg storage temperature 65 +150 C

VESD electrostatic discharge voltage HBM [1] - 7000 V

CDM [2] - 1000 V

IEC contact discharge to signal

pins (to GND) [3] - 8000 V

Product data sheet Rev. 4 — 8 Oct ober 2012 17 of 30

NXP Semiconductors PTN3392

2-lane DisplayPort to VGA adapter IC

11. Recommended operating conditions

[1] Input signals to these pins must be AC-coupled.

12. Characteristics

12.1 Current consumption, power dissipation and thermal characteristics

Table 6. Operating conditions

Symbol Parameter Conditions Min Typ Max Unit

VDDA analog supply voltage 3.0 3.3 3.6 V

VDDD digital supply voltage 3.0 3.3 3.6 V

VIinput voltage 3.3 V CMOS inputs 0 3.3 3.6 V

SDA and SCL inputs with respect

to ground 05 5.5V

VI(AV) average input voltage DC value at

ML_LANE0+, ML_LANE0,

ML_LANE1+, ML_LANE1,

AUX_CH+, AUX_CH inputs

[1] -0 - V

Rext(RSET) external resistance on pin RSET between RSET (pin 22) and GND - 1.2 1% - k

Tamb ambient temperature commercial gr ad e 0 - 85 C

Table 7. Current consumption, power dissipation and thermal characteristics

Symbol Parameter Conditions Min Typ Max Unit

IDD supply current normal operation,

UXGA / 162 MHz pixel clock -180-mA

IDD(stb) standby supply current Standby mode - 1 2 - mA

P power dissipation normal operation,

UXGA / 162 MHz pixel clock -600-mW

Rth(j-a) thermal resistance from junction

to ambie nt in free air for SOT619-1 - 35 - K/W

RPU pull-up resistance RESET_N pin; 0 V VIVDD 44 66 95 k

Rpd pull-down resistance S0 to S3 pins; 0 V VIVDD 44 66 95 k

Product data sheet Rev. 4 — 8 Oct ober 2012 18 of 30

NXP Semiconductors PTN3392

2-lane DisplayPort to VGA adapter IC

12.2 DisplayPort receiver main link

[1] Range is nominal 350 ppm. DisplayPort link RX does not require local crystal for link clock generation.

[2] Up to 0.5 % down spread is supported. Modulation frequency range of 30 kHz to 33 kHz must be supported.

[3] Informative; refer to Figure 7 for definition of differential voltage.

[4] tRX_EYE_m-mJT_CHP specifies the total allowable Deterministic Jitter (DJ).

[5] 1 tRX_EYE_CONN specifies the allowable Total Jitter (TJ).

[6] Common mode voltage is equal to Vbias_RX voltage.

[7] Total drive current of the input bias circuit when it is shorted to its ground.

[8] Maximum skew limit between different RX lanes of a DisplayPort link.

[9] Maximum skew limit between D+ and D of the same lane.

[10] Minimum CDR tracking bandwidth at the receiver when the input is repetition of D10.2 symbols without scrambling.

Table 8. DisplayPort receiver main link characteristics

Symbol Parameter Conditions Min Typ Max Unit

UI unit interval for high bit rate

(2.7 Gbit/s per lane) [1] - 370 - ps

for low bit rate

(1.62 Gbit/s per lane) [1] - 617 - ps

fDOWN_SPREAD link clock down spreading [2] 0.0- 0.5%

VRX_DIFFp-p differential input peak-to-pea k

voltage at RX package pins

for high bit rate [3] 120 - - mV

for reduced bit rate [3] 40 - - mV

tRX_EYE_CONN receiver eye time at RX-side

connector pins for high bit rate [4] 0.51 - - UI

for reduced bit rate [4][5] 0.25 - - UI

tRX_EYE_CHIP receiver eye time at RX

package pins for high bit rate [4] 0.47 - - UI

for reduced bit rate [4][5] 0.22 - - UI

tRX_EYE_m-mJT_CHP time between jitter median and

maximum median deviation

(package pins)

for high bit rate [4] - - 0.265 UI

for reduced bit rate [4][5] - - 0.39 UI

VRX_DC_CM RX DC common mode voltage [6] 0- 2.0V

IRX_SHORT RX short-circuit current limit [7] --50mA

LRX_SKEW total skew inter-pair; lane-to-lane skew

at RX package pins [8] - - 5200 ps

lane intra-pair skew at RX

package pins;

for high bit rate [9] - - 100 ps

for reduced bit rate [9] - - 300 ps

fRX_TRACKING_BW jitter tracking bandwidth [10] 20 - - MHz

Product data sheet Rev. 4 — 8 Oct ober 2012 19 of 30

NXP Semiconductors PTN3392

2-lane DisplayPort to VGA adapter IC

12.3 DisplayPort receiver AUX CH

[1] Results in the bit rate of 1 Mbit/s including the overhead of Manchester II coding.

[2] Each pulse is a ‘0’ in Manchester II code.

[3] Period after the AUX CH STOP condition for which the bus is parked.

[4] Maximum allowable UI variation within a single transaction at connector pins of a transmitting device. Equal to 24 ns maximum. The

transmitting device is a source device for a request transaction and a sink device for a reply transaction.

[5] Maximum allowable UI variation within a single transaction at connector pins of a re ceiving device. Equal to 30 ns maximum. The

transmitting device is a source device for a request transaction and a sink device for a reply transaction.

[6] VAUX_DIFFp-p = 2 VAUX+ VAUX.

[7] Common-mode voltage is equal to Vbias_TX (or Vbias_RX) voltage.

[8] Steady-state common-mode voltage shift between transmit and receive modes of operation.

[9] Total drive current of the transmitter when it is shorted to its ground.

[10] The AUX CH AC coupling capacitor placed both on the DisplayPort source and sink devices.

pre-emphasis = 20Log(VDIFF_PRE /V

DIFF)

Fig 7. Definitions of pre-emphasis and differential voltage

002aaf363

VD+

VCM

VD−

VDIFF_PRE VDIFF

Table 9. DisplayPort receiver AUX CH characteristics

Symbol Parameter Conditions Min Typ Max Unit

UI unit interval AUX [1] 0.4 0.5 0.6 s

NPRECHARGE_PULSES number of precharge pulses [2] 10 - 16

tAUX_BUS_PARK AUX CH bus park time [3] 10 - - ns

tjit(cc) cycle-to-cycle jitter time transmitting device [4] - - 0.04 UI

receiving device [5] - - 0.05 UI

VAUX_DIFFp-p AUX differential peak-to-peak

voltage transmitting device [6] 0.39 - 1.38 V

receiving device [6] 0.32 - 1.36 V

RAUX_TERM(DC) AUX CH termination DC resistance informative - 100 - 

VAUX_DC_CM AUX DC common-mode voltage [7] 0- 2.0V

VAUX_TURN_CM AUX turnaround common-mode

voltage [8] --0.4V

IAUX_SHORT AUX short-circuit current limit [9] --90mA

CAUX AUX AC coupling capacitor [10] 75 - 200 nF

Product data sheet Rev. 4 — 8 Oct ober 2012 20 of 30

NXP Semiconductors PTN3392

2-lane DisplayPort to VGA adapter IC

12.4 HPD characteristics

12.5 DDC characteristics

[1] VCC is the pull-up voltage for DDC.

12.6 DAC

Table 10. HPD characteristics

Symbol Parameter Conditions Min Typ Max Unit

Output characteristics

VOH HIGH-level output voltage IOH =2mA 2--V

VOL LOW-level output voltage IOL =2mA - - 0.8 V

IOSH HIGH-level short-circuit output

current drive HIGH;

cell connected to ground --129mA

IOSL LOW-level short-circuit output

current drive LOW;

cell connected to VDD

--126mA

Table 11. DDC characteristics

VCC = 4.5 V to 5.5 V.[1]

Symbol Parameter Conditions Min Typ Max Unit

Input characteristics

VIH HIGH-level input voltage 2 - 5.5 V

VIL LOW-level input voltage 0.5 - +0.8 V

VI(hys) hysteresis of input voltage 0.1 VDD -- V

ILI input leakage current VI=5.5V - - 1A

Output characteristics

IOL LOW-level output current VOL =0.4V 3.0 - - mA

IO(sc) short-circuit output current drive LOW;

cell connected to VDD

--40.0mA

Cio input/output capacitance VI= 3 V or 0 V; VDD =3.3V - 6 7 pF

VI= 3 V or 0 V; VDD =0V - 6 7 pF

Table 12. DAC characteristics

Symbol Parameter Conditions Min Typ Max Unit

Nres(DAC) DAC resolution - - 8 bit

fclk clock frequency - - 240 MHz

Io(DAC) DAC output current variation DAC-to-DAC - - 4 %

INL integral non-linearity 10.5 +1 LSB

DNL differential non-linearity 1- +1LSB

Vo(DAC) DAC output voltage 0 - 1.25 V

Co(DAC) DAC output capacitance - 3.5 - pF

ct(DAC) DAC crosstalk between DAC outputs - 54 - dB

Product data sheet Rev. 4 — 8 Oct ober 2012 21 of 30

NXP Semiconductors PTN3392

2-lane DisplayPort to VGA adapter IC

12.7 HSYNC, VSYNC characteristics

[1] The parameter values specified are simulated and absolute values.

12.8 Strap pins S[3:0]

12.9 JTA G and RESET_N

Table 13. HSYNC and VSYNC characteristics

Symbol Parameter Conditions Min Typ Max Unit

Output characteristics

VOH HIGH-level output voltage I OH =8mA 2 - - V

VOL LOW-level output voltage IOL =8mA - - 0.8 V

IOSH HIGH-level short-circuit output current drive HIGH; cell connected to ground [1] - - 129.0 mA

IOSL LOW-level short-circuit output current drive LOW; cell connected to VDD [1] - - 126.0 mA

Table 14. Strap pins S[3:0] characteristics

Symbol Parameter Conditions Min Typ Max Unit

Input characteristics

VIH HIGH-level input voltage 0.7 VDD -- V

VIL LOW-level input voltage 0.3 VDD V

Weak pull-down characteristic s

Ipd pull-down current VI=V

DD 25.0 50.0 95.0 A

Table 15. JTAG and RESET_N characteristics

Symbol Parameter Conditions Min Typ Max Unit

Input characteristics

VIH HIGH-level input voltage 0.7 VDD -- V

VIL LOW-level input voltage 0.3 VDD V

Output characteristics

VOH HIGH-level output voltage RESET_N; IOH =4mA 2 - - V

JTAG; IOH =2mA 2 - - V

VOL LOW-level output volt age RESET_N; IOL =4mA - - 0.8 V

JTAG; IOL =2mA - - 0.8 V

Product data sheet Rev. 4 — 8 Oct ober 2012 22 of 30

NXP Semiconductors PTN3392

2-lane DisplayPort to VGA adapter IC

13. Package outline

Fig 8. Package outline SOT619-1 (HVQFN48)

0.51

A1Eh

UNIT ye

0.2

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 7.1

6.9

5.25

4.95

7.1

6.9 5.25

4.95

5.5

0.30

0.18

0.05

0.00 0.05 0.1

DIMENSIONS (mm are the original dimensions)

SOT619-1 MO-220 - - -- - -

0.5

0.3

0.1

0.05

0 2.5 5 mm

scale

SOT619-1

HVQFN48: plastic thermal enhanced very thin quad flat package; no leads;

48 terminals; body 7 x 7 x 0.85 mm

A(1)

max.

AA1c

detail X

y1C

13 24

48 37

01-08-08

02-10-18

terminal 1

index area

terminal 1

index area

1/2 e

1/2 e AC

E(1)

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

D(1)

Product data sheet Rev. 4 — 8 Oct ober 2012 23 of 30

NXP Semiconductors PTN3392

2-lane DisplayPort to VGA adapter IC

14. Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note AN10365 “Surface mount reflow

soldering description”.

14.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both

the mechanical and the electrical connection. There is no single soldering method that is

ideal for all IC packages. Wave soldering is often prefe rred when through-hole and

Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not

suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

14.2 Wave and reflow soldering

W ave soldering is a joinin g technology in which the joint s are made by solder coming from

a standing wave of liquid solder. The wave soldering process is suit able for the following:

•Through-hole components

•Leaded or leadless SMDs, which are glued to the surface of the printed circu it board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solder lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reflow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperature profile. Leaded packages,

packages with solder balls, and leadless packages are all reflow solderable.

Key characteristics in both wave and reflow soldering are:

•Board specifications, including the board finish, solder masks and vias

•Package footprints, including solder thieves and orientation

•The moisture sensitivity level of the packages

•Package placement

•Inspection and repair

•Lead-free soldering versus SnPb soldering

14.3 Wave soldering

Key characteristics in wave soldering are:

•Process issues, such as application of adhesive and flux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

•Solder bath specifications, including temperature and impurities

Product data sheet Rev. 4 — 8 Oct ober 2012 24 of 30

NXP Semiconductors PTN3392

2-lane DisplayPort to VGA adapter IC

14.4 Reflow soldering

Key characteristics in reflow soldering are:

•Lead-free ve rsus SnPb soldering; note th at a lead-free reflow process usua lly leads to

higher minimum peak temperatures (see Figure 9) than a SnPb process, thus

reducing the process window

•Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

•Reflow temperature profile; this profile includes preheat, reflow (in which the board is

heated to the peak temperature) and cooling down. It is imperative that the peak

temperature is high enoug h for the solder to make reliable solder joint s (a solder paste

characteristic). In addition, the peak temperature must be low enough that the

packages and/or boards are not damaged. The peak temperature of the package

depends on package thickness and volume and is classified in accordance with

Table 16 and 17

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reflow

soldering, see Figure 9.

Table 16. SnPb eutectic process (from J-STD-020C)

Package thickness (mm) Package reflow temperature (C)

Volume (mm3)

< 350  350

< 2.5 235 220

 2.5 220 220

Table 17. Lead-free process (from J-STD-020C)

Package thickness (mm) Package reflow temperature (C)

Volume (mm3)

< 350 350 to 2000 > 2000

< 1.6 260 260 260

1.6 to 2.5 260 250 245

> 2.5 250 245 245

Product data sheet Rev. 4 — 8 Oct ober 2012 25 of 30

NXP Semiconductors PTN3392

2-lane DisplayPort to VGA adapter IC

For further information on temperature profiles, refer to Application Note AN10365

“Surface mount reflow soldering description”.

15. Abbreviations

MSL: Moisture Sensitivity Level

Fig 9. Temperature profiles for large and small components

001aac844

temperature

time

minimum peak temperature

= minimum soldering temperature

maximum peak temperature

= MSL limit, damage level

peak

temperature

Table 18. Abbreviations

Acronym Description

AUX CH Auxiliary Channel

BER Bit Error Rate

bpc bits per color

CDM Charged-Device Model

CMOS Complementary Metal-Oxide Semiconductor

DAC Digital-to-Analog Converter

DDC Data Display Channel

DJ Deterministic Jitter

DP DisplayPort (VESA)

DPCD DisplayPort Configuration Data

ECC Error Correction Code

EDID Extended Display Identification Data

ESD ElectroStatic Discharge

HBM Human Body Model

HBR High Bit Rate

HDCP High-bandwidth Digital Content Protection

HPD Hot Plug Detect

I2C-bus Inter-Integrated Circuit bus

IEC International Electrotechnical Commission

Product data sheet Rev. 4 — 8 Oct ober 2012 26 of 30

NXP Semiconductors PTN3392

2-lane DisplayPort to VGA adapter IC

16. References

[1] VESA DisplayPort Standard — Version 1, Revision 1a; January 11, 2008

[2] Display Data Channel Command Interface Standard — Version 1.1;

October 29, 2004

[3] Video Signal Standard (VSIS) — Version 1, Rev. 2; December 12, 2002

[4] IEC 61000-4-2, Electromagnetic compatibility (EMC) - Part 4-2: Testing and

measurement techniques — ElectroStatic Discharge (ESD) immunity test, edition

2.0, 2008-12

I/O Input/Output

LSB Least Significant Bit

MCCS Monitor Control Command Set (VESA)

MSB Most Significant Bit

QXGA Quad eXtended Graphics Array

RBR Reduced Bit Rate

RGB Red/Green/Blue

SSC Spread Spectrum Clocking

SVGA Super Video Graphics Array

SXGA Super eXtended Graphics Array

TJ Total Jitter

UI Unit Interval

UXGA Ultra eXten ded Graphics Array

VESA Video Electronics Standards Association

VGA Video Graphics Array

VSIS Video Signal Interface Standard

WUXGA Wide Ultra eXtended Graphics Array

XGA eXtended Graphics Array

Table 18. Abbreviations …continued

Acronym Description

Product data sheet Rev. 4 — 8 Oct ober 2012 27 of 30

NXP Semiconductors PTN3392

2-lane DisplayPort to VGA adapter IC

17. Revision history

Table 19. Revision history

Document ID Release date Data sheet status Change notice Supersedes

PTN3392 v.4 20121008 Product data sheet - PTN3392 v.3

Modifications: •Table 2 “Pin descriptio n”, description for S2 (pin 35), first paragraph: appended “for PTN3392BS/F3,

100 kbit/s for PTN3392BS/F1, PTN3392BS/F2”

•Table 3 “PTN3392 spe ci fi c DPCD reg isters”: added firmware-specific information

–register 0000Ch description: 100 0 0000 b: changed from “50 kbit/s; suppo rted by PTN3392”

to “50 kbit/s; supported by PTN3392BS/F3”;

added new line “1000 0000b = reserved in PTN3392BS/F1, PTN3392BS/F2”

–register 00109h description: 100 0 0000 b: changed from “50 kbit/s; supported by PTN3392”

to “50 kbit/s; supported by PTN3392BS/F3”;

added new line “1000 0000b = reserved in PTN3392BS/F1, PTN3392BS/F2”

–register 00109h description: Default value changed from “1000 0000b (50 kbit/s)”

to “1000 0000b (50 kbit/s) for PTN3392BS/F3”;

added new line “Default value: 0000 1000b (100 kbit/s) for PTN3392BS/F1, PTN3392BS/F2”

•Table 11 “DDC characteristics”: corrected ILI Max value from “10 A” to “1A”

PTN3392 v.3 20120808 Product data sheet - PTN3392 v.2

PTN3392 v.2 20100715 Product data sheet - PTN3392 v.1

PTN3392 v.1 20100 604 Product data sheet - -

Product data sheet Rev. 4 — 8 Oct ober 2012 28 of 30

NXP Semiconductors PTN3392

2-lane DisplayPort to VGA adapter IC

18. Legal information

18.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Definitions”.

[3] The product status of de vice(s) descr ibed in th is docume nt may have cha nged since this docume nt was publis hed and ma y dif fer in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

18.2 Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liab ility for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and tit le. A short data sh eet is intended

for quick reference only and shou ld not be rel ied u pon to cont ain det ailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conf lict with the short data sheet, the

full data sheet shall pre vail.

Product specificat ion — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to off er functions and qualities beyond those described in the

Product data sheet.

18.3 Disclaimers

Limited warr a nty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information. NXP Se miconductors takes no

responsibility for the content in this document if provided by an inf ormation

source outside of NXP Semiconductors.

In no event shall NXP Semiconductors be liable for any indirect, incidental ,

punitive, special or consequ ential damages (including - wit hout limitatio n - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggregate and cumulative liabil ity towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all informa tion supplied prior

to the publication hereof .

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors pro duct can reasonably be expected

to result in perso nal injury, death or severe property or environmental

damage. NXP Semiconductors and its suppliers accept no liability for

inclusion and/or use of NXP Semiconducto rs products in such equipment or

applications and ther efore such inclu sion and/or use is at the cu stomer’s own

risk.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty tha t such application s will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and ope ration of their applications

and products using NXP Semiconductors product s, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suit able and fit for the custome r’s applications and

products planned, as well as fo r the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

NXP Semiconductors does not accept any liabili ty related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessa ry

testing for th e customer’s applications and pro ducts using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by cust omer’s third party

customer(s). NXP does not accept any liability in this respect.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanent ly and irreversibly affect

the quality and reliability of the device.

Terms an d conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individua l agreement. In case an individual

agreement is concluded only the ter ms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

No offer to sell or license — Nothing i n this document may be interpreted or

construed as an of fer t o sell product s that is open for accept ance or t he grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

Document status[1][2] Product status[3] Definition

Objective [short] data sheet Development This document contains data fro m the objective specification fo r product development.

Preliminary [short] dat a sheet Qualification This document contains data fro m the preliminary specification.

Product [short] dat a sheet Production This document contains the product specification.

Product data sheet Rev. 4 — 8 Oct ober 2012 29 of 30

NXP Semiconductors PTN3392

2-lane DisplayPort to VGA adapter IC

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualified,

the product is not suitable for aut omo tive use. It i s neit her qua lif ied nor tested

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

non-automotive qualified products in automotive equipment or applications.

In the event that customer uses the product for design-in and use in

automotive applications to automot ive specifications and standard s, customer

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such automotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

NXP Semiconductors’ specifications such use shall be solely at customer’s

own risk, and (c) customer fully indemnifies NXP Semiconductors for any

liability, damages or failed product claims result ing from customer design and

use of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specif ications.

Translations — A non-English (translated) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

18.4 Trademarks

Notice: All referenced b rands, produc t names, service names and trademarks

are the property of their respect i ve ow ners.

19. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

NXP Semiconductors PTN3392

2-lane DisplayPort to VGA adapter IC

For more information, please visit: http://www.nxp.co m

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 8 October 2012

Document identifier: PTN3392

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

20. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1

2.1 VESA compliant DisplayPort v1.1a converter. . 1

2.2 DDC channel output. . . . . . . . . . . . . . . . . . . . . 1

2.3 Analog video output . . . . . . . . . . . . . . . . . . . . . 2

2.4 General features. . . . . . . . . . . . . . . . . . . . . . . . 2

3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

4 Ordering information. . . . . . . . . . . . . . . . . . . . . 3

5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3

6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4

7 Functional description . . . . . . . . . . . . . . . . . . . 7

7.1 DisplayPort Main Link. . . . . . . . . . . . . . . . . . . . 7

7.2 DisplayPort auxiliary channel . . . . . . . . . . . . . . 7

7.3 DPCD registers. . . . . . . . . . . . . . . . . . . . . . . . . 8

7.3.1 PTN3392 specific DPCD register settings . . . . 8

7.3.2 I2C over AUX CH registers. . . . . . . . . . . . . . . 10

7.3.2.1 I2C-bus speed control register (read only,

0000Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

7.3.2.2 I2C-bus speed control/status register

(read/write, 00109h) . . . . . . . . . . . . . . . . . . . . 10

7.4 Monitor detection . . . . . . . . . . . . . . . . . . . . . . 11

7.4.1 S0 = logic 0. . . . . . . . . . . . . . . . . . . . . . . . . . . 12

7.4.2 S0 = logic 1. . . . . . . . . . . . . . . . . . . . . . . . . . . 12

7.5 EDID handling . . . . . . . . . . . . . . . . . . . . . . . . 12

7.6 Triple 8-bit video DACs and VGA outputs . . . 13

7.6.1 DAC reference resistor. . . . . . . . . . . . . . . . . . 13

8 Power-up and reset . . . . . . . . . . . . . . . . . . . . . 13

9 Application design-in information . . . . . . . . . 14

9.1 Display resolution. . . . . . . . . . . . . . . . . . . . . . 15

9.2 Power supply filter . . . . . . . . . . . . . . . . . . . . . 15

9.3 DAC terminations . . . . . . . . . . . . . . . . . . . . . . 16

10 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 16

11 Recommended operating cond iti on s. . . . . . . 17

12 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 17

12.1 Current consumption, power dissipation and

thermal characteristics . . . . . . . . . . . . . . . . . . 17

12.2 DisplayPort receiver main link . . . . . . . . . . . . 18

12.3 DisplayPort receiver AUX CH. . . . . . . . . . . . . 19

12.4 HPD characteristics . . . . . . . . . . . . . . . . . . . . 20

12.5 DDC characteristics . . . . . . . . . . . . . . . . . . . . 20

12.6 DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

12.7 HSYNC, VSYNC characteristics. . . . . . . . . . . 21

12.8 Strap pins S[3:0]. . . . . . . . . . . . . . . . . . . . . . . 21

12.9 JTAG and RESET_N . . . . . . . . . . . . . . . . . . . 21

13 Package outline. . . . . . . . . . . . . . . . . . . . . . . . 22

14 Soldering of SMD packages. . . . . . . . . . . . . . 23

14.1 Introduction to soldering. . . . . . . . . . . . . . . . . 23

14.2 Wave and reflow soldering. . . . . . . . . . . . . . . 23

14.3 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . 23

14.4 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . 24

15 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 25

16 References. . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

17 Revision history . . . . . . . . . . . . . . . . . . . . . . . 27

18 Legal information . . . . . . . . . . . . . . . . . . . . . . 28

18.1 Data sheet status. . . . . . . . . . . . . . . . . . . . . . 28

18.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

18.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 28

18.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 29

19 Contact information . . . . . . . . . . . . . . . . . . . . 29

20 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30