16-Bit, Isolated Sigma-Delta Modulator, LVDS Interface AD7405 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM VDD1 VDD2 AD7405 MCLKIN+ BUF CLK DECODER CLK ENCODER (5MHz TO 20MHz) MCLKIN- REF VIN+ MDAT+ - ADC VIN- DATA ENCODER DATA DECODER MDAT- GND2 GND1 12536-001 5 MHz to 20 MHz external clock input rate 16 bits, no missing codes Signal-to-noise ratio (SNR): 88 dB typical Effective number of bits (ENOB): 14.2 bits typical Typical offset drift vs. temperature: 1.6 V/C Low voltage differential signaling (LVDS) interface On-board digital isolator On-board reference Full-scale analog input voltage range: 320 mV -40C to + 125C operating temperature range High common-mode transient immunity: >25 kV/s 16-lead, wide-body SOIC_IC, with increased creepage package Safety and regulatory approvals UL recognition 5000 V rms for 1 minute per UL 1577 CSA Component Acceptance Notice 5A VDE Certificate of Conformity DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 Maximum working insulation voltage (VIORM): 1250 VPEAK Figure 1. APPLICATIONS Shunt current monitoring AC motor controls Power and solar inverters Wind turbine inverters Data acquisition systems Analog-to-digital and opto-isolator replacements GENERAL DESCRIPTION The AD74051 is a high performance, second-order, - modulator that converts an analog input signal into a high speed, single-bit LVDS data stream, with on-chip digital isolation based on Analog Devices, Inc., iCoupler(R) technology. The AD7405 operates from a 4.5 V to 5.5 V (VDD1) power supply and accepts a differential input signal of 250 mV (320 mV full-scale). The differential input is ideally suited to shunt voltage monitoring in high voltage applications where galvanic isolation is required. The analog input is continuously sampled by a high performance analog modulator, and converted to a ones density digital output stream with a data rate of up to 20 MHz. The original information 1 can be reconstructed with an appropriate digital filter to achieve 88 dB SNR at 78.1 kSPS. The LVDS input/output can use a 3 V to 5.5 V supply (VDD2). The LVDS interface is digitally isolated. The LVDS interface technology, combined with monolithic transformer technology, means the on-chip isolation provides outstanding performance characteristics, superior to alternatives such as optocoupler devices. The AD7405 device is offered in a 16-lead, wide-body SOIC_IC package and has an operating temperature range of -40C to +125C. Protected by U.S. Patents 5,952,849; 6,873,065; and 7,075,329. Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 (c)2014 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD7405 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Terminology .................................................................................... 12 Applications ....................................................................................... 1 Theory of Operation ...................................................................... 13 Functional Block Diagram .............................................................. 1 Circuit Information.................................................................... 13 General Description ......................................................................... 1 Analog Input ............................................................................... 13 Revision History ............................................................................... 2 Differential Inputs ...................................................................... 14 Specifications..................................................................................... 3 Low Voltage Differential Signaling (LVDS) Interface ........... 14 Timing Specifications .................................................................. 4 Applications Information .............................................................. 15 Package Characteristics ............................................................... 5 Current Sensing Applications ................................................... 15 Insulation and Safety Related Specifications ............................ 5 Voltage Sensing Applications .................................................... 15 Regulatory Information ............................................................... 5 Input Filter .................................................................................. 16 DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 Insulation Characteristics .............................................................................. 6 Digital Filter ................................................................................ 16 Absolute Maximum Ratings............................................................ 7 Insulation Lifetime ..................................................................... 19 ESD Caution .................................................................................. 7 Outline Dimensions ....................................................................... 20 Pin Configuration and Function Descriptions ............................. 8 Ordering Guide .......................................................................... 20 Grounding and Layout .............................................................. 19 Typical Performance Characteristics ............................................. 9 REVISION HISTORY 11/14--Rev. 0 to Rev. A Change to Figure 1 ........................................................................... 1 Changes to Table 7 ............................................................................ 7 Changes to Ordering Guide .......................................................... 20 9/14--Revision 0: Initial Version Rev. A | Page 2 of 20 Data Sheet AD7405 SPECIFICATIONS VDD1 = 4.5 V to 5.5 V, VDD2 = 3 V to 5.5 V, VIN+ = -250 mV to +250 mV, VIN- = 0 V, TA = -40C to +125C, fMCLKIN 1 = 5 MHz to 20 MHz, tested with sinc3 filter, 256 decimation rate, as defined by Verilog code, unless otherwise noted. All voltages are relative to their respective ground. Table 1. Parameter STATIC PERFORMANCE Resolution Integral Nonlinearity 2 Differential Nonlinearity2 Offset Error2 Offset Drift vs. Temperature Symbol Min Gain Error Drift vs. VDD1 ANALOG INPUT Input Voltage Range SINAD Signal-to-Noise Ratio2 Total Harmonic Distortion2 Peak Harmonic or Spurious Noise2 Effective Number of Bits2 SNR THD SFDR ENOB 0.8 0.8 1.2 95 60 +320 +250 -200 to +300 45 0.05 0.01 14 DC Leakage Current Input Capacitance DYNAMIC SPECIFICATIONS Signal-to-Noise-and-Distortion Ratio2 2 12 0.99 0.75 3.8 3.1 -320 -250 Input Common-Mode Voltage Range Dynamic Input Current 1 2 0.2 1.6 1.3 50 0.2 0.2 0.2 65 40 0.6 Gain Error Drift vs. Temperature Power Dissipation Max 16 INL DNL Offset Drift vs. VDD1 Gain Error2 Noise Free Code Resolution2 ISOLATION TRANSIENT IMMUNITY2 LVDS I/O (ANSI-644) Differential Output Voltage Common-Mode Output Voltage Differential Input Voltage Common-Mode Input Voltage POWER REQUIREMENTS VDD1 VDD2 IDD1 IDD2 Typ 50 0.6 Unit Test Conditions/Comments Bits LSB LSB mV V/C V/C V/V % FSR % FSR % FSR ppm/C V/C mV/V Filter output truncated to 16 bits mV mV mV A A A pF Guaranteed no missing codes to 16 bits 0C to 85C fMCLKIN = 16 MHz fMCLKIN = 20 MHz, TA = -40C to +85C fMCLKIN = 20 MHz Full-scale range For specified performance VIN+ = 250 mV, VIN- = 0 V VIN+ = 0 V, VIN- = 0 V VIN+ = 1 kHz VOD VOCM VID VICM 81 83 86 13.1 13.4 14 25 247 1125 150 800 87 87 88 -96 -97 14.2 14.2 dB dB dB dB dB Bits Bits Bits kV/s 30 360 1260 4.5 3 30 18 13 264 208 For fMCLKIN > 16 MHz, mark space ratio is 48/52 to 52/48, and VDD1 = 5 V 5%. See the Terminology section. Rev. A | Page 3 of 20 454 1375 650 1575 mV mV mV mV 5.5 5.5 36 22 15 319 248 V V mA mA mA mW mW -40C to +85C -40C to +85C RL = 100 RL = 100 VDD1 = 5.5 V VDD2 = 5.5 V VDD2 = 3.3 V VDD1 = VDD2 = 5.5 V VDD1 = 5.5 V, VDD2 = 3.3 V AD7405 Data Sheet TIMING SPECIFICATIONS VDD1 = 4.5 V to 5.5 V, VDD2 = 3 V to 5.5 V, TA = -40C to +125C, unless otherwise noted. Sample tested during initial release to ensure compliance. It is recommended to read the MDAT signal on the MCLKIN+ rising edge. Table 2. Parameter 1 fMCLKIN Limit at TMIN, TMAX 5 20 Unit MHz minimum MHz maximum 30 40 ns maximum ns maximum 10 10 ns minimum ns minimum 0.45 x tMCLKIN 0.48 x tMCLKIN ns minimum ns minimum 0.45 x tMCLKIN 0.48 x tMCLKIN ns minimum ns minimum Description Master clock input frequency t1 Data access time after MCLKIN+ rising edge VDD2 = 4.5 V to 5.5 V VDD2 = 3 V to 3.6 V Data hold time after MCLKIN+ rising edge VDD2 = 4.5 V to 5.5 V VDD2 = 3 V to 3.6V Master clock low time fMCLKIN 16 MHz 16 MHz < fMCLKIN 20 MHz Master clock high time fMCLKIN 16 MHz 16 MHz < fMCLKIN 20 MHz t2 t3 t4 Sample tested during initial release to ensure compliance. t4 MCLKIN- MCLKIN+ t1 t2 MDAT- MDAT+ Figure 2. Data Timing Rev. A | Page 4 of 20 t3 12536-002 1 Data Sheet AD7405 PACKAGE CHARACTERISTICS Table 3. Parameter Resistance (Input to Output) 1 Capacitance (Input to Output)1 IC Junction to Ambient Thermal Resistance 1 Symbol RI-O CI-O JA Min Typ 1012 2.2 45 Max Unit pF C/W Test Conditions/Comments f = 1 MHz Thermocouple located at center of package underside, test conducted on 4-layer board with thin traces The device is considered a 2-terminal device: Pin 1 to Pin 8 are shorted together, and Pin 9 to Pin 16 are shorted together. INSULATION AND SAFETY RELATED SPECIFICATIONS Table 4. Parameter Input to Output Momentary Withstand Voltage Minimum External Air Gap (Clearance) Symbol VISO L(I01) Value 5000 min 8.3 min 1, 2 Unit V mm Minimum External Tracking (Creepage) L(I02) 8.3 min1 mm Minimum Internal Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) Isolation Group CTI 0.034 min >400 II mm V Test Conditions/Comments 1 minute duration Measured from input terminals to output terminals, shortest distance through air Measured from input terminals to output terminals, shortest distance path along body Distance through insulation DIN IEC 112/VDE 0303 Part 1 3 Material Group (DIN VDE 0110, 1/89, Table I)3 In accordance with IEC 60950-1 guidelines for the measurement of creepage and clearance distances for a pollution degree of 2 and altitudes 2000 meters. Consideration must be given to pad layout to ensure the minimum required distance for clearance is maintained. 3 CSA CTI rating for the AD7405 is >600 V and a Material Group I isolation group. 1 2 REGULATORY INFORMATION Table 5. UL 1 Recognized under 1577 Component Recognition Program1 5000 V rms Isolation Voltage Single Protection File E214100 CSA Approved under CSA Component Acceptance Notice 5A VDE 2 Certified according to DIN V VDE V 0884-10 (VDE V 0884-10):2006-122 Basic insulation per CSA 60950-1-07 and IEC 60950-1, 830 V rms (1173 VPEAK) maximum working voltage 3 Reinforced insulation per CSA 60950-1-07 and IEC 60950-1, 415 V rms (586 VPEAK) maximum working voltage3 Reinforced insulation per IEC 60601-1, 250 V rms (353 VPEAK) maximum working voltage File 205078 Reinforced insulation per DIN V VDE V 0884-10 (VDE V 0884-10):2006-12, 1250 VPEAK File 2471900-4880-0001 In accordance with UL 1577, each AD7405 is proof tested by applying an insulation test voltage 6000 V rms for 1 second (current leakage detection limit = 15 A). In accordance with DIN V VDE V 0884-10, each AD7405 is proof tested by applying an insulation test voltage of 2344 VPEAK for 1 second (partial discharge detection limit = 5 pC). 3 Rating is calculated for a pollution degree of 2 and a Material Group III. The AD7405 RI-16-2 package material is rated by CSA to a CTI of >600 V and, therefore, Material Group I. 1 2 Rev. A | Page 5 of 20 AD7405 Data Sheet DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 INSULATION CHARACTERISTICS This isolator is suitable for reinforced electrical isolation only within the safety limit data. Maintenance of the safety data is ensured by means of protective circuits. Table 6. Description INSTALLATION CLASSIFICATION PER DIN VDE 0110 For Rated Mains Voltage 300 V rms For Rated Mains Voltage 450 V rms For Rated Mains Voltage 600 V rms For Rated Mains Voltage 1000 V rms CLIMATIC CLASSIFICATION POLLUTION DEGREE (DIN VDE 0110, TABLE 1) MAXIMUM WORKING INSULATION VOLTAGE INPUT TO OUTPUT TEST VOLTAGE, METHOD B1 VIORM x 1.875 = VPR, 100% Production Test, tm = 1 Second, Partial Discharge < 5 pC INPUT TO OUTPUT TEST VOLTAGE, METHOD A After Environmental Test Subgroup 1 VIORM x 1.6 = VPR, tm = 60 Seconds, Partial Discharge < 5 pC After Input and/or Safety Test Subgroup 2/ Safety Test Subgroup 3 VIORM x 1.2 = VPR, tm = 60 Seconds, Partial Discharge < 5 pC HIGHEST ALLOWABLE OVERVOLTAGE (TRANSIENT OVERVOLTAGE, tTR = 10 Seconds) SURGE ISOLATION VOLTAGE 1.2 s Rise Time, 50 s, 50% Fall Time SAFETY LIMITING VALUES (MAXIMUM VALUE ALLOWED IN THE EVENT OF A FAILURE, SEE Figure 3) Case Temperature Side 1 (PVDD1) and Side 2 (PVDD2) Power Dissipation INSULATION RESISTANCE AT TS, VIO = 500 V Symbol Characteristic Unit VIORM I to IV I to IV I to IV I to IV 40/105/21 2 1250 VPEAK 2344 VPEAK 2000 VPEAK 1500 8000 12000 VPEAK VPEAK VPEAK VPEAK 150 2.78 >109 C W VPD(M) VPR(M) VIOTM VIOSM TS PSO RIO 3 2 1 0 0 50 100 150 AMBIENT TEMPERATURE (C) 200 12536-003 SAFE OPERATING POWER (W) 4 Figure 3. Thermal Derating Curve, Dependence of Safety Limiting Values with Case Temperature per DIN V VDE V 0884-10 Rev. A | Page 6 of 20 Data Sheet AD7405 ABSOLUTE MAXIMUM RATINGS TA = 25C, unless otherwise noted. All voltages are relative to their respective ground. Table 7. Parameter VDD1 to GND1 VDD2 to GND2 Analog Input Voltage to GND1 Digital Input Voltage to GND2 Output Voltage to GND2 Input Current to Any Pin Except Supplies1 Operating Temperature Range Storage Temperature Range Junction Temperature Pb-Free Temperature, Soldering Reflow ESD FICDM2 HBM3 Rating -0.3 V to +6.5 V -0.3 V to +6.5 V -1 V to VDD1 + 0.3 V -0.3 V to VDD2 + 0.5 V -0.3 V to VDD2 + 0.3 V 10 mA -40C to +125C -65C to +150C 150C Table 8. Maximum Continuous Working Voltage1 Parameter AC Voltage Bipolar Waveform Unipolar Waveform DC Voltage 1 Max (VPEAK) Constraint 1250 20-year minimum lifetime (VDE approved working voltage) 20-year minimum lifetime 20-year minimum lifetime 1250 1250 Refers to continuous voltage magnitude imposed across the isolation barrier. ESD CAUTION 260C 2 kV 1250 V 4000 V Transient currents of up to 100 mA do not cause silicon controlled rectifier (SCR) to latch up. JESD22-C101; RC Network: 1 , Cpkg; Class: IV. 3 ESDA/JEDEC JS-001-2011; RC Network: 1.5 k, 100 pF; Class: 3A. 1 2 Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. A | Page 7 of 20 AD7405 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS VDD1 1 16 GND2 VIN+ 2 GND1 4 NIC 5 15 NIC AD7405 14 VDD2 13 MCLKIN+ TOP VIEW (Not to Scale) 12 MCLKIN- NIC 6 11 MDAT+ VDD1 7 10 MDAT- GND1 8 9 GND2 NOTES 1. NIC = NOT INTERNALLY CONNECTED. CONNECT TO VDD1 , GND1, OR LEAVE FLOATING. 12536-004 VIN- 3 Figure 4. Pin Configuration Table 9. Pin Function Descriptions Pin No. 1, 7 Mnemonic VDD1 2 3 4, 8 5, 6, 15 9, 16 10, 11 VIN+ VIN- GND1 NIC GND2 MDAT-, MDAT+ MCLKIN-, MCLKIN+ VDD2 12, 13 14 Description Supply Voltage, 4.5 V to 5.5 V. This pin is the supply voltage for the isolated side of the AD7405 and is relative to GND1. For device operation, connect the supply voltage to both Pin 1 and Pin 7. Decouple each supply pin to GND1 with a 10 F capacitor in parallel with a 1 nF capacitor. Positive Analog Input. Negative Analog Input. Normally connected to GND1. Ground 1. This pin is the ground reference point for all circuitry on the isolated side. Not Internally Connected. Connect to VDD1, GND1, or leave floating. Ground 2. This pin is the ground reference point for all circuitry on the nonisolated side. LVDS Data Outputs. The conversion data is output serially on these pins. LVDS Clock Inputs. Conversion results are shifted out on the rising edge of MCLKIN+. Supply Voltage, 3 V to 5.5 V. This pin is the supply voltage for the nonisolated side and is relative to GND2. Decouple this supply to GND2 with a 100 nF capacitor. Rev. A | Page 8 of 20 Data Sheet AD7405 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25C, VDD1 = 5 V, VDD2 = 5 V, VIN+ = -250 mV to +250 mV, VIN- = 0 V, fMCLKIN = 20 MHz, using a sinc3 filter with a 256 oversampling ratio (OSR), unless otherwise noted. 0 0 200mV p-p SINE WAVE ON VDD1 1nF DECOUPLING fIN = 1kHz SNR = 88.6dB SINAD = 88.3dB THD = -100.5dB -20 -20 -40 MAGNITUDE (dB) PSRR (dB) -40 -60 MCLKIN = 20MHz MCLKIN = 10MHz -80 -60 -80 -100 -120 -100 0 200 400 600 800 SUPPLY RIPPLE FREQUENCY (kHz) 1000 -160 12536-005 -120 0 5 10 15 20 25 30 FREQUENCY (kHz) Figure 5. PSRR vs. Supply Ripple Frequency 12536-008 -140 Figure 8. Typical Fast Fourier Transform (FFT) 1.0 0 SHORTED INPUTS 200mV p-p SINE WAVE ON INPUTS -20 0.8 0.6 DNL ERROR (LSB) CMRR (dB) -40 MCLKIN = 20MHz, SINC3 DECIMATION RATE = 256 MCLKIN = 10MHz, SINC3 DECIMATION RATE = 256 MCLKIN = 20MHz, UNFILTERED MCLKIN = 10MHz, UNFILTERED -60 -80 0.4 0.2 0 -0.2 -0.4 -100 -0.6 -120 100 1000 -1.0 RIPPLE FREQUENCY (kHz) 0 10 86 0.6 84 0.4 INL ERROR (LSB) 0.8 82 78 76 = 4.5V = 5.0V = 5.5V = 4.5V = 5.0V = 5.5V -0.6 -0.8 ANALOG INPUT FREQUENCY (Hz) 50 60 0 -0.2 72 1k 60 0.2 74 70 100 50 -0.4 10k -1.0 12536-007 SINAD (dB) 1.0 88 80 40 Figure 9. Typical DNL Error 90 VDD1 VDD1 VDD1 VDD1 VDD1 VDD1 30 CODE (k) Figure 6. CMRR vs. Common-Mode Ripple Frequency 16MHz MCLKIN, 16MHz MCLKIN, 16MHz MCLKIN, 20MHz MCLKIN, 20MHz MCLKIN, 20MHz MCLKIN, 20 0 10 20 30 40 CODE (k) Figure 10. Typical INL Error Figure 7. SINAD vs. Analog Input Frequency Rev. A | Page 9 of 20 12536-010 10 12536-006 1 12536-009 -0.8 -140 0.1 AD7405 Data Sheet 200 800 MCLKIN = 20MHz 700 150 MCLKIN = 10MHz VIN+ = VIN- = 0V 1M SAMPLES 692381 100 50 OFFSET (V) HITS PER CODE (k) 600 500 400 0 -50 300 -100 200 160941 144470 -150 0 1147 32764 32765 32766 32767 32768 1061 0 32769 32770 CODE -200 -50 12536-011 0 -25 0 25 50 75 100 125 150 TEMPERATURE (C) 12536-014 100 Figure 14. Offset vs. Temperature Figure 11. Histogram of Codes at Code Center 10 100 fIN = 1kHz MCLKIN = 10MHz MCLKIN = 20MHz 8 6 GAIN ERROR (mV) SNR AND SINAD (dB) 90 SNR SINAD 80 4 2 0 -2 -4 70 -6 -25 0 25 50 75 100 125 150 TEMPERATURE (C) -10 -50 12536-012 60 -50 0 25 50 75 100 125 150 TEMPERATURE (C) Figure 12. SNR and SINAD vs. Temperature Figure 15. Gain Error vs. Temperature -60 35 fIN = 1kHz 30 -70 25 THD SFDR -90 20 MCLKIN = 20MHz, MCLKIN = 20MHz, MCLKIN = 20MHz, MCLKIN = 20MHz, MCLKIN = 10MHz, MCLKIN = 10MHz, MCLKIN = 10MHz, MCLKIN = 10MHz, 15 -100 10 -110 -120 -50 5 -25 0 25 50 75 100 TEMPERATURE (C) 125 150 Figure 13. THD and SFDR vs. Temperature 0 4.50 4.75 5.00 5.25 -40C +25C +85C +125C -40C +25C +85C +125C 5.50 VDD1 (V) Figure 16. IDD1 vs. VDD1 at Various Temperatures and Clock Rates Rev. A | Page 10 of 20 12536-016 IDD1 (mA) -80 12536-013 THD AND SFDR (dB) -25 12536-015 -8 Data Sheet AD7405 17.4 32 TA = -40C TA = 0C TA = +25C TA = +85C TA = +125C 31 DC INPUT DC INPUT 17.3 IDD2 (mA) 29 28 27 17.2 17.1 TA = -40C TA = 0C TA = +25C TA = +85C TA = +125C 26 -125 0 125 250 VIN+ DC INPUT (mV) 17.0 -250 12536-017 25 -250 -125 0 125 250 VIN+ DC INPUT (mV) Figure 17. IDD1 vs. VIN+ DC Input at Various Temperatures 12536-019 IDD1 (mA) 30 Figure 19. IDD2 vs. VIN+ DC Input at Various Temperatures 20 60 DC INPUT 18 40 16 14 IIN+ (A) 10 MCLKIN = 20MHz, MCLKIN = 20MHz, MCLKIN = 20MHz, MCLKIN = 20MHz, MCLKIN = 10MHz, MCLKIN = 10MHz, MCLKIN = 10MHz, MCLKIN = 10MHz, 6 4 2 0 3.0 3.5 4.0 4.5 5.0 -40C +25C +85C +125C -40C +25C +85C +125C 5.5 VDD2 (V) 0 MCLKIN = 5MHz MCLKIN = 10MHz MCLKIN = 20MHz -20 -40 Figure 18. IDD2 vs. VDD2 at Various Temperatures and Clock Rates -60 -320 -240 -160 -80 0 80 160 240 VIN+ DC INPUT (mV) Figure 20. IIN+ vs. VIN+ DC Input at Various Clock Rates Rev. A | Page 11 of 20 320 12536-020 8 12536-018 IDD2 (mA) 20 12 AD7405 Data Sheet TERMINOLOGY Total Harmonic Distortion (THD) THD is the ratio of the rms sum of harmonics to the fundamental. For the AD7405, it is defined as Differential Nonlinearity (DNL) DNL is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC. Integral Nonlinearity (INL) INL is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function. The endpoints of the transfer function are a specified negative full scale, -250 mV (VIN+ - VIN-), Code 7168 for the 16-bit level, and a specified positive full scale, +250 mV (VIN+ - VIN-), Code 58,368 for the 16-bit level. Offset Error Offset error is the deviation of the midscale code (32,768 for the 16-bit level) from the ideal VIN+ - VIN- (that is, 0 V). Gain Error The gain error includes both positive full-scale gain error and negative full-scale gain error. Positive full-scale gain error is the deviation of the specified positive full-scale code (58,368 for the 16-bit level) from the ideal VIN+ - VIN- (250 mV) after the offset error is adjusted out. Negative full-scale gain error is the deviation of the specified negative full-scale code (7168 for the 16-bit level) from the ideal VIN+ - VIN- (-250 mV) after the offset error is adjusted out. Signal-to-Noise-and-Distortion Ratio (SINAD) SINAD is the measured ratio of signal-to-noise-and-distortion at the output of the ADC. The signal is the rms value of the sine wave, and noise is the rms sum of all nonfundamental signals up to half the sampling frequency (fS/2), including harmonics, but excluding dc. Signal-to-Noise Ratio (SNR) SNR is the measured signal-to-noise ratio at the output of the ADC. The signal is the rms amplitude of the fundamental. Noise is the sum of all nonfundamental signals up to half the sampling frequency (fS/2), excluding dc. The ratio is dependent on the number of quantization levels in the digitization process: the greater the number of levels, the smaller the quantization noise. The theoretical SNR for an ideal N-bit converter with a sine wave input is given by Signal-to-Noise Ratio = (6.02N + 1.76) dB Therefore, for a 12-bit converter, the SNR is 74 dB. Isolation Transient Immunity The isolation transient immunity specifies the rate of rise and fall of a transient pulse applied across the isolation boundary, beyond which clock or data is corrupted. The AD7405 was tested using a transient pulse frequency of 100 kHz. THD(dB) = 20 log V2 2 + V3 2 + V4 2 + V5 2 + V6 2 V1 where: V1 is the rms amplitude of the fundamental. V2, V3, V4, V5, and V6 are the rms amplitudes of the second through the sixth harmonics. Peak Harmonic or Spurious Noise Peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the ADC output spectrum (up to fS/2, excluding dc) to the rms value of the fundamental. Normally, the value of this specification is determined by the largest harmonic in the spectrum, but for ADCs where the harmonics are buried in the noise floor, it is a noise peak. Effective Number of Bits (ENOB) ENOB is defined by ENOB = (SINAD - 1.76)/6.02 bits Noise Free Code Resolution Noise free code resolution represents the resolution in bits for which there is no code flicker. The noise free code resolution for an N-bit converter is defined as Noise Free Code Resolution (Bits) = log2(2N/Peak-to-Peak Noise) The peak-to-peak noise in LSBs is measured with VIN+ = VIN- = 0 V. Common-Mode Rejection Ratio (CMRR) CMRR is defined as the ratio of the power in the ADC output at 250 mV frequency, f, to the power of a +250 mV peak-to-peak sine wave applied to the common-mode voltage of VIN+ and VIN- of frequency, fS, as CMRR (dB) = 10 log(Pf/PfS) where: Pf is the power at frequency, f, in the ADC output. PfS is the power at frequency, fS, in the ADC output. Power Supply Rejection Ratio (PSRR) Variations in power supply affect the full-scale transition but not the linearity of the converter. PSRR is the maximum change in the specified full-scale (250 mV) transition point due to a change in power supply voltage from the nominal value. Rev. A | Page 12 of 20 Data Sheet AD7405 THEORY OF OPERATION CIRCUIT INFORMATION The AD7405 isolated - modulator converts an analog input signal into a high speed (20 MHz maximum), single-bit data stream; the time average single-bit data from the modulator is directly proportional to the input signal. Figure 21 shows a typical application circuit where the AD7405 is used to provide isolation between the analog input, a current sensing resistor or shunt, and the digital output, which is then processed by a digital filter to provide an N-bit word. ANALOG INPUT The differential analog input of the AD7405 is implemented with a switched capacitor circuit. This circuit implements a second-order modulator stage that digitizes the input signal into a single-bit output stream. The sample clock (MCLKIN) provides the clock signal for the conversion process as well as the output data framing clock. This clock source is external on the AD7405. The analog input signal is continuously sampled by the modulator and compared to an internal voltage reference. A digital stream that accurately represents the analog input over time appears at the output of the converter (see Figure 22). A differential input signal of 0 V ideally results in a differential stream of alternating 1s and 0s at the MDAT output pins. This output is high 50% of the time and low 50% of the time. A differential input of 250 mV produces a stream of 1s and 0s that are high 89.06% of the time. A differential input of -250 mV produces a stream of 1s and 0s that are high 10.94% of the time. A differential input of 320 mV ideally results in a stream of all 1s. A differential input of -320 mV ideally results in a stream of all 0s. The absolute full-scale range is 320 mV, and the specified full-scale performance range is 250 mV, as shown in Table 10. Table 10. Analog Input Range Analog Input Positive Full-Scale Value Positive Specified Performance Input Zero Negative Specified Performance Input Negative Full-Scale Value Voltage Input (mV) +320 +250 0 -250 -320 FLOATING POWER SUPPLY +400V NONISOLATED 5V/3V VDD1 GND1 5.1V 220pF 10 10 RSHUNT FLOATING POWER SUPPLY 220pF - MOD/ ENCODER MDAT+ VDD1 MDAT- DECODER DECODER ENCODER MCLKIN- GND2 GND1 GATED DRIVE CIRCUIT MDAT CS SCLK MCLKIN+ VIN- 10F 1nF SINC3 FILTER* VDD VDD2 MCLK 100nF SDAT GND 12536-021 *THIS FILTER IS IMPLEMENTED WITH AN FPGA OR DSP -400V Figure 21. Typical Application Circuit MODULATOR OUTPUT +FS ANALOG INPUT -FS ANALOG INPUT ANALOG INPUT Figure 22. Analog Input vs. Modulator Output Rev. A | Page 13 of 20 12536-022 MOTOR VIN+ AD7405 100 10F 1nF 100 GATED DRIVE CIRCUIT AD7405 Data Sheet To reconstruct the original information, this output must be digitally filtered and decimated. A sinc3 filter is recommended because it is one order higher than that of the AD7405 modulator, which is a second-order modulator. If a 256 decimation rate is used, the resulting 16-bit word rate is 78.1 kSPS, assuming a 20 MHz external clock frequency. See the Digital Filter section for more detailed information on the sinc filter implementation. Figure 23 shows the transfer function of the AD7405 relative to the 16-bit output. VIN- 300 MCLKIN B 1.9pF A 1.9pF B A B A B 12536-024 VIN+ Figure 24. Analog Input Equivalent Circuit Because the AD7405 samples the differential voltage across its analog inputs, an input circuit provides low common-mode noise at each input attaining low noise performance. 65535 58368 LOW VOLTAGE DIFFERENTIAL SIGNALING (LVDS) INTERFACE SPECIFIED RANGE ADC CODE A 300 The AD7405 uses an LVDS interface for both the clock input and the modulator output. The benefits of using LVDS in this case helps to make the interface between the modulator and the controller more robust and less susceptible to electromagnetic interference (EMI) from the surroundings. LVDS also helps to reduce the EMI emissions associated with high speed digital signaling. LVDS signals are treated like transmission lines and must be resistively terminated. The value of the differential terminating resistor is typically 100 . Place the terminating resistor as close to the receiver as possible. 7168 -320mV -250mV +250mV +320mV ANALOG INPUT 12536-023 0 Figure 23. Filtered and Decimated 16-Bit Transfer Function DIFFERENTIAL INPUTS The analog input to the modulator is a switched capacitor design. The analog signal is converted into charge by highly linear sampling capacitors. A simplified equivalent circuit diagram of the analog input is shown in Figure 24. A signal source driving the analog input must provide the charge onto the sampling capacitors every half MCLKIN cycle and settle to the required accuracy within the next half cycle. Rev. A | Page 14 of 20 Data Sheet AD7405 APPLICATIONS INFORMATION 90 CURRENT SENSING APPLICATIONS 85 80 SINAD (dB) 14 -BIT ENOB 70 13-BIT ENOB fIN = 1kHz MCLKIN = 20MHz VDD1 = 5V VDD2 = 5V TA = 25C 65 60 0 12-BIT ENOB 50 100 150 200 250 VIN+ AC INPUT SIGNAL AMPLITUDE (mV) Figure 25. SINAD vs. VIN+ AC Input Signal Amplitude 1.6 DC INPUT 100k SAMPLES PER DATA POINT 1.4 1.2 RMS NOISE (LSB) The shunt resistor (RSHUNT) values used in conjunction with the AD7405 are determined by the specific application requirements in terms of voltage, current, and power. Small resistors minimize power dissipation, whereas low inductance resistors prevent any induced voltage spikes, and good tolerance devices reduce current variations. The final values chosen are a compromise between low power dissipation and accuracy. Higher value resistors use the full performance input range of the ADC, thus achieving maximum SNR performance. Low value resistors dissipate less power but do not use the full performance input range. The AD7405, however, delivers excellent performance, even with lower input signal levels, allowing low value shunt resistors to be used while maintaining system performance. 11-BIT ENOB 12536-025 Choosing RSHUNT To choose a suitable shunt resistor, first determine the current through the shunt. The shunt current for a 3-phase induction motor can be expressed as I RMS 75 MCLKIN = 5MHz MCLKIN = 10MHz MCLKIN = 20MHz 1.0 0.8 0.6 0.4 0.2 0 -320 PW = 1.73 x V x EF x PF -240 -160 -80 0 80 160 240 320 VIN+ DC INPUT SIGNAL AMPLITUDE (mV) 12536-026 The AD7405 is ideally suited for current sensing applications where the voltage across a shunt resistor (RSHUNT) is monitored. The load current flowing through an external shunt resistor produces a voltage at the input terminals of the AD7405. The AD7405 provides isolation between the analog input from the current sensing resistor and the digital outputs. By selecting the appropriate shunt resistor value, a variety of current ranges can be monitored. Figure 26. RMS Noise vs. VIN+ DC Input Signal Amplitude where: IRMS is the motor phase current (A rms). PW is the motor power (Watts). V is the motor supply voltage (V ac). EF is the motor efficiency (%). PF is the power efficiency (%). To determine the shunt peak sense current, ISENSE, consider the motor phase current and any overload that may be possible in the system. When the peak sense current is known, divide the voltage range of the AD7405 (250 mV) by the peak sense current to yield a maximum shunt value. If the power dissipation in the shunt resistor is too large, the shunt resistor can be reduced and less of the ADC input range can be used. Figure 25 shows the SINAD performance characteristics and the ENOB of resolution for the AD7405 for different input signal amplitudes. Figure 26 shows the rms noise performance for dc input signal amplitudes. The AD7405 performance at lower input signal ranges allows smaller shunt values to be used while still maintaining a high level of performance and overall system efficiency. RSHUNT must be able to dissipate the I2R power losses. If the power dissipation rating of the resistor is exceeded, its value may drift or the resistor may be damaged, resulting in an open circuit. This open circuit can result in a differential voltage across the terminals of the AD7405, in excess of the absolute maximum ratings. If ISENSE has a large, high frequency component, choose a resistor with low inductance. VOLTAGE SENSING APPLICATIONS The AD7405 can also be used for isolated voltage monitoring. For example, in motor control applications, it can be used to sense the bus voltage. In applications where the voltage being monitored exceeds the specified analog input range of the AD7405, a voltage divider network can be used to reduce the voltage being monitored to the required range. Rev. A | Page 15 of 20 AD7405 Data Sheet INPUT FILTER DIGITAL FILTER In a typical application, where voltage is being measured across a shunt resistor, connect the AD7405 directly across the shunt resistor with a simple RC low-pass filter on each input. The output of the AD7405 is a continuous LVDS digital bit stream. To reconstruct the original input signal information, this output bit stream needs to be digitally filtered and decimated. A sinc filter is recommended due to its simplicity. A sinc3 filter is recommended because it is one order higher than that of the AD7405 modulator, which is a second-order modulator. The type of filter selected, the decimation rate, and the modulator clock used determines the overall system resolution and throughput rate. The higher the decimation rate, the greater the system accuracy, as illustrated in Figure 30. However, there is a trade-off between accuracy and throughput rate and, therefore, higher decimation rates result in lower throughput solutions. Note that for a given bandwidth requirement, a higher MCLKIN frequency can allow higher decimation rates to be used, resulting in higher SNR performance. The recommended circuit configuration for driving the differential inputs to achieve best performance is shown in Figure 27. An RC low-pass filter is placed on both the analog input pins. Recommended values for the resistors and capacitors are 10 and 220 pF, respectively. If possible, equalize the source impedance on each analog input to minimize offset. C R VIN+ AD7405 R 12536-027 VIN- 100 fIN = 1kHz 90 Figure 27. RC Low-Pass Filter Input Network 80 70 SNR (dB) The input filter configuration for the AD7405 is not limited to the low-pass structure shown in Figure 27. The differential RC filter configuration shown in Figure 28 also achieves excellent performance. Recommended values for the resistors and capacitor are 22 and 47 pF, respectively. R VIN- SINC1 SINC2 SINC3 SINC4 10 0 10 Figure 28. Differential RC Filter Input Network Figure 29 compares the typical performance for the input filter structures outlined in Figure 27 and Figure 28 for different resistor and capacitor values. 95 fIN = 1kHz 90 100 1000 DECIMATION RATE Figure 30. SNR vs. Decimation Rate for Different Sinc Filter Orders A sinc3 filter is recommended for use with the AD7405. This filter can be implemented on a field programmable gate array (FPGA) or a digital signal processor (DSP). Equation 1 describes the transfer function of a sinc filter. 85 1 (1 - Z -DR ) H (z ) = -1 DR (1 - Z ) 80 SNR (dB) 40 20 12536-028 AD7405 C R 75 N (1) where DR is the decimation rate and N is the sinc filter order. 70 The throughput rate of the sinc filter is determined by the modulator clock and the decimation rate selected. 65 LOW PASS, 10, 220pF DIFFERENTIAL, 22, 47pF DIFFERENTIAL, 22, 10nF Throughput = 100 DECIMATION RATE 1000 12536-029 55 50 10 50 30 VIN+ 60 60 12536-030 C Figure 29. SNR vs. Decimation Rate for Different Filter Structures for Different Resistor and Capacitor Values MCLK DR (2) where MCLK is the modulator clock frequency As the decimation rate increases, the data output size from the sinc filter increases. The output data size is expressed in Equation 3. The 16 most significant bits are used to return a 16-bit result. Data size = N x log2 DR Rev. A | Page 16 of 20 (3) Data Sheet AD7405 Z = one sample delay MCLKOUT = modulators conversion bit rate */ MCLKIN Throughput Rate (kHz) 625 312.5 156.2 78.1 39.1 Output Data Size (Bits) 15 18 21 24 27 Filter Response (kHz) 163.7 81.8 40.9 20.4 10.2 The following Verilog code provides an example of a sinc3 filter implementation on a Xilinx(R) Spartan(R)-6 FPGA. Note that the data is read on the positive clock edge. It is recommended to read in the data on the positive clock edge. The code is configurable to accommodate decimation rates from 32 to 4096. module dec256sinc24b ( input mclk1, /* used to clk filter */ input reset, /* used to reset filter */ input mdata1, /* input data to be filtered */ output reg [15:0] DATA, /* filtered output */ output reg data_en, input [15:0] dec_rate ); [36:0] [36:0] [36:0] [36:0] [36:0] [36:0] [36:0] [36:0] [36:0] [36:0] ACC3+ + always @ (negedge mclk1, posedge reset) begin if (reset) begin /* initialize acc registers on reset */ acc1 <= 37'd0; acc2 <= 37'd0; acc3 <= 37'd0; end else begin /*perform accumulation process */ acc1 <= acc1 + ip_data1; acc2 <= acc2 + acc1; acc3 <= acc3 + acc2; end end /*decimation stage (MCLKOUT/WORD_CLK) */ always @ (posedge mclk1, posedge reset) begin if (reset) word_count <= 16'd0; else begin ip_data1; acc1; acc2; acc3; acc3_d2; diff1; diff2; diff3; diff1_d; diff2_d; if ( word_count == dec_rate 1 ) word_count <= 16'd0; else word_count <= word_count + 16'b1; end end always @ ( posedge mclk1, posedge reset ) begin if ( reset ) word_clk <= 1'b0; else begin if ( word_count == dec_rate/2 1 ) word_clk <= 1'b1; else if ( word_count == dec_rate - 1 ) word_clk <= 1'b0; end end reg [15:0] word_count; reg word_clk; reg enable; /*Perform the Sinc always @ (mdata1) if(mdata1==0) ip_data1 <= /* change 0 complement */ else ip_data1 <= + Figure 31. Accumulator /* Data is read on positive clk edge */ reg reg reg reg reg reg reg reg reg reg Z Z Z + Table 11. Sinc3 Filter Characteristics for 20 MHz MCLKIN Decimation Ratio (DR) 32 64 128 256 512 ACC2+ ACC1+ IP_DATA1 12536-031 For a sinc3 filter, the -3 dB filter response point can be derived from the filter transfer function, Equation 1, and is 0.262 times the throughput rate. The filter characteristics for a third-order sinc3 filter are summarized in Table 11. action*/ 37'd0; to a -1 for twos 37'd1; /*Accumulator (Integrator) Perform the accumulation (IIR) at the speed of the modulator. /*Differentiator (including decimation stage) Perform the differentiation stage (FIR) at a lower speed. Rev. A | Page 17 of 20 AD7405 Data Sheet Z = one sample delay WORD_CLK = output word rate */ + ACC3 DIFF1 + - DIFF2 + - Z-1 Z-1 12536-032 Z-1 DIFF3 - WORD_CLK Figure 32. Differentiator always @ (posedge word_clk, posedge reset) begin if(reset) begin acc3_d2 <= 37'd0; diff1_d <= 37'd0; diff2_d <= 37'd0; diff1 <= 37'd0; diff2 <= 37'd0; diff3 <= 37'd0; end else begin end diff1 <= acc3 - acc3_d2; diff2 <= diff1 - diff1_d; diff3 <= diff2 - diff2_d; acc3_d2 <= acc3; diff1_d <= diff1; diff2_d <= diff2; end end /* Clock the Sinc output into an output register WORD_CLK = output word rate */ DATA 12536-033 WORD_CLK DIFF3 16'd256:begin DATA <= (diff3[24:8] == 17'h10000) ? 16'hFFFF : diff3[23:8]; end 16'd512:begin DATA <= (diff3[27:11] == 17'h10000) ? 16'hFFFF : diff3[26:11]; end 16'd1024:begin DATA <= (diff3[30:14] == 17'h10000) ? 16'hFFFF : diff3[29:14]; end 16'd2048:begin DATA <= (diff3[33:17] == 17'h10000) ? 16'hFFFF : diff3[32:17]; end 16'd4096:begin DATA <= (diff3[36:20] == 17'h10000) ? 16'hFFFF : diff3[35:20]; end default:begin DATA <= (diff3[24:8] == 17'h10000) ? 16'hFFFF : diff3[23:8]; end endcase Figure 33. Clocking Sinc3 Output into an Output Register always @ ( posedge word_clk ) begin case ( dec_rate ) 16'd32:begin DATA <= (diff3[15:0] == 16'h8000) ? 16'hFFFF : {diff3[14:0], 1'b0}; end 16'd64:begin DATA <= (diff3[18:2] == 17'h10000) ? 16'hFFFF : diff3[17:2]; end 16'd128:begin DATA <= (diff3[21:5] == 17'h10000) ? 16'hFFFF : diff3[20:5]; end /* Synchronize Data Output*/ always@ ( posedge mclk1, posedge reset ) begin if ( reset ) begin data_en <= 1'b0; enable <= 1'b1; end else begin if ( (word_count == dec_rate/2 - 1) && enable ) begin data_en <= 1'b1; enable <= 1'b0; end else if ( (word_count == dec_rate - 1) && ~enable ) begin data_en <= 1'b0; enable <= 1'b1; end else data_en <= 1'b0; end end endmodule Rev. A | Page 18 of 20 Data Sheet AD7405 * The value that ensures at least a 20-year lifetime of continuous use. The maximum VDE approved working voltage. Note that the lifetime of the AD7405 varies according to the waveform type imposed across the isolation barrier. The iCoupler insulation structure is stressed differently, depending on whether the waveform is bipolar ac, unipolar ac, or dc. Figure 34, Figure 35, and Figure 36 illustrate the different isolation voltage waveforms. INSULATION LIFETIME All insulation structures eventually break down when subjected to voltage stress over a sufficiently long period. The rate of insulation degradation is dependent on the characteristics of the voltage waveform applied across the insulation. In addition to the testing performed by the regulatory agencies, Analog Devices carries out an extensive set of evaluations to determine the lifetime of the insulation structure within the AD7405. Analog Devices performs accelerated life testing using voltage levels higher than the rated continuous working voltage. Acceleration factors for several operating conditions are determined. These factors allow calculation of the time to failure at the actual working voltage. The values shown in Table 8 summarize the peak voltage for 20 years of service life for a bipolar, ac operating condition and the maximum VDE approved working voltages. These tests subjected the AD7405 to continuous cross isolation voltages. To accelerate the occurrence of failures, the selected Rev. A | Page 19 of 20 RATED PEAK VOLTAGE 12536-034 Minimize series resistance in the analog inputs to avoid any distortion effects, especially at high temperatures. If possible, equalize the source impedance on each analog input to minimize offset. To reduce offset drift, check for mismatch and thermocouple effects on the analog input printed circuit board (PCB) tracks. * 0V Figure 34. Bipolar AC Waveform, 50 Hz or 60 Hz RATED PEAK VOLTAGE 12536-035 It is recommended to decouple the VDD1 supply with a 10 F capacitor in parallel with a 1 nF capacitor to GND1. Decouple Pin 1 and Pin 7 individually. Decouple the VDD2 supply with a 100 nF value to GND2. In applications involving high commonmode transients, minimize board coupling across the isolation barrier. Furthermore, design the board layout so that any coupling that occurs equally affects all pins on a given component side. Failure to ensure equal coupling can cause voltage differentials between pins to exceed the absolute maximum ratings of the device, thereby leading to latch-up or permanent damage. Place any decoupling used as close to the supply pins as possible. test voltages were values exceeding those of normal use. The time to failure values of these units were recorded and used to calculate the acceleration factors. These factors were then used to calculate the time to failure under the normal operating conditions. The values shown in Table 8 are the lesser of the following two values: 0V Figure 35. Unipolar AC Waveform, 50 Hz or 60 Hz RATED PEAK VOLTAGE 12536-036 GROUNDING AND LAYOUT 0V Figure 36. DC Waveform AD7405 Data Sheet OUTLINE DIMENSIONS 12.85 12.75 12.65 1.93 REF 16 9 7.60 7.50 7.40 10.51 10.31 10.11 8 PIN 1 MARK 2.64 2.54 2.44 2.44 2.24 0.30 0.20 0.10 COPLANARITY 0.1 0.71 0.50 0.31 0.25 BSC GAGE PLANE 45 SEATING PLANE 1.27 BSC 1.01 0.76 0.51 0.46 0.36 COMPLIANT TO JEDEC STANDARDS MS-013-AC 0.32 0.23 8 0 11-15-2011-A 1 Figure 37. 16-Lead Standard Small Outline Package, with Increased Creepage [SOIC_IC] Wide Body (RI-16-2) Dimensions shown in millimeters ORDERING GUIDE Model 1 AD7405BRIZ AD7405BRIZ-RL AD7405BRIZ-RL7 EVAL-AD7405FMCZ EVAL-SDP-CH1Z 1 Temperature Range -40C to +125C -40C to +125C -40C to +125C Package Description 16-Lead Standard Small Outline Package, with Increased Creepage [SOIC_IC] 16-Lead Standard Small Outline Package, with Increased Creepage [SOIC_IC] 16-Lead Standard Small Outline Package, with Increased Creepage [SOIC_IC] Evaluation Board System Demonstration Platform Z = RoHS Compliant Part. (c)2014 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D12536-0-11/14(A) Rev. A | Page 20 of 20 Package Option RI-16-2 RI-16-2 RI-16-2