16-Bit, Isolated Sigma-Delta Modulator,
LVDS Interface
Data Sheet
AD7405
FEATURES
5 MHz to 20 MHz external clock input rate
16 bits, no missing codes
Signal-to-noise ratio (SNR): 88 dB typical
Effective number of bits (ENOB): 14.2 bits typical
Typical offset drift vs. temperature: 1.6 µV/°C
Low voltage differential signaling (LVDS) interface
On-board digital isolator
On-board reference
Full-scale analog input voltage range: ±320 mV
−40°C to + 125°C operating temperature range
High common-mode transient immunity: >25 kV/µs
16-lead, wide-body SOIC_IC, with increased creepage
package
Safety and regulatory approvals
UL recognition
5000 V rms for 1 minute per UL 1577
CSA Component Acceptance Notice 5A
VDE Certificate of Conformity
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
Maximum working insulation voltage (VIORM): 1250 VPEAK
APPLICATIONS
Shunt current monitoring
AC motor controls
Power and solar inverters
Wind turbine inverters
Data acquisition systems
Analog-to-digital and opto-isolator replacements
FUNCTIONAL BLOCK DIAGRAM
Figure 1.
GENERAL DESCRIPTION
The AD74051 is a high performance, second-order, Σ-Δ modulator
that converts an analog input signal into a high speed, single-bit
LVDS data stream, with on-chip digital isolation based on
Analog Devices, Inc., iCoupler® technology. The AD7405 operates
from a 4.5 V to 5.5 V (VDD1) power supply and accepts a
differential input signal of ±250 mV (±320 mV full-scale). The
differential input is ideally suited to shunt voltage monitoring in
high voltage applications where galvanic isolation is required.
The analog input is continuously sampled by a high performance
analog modulator, and converted to a ones density digital output
stream with a data rate of up to 20 MHz. The original information
can be reconstructed with an appropriate digital filter to achieve
88 dB SNR at 78.1 kSPS. The LVDS input/output can use a 3 V
to 5.5 V supply (VDD2).
The LVDS interface is digitally isolated. The LVDS interface
technology, combined with monolithic transformer technology,
means the on-chip isolation provides outstanding performance
characteristics, superior to alternatives such as optocoupler
devices. The AD7405 device is offered in a 16-lead, wide-body
SOIC_IC package and has an operating temperature range of
−40°C to +125°C.
1 Protected by U.S. Patents 5,952,849; 6,873,065; and 7,075,329.
VDD1 VDD2
AD7405
BUF
REF
CLK
DECODER
GND1GND2
MCLKIN+
(5MHz TO
20MHz)
MCLKIN–
MDAT+
MDAT–
VIN+
VIN–
CLK
ENCODER
DATA
ENCODER DATA
DECODER
Σ-Δ ADC
12536-001
Rev. A Document Feedback
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Technical Support www.analog.com
AD7405 Data Sheet
Rev. A | Page 2 of 20
TABLE OF CONTENTS
Features .............................................................................................. 1
Applicat ions ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Timing Specifications .................................................................. 4
Package Characteristics ............................................................... 5
Insulation and Safety Related Specifications ............................ 5
Regulatory Information ............................................................... 5
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 Insulation
Characteristics .............................................................................. 6
Absolute Maximum Ratings ............................................................ 7
ESD Caution .................................................................................. 7
Pin Configuration and Function Descriptions ............................. 8
Typical Performance Characteristics ............................................. 9
Terminology .................................................................................... 12
Theory of Operation ...................................................................... 13
Circuit Information .................................................................... 13
Analog Input ............................................................................... 13
Differential Inputs ...................................................................... 14
Low Voltage Differential Signaling (LVDS) Interface ........... 14
Applications Information .............................................................. 15
Current Sensing Applications ................................................... 15
Voltage Sensing Applications .................................................... 15
Input Filter .................................................................................. 16
Digital Filter ................................................................................ 16
Grounding and Layout .............................................................. 19
Insulation Lifetime ..................................................................... 19
Outline Dimensions ....................................................................... 20
Ordering Guide .......................................................................... 20
REVISION HISTORY
11/14—Rev. 0 to Rev. A
Change to Figure 1 ........................................................................... 1
Changes to Table 7 ............................................................................ 7
Changes to Ordering Guide .......................................................... 20
9/14—Revision 0: Initial Version
Data Sheet AD7405
SPECIFICATIONS
VDD1 = 4.5 V to 5.5 V, VDD2 = 3 V to 5.5 V, VIN+ = −250 mV to +250 mV, VIN− = 0 V, T A = −40°C to +125°C, fMCLKIN1 = 5 MHz to 20 MHz, tested
with sinc3 filter, 256 decimation rate, as defined by Verilog code, unless otherwise noted. All voltages are relative to their respective ground.
Table 1.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
STATIC PERFORMANCE
Resolution 16 Bits Filter output truncated to 16 bits
Integral Nonlinearity2 INL ±2 ±12 LSB
Differential Nonlinearity2 DNL ±0.99 LSB Guaranteed no missing codes to 16 bits
Offset Error2 ±0.2 ±0.75 mV
Offset Drift vs. Temperature
1.6
3.8
1.3 3.1 µV/°C 0°C to 85°C
Offset Drift vs. VDD1 50 µV/V
Gain Error2 ±0.2 ±0.8 % FSR fMCLKIN = 16 MHz
±0.2 ±0.8 % FSR fMCLKIN = 20 MHz, TA = −40°C to +85°C
±0.2 ±1.2 % FSR fMCLKIN = 20 MHz
Gain Error Drift vs. Temperature 65 95 ppm/°C
40 60 µV/°C
Gain Error Drift vs. VDD1 ±0.6 mV/V
ANALOG INPUT
Input Voltage Range −320 +320 mV Full-scale range
−250 +250 mV For specified performance
Input Common-Mode Voltage Range −200 to +300 mV
Dynamic Input Current ±45 ±50 µA VIN+ = ±250 mV, VIN− = 0 V
0.05
V
IN+
= 0 V, V
IN−
= 0 V
DC Leakage Current ±0.01 ±0.6 µA
Input Capacitance 14 pF
DYNAMIC SPECIFICATIONS VIN+ = 1 kHz
Signal-to-Noise-and-Distortion Ratio2 SINAD 81 87 dB
83 87 dB −40°C to +85°C
Signal-to-Noise Ratio2 SNR 86 88 dB
Total Harmonic Distortion2 THD −96 dB
Peak Harmonic or Spurious Noise2 SFDR −97 dB
Effective Number of Bits
2
ENOB
13.1
14.2
13.4 14.2 Bits −40°C to +85°C
Noise Free Code Resolution2 14 Bits
ISOLATION TRANSIENT IMMUNITY2 25 30 kV/µs
LVDS I/O (ANSI-644)
Differential Output Voltage VOD 247 360 454 mV RL = 100 Ω
Common-Mode Output Voltage VOCM 1125 1260 1375 mV RL = 100 Ω
Differential Input Voltage VID 150 650 mV
Common-Mode Input Voltage VICM 800 1575 mV
POWER REQUIREMENTS
VDD1 4.5 5.5 V
V
DD2
3
5.5
IDD1 30 36 mA VDD1 = 5.5 V
IDD2 18 22 mA VDD2 = 5.5 V
13 15 mA VDD2 = 3.3 V
Power Dissipation 264 319 mW VDD1 = VDD2 = 5.5 V
208 248 mW VDD1 = 5.5 V, VDD2 = 3.3 V
1 For fMCLKIN > 16 MHz, mark space ratio is 48/52 to 52/48, and VDD1 = 5 V ± 5%.
2 See the Terminology section.
Rev. A | Page 3 of 20
AD7405 Data Sheet
TIMING SPECIFICATIONS
VDD1 = 4.5 V to 5.5 V, VDD2 = 3 V to 5.5 V, TA = −40°C to +125°C, unless otherwise noted. Sample tested during initial release to ensure
compliance. It is recommended to read the MDAT signal on the MCLKIN+ rising edge.
Table 2.
Parameter1 Limit at TMIN, TMAX Unit Description
fMCLKIN 5 MHz minimum Master clock input frequency
20 MHz maximum
t1 Data access time after MCLKIN+ rising edge
30 ns maximum VDD2 = 4.5 V to 5.5 V
40 ns maximum VDD2 = 3 V to 3.6 V
t2 Data hold time after MCLKIN+ rising edge
10 ns minimum VDD2 = 4.5 V to 5.5 V
10 ns minimum VDD2 = 3 V to 3.6V
t3 Master clock low time
0.45 × tMCLKIN ns minimum fMCLKIN ≤ 16 MHz
0.48 × t
MCLKIN
ns minimum
16 MHz < f
MCLKIN
≤ 20 MHz
t4 Master clock high time
0.45 × tMCLKIN ns minimum fMCLKIN ≤ 16 MHz
0.48 × tMCLKIN ns minimum 16 MHz < fMCLKIN ≤ 20 MHz
1 Sample tested during initial release to ensure compliance.
Figure 2. Data Timing
MCLKIN+
MDAT+
t
1
t
2
t
3
t
4
MCLKIN–
MDAT–
12536-002
Rev. A | Page 4 of 20
Data Sheet AD7405
PACKAGE CHARACTERISTICS
Table 3.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
Resistance (Input to Output)
1
R
I-O
10
12
Ω
Capacitance (Input to Output)1 CI-O 2.2 pF f = 1 MHz
IC Junction to Ambient Thermal Resistance θJA 45 °C/W Thermocouple located at center of package underside,
test conducted on 4-layer board with thin traces
1 The device is considered a 2-terminal device: Pin 1 to Pin 8 are shorted together, and Pin 9 to Pin 16 are shorted together.
INSULATION AND SAFETY RELATED SPECIFICATIONS
Table 4.
Parameter Symbol Value Unit Test Conditions/Comments
Input to Output Momentary Withstand Voltage VISO 5000 min V 1 minute duration
Minimum External Air Gap (Clearance) L(I01) 8.3 min1, 2 mm Measured from input terminals to output
terminals, shortest distance through air
Minimum External Tracking (Creepage) L(I02) 8.3 min1 mm Measured from input terminals to output
terminals, shortest distance path along body
Minimum Internal Gap (Internal Clearance) 0.034 min mm Distance through insulation
Tracking Resistance (Comparative Tracking Index) CTI >400 V DIN IEC 112/VDE 0303 Part 13
Isolation Group II Material Group (DIN VDE 0110, 1/89, Table I)3
1 In accordance with IEC 60950-1 guidelines for the measurement of creepage and clearance distances for a pollution degree of 2 and altitudes ≤2000 meters.
2 Consideration must be given to pad layout to ensure the minimum required distance for clearance is maintained.
3 CSA CTI rating for the AD7405 is >600 V and a Material Group I isolation group.
REGULATORY INFORMATION
Table 5.
UL1 CSA VDE2
Recognized under 1577
Component Recognition
Program1
Approved under CSA Component Acceptance Notice 5A Certified according to DIN V VDE V 0884-10
(VDE V 0884-10):2006-122
5000 V rms Isolation Voltage
Single Protection
Basic insulation per CSA 60950-1-07 and IEC 60950-1,
830 V rms (1173 VPEAK) maximum working voltage3
Reinforced insulation per DIN V VDE V 0884-10
(VDE V 0884-10):2006-12, 1250 VPEAK
Reinforced insulation per CSA 60950-1-07 and
IEC 60950-1, 415 V rms (586 VPEAK) maximum working
voltage3
Reinforced insulation per IEC 60601-1, 250 V rms
(353 VPEAK) maximum working voltage
File E214100 File 205078 File 2471900-4880-0001
1 In accordance with UL 1577, each AD7405 is proof tested by applying an insulation test voltage ≥ 6000 V rms for 1 second (current leakage detection limit = 15 µA).
2 In accordance with DIN V VDE V 0884-10, each AD7405 is proof tested by applying an insulation test voltage of ≥ 2344 VPEAK for 1 second (partial discharge detection limit = 5 pC).
3 Rating is calculated for a pollution degree of 2 and a Material Group III. The AD7405 RI-16-2 package material is rated by CSA to a CTI of >600 V and, therefore,
Material Group I.
Rev. A | Page 5 of 20
AD7405 Data Sheet
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 INSULATION CHARACTERISTICS
This isolator is suitable for reinforced electrical isolation only within the safety limit data. Maintenance of the safety data is ensured by
means of protective circuits.
Table 6.
Description Symbol Characteristic Unit
INSTALLATION CLASSIFICATION PER DIN VDE 0110
For Rated Mains Voltage ≤300 V rms I to IV
For Rated Mains Voltage ≤450 V rms I to IV
For Rated Mains Voltage ≤600 V rms I to IV
For Rated Mains Voltage ≤1000 V rms I to IV
CLIMATIC CLASSIFICATION 40/105/21
POLLUTION DEGREE (DIN VDE 0110, TABLE 1) 2
MAXIMUM WORKING INSULATION VOLTAGE
V
IORM
1250
V
PEAK
INPUT TO OUTPUT TEST VOLTAGE, METHOD B1
VIORM × 1.875 = VPR, 100% Production Test, tm = 1 Second, Partial Discharge < 5 pC VPD(M) 2344 VPEAK
INPUT TO OUTPUT TEST VOLTAGE, METHOD A VPR(M)
After Environmental Test Subgroup 1
VIORM × 1.6 = VPR, tm = 60 Seconds, Partial Discharge < 5 pC 2000 VPEAK
After Input and/or Safety Test Subgroup 2/ Safety Test Subgroup 3
VIORM × 1.2 = VPR, tm = 60 Seconds, Partial Discharge < 5 pC 1500 VPEAK
HIGHEST ALLOWABLE OVERVOLTAGE (TRANSIENT OVERVOLTAGE, t
TR
= 10 Seconds)
V
IOTM
8000
V
PEAK
SURGE ISOLATION VOLTAGE VIOSM VPEAK
1.2 µs Rise Time, 50 µs, 50% Fall Time 12000 VPEAK
SAFETY LIMITING VALUES (MAXIMUM VALUE ALLOWED IN THE EVENT OF A FAILURE, SEE Figure 3)
Case Temperature TS 150 °C
Side 1 (PVDD1) and Side 2 (PVDD2) Power Dissipation PSO 2.78 W
INSULATION RESISTANCE AT TS, VIO = 500 V RIO >109 Ω
Figure 3. Thermal Derating Curve, Dependence of Safety Limiting Values
with Case Temperature per DIN V VDE V 0884-10
0
1
2
3
4
050 100 150 200
SAFE OPERATING POWER (W)
AMBIENT TEMPERAT URE ( °C)
12536-003
Rev. A | Page 6 of 20
Data Sheet AD7405
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted. All voltages are relative to
their respective ground.
Table 7.
Parameter Rating
VDD1 to GND1 −0.3 V to +6.5 V
VDD2 to GND2 −0.3 V to +6.5 V
Analog Input Voltage to GND1 −1 V to VDD1 + 0.3 V
Digital Input Voltage to GND2−0.3 V to VDD2 + 0.5 V
Output Voltage to GND2 −0.3 V to VDD2 + 0.3 V
Input Current to Any Pin Except Supplies1 ±10 mA
Operating Temperature Range −40°C to +125°C
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
Pb-Free Temperature, Soldering
Reflow 260°C
ESD 2 kV
FICDM2 ±1250 V
HBM3 ±4000 V
1 Transient currents of up to 100 mA do not cause silicon controlled rectifier (SCR)
to latch up.
2 JESD22-C101; RC Network: 1 Ω, Cpkg; Class: IV.
3 ESDA/JEDEC JS-001-2011; RC Network: 1.5 kΩ, 100 pF; Class: 3A.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Table 8. Maximum Continuous Working Voltage1
Parameter Max (VPEAK) Constraint
AC Voltage
Bipolar Waveform
1250
20-year minimum
lifetime (VDE approved
working voltage)
Unipolar Waveform 1250 20-year minimum
lifetime
DC Voltage 1250 20-year minimum
lifetime
1 Refers to continuous voltage magnitude imposed across the isolation barrier.
ESD CAUTION
Rev. A | Page 7 of 20
AD7405 Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 4. Pin Configuration
Table 9. Pin Function Descriptions
Pin No. Mnemonic Description
1, 7 VDD1 Supply Voltage, 4.5 V to 5.5 V. This pin is the supply voltage for the isolated side of the AD7405 and is relative to
GND1. For device operation, connect the supply voltage to both Pin 1 and Pin 7. Decouple each supply pin to
GND1 with a 10 µF capacitor in parallel with a 1 nF capacitor.
2 VIN+ Positive Analog Input.
3 VIN− Negative Analog Input. Normally connected to GND1.
4, 8 GND1Ground 1. This pin is the ground reference point for all circuitry on the isolated side.
5, 6, 15 NIC Not Internally Connected. Connect to VDD1, GND1, or leave floating.
9, 16 GND2 Ground 2. This pin is the ground reference point for all circuitry on the nonisolated side.
10, 11 MDAT−,
MDAT+
LVDS Data Outputs. The conversion data is output serially on these pins.
12, 13 MCLKIN−,
MCLKIN+
LVDS Clock Inputs. Conversion results are shifted out on the rising edge of MCLKIN+.
14 VDD2 Supply Voltage, 3 V to 5.5 V. This pin is the supply voltage for the nonisolated side and is relative to GND2.
Decouple this supply to GND2 with a 100 nF capacitor.
VDD1 1
VIN+ 2
VIN– 3
GND14
GND2
16
NIC
15
VDD2
14
MCLKIN+
13
NIC 5MCLKIN–
12
NIC 6MDAT+
11
VDD1 7MDAT–
10
GND18GND2
9
AD7405
TOP VIEW
(No t t o Scal e)
NOTES
1. NIC = NOT INT E RNALL Y CONNECTED. CO NNE CT
TO VDD1, GND1, OR LEAVE FLOATING.
12536-004
Rev. A | Page 8 of 20
Data Sheet AD7405
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VDD1 = 5 V, V DD2 = 5 V, VIN+ = −250 mV to +250 mV, VIN− = 0 V, f MCLKIN = 20 MHz, using a sinc3 filter with a 256 oversampling
ratio (OSR), unless otherwise noted.
Figure 5. PSRR vs. Supply Ripple Frequency
Figure 6. CMRR vs. Common-Mode Ripple Frequency
Figure 7. SINAD vs. Analog Input Frequency
Figure 8. Typical Fast Fourier Transform (FFT)
Figure 9. Typical DNL Error
Figure 10. Typical INL Error
–120
–100
–80
–60
–40
–20
0
0200 400 600 800 1000
PSRR ( dB)
SUPPLY RIPPLE FREQUENCY (kHz)
200mV p-p SINE WAVEON VDD1
1nF DECOUPLING
MCLKIN = 20MHz
MCLKIN = 10MHz
12536-005
–140
–120
–100
–80
–60
–40
–20
0
0.1 110 100 1000
CMRR (dB)
RIPPLE FREQUENCY (kHz)
SHORTED INPUTS
200mV p-p SINE WAVEON INPUTS
MCL KIN = 20MHz, SINC3 DECIMATION RATE = 256
MCL KIN = 10MHz, SINC3 DECIMATION RATE = 256
MCL KIN = 20MHz, UNFILTERED
MCL KIN = 10MHz, UNFILTERED
12536-006
70
72
74
76
78
80
82
84
86
88
90
100 1k 10k
SINAD (dB)
ANALOG INPUT F RE QUENCY ( Hz )
16MHz M CLKIN, V
DD1
= 4.5V
16MHz M CLKIN, V
DD1
= 5.0V
16MHz M CLKIN, V
DD1
= 5.5V
20MHz M CLKIN, V
DD1
= 4.5V
20MHz M CLKIN, V
DD1
= 5.0V
20MHz M CLKIN, V
DD1
= 5.5V
12536-007
–160
–140
–120
–100
–80
–60
–40
–20
0
0 5 10 15 20 25 30
MAG NITUDE ( dB)
FREQUENCY (kHz)
SNR = 88.6dB
f
IN =1kHz
SINAD = 88.3dB
THD = –100 .5dB
12536-008
010 20 30 40 50 60
DNL ERRO R ( LSB)
CODE (k)
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
1.0
12536-009
010 20 30 40 50 60
INL ERROR ( LSB)
CODE (k)
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
1.0
12536-010
Rev. A | Page 9 of 20
AD7405 Data Sheet
Figure 11. Histogram of Codes at Code Center
Figure 12. SNR and SINAD vs. Temperature
Figure 13. THD and SFDR vs. Temperature
Figure 14. Offset vs. Temperature
Figure 15. Gain Error vs. Temperature
Figure 16. IDD1 vs. VDD1 at Various Temperatures and Clock Rates
01147
144470
692381
160941
1061 0
0
100
200
300
400
500
600
700
800
32764 32765 32766 32767 32768 32769 32770
HITS PE R CODE ( k)
CODE
MCL KIN = 10MHz
V
IN+
= V
IN–
= 0V
1M SAMPLES
12536-011
60
70
80
100
90
–50 –25 025 50 75 100 125 150
SNR AND SI NAD ( dB)
TEMPERATURE ( °C)
SNR
SINAD
f
IN =1kHz
12536-012
–120
–110
–100
–90
–80
–70
–60
–50 –25 025 50 75 100 125 150
THD AND S FDR (d B)
TEMPERATURE ( °C)
THD
SFDR
f
IN
=1kHz
12536-013
–200
–150
–100
–50
0
50
100
150
200
–50 –25 025 50 75 100 125 150
OFF SET (µV)
TEMPERATURE (°C)
MCL KIN = 20MHz
12536-014
–10
–8
–6
–4
–2
0
2
4
6
8
10
–50 –25 025 50 75 100 125 150
GAI N E RROR (mV )
TEMPERATURE (°C)
MCL KIN = 10MHz
MCL KIN = 20MHz
12536-015
0
5
10
15
20
25
30
35
4.50 4.75 5.00 5.25 5.50
I
DD1
(mA)
V
DD1
(V)
MCL KIN = 20MHz , –40° C
MCL KIN = 20MHz , +25°C
MCL KIN = 20MHz , +85°C
MCL KIN = 20MHz , +125°C
MCL KIN = 10MHz , –40° C
MCL KIN = 10MHz , +25°C
MCL KIN = 10MHz , +85°C
MCL KIN = 10MHz , +125°C
12536-016
Rev. A | Page 10 of 20
Data Sheet AD7405
Figure 17. IDD1 vs. VIN+ DC Input at Various Temperatures
Figure 18. IDD2 vs. VDD2 at Various Temperatures and Clock Rates
Figure 19. IDD2 vs. VIN+ DC Input at Various Temperatures
Figure 20. IIN+ vs. VIN+ DC Input at Various Clock Rates
25
26
27
28
29
30
31
32
–250 –125 0125 250
I
DD1
(mA)
V
IN+
DC INPUT (mV )
DC INPUT
T
A
= –40° C
T
A
= 0° C
T
A
= +25°C
T
A
= +85°C
T
A
= +125°C
12536-017
0
2
4
6
8
10
12
20
18
16
14
3.0 4.03.5 4.5 5.0 5.5
IDD2 (mA)
VDD2 (V)
MCL KIN = 20MHz , –40° C
MCL KIN = 20MHz , +25°C
MCL KIN = 20MHz , +85°C
MCL KIN = 20MHz , +125°C
MCL KIN = 10MHz , –40° C
MCL KIN = 10MHz , +25°C
MCL KIN = 10MHz , +85°C
MCL KIN = 10MHz , +125°C
12536-018
17.0
17.1
17.2
17.3
17.4
–250 –125 0
V
IN+
DC INPUT (mV ) 125 250
I
DD2
(mA)
DC INPUT
T
A
= –40° C
T
A
= 0° C
T
A
= +25°C
T
A
= +85°C
T
A
= +125°C
12536-019
–60
–40
–20
0
20
40
60
–320 –240 –160 –80 080 160 240 320
I
IN+
(µA)
V
IN+
DC INPUT (mV )
MCL KIN = 5MHz
MCL KIN = 10MHz
MCL KIN = 20MHz
DC INPUT
12536-020
Rev. A | Page 11 of 20
AD7405 Data Sheet
TERMINOLOGY
Differential Nonlinearity (DNL)
DNL is the difference between the measured and the ideal
1 LSB change between any two adjacent codes in the ADC.
Integral Nonlinearity (INL)
INL is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function. The
endpoints of the transfer function are a specified negative full
scale, −250 mV (VIN+ − VIN−), Code 7168 for the 16-bit level,
and a specified positive full scale, +250 mV (VIN+ − VIN−),
Code 58,368 for the 16-bit level.
Offset Error
Offset error is the deviation of the midscale code (32,768 for the
16-bit level) from the ideal VIN+ − VIN− (that is, 0 V).
Gain Error
The gain error includes both positive full-scale gain error and
negative full-scale gain error. Positive full-scale gain error is the
deviation of the specified positive full-scale code (58,368 for the
16-bit level) from the ideal VIN+ − VIN− (250 mV) after the offset
error is adjusted out. Negative full-scale gain error is the
deviation of the specified negative full-scale code (7168 for the
16-bit level) from the ideal VIN+ − VIN− (−250 mV) after the
offset error is adjusted out.
Signal-to-Noise-and-Distortion Ratio (SINAD)
SINAD is the measured ratio of signal-to-noise-and-distortion
at the output of the ADC. The signal is the rms value of the sine
wave, and noise is the rms sum of all nonfundamental signals
up to half the sampling frequency (fS/2), including harmonics,
but excluding dc.
Signal-to-Noise Ratio (SNR)
SNR is the measured signal-to-noise ratio at the output of the
ADC. The signal is the rms amplitude of the fundamental. Noise
is the sum of all nonfundamental signals up to half the sampling
frequency (fS/2), excluding dc.
The ratio is dependent on the number of quantization levels in the
digitization process: the greater the number of levels, the smaller
the quantization noise. The theoretical SNR for an ideal N-bit
converter with a sine wave input is given by
Signal-to-Noise Ratio = (6.02N + 1.76) dB
Therefore, for a 12-bit converter, the SNR is 74 dB.
Isolation Transient Immunity
The isolation transient immunity specifies the rate of rise and
fall of a transient pulse applied across the isolation boundary,
beyond which clock or data is corrupted. The AD7405 was
tested using a transient pulse frequency of 100 kHz.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of harmonics to the
fundamental. For the AD7405, it is defined as
1
6
54
32
V
VVVVV
THD
22222
log20(dB) ++++
=
where:
V1 is the rms amplitude of the fundamental.
V2, V3, V4, V5, and V6 are the rms amplitudes of the second
through the sixth harmonics.
Peak Harmonic or Spurious Noise
Peak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to fS/2, excluding dc) to the rms value of the
fundamental. Normally, the value of this specification is
determined by the largest harmonic in the spectrum, but for
ADCs where the harmonics are buried in the noise floor, it is a
noise peak.
Effective Number of Bits (ENOB)
ENOB is defined by
ENOB = (SINAD − 1.76)/6.02 bits
Noise Free Code Resolution
Noise free code resolution represents the resolution in bits for
which there is no code flicker. The noise free code resolution
for an N-bit converter is defined as
Noise Free Code Resolution (Bits) = log2(2N/Peak-to-Peak Noise)
The peak-to-peak noise in LSBs is measured with VIN+ = VIN− = 0 V.
Common-Mode Rejection Ratio (CMRR)
CMRR is defined as the ratio of the power in the ADC output at
±250 mV frequency, f, to the power of a +250 mV peak-to-peak
sine wave applied to the common-mode voltage of VIN+ and VIN−
of frequency, fS, as
CMRR (dB) = 10 log(Pf/PfS)
where:
Pf is the power at frequency, f, in the ADC output.
PfS is the power at frequency, fS, in the ADC output.
Power Supply Rejection Ratio (PSRR)
Variations in power supply affect the full-scale transition but
not the linearity of the converter. PSRR is the maximum change
in the specified full-scale (±250 mV) transition point due to a
change in power supply voltage from the nominal value.
Rev. A | Page 12 of 20
Data Sheet AD7405
THEORY OF OPERATION
CIRCUIT INFORMATION
The AD7405 isolated Σ-Δ modulator converts an analog input
signal into a high speed (20 MHz maximum), single-bit data
stream; the time average single-bit data from the modulator is
directly proportional to the input signal. Figure 21 shows a
typical application circuit where the AD7405 is used to provide
isolation between the analog input, a current sensing resistor or
shunt, and the digital output, which is then processed by a
digital filter to provide an N-bit word.
ANALOG INPUT
The differential analog input of the AD7405 is implemented
with a switched capacitor circuit. This circuit implements a
second-order modulator stage that digitizes the input signal
into a single-bit output stream. The sample clock (MCLKIN)
provides the clock signal for the conversion process as well as
the output data framing clock. This clock source is external on
the AD7405. The analog input signal is continuously sampled
by the modulator and compared to an internal voltage
reference. A digital stream that accurately represents the
analog input over time appears at the output of the converter
(see Figure 22).
A differential input signal of 0 V ideally results in a differential
stream of alternating 1s and 0s at the MDAT± output pins. This
output is high 50% of the time and low 50% of the time. A
differential input of 250 mV produces a stream of 1s and 0s that
are high 89.06% of the time. A differential input of −250 mV
produces a stream of 1s and 0s that are high 10.94% of the time.
A differential input of 320 mV ideally results in a stream of all
1s. A differential input of −320 mV ideally results in a stream of
all 0s. The absolute full-scale range is ±320 mV, and the specified
full-scale performance range is ±250 mV, as shown in Table 10.
Table 10. Analog Input Range
Analog Input Voltage Input (mV)
Positive Full-Scale Value +320
Positive Specified Performance Input +250
Zero 0
Negative Specified Performance Input −250
Negative Full-Scale Value −320
Figure 21. Typical Application Circuit
Figure 22. Analog Input vs. Modulator Output
Σ-Δ
MOD/
ENCODER
NONISOLATED
5V/3V
V
DD1
GND
1
V
IN+
V
IN–
GND
1
V
DD1
V
DD
GND
V
DD2
MDAT+
MDAT– MDAT
SINC3 FILTER*
AD7405
MCLKIN+
SDAT
CS
SCLK
MCLKIN– MCLK
100nF
GND
2
DECODER
1nF10µF
+400V
–400V
220pF
220pF
10Ω
5.1V
R
SHUNT
10Ω
DECODER
ENCODER
1nF10µF
GATED
DRIVE
CIRCUIT
FLOATING
POWER SUPPLY
GATED
DRIVE
CIRCUIT
FLOATING
POWER SUPPLY
MOTOR
*THIS FILTER IS IMPLEMENTED
WITH AN FPGA O R DS P
100Ω
100Ω
12536-021
MO DULATOR O UTPUT
+FS ANALO G I NP UT
–FS ANALOG I NP UT
ANALOG INPUT
12536-022
Rev. A | Page 13 of 20
AD7405 Data Sheet
To reconstruct the original information, this output must be
digitally filtered and decimated. A sinc3 filter is recommended
because it is one order higher than that of the AD7405 modulator,
which is a second-order modulator. If a 256 decimation rate is
used, the resulting 16-bit word rate is 78.1 kSPS, assuming a
20 MHz external clock frequency. See the Digital Filter section
for more detailed information on the sinc filter implementation.
Figure 23 shows the transfer function of the AD7405 relative to
the 16-bit output.
Figure 23. Filtered and Decimated 16-Bit Transfer Function
DIFFERENTIAL INPUTS
The analog input to the modulator is a switched capacitor
design. The analog signal is converted into charge by highly
linear sampling capacitors. A simplified equivalent circuit
diagram of the analog input is shown in Figure 24. A signal
source driving the analog input must provide the charge onto
the sampling capacitors every half MCLKIN cycle and settle to the
required accuracy within the next half cycle.
Figure 24. Analog Input Equivalent Circuit
Because the AD7405 samples the differential voltage across its
analog inputs, an input circuit provides low common-mode
noise at each input attaining low noise performance.
LOW VOLTAGE DIFFERENTIAL SIGNALING (LVDS)
INTERFACE
The AD7405 uses an LVDS interface for both the clock input
and the modulator output. The benefits of using LVDS in this
case helps to make the interface between the modulator and the
controller more robust and less susceptible to electromagnetic
interference (EMI) from the surroundings. LVDS also helps to
reduce the EMI emissions associated with high speed digital
signaling. LVDS signals are treated like transmission lines and
must be resistively terminated. The value of the differential
terminating resistor is typically 100 Ω. Place the terminating
resistor as close to the receiver as possible.
65535
58368
SPECIF IED RANGE
ANALOG INPUT
ADC CODE
7168
–320mV –250mV +250mV +320mV
0
12536-023
φA
φB
300Ω
V
IN–
φA
φB
φB φB
300Ω
V
IN+
1.9pF
1.9pF
φA φA
MCLKIN
12536-024
Rev. A | Page 14 of 20
Data Sheet AD7405
APPLICATIONS INFORMATION
CURRENT SENSING APPLICATIONS
The AD7405 is ideally suited for current sensing applications
where the voltage across a shunt resistor (RSHUNT) is monitored.
The load current flowing through an external shunt resistor
produces a voltage at the input terminals of the AD7405. The
AD7405 provides isolation between the analog input from the
current sensing resistor and the digital outputs. By selecting the
appropriate shunt resistor value, a variety of current ranges can
be monitored.
Choosing RSHUNT
The shunt resistor (RSHUNT) values used in conjunction with the
AD7405 are determined by the specific application requirements
in terms of voltage, current, and power. Small resistors minimize
power dissipation, whereas low inductance resistors prevent any
induced voltage spikes, and good tolerance devices reduce
current variations. The final values chosen are a compromise
between low power dissipation and accuracy. Higher value
resistors use the full performance input range of the ADC, thus
achieving maximum SNR performance. Low value resistors
dissipate less power but do not use the full performance input
range. The AD7405, however, delivers excellent performance,
even with lower input signal levels, allowing low value shunt
resistors to be used while maintaining system performance.
To choose a suitable shunt resistor, first determine the current
through the shunt. The shunt current for a 3-phase induction
motor can be expressed as
PFEFV
P
I
W
RMS
×××
=73.1
where:
IRMS is the motor phase current (A rms).
PW is the motor power (Watts).
V is the motor supply voltage (V ac).
EF is the motor efficiency (%).
PF is the power efficiency (%).
To determine the shunt peak sense current, ISENSE, consider the
motor phase current and any overload that may be possible in
the system. When the peak sense current is known, divide the
voltage range of the AD7405 (±250 mV) by the peak sense
current to yield a maximum shunt value.
If the power dissipation in the shunt resistor is too large, the
shunt resistor can be reduced and less of the ADC input range can
be used. Figure 25 shows the SINAD performance characteristics
and the ENOB of resolution for the AD7405 for different input
signal amplitudes. Figure 26 shows the rms noise performance
for dc input signal amplitudes. The AD7405 performance at
lower input signal ranges allows smaller shunt values to be used
while still maintaining a high level of performance and overall
system efficiency.
Figure 25. SINAD vs. VIN+ AC Input Signal Amplitude
Figure 26. RMS Noise vs. VIN+ DC Input Signal Amplitude
RSHUNT must be able to dissipate the I2R power losses. If the
power dissipation rating of the resistor is exceeded, its value
may drift or the resistor may be damaged, resulting in an open
circuit. This open circuit can result in a differential voltage
across the terminals of the AD7405, in excess of the absolute
maximum ratings. If ISENSE has a large, high frequency
component, choose a resistor with low inductance.
VOLTAGE SENSING APPLICATIONS
The AD7405 can also be used for isolated voltage monitoring.
For example, in motor control applications, it can be used to
sense the bus voltage. In applications where the voltage being
monitored exceeds the specified analog input range of the
AD7405, a voltage divider network can be used to reduce the
voltage being monitored to the required range.
60
65
70
75
80
85
90
050 100 150 200 250
SINAD (dB)
V
IN+
AC INPUT SIG NAL AMP LI TUDE ( mV )
14 -BIT
ENOB
11-BIT
ENOB
12-BIT
ENOB
13-BIT
ENOB
fIN
= 1kHz
T
A
= 25° C
MCL KIN = 20MHz
V
DD1
= 5V
V
DD2
= 5V
12536-025
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
–320 –240 –160 –80 080 160 240 320
RMS NOISE (LSB)
MCL KIN = 5MHz
MCL KIN = 10MHz
MCL KIN = 20MHz
V
IN+
DC INPUT SIG NAL AMP LI TUDE ( mV )
DC INPUT
100k SAMP LES P E R DATA POI NT
12536-026
Rev. A | Page 15 of 20
AD7405 Data Sheet
INPUT FILTER
In a typical application, where voltage is being measured across
a shunt resistor, connect the AD7405 directly across the shunt
resistor with a simple RC low-pass filter on each input.
The recommended circuit configuration for driving the
differential inputs to achieve best performance is shown in
Figure 27. An RC low-pass filter is placed on both the analog
input pins. Recommended values for the resistors and capacitors
are 10 Ω and 220 pF, respectively. If possible, equalize the
source impedance on each analog input to minimize offset.
Figure 27. RC Low-Pass Filter Input Network
The input filter configuration for the AD7405 is not limited to
the low-pass structure shown in Figure 27. The differential RC
filter configuration shown in Figure 28 also achieves excellent
performance. Recommended values for the resistors and
capacitor are 22 Ω and 47 pF, respectively.
Figure 28. Differential RC Filter Input Network
Figure 29 compares the typical performance for the input filter
structures outlined in Figure 27 and Figure 28 for different
resistor and capacitor values.
Figure 29. SNR vs. Decimation Rate for Different Filter Structures for Different
Resistor and Capacitor Values
DIGITAL FILTER
The output of the AD7405 is a continuous LVDS digital bit stream.
To reconstruct the original input signal information, this output
bit stream needs to be digitally filtered and decimated. A sinc
filter is recommended due to its simplicity. A sinc3 filter is
recommended because it is one order higher than that of the
AD7405 modulator, which is a second-order modulator. The type
of filter selected, the decimation rate, and the modulator clock used
determines the overall system resolution and throughput rate. The
higher the decimation rate, the greater the system accuracy, as
illustrated in Figure 30. However, there is a trade-off between
accuracy and throughput rate and, therefore, higher decimation
rates result in lower throughput solutions. Note that for a given
bandwidth requirement, a higher MCLKIN frequency can allow
higher decimation rates to be used, resulting in higher SNR
performance.
Figure 30. SNR vs. Decimation Rate for Different Sinc Filter Orders
A sinc3 filter is recommended for use with the AD7405. This
filter can be implemented on a field programmable gate array
(FPGA) or a digital signal processor (DSP).
Equation 1 describes the transfer function of a sinc filter.
( )
( )
N
DR
Z
Z
DR
zH
−
−
=
−
−
1
1
11
)(
(1)
where DR is the decimation rate and N is the sinc filter order.
The throughput rate of the sinc filter is determined by the
modulator clock and the decimation rate selected.
DR
MCLK
Throughput =
(2)
where MCLK is the modulator clock frequency
As the decimation rate increases, the data output size from the
sinc filter increases. The output data size is expressed
in Equation 3. The 16 most significant bits are used to return a
16-bit result.
Data size = N × log2 DR (3)
R
V
IN–
R
V
IN+
C
C
AD7405
12536-027
R
VIN–
R
VIN+
CAD7405
12536-028
50
55
60
65
70
75
80
85
90
95
10 100 1000
SNR (dB)
DECIMATIO N RATE
LOW PASS, 10Ω, 220pF
DIFFERENTIAL, 22Ω, 47pF
DIFFERENTIAL, 22Ω, 10nF
fIN = 1kHz
12536-029
0
10
20
30
40
50
60
70
80
90
100
10 100 1000
SNR (dB)
DECIMATION RATE
SINC1
SINC2
SINC3
SINC4
f
IN
=1kHz
12536-030
Rev. A | Page 16 of 20
Data Sheet AD7405
For a sinc3 filter, the −3 dB filter response point can be derived
from the filter transfer function, Equation 1, and is 0.262 times
the throughput rate. The filter characteristics for a third-order
sinc3 filter are summarized in Table 11.
Table 11. Sinc3 Filter Characteristics for 20 MHz MCLKIN
Decimation
Ratio (DR)
Throughput
Rate (kHz)
Output Data
Size (Bits)
Filter
Response (kHz)
32 625 15 163.7
64 312.5 18 81.8
128 156.2 21 40.9
256 78.1 24 20.4
512 39.1 27 10.2
The following Verilog code provides an example of a sinc3 filter
implementation on a Xilinx® Spartan®-6 FPGA. Note that the
data is read on the positive clock edge. It is recommended to
read in the data on the positive clock edge. The code is
configurable to accommodate decimation rates from 32 to 4096.
module dec256sinc24b
(
input mclk1, /* used to clk filter */
input reset, /* used to reset filter */
input mdata1, /* input data to be filtered
*/
output reg [15:0] DATA, /* filtered output
*/
output reg data_en,
input [15:0] dec_rate
);
/* Data is read on positive clk edge */
reg [36:0] ip_data1;
reg [36:0] acc1;
reg [36:0] acc2;
reg [36:0] acc3;
reg [36:0] acc3_d2;
reg [36:0] diff1;
reg [36:0] diff2;
reg [36:0] diff3;
reg [36:0] diff1_d;
reg [36:0] diff2_d;
reg [15:0] word_count;
reg word_clk;
reg enable;
/*Perform the Sinc action*/
always @ (mdata1)
if(mdata1==0)
ip_data1 <= 37'd0;
/* change 0 to a -1 for twos
complement */
else ip_data1 <= 37'd1;
/*Accumulator (Integrator)
Perform the accumulation (IIR) at the speed
of the modulator.
Z = one sample delay MCLKOUT = modulators
conversion bit rate */
Figure 31. Accumulator
always @ (negedge mclk1, posedge reset)
begin if (reset)
begin
/* initialize acc registers on reset
*/ acc1 <= 37'd0;
acc2 <= 37'd0;
acc3 <= 37'd0;
end
else
begin
/*perform accumulation process */
acc1 <= acc1 + ip_data1;
acc2 <= acc2 + acc1;
acc3 <= acc3 + acc2;
end
end
/*decimation stage (MCLKOUT/WORD_CLK) */
always @ (posedge mclk1, posedge reset)
begin if (reset)
word_count <= 16'd0;
else
begin if ( word_count == dec_rate -
1 ) word_count <= 16'd0;
else word_count <= word_count
+ 16'b1;
end
end
always @ ( posedge mclk1, posedge reset )
begin if ( reset )
word_clk <= 1'b0;
else
begin if ( word_count == dec_rate/2 -
1 ) word_clk <= 1'b1;
else if ( word_count ==
dec_rate - 1 ) word_clk <= 1'b0;
end
end
/*Differentiator (including decimation
stage)
Perform the differentiation stage (FIR) at a
lower speed.
MCLKIN
IP_DATA1
ACC1+ ACC2+ ACC3+
+Z
+Z
+Z
12536-031
Rev. A | Page 17 of 20
AD7405 Data Sheet
Z = one sample delay WORD_CLK = output word
rate */
Figure 32. Differentiator
always @ (posedge word_clk, posedge reset)
begin
if(reset)
begin acc3_d2 <= 37'd0;
diff1_d <= 37'd0;
diff2_d <= 37'd0;
diff1 <= 37'd0;
diff2 <= 37'd0;
diff3 <= 37'd0;
end
else
begin
diff1 <= acc3 - acc3_d2;
diff2 <= diff1 - diff1_d;
diff3 <= diff2 - diff2_d;
acc3_d2 <= acc3;
diff1_d <= diff1;
diff2_d <= diff2;
end
end
/* Clock the Sinc output into an output
register
WORD_CLK = output word rate */
Figure 33. Clocking Sinc3 Output into an Output Register
always @ ( posedge word_clk )
begin
case ( dec_rate )
16'd32:begin
DATA <= (diff3[15:0] ==
16'h8000) ? 16'hFFFF : {diff3[14:0], 1'b0};
end
16'd64:begin
DATA <= (diff3[18:2] ==
17'h10000) ? 16'hFFFF : diff3[17:2];
end
16'd128:begin
DATA <= (diff3[21:5] ==
17'h10000) ? 16'hFFFF : diff3[20:5];
end
16'd256:begin
DATA <= (diff3[24:8] ==
17'h10000) ? 16'hFFFF : diff3[23:8];
end
16'd512:begin
DATA <= (diff3[27:11] ==
17'h10000) ? 16'hFFFF : diff3[26:11];
end
16'd1024:begin
DATA <= (diff3[30:14] ==
17'h10000) ? 16'hFFFF : diff3[29:14];
end
16'd2048:begin
DATA <= (diff3[33:17] ==
17'h10000) ? 16'hFFFF : diff3[32:17];
end
16'd4096:begin
DATA <= (diff3[36:20] ==
17'h10000) ? 16'hFFFF : diff3[35:20];
end
default:begin
DATA <= (diff3[24:8] ==
17'h10000) ? 16'hFFFF : diff3[23:8];
end
endcase
end
/* Synchronize Data Output*/
always@ ( posedge mclk1, posedge reset )
begin
if ( reset )
begin data_en <= 1'b0;
enable <= 1'b1;
end
else
begin if ( (word_count == dec_rate/2
- 1) && enable )
begin data_en <= 1'b1;
enable <= 1'b0;
end
else if ( (word_count ==
dec_rate - 1) && ~enable )
begin data_en <= 1'b0;
enable <= 1'b1;
end
else data_en <= 1'b0;
end
end
endmodule
WORD_CLK
ACC3 DIFF1 DIFF3
+
–
+
–
DIFF2
Z
–1
–
+
–
Z
–1
Z
–1
12536-032
WORD_CLK
DATA
DIFF3
12536-033
Rev. A | Page 18 of 20
Data Sheet AD7405
GROUNDING AND LAYOUT
It is recommended to decouple the VDD1 supply with a 10 µF
capacitor in parallel with a 1 nF capacitor to GND1. Decouple
Pin 1 and Pin 7 individually. Decouple the VDD2 supply with a
100 nF value to GND2. In applications involving high common-
mode transients, minimize board coupling across the isolation
barrier. Furthermore, design the board layout so that any
coupling that occurs equally affects all pins on a given
component side. Failure to ensure equal coupling can cause
voltage differentials between pins to exceed the absolute
maximum ratings of the device, thereby leading to latch-up or
permanent damage. Place any decoupling used as close to the
supply pins as possible.
Minimize series resistance in the analog inputs to avoid any
distortion effects, especially at high temperatures. If possible,
equalize the source impedance on each analog input to minimize
offset. To reduce offset drift, check for mismatch and thermocouple
effects on the analog input printed circuit board (PCB) tracks.
INSULATION LIFETIME
All insulation structures eventually break down when subjected
to voltage stress over a sufficiently long period. The rate of
insulation degradation is dependent on the characteristics of the
voltage waveform applied across the insulation. In addition to
the testing performed by the regulatory agencies, Analog
Devices carries out an extensive set of evaluations to determine
the lifetime of the insulation structure within the AD7405.
Analog Devices performs accelerated life testing using voltage
levels higher than the rated continuous working voltage.
Acceleration factors for several operating conditions are
determined. These factors allow calculation of the time to
failure at the actual working voltage. The values shown in Table 8
summarize the peak voltage for 20 years of service life for a
bipolar, ac operating condition and the maximum VDE
approved working voltages.
These tests subjected the AD7405 to continuous cross isolation
voltages. To accelerate the occurrence of failures, the selected
test voltages were values exceeding those of normal use. The
time to failure values of these units were recorded and used to
calculate the acceleration factors. These factors were then used
to calculate the time to failure under the normal operating
conditions. The values shown in Table 8 are the lesser of the
following two values:
•The value that ensures at least a 20-year lifetime of
continuous use.
•The maximum VDE approved working voltage.
Note that the lifetime of the AD7405 varies according to the
waveform type imposed across the isolation barrier. The
iCoupler insulation structure is stressed differently, depending
on whether the waveform is bipolar ac, unipolar ac, or dc.
Figure 34, Figure 35, and Figure 36 illustrate the different
isolation voltage waveforms.
Figure 34. Bipolar AC Waveform, 50 Hz or 60 Hz
Figure 35. Unipolar AC Waveform, 50 Hz or 60 Hz
Figure 36. DC Waveform
0V
RATE D PE AK V OL TAG E
12536-034
0V
RATE D PE AK V OL TAG E
12536-035
0V
RATE D PE AK V OL TAG E
12536-036
Rev. A | Page 19 of 20
AD7405 Data Sheet
OUTLINE DIMENSIONS
Figure 37. 16-Lead Standard Small Outline Package, with Increased Creepage [SOIC_IC]
Wide Body
(RI-16-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description
Package
Option
AD7405BRIZ −40°C to +125°C 16-Lead Standard Small Outline Package, with Increased Creepage [SOIC_IC] RI-16-2
AD7405BRIZ-RL
−40°C to +125°C
16-Lead Standard Small Outline Package, with Increased Creepage [SOIC_IC]
RI-16-2
AD7405BRIZ-RL7 −40°C to +125°C 16-Lead Standard Small Outline Package, with Increased Creepage [SOIC_IC] RI-16-2
EVAL-AD7405FMCZ Evaluation Board
EVAL-SDP-CH1Z System Demonstration Platform
1 Z = RoHS Compliant Part.
11-15-2011-A
16 9
81
SEATING
PLANE
COPLANARITY
0.1
1.27 BSC
12.85
12.75
12.65
7.60
7.50
7.40
2.64
2.54
2.44
1.01
0.76
0.51
0.30
0.20
0.10
10.51
10.31
10.11
0.46
0.36
2.44
2.24
PIN 1
MARK
1.93 REF
8°
0°
0.32
0.23
0.71
0.50
0.31 45°
0.25 BSC
GAGE
PLANE
COMPLIANT TO JE DE C S TANDARDS MS-013-AC
©2014 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D12536-0-11/14(A)
Rev. A | Page 20 of 20