CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper I.C. Handling Procedures.
Copyright © Harris Corporation 1993
December 1993
8-5
SEMICONDUCTOR
AD7520, AD7530
AD7521, AD7531
10-Bit, 12-Bit Multiplying D/A Converters
Description
The AD7520/AD7530 and AD7521/AD7531 are monolithic,
high accuracy, low cost 10-bit and 12-bit resolution,
multiplying digital-to-analog converters (DAC). Harris' thin-
film on CMOS processing gives up to 10-bit accuracy with
TTL/CMOS compatible operation. Digital inputs are fully
protected against static discharge by diodes to ground and
positive supply.
Typical applications include digital/analog interfacing,
multiplication and division, programmable power supplies,
CRT character generation, digitally controlled gain circuits,
integrators and attenuators, etc.
The AD7530 and AD7531 are identical to the AD7520 and
AD7521, respectively, with the exception of output leakage
current and feedthrough specifications.
Features
• AD7520/AD7530 10 Bit Resolution; 8, 9 and 10 Bit
Linearity
• AD7521/AD7531 12 Bit Resolution; 8, 9 and 10 Bit
Linearity
• Low Power Dissipation of 20mW (Max)
• Low Nonlinearity Tempco at 2ppm of FSR/oC
• Current Settling Time 1.0µs to 0.05% of FSR
•±5V to +15V Supply Voltage Range
• TTL/CMOS Compatible
• Full Input Static Protection
• /883B Processed Versions Available
File Number 3104
December 1993
Ordering Information
PART NUMBER NONLINEARITY TEMPERATURE RANGE PACKAGE
AD7520JN, AD7530JN 0.2% (8-Bit) 0oC to +70oC 16 Lead Plastic DIP
AD7520KN, AD7530KN 0.1% (9-Bit) 0oC to +70oC 16 Lead Plastic DIP
AD7521JN, AD7531JN 0.2% (8-Bit) 0oC to +70oC 18 Lead Plastic DIP
AD7521KN, AD7531KN 0.1% (9-Bit) 0oC to +70oC 18 Lead Plastic DIP
AD7520LN, AD7530LN 0.05% (10-Bit) -40oC to +85oC 16 Lead Plastic DIP
AD7521LN, AD7531LN 0.05% (10-Bit) -40oC to +85oC 18 Lead Plastic DIP
AD7520JD 0.2% (8-Bit) -25oC to +85oC 16 Lead Ceramic DIP
AD7520KD 0.1% (9-Bit) -25oC to +85oC 16 Lead Ceramic DIP
AD7520LD 0.05% (10-Bit) -25oC to +85oC 16 Lead Ceramic DIP
AD7520SD, AD7520SD/883B 0.2% (8-Bit) -55oC to +125oC 16 Lead Ceramic DIP
AD7520TD 0.1% (9-Bit) -55oC to +125oC 16 Lead Ceramic DIP
AD7520UD, AD7520UD/883B 0.05% (10-Bit) -55oC to +125oC 16 Lead Ceramic DIP
Pinouts
AD7520, AD7530 (CDIP, PDIP)
TOP VIEW AD7521, AD7531 (PDIP)
TOP VIEW
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
IOUT1
IOUT2
GND
BIT 1 (MSB)
BIT 2
BIT 3
BIT 5
BIT 4
RFEEDBACK
V+
BIT 10 (LSB)
BIT 9
BIT 8
BIT 7
BIT 6
VREF
IOUT1
IOUT2
GND
BIT 1 (MSB)
BIT 2
BIT 3
BIT 5
BIT 4
RFEEDBACK
V+
BIT 11
BIT 9
BIT 8
BIT 7
VREF
10
11
12
13
14
15
16
17
18
9
8
7
6
5
4
3
2
1
BIT 12 (LSB)
BIT 10
BIT 6
8-6
Specifications AD7520, AD7530, AD7521, AD7531
Absolute Maximum Ratings Thermal Information
Supply Voltage (V+ to GND). . . . . . . . . . . . . . . . . . . . . . . . . . . +17V
VREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25V
Digital Input Voltage Range . . . . . . . . . . . . . . . . . . . . . . .V+ to GND
Output Voltage Compliance . . . . . . . . . . . . . . . . . . . . -100mV to V+
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . -65oC to +150oC
Lead Temperature (Soldering 10s). . . . . . . . . . . . . . . . . . . . . 300oC
Thermal Resistance θJA θJC
16 Lead Plastic DIP. . . . . . . . . . . . . . . . . 100oC/W -
18 Lead Plastic DIP. . . . . . . . . . . . . . . . . 90oC/W -
16 Lead Ceramic DIP . . . . . . . . . . . . . . . 80oC/W 24oC/W
Maximum Power Dissipation
Up to +75oC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450mW
Derate Above +75oC at 6mW/oC
Operating Temperature
JN, KN, LN Versions . . . . . . . . . . . . . . . . . . . . . . . . 0oC to +70oC
JD, KD, LD Versions . . . . . . . . . . . . . . . . . . . . . . .-25oC to +85oC
SD, TD, UD Versions. . . . . . . . . . . . . . . . . . . . . .-55oC to +125oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
The digital control inputs are zener protected; however , permanent damage may occur on unconnected units under high energy electrostatic fields. Keep unused
units in conductive foam at all times.
Do not apply voltages higher than V
DD
or less than GND potential on any terminal except V
REF
and R
FEEDBACK
.
Electrical Specifications V+ = +15V, VREF = +10V, TA = +25oC Unless Otherwise Specified
PARAMETER TEST CONDITIONS
AD7520/AD7530 AD7521/AD7531
UNITSMIN TYP MAX MIN TYP MAX
SYSTEM PERFORMANCE (Note 1)
Resolution 10 10 10 12 12 12 Bits
Nonlinearity J, S S Over -55oC to +125oC
(Notes 2, 5) (Figure 2) --±0.2
(8-Bit) --±0.2
(8-Bit) % of
FSR
K, T T Over -55oC to +125oC
(Figure 2) --±0.1
(9-Bit) --±0.1
(9-Bit) % of
FSR
L, U -10V ≤ VREF ≤ +10V
U Over -55oC to +125oC
(Figure 2)
--±0.05
(10-Bit) --±0.05
(10-Bit) % of
FSR
Nonlinearity Tempco -10V ≤ VREF ≤ +10V
(Notes 2, 3) -- ±2- - ±2 ppm of
FSR/oC
Gain Error - ±0.3 - - ±0.3 - % of
FSR
Gain Error Tempco - - ±10 - - ±10 ppm of
FSR/oC
Output Leakage Current
(Either Output) Over the Specified
Temperature Range --±200
(±300) --±200
(±300) nA
DYNAMIC CHARACTERISTICS
Output Current Settling Time To 0.05% of FSR (All Digital
Inputs Low To High And High
To Low) (Note 3) (Figure 7)
- 1.0 - - 1.0 - µs
Feedthrough Error VREF = 20VP-P, 10kHz
(50kHz) All Digital Inputs Low
(Note 3) (Figure 6)
- - 10 - - 10 mVP-P
REFERENCE INPUT
Input Resistance All Digital Inputs High
IOUT1 at Ground 5 10 20 5 10 20 kΩ
ANALOG OUTPUT
Output Capacitance IOUT1 All Digital Inputs High
(Note 3) (Figure 5) - 200 - - 200 - pF
IOUT2 -75 --75 -pF
I
OUT1 All Digital Inputs Low
(Note 3) (Figure 5) -75 --75 -pF
I
OUT2 - 200 - - 200 - pF
8-7
Specifications AD7520, AD7530, AD7521, AD7531
Functional Diagram
Switches shown for Digital Inputs “High”.
Resistor values are typical.
Output Noise Both Outputs
(Note 3) (Figure 4) - Equivalent
to 10kΩ- - Equivalent
to 10kΩ- Johnson
Noise
DIGITAL INPUTS
Low State Threshold, VIL Over the Specified
Temperature Range
VIN = 0V or +15V
- - 0.8 - - 0.8 V
High State Threshold, VIH 2.4 - - 2.4 - - V
Input Current, IIL, IIH -- ±1- - ±1µA
Input Coding See Tables 1 & 2 Binary/Offset Binary
POWER SUPPLY CHARACTERISTICS
Power Supply Rejection V+ = 14.5V to 15.5V
(Note 2) (Figure 3) -±0.005 - - ±0.005 - %
FSR/%
∆V+
Power Supply Voltage Range +5 to +15 +5 to +15 V
I+ All Digital Inputs at 0V or V+
Excluding Ladder Network -±1--±1-µA
All Digital Inputs High or Low
Excluding Ladder Network -- 2-- 2mA
Total Power Dissipation Including the Ladder Network - 20 - - 20 - mW
NOTES:
1. Full scale range (FSR) is 10V for Unipolar and ±10V for Bipolar modes.
2. Using internal feedback resistor RFEEDBACK.
3. Guaranteed by design, or characterization and not production tested.
4. Accuracy not guaranteed unless outputs at GND potential.
5. Accuracy is tested and guaranteed at V+ = 15V only.
Electrical Specifications V+ = +15V, VREF = +10V, TA = +25oC Unless Otherwise Specified (Continued)
PARAMETER TEST CONDITIONS
AD7520/AD7530 AD7521/AD7531
UNITSMIN TYP MAX MIN TYP MAX
20kΩ
GND
IOUT2
IOUT1
RFEEDBACK
BIT 3BIT 2MSB
VREF
20kΩ20kΩ20kΩ20kΩ20kΩ
10kΩ10kΩ10kΩ10kΩ
SPDT NMOS
SWITCHES
10kΩ
8-8
AD7520, AD7530, AD7521, AD7531
Pin Descriptions
AD7520/30 AD7521/31 PIN NAME DESCRIPTION
11I
OUT1 Current Out summing junction of the R2R ladder network.
22I
OUT2 Current Out virtual ground, return path for the R2R ladder network
3 3 GND Digital Ground. Ground potential for digital side of D/A.
4 4 Bits 1(MSB) Most Significant Digital Data Bit
5 5 Bit 2 Digital Bit 2
6 6 Bit 3 Digital Bit 3
7 7 Bit 4 Digital Bit 4
8 8 Bit 5 Digital Bit 5
9 9 Bit 6 Digital Bit 6
10 10 Bit 7 Digital Bit 7
11 11 Bit 8 Digital Bit 8
12 12 Bit 9 Digital Bit 9
13 13 Bit 10 Digital Bit 10 (AD7521/31), Least Significant Digital Data Bit (AD7520/30)
- 14 Bit 11 Digital Bit 11 (AD7521/31)
- 15 Bit 12 Least Significant Digital Data Bit (AD7521/31)
14 16 V+ Power Supply +5 to +15 Volts
15 17 VREF Voltage Reference Input to set the output range. Supplies the R2R resistor ladder.
16 18 RFEEDBACK Feedback resistor used for the current to voltage conversion when using and external OP-Amp.
Definition of Terms
Nonlinearity: Error contributed by deviation of the DAC
transfer function from a “best straight line” through the actual
plot of transfer function. Normally expressed as a percent-
age of full scale range or in (sub)multiples of 1 LSB.
Resolution: It is addressing the smallest distinct analog
output change that a D/A converter can produce. It is
commonly expressed as the number of converter bits. A
converter with resolution of n bits can resolve output changes
of 2-N of the full-scale range, e.g. 2-N V
REF for a unipolar
conversion. Resolution by no means implies linearity.
Settling Time: Time required for the output of a DAC to set-
tle to within specified error band around its final value (e.g.
1/2 LSB) for a given digital input change, i.e. all digital inputs
LOW to HIGH and HIGH to LOW.
Gain Error: The difference between actual and ideal analog
output values at full-scale range, i.e. all digital inputs at
HIGH state. It is expressed as a percentage of full-scale
range or in (sub)multiples of 1 LSB.
Feedthrough Error: Error caused by capacitive coupling
from VREF to IOUT1 with all digital inputs LOW.
Output Capacitance: Capacitance from IOUT1, and IOUT2
terminals to ground.
Output Leakage Current: Current which appears on IOUT1,
terminal when all digital inputs are LOW or on IOUT2 terminal
when all digital inputs are HIGH.
Detailed Description
The AD7520, AD7530, AD7521 and AD7531 are monolithic,
multiplying D/A converters. A highly stable thin film R-2R
resistor ladder network and NMOS SPDT switches form the
basis of the converter circuit, CMOS level shifters permit low
power TTL/CMOS compatible operation. An external voltage
or current reference and an operational amplifier are all that
is required for most voltage output applications.
A simplified equivalent circuit of the DAC is shown in the Func-
tional Diagram. The NMOS SPDT switches steer the ladder leg
currents between IOUT1 and IOUT2 buses which must be held
either at ground potential. This configuration maintains a con-
stant current in each ladder leg independent of the input code.
Converter errors are further reduced by using separate
metal interconnections between the major bits and the out-
puts. Use of high threshold switches reduce offset (leakage)
errors to a negligible level.
The level shifter circuits are comprised of three inverters with
positive feedback from the output of the second to the first, see
Figure 1. This configuration results in TTL/CMOS compatible
operation over the full military temperature range. With the lad-
der SPDT switches driven by the level shifter, each switch is
binarily weighted for an ON resistance proportional to the
respective ladder leg current. This assures a constant voltage
drop across each switch, creating equipotential terminations for
the 2R ladder resistors and highly accurate leg currents.
FIGURE 1. CMOS SWITCH
V+
DTL/TTL/
CMOS INPUT
13 4
5
6
72
89
TO LADDER
IOUT2 IOUT1
8-9
AD7520, AD7530, AD7521, AD7531
Test Circuits
The following test circuits apply for the AD7520. Similar circuits are used for the AD7530, AD7521 and AD7531.
FIGURE 2. NONLINEARITY FIGURE 3. POWER SUPPLY REJECTION
FIGURE 4. NOISE FIGURE 5. OUTPUT CAPACITANCE
FIGURE 6. FEEDTHROUGH ERROR FIGURE 7. OUTPUT CURRENT SETTLING TIME
10 BIT
BINARY
COUNTER
GND
15 16
1
5
4
13 32
AD7520
BIT 1
(MSB)
BIT 10
(LSB)
LINEARITY
ERROR
X 100
RFEEDBACK
IOUT1
IOUT2 HA2600
-
+
VREF
BIT 1
(LSB)
BIT 10
BIT 11
BIT 12
10kΩ 0.01%
1MΩ
10kΩ
0.01%
CLOCK
+15V
VREF
HA2600
-
+
12 BIT
REFERENCE
DAC
15 16
1
5
4
13 32
AD7520
BIT 1
(MSB)
BIT 10
(LSB)
HA2600
-
+
HA2600
-
+
500kΩ
UNGROUNDED
SINE WAVE
GENERATOR
400Hz 1.0VP-P
5kΩ 0.01%
5K 0.01%
RFEEDBACK
+15V
+10V
VREF
IOUT1
IOUT2
14
GND
15 2
5
4
13 31
AD7520 101ALN
-
+
0.1µF
IOUT1
IOUT2
14 10kΩ
VOUT
100Ω
15µF
1k +15V
50kΩ1kΩ50V
f = 1kHz
BW = 1Hz
QUAN
TECH
MODEL 134D
WAVE
ANALYZER
+11V (ADJUST FOR VOUT = 0V)
15 16
1
5
4
13 32
AD7520
BIT 1 (MSB)
BIT 10 (LSB)
14
+15VNC
SCOPE
100mVP-P
1MHz
NC
1kΩ
+15V
15 16
1
5
4
13 32
AD7520
BIT 1 (MSB)
BIT 10 (LSB)
14
+15V
VREF = 20VP-P
GND
IOUT1
IOUT2 2
3
6VOUT
100kHz SINE WAVE
HA2600
-
+
15
1
5
4
13 32
AD7520
BIT 1 (MSB)
BIT 10 (LSB)
14
+15V
SCOPE
+100mV
100Ω
GND
VREF
DIGITAL IOUT2
EXTRAPOLATE 5t: 1% SETTLING (1mV)
8t: 0.03% SETTLING
t = RISE TIME
INPUT
+5V
0V
-10V
8-10
AD7520, AD7530, AD7521, AD7531
Applications
Unipolar Binary Operation
The circuit configuration for operating the AD7520 in unipo-
lar mode is shown in Figure 8. Similar circuits can be used
for AD7521, AD7530 and AD7531. With positive and nega-
tive VREF values the circuit is capable of 2-Quadrant multipli-
cation. The “Digital Input Code/Analog Output Value” table
for unipolar mode is given in Table 1.
FIGURE 8. UNIPOLAR BINARY OPERATION (2-QUADRANT
MULTIPLICATION
Zero Offset Adjustment
1. Connect all digital inputs to GND.
2. Adjust the offset zero adjust trimpot of the output opera-
tional amplifier for 0V at VOUT.
Gain Adjustment
1. Connect all digital inputs to V+.
2. Monitor VOUT for a -VREF (1-2-N) reading. (N = 10 for
AD7520/30 and N = 12 for AD7521/31).
3. To decrease VOUT, connect a series resistor (0 to 250Ω)
between the reference voltage and the VREF terminal.
4. To increase VOUT, connect a series resistor (0 to 250Ω) in
the IOUT1 amplifier feedback loop.
Bipolar (Offset Binary) Operation
The circuit configuration for operating the AD7520 in the
bipolar mode is given in Figure 9. Similar circuits can be
used for AD7521, AD7530 and AD7531. Using offset binary
digital input codes and positive and negative reference volt-
age values, 4-Quadrant multiplication can be realized. The
TABLE 1. CODE TABLE - UNlPOLAR BINARY OPERATION
DIGITAL INPUT ANALOG OUTPUT
1111111111 -VREF (1-2-N)
1000000001 -VREF (1/2 + 2-N)
1000000000 -VREF/2
0111111111 -VREF (1/2-2-N)
0000000001 -VREF (2-N)
0000000000 0
NOTES:
1. LSB = 2-N VREF
2. N = 10 for 7520, 7530
N = 12 for 7521, 7531
15 16
1
5
4
13 32
AD7520
BIT 1 (MSB)
BIT 10 (LSB)
14
+15V
VREF
GND
IOUT1
IOUT2 6VOUT
-
+
RFEEDBACK
DIGITAL
INPUT
“Digital Input Code/Analog Output Value” table for bipolar
mode is given in Table 2.
FIGURE 9. BIPOLAR OPERATION (4-QUADRANT MULTIPLICA TION)
A “Logic 1” input at any digital input forces the corresponding
ladder switch to steer the bit current to IOUT1 bus. A “Logic 0”
input forces the bit current to IOUT2 bus. For any code the IOUT1
and IOUT2 bus currents are complements of one another. The
current amplifier at IOUT2 changes the polarity of IOUT2 current
and the transconductance amplifier at IOUT1 output sums the
two currents. This configuration doubles the output range. The
difference current resulting at zero offset binary code, (MSB =
“Logic 1”, All other bits = “Logic 0”), is corrected by using an
external resistor, (10M Ω), from V REF to IOUT2.
Offset Adjustment
1. Adjust VREF to approximately +10V.
2. Connect all digital inputs to “Logic 1”.
3. Adjust IOUT2 amplifier offset adjust trimpot for 0V±1mV at
IOUT2 amplifier output.
4. Connect MSB (Bit 1) to “Logic 1” and all other bits to “Logic 0”.
5. Adjust IOUT1 amplifier offset adjust trimpot for 0V±1mV at VOUT.
Gain Adjustment
1. Connect all digital inputs to V+.
2. Monitor VOUT for a -V REF (1-2-(N-1) volts reading. (N = 10 for
AD7520 and AD7530, and N = 12 for AD7521 and AD7531).
3. To increase VOUT, connect a series resistor of up to 250Ω
between VOUT and RFEEDBACK.
4. To decrease VOUT, connect a series resister of up to 250Ω
between the reference voltage and the VREF terminal.
TABLE 2. BlPOLAR (OFFSET BINARY) CODE TABLE
DIGITAL INPUT ANALOG OUTPUT
1111111111 -VREF (1-2-(N-1))
1000000001 -VREF (2-(N-1))
1000000000 0
0111111111 VREF (2-(N-1))
0000000001 VREF (1-2-(N-1))
0000000000 VREF
NOTES:
1. LSB = 2-(N-1) VREF 2. N = 10 for 7520, 7521
N = 12 for 7530,7531
15 16
1
5
4
13 32
AD7520
BIT 1
BIT 10
14
+15V
VREF
IOUT2 6
VOUT
-
+
RFEEDBACK
6
-
+
(MSB)
(LSB)
IOUT1
R1 10k
0.01% R2 10k
0.01%
DIGITAL
INPUT
R3
10MΩ
8-11
AD7520, AD7530
Die Characteristics
DIE DIMENSIONS:
101 x 103mils (2565 x 2616micrms)
METALLIZATION:
Type: Pure Aluminum
Thickness: 10 ± 1kÅ
GLASSIVATION:
Type: PSG/NITRIDE
PSG: 7 ± 1.4kÅ
NITRIDE: 8 ± 1.2kÅ
PROCESS: CMOS Metal Gate
Metallization Mask Layout
AD7520, AD7530
PIN 3
GND
PIN 2
IOUT2
PIN 1
IOUT1
PIN 16
RFEEDBACK
PIN 15
VREF
PIN 14
V+
NCNCPIN 12
PIN 4
BIT 1
(MSB)
PIN 5
BIT 2
PIN 6
BIT 3
PIN 7
BIT 4
PIN 11
BIT 8
PIN 10
BIT 7
PIN 9
BIT 6
PIN 8
BIT 5
BIT 9 PIN 13
BIT 10
(LSB)
8-12
AD7521, AD7531
Die Characteristics
DIE DIMENSIONS:
101 x 103mils (2565 x 2616micrms)
METALLIZATION:
Type: Pure Aluminum
Thickness: 10 ± 1kÅ
GLASSIVATION:
Type: PSG/NITRIDE
PSG: 7 ± 1.4kÅ
NITRIDE: 8 ± 1.2kÅ
PROCESS: CMOS Metal Gate
Metallization Mask Layout
AD7521, AD7531
PIN 3
GND
PIN 2
IOUT2
PIN 1
IOUT1
PIN 18
RFEEDBACK
PIN 17
VREF
PIN 16
V+
PIN 12
PIN 4
BIT 1
(MSB)
PIN 5
BIT 2
PIN 6
BIT 3
PIN 7
BIT 4
PIN 11
BIT 8
PIN 10
BIT 7
PIN 9
BIT 6
PIN 8
BIT 5
BIT 9 PIN 13
BIT 10 PIN 14
BIT 11 PIN 15
BIT 12
(LSB)
