September 2000 1
© 2000 Actel Corporation
Preliminary v1.5.2
54SX Family FPGAs
RadTolerant and HiRel
Features
RadTolerant 54SX Family
• Tested Total Ionizing Dose (TID) Survivability Level
• Radiation Performance to 100Krads (Si) (ICC Standby
Parametric)
• Devices Available from Tested Pedigreed Lots
• Up to 160 MHz On-Chip Performance
• Offered as Class B and E-Flow (Actel Space Level Flow)
• QMl Certified Devices
HiRel 54SX Family
• Fastest HiRel FPGA Family Available
• Up to 240 MHz On-Chip Performance
• Low Cost Prototyping Vehicle for RadTolerant Devices
• Offered as Commercial or Military Temperature Tested
and Class B
• Cost Effective QML MIL-Temp Plastic Packaging Options
• Standard Hermetic Packaging Offerings
•QML Certified Devices
High Density Devices
• 16,000 and 32,000 Available Logic Gates
• Up to 225 User I/Os
• Up to 1,080 Dedicated Flip-Flops
Easy Logic Integration
• Non-Volatile, User Programmable
• Highly Predictable Performance with 100% Automatic
Place and Route
• 100% Resource Utilization with 100% Pin Locking
• Mixed Voltage Support—3.3V Operation with 5.0V Input
Tolerance for Low Power Operation
• JTAG Boundary Scan Testing in Compliance with IEEE
Standard 1149.1
• Secure Programming Technology Prevents Reverse
Engineering and Design Theft
• Permanently Programmed for Operation on Power-Up
• Unique In-System Diagnostic and Debug Facility with
Silicon Explorer
• Supported by Actel’s Designer Series and DeskTOP Series
Development Systems with Automatic Timing Driven
Place and Route
• Predictable, Reliable, and Permanent Antifuse Technology
Performance
SX Product Profile
Device RT54SX16 A54SX16 RT54SX32 A54SX32
Capacity
System Gates
Logic Gates
24,000
16,000
24,000
16,000
48,000
32,000
48,000
32,000
Logic Modules 1,452 1,452 2,880 2,880
Register Cells 528 528 1,080 1,080
Combinatorial Cells 924 924 1,800 1,800
User I/Os (Maximum) 177 176 224 225
JTAG Yes Yes Yes Yes
Packages (by pin count)
CQFP 208, 256 208, 256 208, 256 208, 256
2
General Description
Actel’s SX family of FPGAs features a revolutionary
sea-of-modules architecture that delivers next-generation
device performance and integration levels not currently
achieved by any other FPGA architecture. SX devices greatly
simplify design time, enable dramatic reductions in design
costs and power consumption, and speed time-to-market for
performance-intensive applications.
Actel’s RadTolerant (RT) and HiRel versions of the SX Family
of FPGAs offer all of these advantages for applications such as
commercial and military satellites, deep space probes, and all
types of military and high reliability equipment.
The RT and HiRel versions are fully pin compatible allowing
designs to migrate across different applications that may or
may not have radiation requirements. Also, the HiRel devices
can be used as a low cost prototyping tool for RT designs.
The programmable architecture of these devices offer high
performance, design flexibility, and fast and inexpensive
prototyping—all without the expense of test vectors, NRE
charges, long lead times, and schedule and cost penalties for
design modifications that are required by ASIC devices.
Fast and Flexible New Architecture
Actel’s SX architecture features two types of logic modules,
the combinatorial cell (C-cell) and the register cell (R-cell),
each optimized for fast and efficient mapping of synthesized
logic functions. Optimal use of the silicon is made by locating
the routing and interconnect resources in the metal layers
above the logic modules, enabling the entire floor of the
device to be spanned with an uninterrupted grid of
fine-grained, synthesis-friendly logic modules (or
“sea-of-modules”) which reduces the distance signals have to
travel between logic modules.
To minimize signal propagation delay, SX devices employ both
local and general routing resources. The high-speed local
routing resources (DirectConnect and FastConnect) enable
very fast local signal propagation that is optimal for fast
counters, state machines, and datapath logic. The general
system of segmented routing tracks allows any logic module in
the array to be connected to any other logic or I/O module.
Within this system, propagation delay is minimized by limiting
the number of antifuse interconnect elements to five
(typically 90 percent of connections use only three antifuses).
The unique local and general routing structure featured in SX
devices gives fast and predictable performance, allows
100 percent pin-locking with full logic utilization, enables
concurrent PCB development, reduces design time, and
allows designers to achieve performance goals with a
minimum of effort.
Further complementing the SX’s flexible routing structure is
a hard-wired, constantly-loaded clock network that has been
tuned to provide fast clock propagation with minimal clock
skew. Additionally, the high performance of the internal logic
has eliminated the need to embed latches or flip-flops in the
I/O cells to achieve fast clock-to-out or fast input set-up times.
SX devices have easy-to-use I/O cells that do not require HDL
instantiation, facilitating design re-use and reducing design
and verification time.
Device Description
The RT54SX16 and A54SX16 devices have 16,000 available
gates and up to 177 I/Os. The RT54SX32 and A54SX32 have
32,000 available gates and up to 225 I/Os. All of these devices
support JTAG boundary scan testability.
All of these devices are available in Ceramic Quad Flat Pack
(CQFP) packaging, with 208-pin and 256-pin versions. The
256-pin version offers the user the highest I/O capability,
while the 208-pin version offers pin compatibility with the
commercial Plastic Quad Flat Pack (PQFP-208). This
compatibility allows the user to prototype using the very low
cost plastic package and then switch to the ceramic package
for production. For more information on plastic packages,
refer to the SX family FPGAs data sheet at:
http://www.actel.com/docs/datasheets/A54SXDS.pdf
The A54SX16 and A54SX32 are manufactured using a 0.35µ
technology at the Chartered Semiconductor facility in
Singapore. These devices offer the highest speed
performance available in FPGAs today.
The RT54SX16 and RT54SX32 are manufactured using a 0.6µ
technology at the Matsushita (MEC) facility in Japan. These
devices offer levels of radiation survivability far in excess of
typical CMOS devices.
Radiation Survivability
Total dose results are summarized in two ways. First by the
maximum total dose level that is reached when the parts fail
to meet a device specification but remain functional. For
Actel FPGAs, the parameter that exceeds the specification
first is ICC, the standby supply current. Second by the
maximum total dose that is reached prior to the functional
failure of the device.
The RT SX devices have varying total dose radiation
survivability. The ability of these devices to survive radiation
effects is both device and lot dependent. The customer must
evaluate and determine the applicability of these devices to
their specific design and environmental requirements.
3
54SX Family FPGAs RadTolerant and HiRel
Actel will provide total dose radiation testing along with the
test data on each pedigreed lot that is available for sale.
These reports are available on our website or you can contact
your local sales representative to receive a copy. A listing of
available lots and devices will also be provided. These results
are only provided for reference and for customer information.
For a radiation performance summary, see Radiation
Performance of Actel Products at
http://www.actel.com/hirel. This summary will also show
single event upset (SEU) and single event latch-up (SEL)
testing that has been performed on Actel FPGAs.
QML Certification
Actel has achieved full QML certification, demonstrating that
quality management, procedures, processes, and controls are
in place and comply with MIL-PRF-38535, the performance
specification used by the Department of Defense for
monolithic integrated circuits. QML certification is a good
example of Actel’s commitment to supplying the highest
quality products for all types of high-reliability, military and
space applications.
Many suppliers of microelectronics components have
implemented QML as their primary worldwide business
system. Appropriate use of this system not only helps in the
implementation of advanced technologies, but also allows for
a quality, reliable and cost-effective logistics support
throughout QML products’ life cycles.
Disclaimer
All radiation performance information is provided for
information purposes only and is not guaranteed. The total
dose effects are lot-dependent, and Actel does not guarantee
that future devices will continue to exhibit similar radiation
characteristics. In addition, actual performance can vary
widely due to a variety of factors, including but not limited to,
characteristics of the orbit, radiation environment, proximity
to satellite exterior, amount of inherent shielding from other
sources within the satellite and actual bare die variations.
For these reasons, Actel does not guarantee any level of
radiation survivability, and it is solely the responsibility of the
customer to determine whether the device will meet the
requirements of the specific design.
Development Tool Support
The 54SX RadTolerant and RadHard devices are fully
supported by Actel’s line of FPGA development tools,
including the Actel DeskTOP series and Designer Advantage
tools. The Actel DeskTOP Series is an integrated design
environment for PCs that includes design entry, simulation,
synthesis, and place and route tools. Designer Advantage is
Actel’s suite of FPGA development point tools for PCs and
Workstations that includes the ACTgen Macro Builder,
Designer with DirectTime timing driven place and route and
analysis tools, and device programming software.
In addition, the 54SX RadTolerant and RadHard devices
contain ActionProbe circuitry that provides built-in access to
every node in a design, enabling 100-percent real-time
observation and analysis of a device's internal logic nodes
without design iteration. The probe circuitry is accessed by
Silicon Explorer, an easy to use integrated verification and
logic analysis tool that can sample data at 100 MHz
(asynchronous) or 66 MHz (synchronous). Silicon Explorer
attaches to a PC’s standard COM port, turning the PC into a
fully functional 18 channel logic analyzer. Silicon Explorer
allows designers to complete the design verification process
at their desks and reduces verification time from several
hours per cycle to a few seconds.
4
Ordering Information
Product Plan
Speed Grade Application
Std –1* C M B E
RT54SX16 Devices
208-Pin Ceramic Quad Flat Pack (CQFP) ✔✔ ✔✔✔✔
256-Pin Ceramic Quad Flat Pack (CQFP) ✔✔ ✔✔✔✔
A54SX16 Devices
208-Pin Ceramic Quad Flat Pack (CQFP) ✔✔ ✔✔✔—
256-Pin Ceramic Quad Flat Pack (CQFP) ✔✔ ✔✔✔—
RT54SX32 Devices
208-Pin Ceramic Quad Flat Pack (CQFP) ✔✔ ✔✔✔✔
256-Pin Ceramic Quad Flat Pack (CQFP) ✔✔ ✔✔✔✔
A54SX32 Devices
208-Pin Ceramic Quad Flat Pack (CQFP) ✔✔ ✔✔✔—
256-Pin Ceramic Quad Flat Pack (CQFP) ✔✔ ✔✔✔—
Contact your Actel sales representative for product availability.
Applications: C = Commercial Availability: ✔= Available * Speed Grade: –1 = Approx. 15% Faster than Standard
M = Military P = Planned
B = MIL-STD-883 — = Not Planned
E = E-flow (Actel Space Level Flow)
Application (Temperature Range)
Blank = Commercial (0 to +70°C)
M = Military (–55 to +125°C)
B = MIL-STD-883
E = E-Flow (Actel Space Level Flow)
Package Type
CQ = Ceramic Quad Flat Pack
Speed Grade
Blank = Standard Speed
–1 = Approximately 15% Faster than Standard
Part Number
A54SX16 = 16,000 Gates
A54SX32 = 32,000 Gates
RT54SX16 = 16,000 Gates—RadTolerant
RT54SX32 = 32,000 Gates—Rad Tolerant
Package Lead Count
RT54SX32 – CQ 2561B
5
54SX Family FPGAs RadTolerant and HiRel
Ceramic Device Resources
JTAG
All SX devices feature hard-wired IEEE 1149.1 JTAG
Boundary Scan Test circuitry and offer superior diagnostic
and testing capabilities by providing JTAG and probing
capabilities. These functions are controlled through the
special JTAG pins in conjunction with the program fuse. The
functionality of each pin is described in Table 1. Figure 1 is
a block diagram of the A54SX JTAG circuitry and Figure 2 on
page 6 shows the RT54SX JTAG circuitry.
In the dedicated JTAG mode, TCK, TDI, and TDO are
dedicated JTAG pins and cannot be used as regular I/Os. In
flexible mode, TMS should be set HIGH through a pull-up
resistor of 10 kΩ. TMS can be pulled LOW to initiate the
JTAG sequence. In addition, RT54SX devices include a TRST
pin which is used to reset the JTAG state machine in
“test-logic-reset” mode.
The program fuse determines whether the device is in
dedicated or flexible mode. The default (fuse not blown) is
flexible mode. Regardless of which mode is chosen, tying the
TRST pin LOW will disable all JTAG functionality.
User I/Os
Device CQFP 208-Pin CQFP 256-Pin
RT54SX16 171 176
A54SX16 172 177
RT54SX32 170 224
A54SX32 171 225
Package Definitions: CQFP = Ceramic Quad Flat Pack
(Contact your Actel sales representative for product availability.)
Table 1 • JTAG Pin Functionality
Program Fuse Blown
(Dedicated JTAG Mode)
Program Fuse Not Blown
(Flexible Mode)
TCK, TDI, TDO are
dedicated JTAG pins
TCK, TDI, TDO are flexible
and may be used as I/Os
No need for pull-up
resistor for TMS
Use a pull-up resistor of
10 kΩ on TMS
Figure 1 • A54SX JTAG Circuitry
Instruction Register (IR)
Data Registers (DRs)
clocks and/or controls
TAP Controller
output
stage
0
1
TDO
TDI
TMS
TCK
Power-up
Reset
6
Figure 2 •RT54SX JTAG Circuitry
Instruction Register (IR)
Data Registers (DRs)
clocks and/or controls
TAP Controller
output
stage
0
1
TDO
TDI
TMS
TCK
TRST external
hard-wired pin
7
54SX Family FPGAs RadTolerant and HiRel
SX Family Architecture
The SX family architecture was designed to satisfy
next-generation performance and integration requirements
for production-volume designs in a broad range of
applications.
Programmable Interconnect Element
Actel’s SX family provides much more efficient use of silicon
by locating the routing interconnect resources between the
Metal 2 (M2) and Metal 3 (M3) layers (Figure 3). This
completely eliminates the channels of routing and
interconnect resources between logic modules (as
implemented on SRAM FPGAs and previous generations of
antifuse FPGAs), and enables the entire floor of the device to
be spanned with an uninterrupted grid of logic modules.
Interconnection between these logic modules is achieved
using Actel’s patented metal-to-metal programmable antifuse
interconnect elements, which are embedded between the M2
and M3 layers. The antifuses are normally open circuit and,
when programmed, form a permanent low-impedance
connection.
The extremely small size of these interconnect elements gives
the SX family abundant routing resources and provides
excellent protection against design pirating. Reverse
engineering is virtually impossible, because it is extremely
difficult to distinguish between programmed and
unprogrammed antifuses, and there is no configuration
bitstream to intercept.
Additionally, the interconnects (i.e., the antifuses and metal
tracks) have lower capacitance and lower resistance than any
other device of similar capacity, leading to the fastest signal
propagation in the industry.
Figure 3 •SX Family Interconnect Elements
Silicon Substrate
Tungsten Plug
Contact
Metal 1
Metal 2
Metal 3
Routing Tracks
Amorphous Silicon/
Dielectric Antifuse
Tungsten Plug Via
Tungsten Plug Via
8
Logic Module Design
The SX family architecture has been called a “sea-of-modules”
architecture because the entire floor of the device is covered
with a grid of logic modules with virtually no chip area lost to
interconnect elements or routing (see Figure 4). Actel
provides two types of logic modules, the register cell (R-cell)
and the combinatorial cell (C-cell).
The R-cell contains a flip-flop featuring more control signals
than in previous Actel architectures, including asynchronous
clear, asynchronous preset, and clock enable (using the S0
and S1 lines). The R-cell registers feature programmable clock
polarity, selectable on a register-by-register basis (Figure 5
on page 9). This provides the designer with additional
flexibility while allowing mapping of synthesized functions
into the SX FPGA. The clock source for the R-cell can be
chosen from the hard-wired clock or the routed clock.
The C-cell implements a range of combinatorial functions up
to 5-inputs (Figure 6 on page 9). Inclusion of the DB input
and its associated inverter function dramatically increases
the number of combinatorial functions that can be
implemented in a single module from 800 options in previous
architectures to more than 4,000 in the SX architecture. An
example of the improved flexibility enabled by the inversion
capability is the ability to integrate a 3-input exclusive-OR
function into a single C-cell. This facilitates construction of
9-bit parity-tree functions with 2 ns propagation delays. At the
same time, the C-cell structure is extremely
synthesis-friendly, simplifying the overall design and reducing
synthesis time.
Chip Architecture
The SX family’s chip architecture provides a unique approach
to module organization and chip routing that delivers the best
register/logic mix for a wide variety of new and emerging
applications.
Figure 4 •Channelled Array and Sea-of-Modules Architectures
Channelled Array Architecture
Sea-of-Modules Architecture
9
54SX Family FPGAs RadTolerant and HiRel
Module Organization
Actel has arranged all C-cell and R-cell logic modules into
horizontal banks called Clusters. There are two types of
Clusters: Type 1 contains two C-cells and one R-cell, while
Type 2 contains one C-cell and two R-cells.
To increase design efficiency and device performance, Actel
has further organized these modules into SuperClusters (see
Figure 7 on page 10). SuperCluster 1 is a two-wide grouping of
Type 1 clusters. SuperCluster 2 is a two-wide group
containing one Type 1 cluster and one Type 2 cluster. SX
devices feature more SuperCluster 1 modules than
SuperCluster 2 modules because designers typically require
more combinatorial logic than flip-flops.
Routing Resources
Clusters and SuperClusters can be connected through the use
of two innovative local routing resources called FastConnect
and DirectConnect that enable extremely fast and
predictable interconnections of modules within Clusters and
SuperClusters (see Figure 8 and Figure 9 on page 11). This
routing architecture also dramatically reduces the number of
antifuses required to complete a circuit, ensuring the highest
possible performance.
Figure 5 •R-Cell
Figure 6 •C-Cell
Direct
Connect
Input
CLKA,
CLKB
HCLK
CKS CKP
CLRB
PSETB
YDQ
Routed
Data Input
S0
S1
D0
D1
D2
D3
DB
A0 B0 A1 B1
Sa Sb
Y
10
DirectConnect is a horizontal routing resource that provides
connections from a C-cell to its neighboring R-cell in a given
SuperCluster. DirectConnect uses a hard-wired signal path
requiring no programmable interconnection to achieve its
fast signal propagation time of less than 0.1 ns.
FastConnect enables horizontal routing between any two
logic modules within a given SuperCluster, and vertical
routing with the SuperCluster immediately below it. Only one
programmable connection is used in a FastConnect path,
delivering maximum pin-to-pin propagation of 0.4 ns.
In addition to DirectConnect and FastConnect, the
architecture makes use of two globally-oriented routing
resources known as segmented routing and high-drive
routing. Actel’s segmented routing structure provides a
variety of track lengths for extremely fast routing between
SuperClusters. The exact combination of track lengths and
antifuses within each path is chosen by the 100% automatic
place and route software to minimize signal propagation
delays.
Actel’s high-drive routing structure provides three clock
networks. The first clock, called HCLK, is hard-wired from the
HCLK buffer to the clock select MUX in each R-cell. This
provides a fast propagation path for the clock signal. The
hard-wired clock is tuned to provide clock skew as low as
0.25 ns. The remaining two clocks (CLKA, CLKB) are global
clocks that can be sourced from external pins or from internal
signal logic within the SX device.
Figure 7 •Cluster Organization
Type 1 SuperCluster Type 2 SuperCluster
Cluster 1 Cluster 2 Cluster 2 Cluster 1
R-Cell C-Cell
D0
D1
D2
D3
DB
A0 B0 A1 B1
Sa Sb
Y
Direct
Connect
Input
CLKA,
CLKB
HCLK
CKS CKP
CLRB
PSETB
YDQ
Routed
Data Input
S0
S1
11
54SX Family FPGAs RadTolerant and HiRel
Figure 8 •DirectConnect and FastConnect for Type 1 SuperClusters
Figure 9 •DirectConnect and FastConnect for Type 2 SuperClusters
Type 1 SuperClusters
Routing Segments
• Typically 2 antifuses
• Max. 5 antifuses
FastConnect
• One antifuse
DirectConnect
• No antifuses
Type 2 SuperClusters
Routing Segments
• Typically 2 antifuses
• Max. 5 antifuses
FastConnect
• One antifuse
DirectConnect
• No antifuses
12
3.3V/5V Operating Conditions
Absolute Maximum Ratings1
Electrical Specifications
Symbol Parameter Limits Units
VCCR DC Supply Voltage –0.3 to +6.0 V
VCCA DC Supply Voltage –0.3 to +4.0 V
VCCI DC Supply Voltage –0.3 to +4.0 V
VIInput Voltage –0.5 to +5.5 V
VOOutput Voltage –0.5 to +3.6 V
IIO
I/O Source Sink
Current2–30 to +5.0 mA
TSTG Storage Temperature –40 to +125 °C
Notes:
1. Stresses beyond those listed in the Absolute Maximum Ratings
table may cause permanent damage to the device. Exposure to
absolute maximum rated conditions for extended periods may
affect device reliability. Device should not be operated outside
the Recommended Operating Conditions.
2. The I/O source sink numbers refer to tristated inputs and
outputs
Recommended Operating Conditions
Parameter Commercial Military Units
Temperature
Range10 to +70 –55 to +125 °C
3.3V Power2
Supply Tolerance ±10 ±10 %VCC
5V Power Supply 2
Tole r a n ce ±5±10 %VCC
Note:
1. Ambient temperature (TA) is used for commercial and
industrial; case temperature (TC) is used for military.
2. All power supplies must be in the recommended operating range
for 250µs. For more information, please refer to the
Power-Up Design Considerations application note at
http://www.actel.com/appnotes.
Commercial Military
Symbol Parameter Min. Max. Min. Max. Units
VOH
(IOH = –20µA) (CMOS)
(IOH = –8mA) (TTL)
(IOH = –6mA) (TTL)
(VCCI – 0.1)
2.4
VCCI
VCCI
(VCCI – 0.1)
2.4
VCCI
VCCI
V
VOL
(IOL= 20µA) (CMOS)
(IOL = 12mA) (TTL)
(IOL = 8mA) (TTL)
0.10
0.50
0.50
V
VIL Low Level Inputs 0.8 0.8 V
VIH High Level Inputs 2.0 2.0 V
tR, tFInput Transition Time tR, tF50 50 ns
CIO CIO I/O Capacitance 10 10 pF
ICC Standby Current, ICC 4.0 25 mA
ICC(D) ICC(D) IDynamic VCC Supply Current See the “Power Dissipation” section on page 14.
13
54SX Family FPGAs RadTolerant and HiRel
Power-Up Sequencing
RT54SX16, A54SX16, RT54SX32, A54SX32
Power-Down Sequencing
RT54SX16, A54SX16, RT54SX32, A54SX32
Package Thermal Characteristics
The device junction to case thermal characteristic is θjc, and
the junction to ambient air characteristic is θja. The thermal
characteristics for θja are shown with two different air flow
rates.
Maximum junction temperature is 150°C.
A sample calculation of the absolute maximum power
dissipation allowed for an RT54SX16 in a CQFP 256-pin
package at military temperature and still air is as follows:
VCCA VCCR VCCI Power-Up Sequence Comments
3.3V 5.0V 3.3V
5.0V First
3.3V Second No possible damage to device.
3.3V First
5.0V Second Possible damage to device.
VCCA VCCR VCCI Power-Down Sequence Comments
3.3V 5.0V 3.3V
5.0V First
3.3V Second Possible damage to device.
3.3V First
5.0V Second No possible damage to device.
Package Type Pin Count θjc
θja
Still Air Units
RT54SX16
Ceramic Quad Flat Pack (CQFP) 208 7.5 29 °C/W
Ceramic Quad Flat Pack (CQFP) 256 4.6 23 °C/W
RT54SX32
Ceramic Quad Flat Pack (CQFP) 208 6.9 35 °C/W
Ceramic Quad Flat Pack (CQFP) 256 3.5 20 °C/W
A54SX16
Ceramic Quad Flat Pack (CQFP) 208 7.9 30 °C/W
Ceramic Quad Flat Pack (CQFP) 256 5.6 25 °C/W
A54SX32
Ceramic Quad Flat Pack (CQFP) 208 7.6 30 °C/W
Ceramic Quad Flat Pack (CQFP) 256 4.8 24 °C/W
Absolute Maximum Power Allowed Max. junction temp. (°C) – Max. ambient temp. (°C)
θja (°C/W)
------------------------------------------------------------------------------------------------------------------------------ 150°C – 125°C
23°C/W
------------------------------------ 1 . 0 9 W===
14
Power Dissipation
P = [ICCstandby + ICCactive] * VCCA + IOL * VOL * N +
IOH *(VCCA – VOH) * M
where:
ICCstandby is the current flowing when no inputs or
outputs are changing.
ICCactive is the current flowing due to CMOS switching.
IOL, IOH are TTL sink/source currents.
VOL, VOH are TTL level output voltages.
N equals the number of outputs driving TTL loads to VOL.
M equals the number of outputs driving TTL loads to VOH.
Accurate values for N and M are difficult to determine
because they depend on the design and on the system I/O. The
power can be divided into two components: static and active.
Static Power Component
The power due to standby current is typically a small
component of the overall power. Standby power is shown
below for military, worst case conditions (70°C).
Active Power Component
Power dissipation in CMOS devices is usually dominated by
the active (dynamic) power dissipation. This component is
frequency-dependent, a function of the logic and the external
I/O. Active power dissipation results from charging internal
chip capacitances of the interconnect, unprogrammed
antifuses, module inputs, and module outputs, plus external
capacitance due to PC board traces and load device inputs.
An additional component of the active power dissipation is
the totempole current in CMOS transistor pairs. The net
effect can be associated with an equivalent capacitance that
can be combined with frequency and voltage to represent
active power dissipation.
Equivalent Capacitance
The power dissipated by a CMOS circuit can be expressed by
Equation 1:
Power (µW) = CEQ * VCCA2 * F (1)
where:
Equivalent capacitance is calculated by measuring ICCactive
at a specified frequency and voltage for each circuit
component of interest. Measurements have been made over a
range of frequencies at a fixed value of VCCA. Equivalent
capacitance is frequency-independent so that the results may
be used over a wide range of operating conditions. Equivalent
capacitance values are shown below.
CEQ Values (pF)
To calculate the active power dissipated from the complete
design, the switching frequency of each part of the logic must
be known. Equation 2 shows a piece-wise linear summation
over all components.
Power =VCCA2 * [(m * CEQM * fm)modules +
(n * CEQI * fn)inputs+ (p * (CEQO + CL) * fp)outputs+
0.5 * (q1 * CEQCR * fq1)routed_Clk1 + (r1 * fq1)routed_Clk1 +
0.5 * (q2 * CEQCR * fq2)routed_Clk2+ (r2 * fq2)routed_Clk2 +
0.5 * (s1 * CEQCD * fs1)dedicated_CLK](2)
ICC VCC Power
20 mA 3.6V 72 mW
CEQ = Equivalent capacitance in pF
VCCA = Power supply in volts (V)
F = Switching frequency in MHz
RT54SX16 A54SX16 RT54SX32 A54SX32
Equivalent Capacitance (pF)
Modules CEQM 7.0 3.9 7.0 3.9
Input Buffers CEQI 2.0 1.0 2.0 1.0
Output Buffers CEQO 10.0 5.0 10.0 5.0
Routed Array Clock Buffer Loads CEQCR 0.4 0.2 0.6 0.3
Dedicated Clock Buffer Loads CEQCD 0.25 0.15 0.34 0.23
Fixed Capacitance (pF)
routed_Clk1 r1120 60 210 107
routed_Clk2 r2120 60 210 107
Fixed Clock Loads
Clock Loads on Dedicated Array Clock s1528 528 1,080 1,080
15
54SX Family FPGAs RadTolerant and HiRel
where: Determining Average Switching Frequency
To determine the switching frequency for a design, you must
have a detailed understanding of the data input values to the
circuit. The following guidelines are meant to represent
worst-case scenarios so that they can be generally used to
predict the upper limits of power dissipation. These
guidelines are as follows:
m = Number of logic modules switching at fm
n = Number of input buffers switching at fn
p = Number of output buffers switching at fp
q1= Number of clock loads on the first routed array
clock
q2= Number of clock loads on the second routed
array clock
r1= Fixed capacitance due to first routed array clock
r2= Fixed capacitance due to second routed array
clock
s1= Fixed number of clock loads on the dedicated
array clock = (528 for A54SX16)
CEQM = Equivalent capacitance of logic modules in pF
CEQI = Equivalent capacitance of input buffers in pF
CEQO = Equivalent capacitance of output buffers in pF
CEQCR = Equivalent capacitance of routed array clock in
pF
CEQCD = Equivalent capacitance of dedicated array clock
in pF
CL= Output lead capacitance in pF
fm= Average logic module switching rate in MHz
fn= Average input buffer switching rate in MHz
fp= Average output buffer switching rate in MHz
fq1 = Average first routed array clock rate in MHz
fq2 = Average second routed array clock rate in MHz
Logic Modules (m) = 80% of modules
Inputs Switching (n) = # inputs/4
Outputs Switching (p) = # output/4
First Routed Array Clock Loads (q1) = 40% of sequential
modules
Second Routed Array Clock Loads
(q2)
= 40% of sequential
modules
Load Capacitance (CL) = 35 pF
Average Logic Module Switching
Rate (fm)
=F/10
Average Input Switching Rate (fn)= F/5
Average Output Switching Rate (fp)= F/10
Average First Routed Array Clock
Rate (fq1)
=F/2
Average Second Routed Array Clock
Rate (fq2)
=F/2
Average Dedicated Array Clock Rate
(fs1)
=F
16
Temperature and Voltage Derating Factors
(Normalized to Worst-Case Commercial, TJ = 70°C, VCCA = 3.0V)
54SX Timing Model*
Hard-Wired Clock
External Set-Up = tINY + tIRD1 + tSUD – tHCKH
= 2.2 + 0.7 + 0.8 – 1.7 = 2.0 ns
Clock-to-Out (Pin-to-Pin)
=t
HCKH + tRCO + tRD1 + tDHL
= 1.7 + 0.6 + 0.7 + 2.8 = 5.8 ns
Routed Clock
External Set-Up = tINY + tIRD1 + tSUD – tRCKH
= 2.2 + 0.7 + 0.8 – 2.4 = 1.3 ns
Clock-to-Out (Pin-to-Pin)
=t
RCKH + tRCO + tRD1 + tDHL
= 2.4 + 0.6 + 0.7 + 2.8 = 6.5 ns
VCCA
Junction Temperature (TJ)
–40 0 25 70 85 125
3.0 0.78 0.87 0.89 1.00 1.04 1.16
3.3 0.73 0.82 0.83 0.93 0.97 1.08
3.6 0.69 0.77 0.78 0.87 0.92 1.02
*Values shown for A54SX16-1 at worst-case commercial conditions.
Output DelaysInternal DelaysInput Delays
Hard-Wired
I/O Module
FHMAX = 240 MHz
tINY = 2.2 ns tIRD2 = 1.2 ns
Combinatorial
Cell
tPD =0.9 ns
Register
Cell
I/O Module
tRD1 = 0.7 ns
tDHL = 2.8 ns
I/O Module
Routed
Clock
FMAX = 175 MHz
DQDQ
tDHL = 2.8 ns
tENZH = 2.8 ns
tRD1 = 0.7 ns
tRCO = 0.6 ns
tSUD = 0.8 ns
tHD = 0.0 ns
tRD4 = 2.2 ns
tRD8 = 4.3 ns
Predicted
Routing
Delays
tRCKH = 2.8 ns (100% Load)
tRD1 = 0.7 ns
Register
Cell
tRCO = 0.6 ns
Clock tHCKH = 1.3 ns
17
54SX Family FPGAs RadTolerant and HiRel
Output Buffer Delays
AC Test Loads
Input Buffer Delays C-Cell Delays
To AC test loads (shown below)
PAD
D
E
TRIBUFF
In
VCC
GND
50%
Out
VOL
VOH
1.5V
tDLH
50%
1.5V
tDHL
En
VCC
GND
50%
Out
VOL
1.5V
tENZL
50%
10%
tENLZ
En
VCC
GND
50%
Out
GND
VOH
1.5V
tENZH
50%
90%
tENHZ
VCC
Load 1
(Used to measure propagation delay)
Load 2
(Used to measure rising/falling edges)
50 pF
To the output under test
VCC GND
50 pF
To the output under test
R to VCC for tPLZ/tPZL
R to GND for tPHZ/tPZH
R = 1 kΩ
PAD Y
INBUF
In
3V
0V
1.5V
Out
GND
VCC
50%
tINY
1.5V
50%
tINY
S
A
B
Y
S, A or B
Out
GND
VCC
50%
tPD
Out
GND
GND
VCC
50%
50% 50%
VCC
50% 50%
tPD
tPD
tPD
18
Timing Characteristics
Timing characteristics for 54SX devices fall into three
categories: family-dependent, device-dependent, and
design-dependent. The input and output buffer
characteristics are common to all 54SX family members.
Internal routing delays are device dependent. Design
dependency means actual delays are not determined until
after placement and routing of the user’s design is complete.
Delay values may then be determined by using the DirectTime
Analyzer utility or performing simulation with post-layout
delays.
Critical Nets and Typical Nets
Propagation delays are expressed only for typical nets, which
are used for initial design performance evaluation. Critical
net delays can then be applied to the most time-critical paths.
Critical nets are determined by net property assignment prior
to placement and routing. Up to 6 percent of the nets in a
design may be designated as critical, while 90 percent of the
nets in a design are typical.
Long Tracks
Some nets in the design use long tracks. Long tracks are
special routing resources that span multiple rows, columns, or
modules. Long tracks employ three and sometimes five
antifuse connections. This increases capacitance and
resistance, resulting in longer net delays for macros
connected to long tracks. Typically up to 6% of nets in a fully
utilized device require long tracks. Long tracks contribute
approximately 4 ns to 8.4 ns delay. This additional delay is
represented statistically in higher fanout (FO=24) routing
delays in the data sheet specifications section.
Timing Derating
54SX devices are manufactured in a CMOS process.
Therefore, device performance varies according to
temperature, voltage, and process variations. Minimum
timing parameters reflect maximum operating voltage,
minimum operating temperature, and best-case processing.
Maximum timing parameters reflect minimum operating
voltage, maximum operating temperature, and worst-case
processing.
Register Cell Timing Characteristics
Flip-Flops
(Positive edge triggered)
D
CLK CLR
Q
D
CLK
Q
CLR
tHPWH,
tWASYN
tHD
tSUD tHP
tHPWL,
tRCO
tCLR
tRPWL
tRPWH
PRESET
tPRESET
PRESET
19
54SX Family FPGAs RadTolerant and HiRel
A54SX16 Timing Characteristics
(Worst-Case Military Conditions, VCCR = 4.75V, VCCA, VCCI = 3.0V, TJ = 125°C)
C-Cell Propagation Delays1‘–1’ Speed ‘Std’ Speed
Parameter Description Min. Max. Min. Max. Units
tPD Internal Array Module 0.9 1.0 ns
Predicted Routing Delays2
tDC FO=1 Routing Delay, Direct Connect 0.1 0.1 ns
tFC FO=1 Routing Delay, Fast Connect 0.6 0.7 ns
tRD1 FO=1 Routing Delay 0.7 0.8 ns
tRD2 FO=2 Routing Delay 1.2 1.4 ns
tRD3 FO=3 Routing Delay 1.7 2.0 ns
tRD4 FO=4 Routing Delay 2.2 2.6 ns
tRD8 FO=8 Routing Delay 4.3 5.0 ns
tRD12 FO=12 Routing Delay 5.6 6.6 ns
tRD18 FO=18 Routing Delay 9.4 11.0 ns
tRD24 FO=24 Routing Delay 12.4 14.6 ns
R-Cell Timing
tRCO Sequential Clock-to-Q 0.6 0.8 ns
tCLR Asynchronous Clear-to-Q 0.6 0.8 ns
tSUD Flip-Flop Data Input Set-Up 0.8 0.9 ns
tHD Flip-Flop Data Input Hold 0.0 0.0 ns
tWASYN Asynchronous Pulse Width 2.4 2.9 ns
I/O Module Input Propagation Delays
tINYH Input Data Pad-to-Y HIGH 2.2 2.6 ns
tINYL Input Data Pad-to-Y LOW 2.2 2.6 ns
Predicted Input Routing Delays3
tIRD1 FO=1 Routing Delay 0.7 0.8 ns
tIRD2 FO=2 Routing Delay 1.2 1.4 ns
tIRD3 FO=3 Routing Delay 1.7 2.0 ns
tIRD4 FO=4 Routing Delay 2.2 2.6 ns
tIRD8 FO=8 Routing Delay 4.3 5.0 ns
tIRD12 FO=12 Routing Delay 5.6 6.6 ns
tIRD18 FO=18 Routing Delay 9.4 11.0 ns
tIRD24 FO=24 Routing Delay 12.4 14.6 ns
Notes:
1. For dual-module macros, use tPD + tRD1 + tPDn , tRCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD , whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is
based on actual routing delay measurements performed on the device prior to shipment.
3. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is
based on actual routing delay measurements performed on the device prior to shipment.
20
A54SX16 Timing Characteristics (continued)
(Worst-Case Military Conditions, VCCR = 4.75V, VCCA, VCCI = 3.0V, TJ = 125°C)
I/O Module – TTL Output Timing1‘–1’ Speed ‘Std’ Speed
Parameter Description Min. Max. Min. Max. Units
tDLH Data-to-Pad LOW to HIGH 2.8 3.3 ns
tDHL Data-to-Pad HIGH to LOW 2.8 3.3 ns
tENZL Enable-to-Pad, Z to L 2.3 2.8 ns
tENZH Enable-to-Pad, Z to H 2.8 3.3 ns
tENLZ Enable-to-Pad, L to Z 4.5 5.2 ns
tENHZ Enable-to-Pad, H to Z 2.2 2.6 ns
dTLH Delta LOW to HIGH 0.05 0.06 ns/pF
dTHL Delta HIGH to LOW 0.05 0.08 ns/pF
Dedicated (Hard-Wired) Array Clock Network
tHCKH Input LOW to HIGH
(Pad to R-Cell Input) 1.7 2.0 ns
tHCKL Input HIGH to LOW
(Pad to R-Cell Input) 1.9 2.2 ns
tHPWH Minimum Pulse Width HIGH 2.1 2.4 ns
tHPWL Minimum Pulse Width LOW 2.1 2.4 ns
tHCKSW Maximum Skew 0.4 0.4 ns
tHP Minimum Period 4.2 4.9 ns
fHMAX Maximum Frequency 240 205 MHz
Routed Array Clock Networks
tRCKH Input LOW to HIGH (Light Load)
(Pad to R-Cell Input) 2.4 2.9 ns
tRCKL Input HIGH to LOW (Light Load)
(Pad to R-Cell Input) 2.7 3.1 ns
tRCKH Input LOW to HIGH (50% Load)
(Pad to R-Cell Input) 2.9 3.3 ns
tRCKL Input HIGH to LOW (50% Load)
(Pad to R-Cell Input) 2.9 3.5 ns
tRCKH Input LOW to HIGH (100% Load)
(Pad to R-Cell Input) 2.8 3.3 ns
tRCKL Input HIGH to LOW (100% Load)
(Pad to R-Cell Input) 2.9 3.5 ns
tRPWH Min. Pulse Width HIGH 3.1 3.7 ns
tRPWL Min. Pulse Width LOW 3.1 3.7 ns
tRCKSW Maximum Skew (Light Load) 0.6 0.8 ns
tRCKSW Maximum Skew (50% Load) 0.8 0.9 ns
tRCKSW Maximum Skew (100% Load) 0.8 0.9 ns
Note:
1. Delays based on 35 pF loading, except for tENZL and tENZH . For tENZL and tENZH the loading is 5 pF.
21
54SX Family FPGAs RadTolerant and HiRel
RT54SX16 Timing Characteristics
(Worst-Case Military Conditions, VCCR = 4.75V, VCCA, VCCI = 3.0V, TJ = 125°C)
C-Cell Propagation Delays1‘–1’ Speed ‘Std’ Speed
Parameter Description Min. Max. Min. Max. Units
tPD Internal Array Module 1.7 1.8 ns
Predicted Routing Delays2
tDC FO=1 Routing Delay, Direct Connect 0.2 0.2 ns
tFC FO=1 Routing Delay, Fast Connect 1.1 1.3 ns
tRD1 FO=1 Routing Delay 1.3 1.5 ns
tRD2 FO=2 Routing Delay 2.2 2.6 ns
tRD3 FO=3 Routing Delay 3.1 3.6 ns
tRD4 FO=4 Routing Delay 4.0 4.7 ns
tRD8 FO=8 Routing Delay 7.8 9.0 ns
tRD12 FO=12 Routing Delay 10.1 11.9 ns
tRD18 FO=18 Routing Delay 17.0 19.8 ns
tRD24 FO=24 Routing Delay 22.4 26.3 ns
R-Cell Timing
tRCO Sequential Clock-to-Q 1.5 2.0 ns
tCLR Asynchronous Clear-to-Q 1.5 2.0 ns
tSUD Flip-Flop Data Input Set-Up 2.0 2.2 ns
tHD Flip-Flop Data Input Hold 0.0 0.0 ns
tWASYN Asynchronous Pulse Width 4.4 5.3 ns
I/O Module Input Propagation Delays
tINYH Input Data Pad-to-Y HIGH 4.0 4.7 ns
tINYL Input Data Pad-to-Y LOW 4.0 4.7 ns
Predicted Input Routing Delays3
tIRD1 FO=1 Routing Delay 1.3 1.5 ns
tIRD2 FO=2 Routing Delay 2.2 2.6 ns
tIRD3 FO=3 Routing Delay 3.1 3.6 ns
tIRD4 FO=4 Routing Delay 4.0 4.7 ns
tIRD8 FO=8 Routing Delay 7.8 9.0 ns
tIRD12 FO=12 Routing Delay 10.1 11.9 ns
tIRD18 FO=18 Routing Delay 17.0 19.8 ns
tIRD24 FO=24 Routing Delay 22.4 26.3 ns
Notes:
1. For dual-module macros, use tPD + tRD1 + tPDn , tRCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD , whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is
based on actual routing delay measurements performed on the device prior to shipment.
3. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is
based on actual routing delay measurements performed on the device prior to shipment.
22
RT54SX16 Timing Characteristics (continued)
(Worst-Case Military Conditions, VCCR = 4.75V, VCCA, VCCI = 3.0V, TJ = 125°C)
I/O Module – TTL Output Timing1‘–1’ Speed ‘Std’ Speed
Parameter Description Min. Max. Min. Max. Units
tDLH Data-to-Pad LOW to HIGH 5.1 6.0 ns
tDHL Data-to-Pad HIGH to LOW 5.1 6.0 ns
tENZL Enable-to-Pad, Z to L 4.2 5.1 ns
tENZH Enable-to-Pad, Z to H 5.1 6.0 ns
tENLZ Enable-to-Pad, L to Z 8.1 9.4 ns
tENHZ Enable-to-Pad, H to Z 4.0 4.7 ns
dTLH Delta LOW to HIGH 0.09 0.11 ns/pF
dTHL Delta HIGH to LOW 0.09 0.15 ns/pF
Dedicated (Hard-Wired) Array Clock Network
tHCKH Input LOW to HIGH
(Pad to R-Cell Input) 3.1 3.6 ns
tHCKL Input HIGH to LOW
(Pad to R-Cell Input) 3.5 4.0 ns
tHPWH Minimum Pulse Width HIGH 3.8 4.4 ns
tHPWL Minimum Pulse Width LOW 3.8 4.4 ns
tHCKSW Maximum Skew 0.8 0.8 ns
tHP Minimum Period 7.6 8.9 ns
fHMAX Maximum Frequency 130 110 MHz
Routed Array Clock Networks
tRCKH Input LOW to HIGH (Light Load)
(Pad to R-Cell Input) 4.4 5.3 ns
tRCKL Input HIGH to LOW (Light Load)
(Pad to R-Cell Input) 4.9 5.6 ns
tRCKH Input LOW to HIGH (50% Load)
(Pad to R-Cell Input) 5.3 6.0 ns
tRCKL Input HIGH to LOW (50% Load)
(Pad to R-Cell Input) 5.3 6.3 ns
tRCKH Input LOW to HIGH (100% Load)
(Pad to R-Cell Input) 5.1 6.0 ns
tRCKL Input HIGH to LOW (100% Load)
(Pad to R-Cell Input) 5.3 6.3 ns
tRPWH Min. Pulse Width HIGH 5.6 6.7 ns
tRPWL Min. Pulse Width LOW 5.6 6.7 ns
tRCKSW Maximum Skew (Light Load) 1.1 1.5 ns
tRCKSW Maximum Skew (50% Load) 1.5 1.7 ns
tRCKSW Maximum Skew (100% Load) 1.5 1.7 ns
Note:
1. Delays based on 35 pF loading, except for tENZL and tENZH . For tENZL and tENZH the loading is 5 pF.
23
54SX Family FPGAs RadTolerant and HiRel
A54SX32 Timing Characteristics
(Worst-Case Military Conditions, VCCR = 4.75V, VCCA, VCCI = 3.0V, TJ = 125°C)
C-Cell Propagation Delays1‘–1’ Speed ‘Std’ Speed
Parameter Description Min. Max. Min. Max. Units
tPD Internal Array Module 0.9 1.0 ns
Predicted Routing Delays2
tDC FO=1 Routing Delay, Direct Connect 0.1 0.1 ns
tFC FO=1 Routing Delay, Fast Connect 0.6 0.7 ns
tRD1 FO=1 Routing Delay 0.7 0.8 ns
tRD2 FO=2 Routing Delay 1.2 1.4 ns
tRD3 FO=3 Routing Delay 1.7 2.0 ns
tRD4 FO=4 Routing Delay 2.2 2.6 ns
tRD8 FO=8 Routing Delay 4.3 5.0 ns
tRD12 FO=12 Routing Delay 5.6 6.6 ns
tRD18 FO=18 Routing Delay 9.4 11.0 ns
tRD24 FO=24 Routing Delay 12.4 14.6 ns
R-Cell Timing
tRCO Sequential Clock-to-Q 0.6 0.8 ns
tCLR Asynchronous Clear-to-Q 0.6 0.8 ns
tSUD Flip-Flop Data Input Set-Up 0.8 0.9 ns
tHD Flip-Flop Data Input Hold 0.0 0.0 ns
tWASYN Asynchronous Pulse Width 2.4 2.9 ns
I/O Module Input Propagation Delays
tINYH Input Data Pad-to-Y HIGH 2.2 2.6 ns
tINYL Input Data Pad-to-Y LOW 2.2 2.6 ns
Predicted Input Routing Delays3
tIRD1 FO=1 Routing Delay 0.7 0.8 ns
tIRD2 FO=2 Routing Delay 1.2 1.4 ns
tIRD3 FO=3 Routing Delay 1.7 2.0 ns
tIRD4 FO=4 Routing Delay 2.2 2.6 ns
tIRD8 FO=8 Routing Delay 4.3 5.0 ns
tIRD12 FO=12 Routing Delay 5.6 6.6 ns
tIRD18 FO=18 Routing Delay 9.4 11.0 ns
tIRD24 FO=24 Routing Delay 12.4 14.6 ns
Notes:
1. For dual-module macros, use tPD + tRD1 + tPDn , tRCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD , whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is
based on actual routing delay measurements performed on the device prior to shipment.
3. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is
based on actual routing delay measurements performed on the device prior to shipment.
24
A54SX32 Timing Characteristics (continued)
(Worst-Case Military Conditions, VCCR = 4.75V, VCCA, VCCI = 3.0V, TJ = 125°C)
I/O Module – TTL Output Timing1‘–1’ Speed ‘Std’ Speed
Parameter Description Min. Max. Min. Max. Units
tDLH Data-to-Pad LOW to HIGH 2.8 3.3 ns
tDHL Data-to-Pad HIGH to LOW 2.8 3.3 ns
tENZL Enable-to-Pad, Z to L 2.3 2.8 ns
tENZH Enable-to-Pad, Z to H 2.8 3.3 ns
tENLZ Enable-to-Pad, L to Z 4.5 5.2 ns
tENHZ Enable-to-Pad, H to Z 2.2 2.6 ns
dTLH Delta LOW to HIGH 0.05 0.06 ns/pF
dTHL Delta HIGH to LOW 0.05 0.08 ns/pF
Dedicated (Hard-Wired) Array Clock Network
tHCKH Input LOW to HIGH
(Pad to R-Cell Input) 1.7 2.0 ns
tHCKL Input HIGH to LOW
(Pad to R-Cell Input) 1.9 2.2 ns
tHPWH Minimum Pulse Width HIGH 2.1 2.4 ns
tHPWL Minimum Pulse Width LOW 2.1 2.4 ns
tHCKSW Maximum Skew 0.4 0.4 ns
tHP Minimum Period 4.2 4.8 ns
fHMAX Maximum Frequency 240 205 MHz
Routed Array Clock Networks
tRCKH Input LOW to HIGH (Light Load)
(Pad to R-Cell Input) 2.4 2.9 ns
tRCKL Input HIGH to LOW (Light Load)
(Pad to R-Cell Input) 2.7 3.1 ns
tRCKH Input LOW to HIGH (50% Load)
(Pad to R-Cell Input) 2.9 3.3 ns
tRCKL Input HIGH to LOW (50% Load)
(Pad to R-Cell Input) 2.9 3.5 ns
tRCKH Input LOW to HIGH (100% Load)
(Pad to R-Cell Input) 2.8 3.3 ns
tRCKL Input HIGH to LOW (100% Load)
(Pad to R-Cell Input) 2.9 3.5 ns
tRPWH Min. Pulse Width HIGH 3.1 3.7 ns
tRPWL Min. Pulse Width LOW 3.1 3.7 ns
tRCKSW Maximum Skew (Light Load) 0.6 0.8 ns
tRCKSW Maximum Skew (50% Load) 0.8 0.9 ns
tRCKSW Maximum Skew (100% Load) 0.8 0.9 ns
Note:
1. Delays based on 35 pF loading, except tENZL and tENZH . For tENZL and tENZH the loading is 5 pF.
25
54SX Family FPGAs RadTolerant and HiRel
RT54SX32 Timing Characteristics
(Worst-Case Military Conditions, VCCR = 4.75V, VCCA, VCCI = 3.0V, TJ = 125°C)
C-Cell Propagation Delays1‘–1’ Speed ‘Std’ Speed
Parameter Description Min. Max. Min. Max. Units
tPD Internal Array Module 1.7 1.8 ns
Predicted Routing Delays2
tDC FO=1 Routing Delay, Direct Connect 0.2 0.2 ns
tFC FO=1 Routing Delay, Fast Connect 1.1 1.3 ns
tRD1 FO=1 Routing Delay 1.3 1.5 ns
tRD2 FO=2 Routing Delay 2.2 2.6 ns
tRD3 FO=3 Routing Delay 3.1 3.6 ns
tRD4 FO=4 Routing Delay 4.0 4.7 ns
tRD8 FO=8 Routing Delay 7.8 9.0 ns
tRD12 FO=12 Routing Delay 10.1 11.9 ns
tRD18 FO=18 Routing Delay 17.0 19.8 ns
tRD24 FO=24 Routing Delay 22.4 26.3 ns
R-Cell Timing
tRCO Sequential Clock-to-Q 1.5 2.0 ns
tCLR Asynchronous Clear-to-Q 1.5 2.0 ns
tSUD Flip-Flop Data Input Set-Up 2.0 2.2 ns
tHD Flip-Flop Data Input Hold 0.0 0.0 ns
tWASYN Asynchronous Pulse Width 4.4 5.3 ns
I/O Module Input Propagation Delays
tINYH Input Data Pad-to-Y HIGH 4.0 4.7 ns
tINYL Input Data Pad-to-Y LOW 4.0 4.7 ns
Predicted Input Routing Delays3
tIRD1 FO=1 Routing Delay 1.3 1.5 ns
tIRD2 FO=2 Routing Delay 2.2 2.6 ns
tIRD3 FO=3 Routing Delay 3.1 3.6 ns
tIRD4 FO=4 Routing Delay 4.0 4.7 ns
tIRD8 FO=8 Routing Delay 7.8 9.0 ns
tIRD12 FO=12 Routing Delay 10.1 11.9 ns
tIRD18 FO=18 Routing Delay 17.0 19.8 ns
tIRD24 FO=24 Routing Delay 22.4 26.3 ns
Notes:
1. For dual-module macros, use tPD + tRD1 + tPDn , tRCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD , whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is
based on actual routing delay measurements performed on the device prior to shipment.
3. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is
based on actual routing delay measurements performed on the device prior to shipment.
26
RT54SX32 Timing Characteristics (continued)
(Worst-Case Military Conditions, VCCR = 4.75V, VCCA, VCCI = 3.0V, TJ = 125°C)
I/O Module – TTL Output Timing1‘–1’ Speed ‘Std’ Speed
Parameter Description Min. Max. Min. Max. Units
tDLH Data-to-Pad LOW to HIGH 5.1 6.0 ns
tDHL Data-to-Pad HIGH to LOW 5.1 6.0 ns
tENZL Enable-to-Pad, Z to L 4.2 5.1 ns
tENZH Enable-to-Pad, Z to H 5.1 6.0 ns
tENLZ Enable-to-Pad, L to Z 8.1 9.4 ns
tENHZ Enable-to-Pad, H to Z 4.0 4.7 ns
dTLH Delta LOW to HIGH 0.09 0.11 ns/pF
dTHL Delta HIGH to LOW 0.09 0.15 ns/pF
Dedicated (Hard-Wired) Array Clock Network
tHCKH Input LOW to HIGH
(Pad to R-Cell Input) 3.1 3.6 ns
tHCKL Input HIGH to LOW
(Pad to R-Cell Input) 3.5 4.0 ns
tHPWH Minimum Pulse Width HIGH 3.8 4.4 ns
tHPWL Minimum Pulse Width LOW 3.8 4.4 ns
tHCKSW Maximum Skew 0.8 0.8 ns
tHP Minimum Period 7.6 8.9 ns
fHMAX Maximum Frequency 130 110 MHz
Routed Array Clock Networks
tRCKH Input LOW to HIGH (Light Load)
(Pad to R-Cell Input) 4.4 5.3 ns
tRCKL Input HIGH to LOW (Light Load)
(Pad to R-Cell Input) 4.9 5.6 ns
tRCKH Input LOW to HIGH (50% Load)
(Pad to R-Cell Input) 5.3 6.0 ns
tRCKL Input HIGH to LOW (50% Load)
(Pad to R-Cell Input) 5.3 6.3 ns
tRCKH Input LOW to HIGH (100% Load)
(Pad to R-Cell Input) 5.1 6.0 ns
tRCKL Input HIGH to LOW (100% Load)
(Pad to R-Cell Input) 5.3 6.3 ns
tRPWH Min. Pulse Width HIGH 5.6 6.7 ns
tRPWL Min. Pulse Width LOW 5.6 6.7 ns
tRCKSW Maximum Skew (Light Load) 1.1 1.5 ns
tRCKSW Maximum Skew (50% Load) 1.5 1.7 ns
tRCKSW Maximum Skew (100% Load) 1.5 1.7 ns
Note:
1. Delays based on 35 pF loading, except tENZL and tENZH . For tENZL and tENZH the loading is 5 pF.
27
54SX Family FPGAs RadTolerant and HiRel
Pin Description
CLKA Clock A (Input)
TTL clock input for clock distribution networks. The clock
input is buffered prior to clocking the R-cells. If not used, this
pin must be set LOW or HIGH on the board. It must not be left
floating.
CLKB Clock B (Input)
TTL clock input for clock distribution networks. The clock
input is buffered prior to clocking the R-cells. If not used, this
pin must be set LOW or HIGH on the board. It must not be left
floating.
GND Ground
LOW supply voltage.
HCLK Dedicated (Hard-wired)
Array Clock (Input)
TTL clock input for sequential modules. This input is directly
wired to each R-cell and offers clock speeds independent of
the number of R-cells being driven. If not used, this pin must
be set LOW or HIGH on the board. It must not be left floating.
I/O Input/Output (Input, Output)
The I/O pin functions as an input, output, three-state, or
bi-directional buffer. Input and output levels are compatible
with standard TTL and CMOS specifications. Unused I/O pins
are tri-stated by the Designer Series software.
NC No Connection
This pin is not connected to circuitry within the device.
PRA ActionProbe A (Output)
The Probe A pin is used to output data from any user-defined
design node within the device. This independent diagnostic
pin can be used in conjunction with the Probe B pin to allow
real-time diagnostic output of any signal path within the
device. The Probe A pin can be used as a user-defined I/O
when verification has been completed.
PRB ActionProbe B (Output)
The Probe B pin is used to output data from any node within
the device. This diagnostic pin can be used in conjunction
with the Probe A pin to allow real-time diagnostic output of
any signal path within the device. The Probe B pin can be
used as a user-defined I/O when verification has been
completed.
TCK Test Clock (Input)
Test clock input for diagnostic probe and device
programming. In flexible mode, TCK becomes active when
the TMS pin is set LOW (Table 1 on page 5). This pin
functions as an I/O when the JTAG state machine reaches the
“logic reset” state.
TDI Test Data Input (Input)
Serial input for JTAG and diagnostic probe. In flexible mode,
TDI is active when the TMS pin is set LOW (Table 1 on
page 5). This pin functions as an I/O when the JTAG state
machine reaches the “logic reset” state.
TDO Test Data Output (output)
Serial output for JTAG. In flexible mode, TDO is active when
the TMS pin is set LOW (Table 1 on page 5). This pin
functions as an I/O when the JTAG state machine reaches the
“logic reset” state.
TMS Test Mode Select (Input)
The TMS pin controls the use of JTAG pins (TCK, TDI, TDO).
In flexible mode, when the TMS pin is set LOW, the TCK, TDI,
and TDO pins are JTAG pins (Table 1 on page 5). Once the
JTAG pins are in JTAG mode they will remain in JTAG mode
until the internal JTAG state machine reaches the “logic
reset” state. At this point the JTAG pins will be released and
will function as regular I/O pins. The “logic reset” state is
reached 5 TCK cycles after the TMS pin is set HIGH. In
dedicated JTAG mode, TMS functions as specified in the
IEEE 499.1 JTAG Specifications. JTAG operation is further
described on page 5.
TRST Test Reset Pin (Input)
JTAG reset pin (active LOW). This pin is used to reset the
JTAG state machine in “test-logic-reset” state to avoid
accidental shifts into various JTAG operations due to the
effects of heavy ions in a radiation environment. When this
pin is tied LOW, the device is held in the “test-logic-reset”
state and the JTAG functionality cannot be used. When this
pin is tied HIGH, the JTAG function can operate. This pin
should not be left floating.
VCCI 3.3V Supply Voltage
Supply voltage for I/Os.
VCCA 3.3V Supply Voltage
Supply voltage for Array.
VCCR 5.0V Supply Voltage
Supply voltage for input tolerance (required for internal
biasing).
Table 2 •Supply Voltages
VCCA VCCI VCCR
Maximum
Input
Tolerance
Maximum
Output
Drive
A54SX16
A54SX32 3.3V 3.3V 5.0V 3.3V 3.3V
RTSX16
RTSX32 3.3V 3.3V 5.0V 5.0V 3.3V
28
Package Pin Assignments
208-Pin CQFP (Top View)
208-Pin
CQFP
Pin #1
Index
208 207 206 205 204 203 202 201 200 164 163 162 161 160 159 158 157
53 54 55 56 57 58 59 60 61 97 98 99 100 101 102 103 104
105
106
107
108
109
110
111
112
113
149
150
151
152
153
154
155
156
52
51
50
49
48
47
46
45
44
8
7
6
5
4
3
2
1
54SX Family FPGAs RadTolerant and HiRel
29
208-Pin CQFP
Pin
Number
A54SX16
Function
RT54SX16
Function
A54SX32
Function
RT54SX32
Function
Pin
Number
A54SX16
Function
RT54SX16
Function
A54SX32
Function
RT54SX32
Function
1 GND GND GND GND 53 I/O I/O I/O I/O
2 TDI, I/O TDI, I/O TDI, I/O TDI, I/O 54 I/O I/O I/O I/O
3 I/O I/O I/O I/O 55 I/O I/O I/O I/O
4 I/O I/O I/O I/O 56 I/O I/O I/O I/O
5 I/O I/O I/O I/O 57 I/O I/O I/O I/O
6 I/O I/O I/O I/O 58 I/O I/O I/O I/O
7 I/O I/O I/O I/O 59 I/O I/O I/O I/O
8 I/O I/O I/O I/O 60 VCCI VCCI VCCI VCCI
9 I/O I/O I/O I/O 61 I/O I/O I/O I/O
10 I/O I/O I/O I/O 62 I/O I/O I/O I/O
11 TMS TMS TMS TMS 63 I/O I/O I/O I/O
12 VCCI VCCI VCCI VCCI 64 I/O I/O I/O I/O
13 I/O I/O I/O I/O 65 I/O I/O NC NC
14 I/O I/O I/O I/O 66 I/O I/O I/O I/O
15 I/O I/O I/O I/O 67 I/O I/O I/O I/O
16 I/O I/O I/O I/O 68 I/O I/O I/O I/O
17 I/O I/O I/O I/O 69 I/O I/O I/O I/O
18 I/O I/O I/O I/O 70 I/O I/O I/O I/O
19 I/O I/O I/O I/O 71 I/O I/O I/O I/O
20 I/O I/O I/O I/O 72 I/O I/O I/O I/O
21 I/O I/O I/O I/O 73 I/O I/O I/O I/O
22 I/O I/O I/O I/O 74 I/O I/O I/O I/O
23 I/O I/O I/O I/O 75 I/O I/O I/O I/O
24 I/O I/O I/O I/O 76 PRB, I/O PRB, I/O PRB, I/O PRB, I/O
25 VCCR VCCR VCCR VCCR 77 GND GND GND GND
26 GND GND GND GND 78 VCCA VCCA VCCA VCCA
27 VCCA VCCA VCCA VCCA 79 GND GND GND GND
28 GND GND GND GND 80 VCCR VCCR VCCR VCCR
29 I/O I/O I/O I/O 81 I/O I/O I/O I/O
30 I/O TRST I/O TRST 82 HCLK HCLK HCLK HCLK
31 I/O I/O I/O I/O 83 I/O I/O I/O I/O
32 I/O I/O I/O I/O 84 I/O I/O I/O I/O
33 I/O I/O I/O I/O 85 I/O I/O I/O I/O
34 I/O I/O I/O I/O 86 I/O I/O I/O I/O
35 I/O I/O I/O I/O 87 I/O I/O I/O I/O
36 I/O I/O I/O I/O 88 I/O I/O I/O I/O
37 I/O I/O I/O I/O 89 I/O I/O I/O I/O
38 I/O I/O I/O I/O 90 I/O I/O I/O I/O
39 I/O I/O I/O I/O 91 I/O I/O I/O I/O
40 VCCI VCCI VCCI VCCI 92 I/O I/O I/O I/O
41 VCCA VCCA VCCA VCCA 93 I/O I/O I/O I/O
42 I/O I/O I/O I/O 94 I/O I/O I/O I/O
43 I/O I/O I/O I/O 95 I/O I/O I/O I/O
44 I/O I/O I/O I/O 96 I/O I/O I/O I/O
45 I/O I/O I/O I/O 97 I/O I/O I/O I/O
46 I/O I/O I/O I/O 98 VCCI VCCI VCCI VCCI
47 I/O I/O I/O I/O 99 I/O I/O I/O I/O
48 I/O I/O I/O I/O 100 I/O I/O I/O I/O
49 I/O I/O I/O I/O 101 I/O I/O I/O I/O
50 I/O I/O I/O I/O 102 I/O I/O I/O I/O
51 I/O I/O I/O I/O 103 TDO, I/O TDO, I/O TDO, I/O TDO, I/O
52 GND GND GND GND 104 I/O I/O I/O I/O
Notes:
1. Pin 30 in RT54SX16 and RT54SX32-CQ208 are TRST pins.
2. Pin 65 in A54SX32 and RT54SX32-CQ208 are No Connects.
30
105 GND GND GND GND 157 GND GND GND GND
106 I/O I/O I/O I/O 158 I/O I/O I/O I/O
107 I/O I/O I/O I/O 159 I/O I/O I/O I/O
108 I/O I/O I/O I/O 160 I/O I/O I/O I/O
109 I/O I/O I/O I/O 161 I/O I/O I/O I/O
110 I/O I/O I/O I/O 162 I/O I/O I/O I/O
111 I/O I/O I/O I/O 163 I/O I/O I/O I/O
112 I/O I/O I/O I/O 164 VCCI VCCI VCCI VCCI
113 I/O I/O I/O I/O 165 I/O I/O I/O I/O
114 VCCA VCCA VCCA VCCA 166 I/O I/O I/O I/O
115 VCCI VCCI VCCI VCCI 167 I/O I/O I/O I/O
116 I/O I/O I/O I/O 168 I/O I/O I/O I/O
117 I/O I/O I/O I/O 169 I/O I/O I/O I/O
118 I/O I/O I/O I/O 170 I/O I/O I/O I/O
119 I/O I/O I/O I/O 171 I/O I/O I/O I/O
120 I/O I/O I/O I/O 172 I/O I/O I/O I/O
121 I/O I/O I/O I/O 173 I/O I/O I/O I/O
122 I/O I/O I/O I/O 174 I/O I/O I/O I/O
123 I/O I/O I/O I/O 175 I/O I/O I/O I/O
124 I/O I/O I/O I/O 176 I/O I/O I/O I/O
125 I/O I/O I/O I/O 177 I/O I/O I/O I/O
126 I/O I/O I/O I/O 178 I/O I/O I/O I/O
127 I/O I/O I/O I/O 179 I/O I/O I/O I/O
128 I/O I/O I/O I/O 180 CLKA CLKA CLKA CLKA
129 GND GND GND GND 181 CLKB CLKB CLKB CLKB
130 VCCA VCCA VCCA VCCA 182 VCCR VCCR VCCR VCCR
131 GND GND GND GND 183 GND GND GND GND
132 VCCR VCCR VCCR VCCR 184 VCCA VCCA VCCA VCCA
133 I/O I/O I/O I/O 185 GND GND GND GND
134 I/O I/O I/O I/O 186 PRA, I/O PRA, I/O PRA, I/O PRA, I/O
135 I/O I/O I/O I/O 187 I/O I/O I/O I/O
136 I/O I/O I/O I/O 188 I/O I/O I/O I/O
137 I/O I/O I/O I/O 189 I/O I/O I/O I/O
138 I/O I/O I/O I/O 190 I/O I/O I/O I/O
139 I/O I/O I/O I/O 191 I/O I/O I/O I/O
140 I/O I/O I/O I/O 192 I/O I/O I/O I/O
141 I/O I/O I/O I/O 193 I/O I/O I/O I/O
142 I/O I/O I/O I/O 194 I/O I/O I/O I/O
143 I/O I/O I/O I/O 195 I/O I/O I/O I/O
144 I/O I/O I/O I/O 196 I/O I/O I/O I/O
145 VCCA VCCA VCCA VCCA 197 I/O I/O I/O I/O
146 GND GND GND GND 198 I/O I/O I/O I/O
147 I/O I/O I/O I/O 199 I/O I/O I/O I/O
148 VCCI VCCI VCCI VCCI 200 I/O I/O I/O I/O
149 I/O I/O I/O I/O 201 VCCI VCCI VCCI VCCI
150 I/O I/O I/O I/O 202 I/O I/O I/O I/O
151 I/O I/O I/O I/O 203 I/O I/O I/O I/O
152 I/O I/O I/O I/O 204 I/O I/O I/O I/O
153 I/O I/O I/O I/O 205 I/O I/O I/O I/O
154 I/O I/O I/O I/O 206 I/O I/O I/O I/O
155 I/O I/O I/O I/O 207 I/O I/O I/O I/O
156 I/O I/O I/O I/O 208 TCK, I/O TCK, I/O TCK, I/O TCK, I/O
208-Pin CQFP (Continued)
Pin
Number
A54SX16
Function
RT54SX16
Function
A54SX32
Function
RT54SX32
Function
Pin
Number
A54SX16
Function
RT54SX16
Function
A54SX32
Function
RT54SX32
Function
Notes:
1. Pin 30 in RT54SX16 and RT54SX32-CQ208 are TRST pins.
2. Pin 65 in A54SX32 and RT54SX32-CQ208 are No Connects.
31
54SX Family FPGAs RadTolerant and HiRel
Package Pin Assignments (continued)
256-Pin CQFP (Top View)
256-Pin
CQFP
Pin #1
Index
256 255 254 253 252 251 250 249 248 200 199 198 197 196 195 194 193
65 66 67 68 69 70 71 72 73 121 122 123 124 125 126 127 128
129
130
131
132
133
134
135
136
137
185
186
187
188
189
190
191
192
64
63
62
61
60
59
58
57
56
8
7
6
5
4
3
2
1
32
256-Pin CQFP
Pin
Number
A54SX16
Function
RT54SX16
Function
A54SX32
Function
RT54SX32
Function
Pin
Number
A54SX16
Function
RT54SX16
Function
A54SX32
Function
RT54SX32
Function
1 GND GND GND GND 53 I/O I/O I/O I/O
2 TDI, I/O TDI, I/O TDI, I/O TDI, I/O 54 NC NC I/O I/O
3 I/O I/O I/O I/O 55 I/O I/O I/O I/O
4 I/O I/O I/O I/O 56 I/O I/O I/O I/O
5 I/O I/O I/O I/O 57 NC NC I/O I/O
6 I/O I/O I/O I/O 58 I/O I/O I/O I/O
7 I/O I/O I/O I/O 59 GND GND GND GND
8 I/O I/O I/O I/O 60 I/O I/O I/O I/O
9 I/O I/O I/O I/O 61 NC NC I/O I/O
10 I/O I/O I/O I/O 62 I/O I/O I/O I/O
11 TMS TMS TMS TMS 63 NC NC I/O I/O
12 NC NC I/O I/O 64 I/O I/O I/O I/O
13 NC NC I/O I/O 65 I/O I/O I/O I/O
14 I/O I/O I/O I/O 66 I/O I/O I/O I/O
15 I/O I/O I/O I/O 67 I/O I/O I/O I/O
16 NC NC I/O I/O 68 NC NC I/O I/O
17 I/O I/O I/O I/O 69 I/O I/O I/O I/O
18 I/O I/O I/O I/O 70 I/O I/O I/O I/O
19 I/O I/O I/O I/O 71 I/O I/O I/O I/O
20 NC NC I/O I/O 72 I/O I/O I/O I/O
21 I/O I/O I/O I/O 73 NC NC I/O I/O
22 I/O I/O I/O I/O 74 I/O I/O I/O I/O
23 I/O I/O I/O I/O 75 I/O I/O I/O I/O
24 I/O I/O I/O I/O 76 I/O I/O I/O I/O
25 I/O I/O I/O I/O 77 NC NC I/O I/O
26 I/O I/O I/O I/O 78 I/O I/O I/O I/O
27 I/O I/O I/O I/O 79 I/O I/O I/O I/O
28 VCCI VCCI VCCI VCCI 80 I/O I/O I/O I/O
29 GND GND GND GND 81 I/O I/O I/O I/O
30 VCCA VCCA VCCA VCCA 82 I/O I/O I/O I/O
31 GND GND GND GND 83 I/O I/O I/O I/O
32 NC NC I/O I/O 84 I/O I/O I/O I/O
33 I/O I/O I/O I/O 85 I/O I/O I/O I/O
34 I/O TRST I/O TRST 86 I/O I/O I/O I/O
35 I/O I/O I/O I/O 87 I/O I/O I/O I/O
36 NC NC I/O I/O 88 I/O I/O I/O I/O
37 I/O I/O I/O I/O 89 I/O I/O I/O I/O
38 I/O I/O I/O I/O 90 PRB, I/O PRB, I/O PRB, I/O PRB, I/O
39 I/O I/O I/O I/O 91 GND GND GND GND
40 I/O I/O I/O I/O 92 VCCI VCCI VCCI VCCI
41 NC NC I/O I/O 93 GND GND GND GND
42 I/O I/O I/O I/O 94 VCCA VCCA VCCA VCCA
43 I/O I/O I/O I/O 95 I/O I/O I/O I/O
44 I/O I/O I/O I/O 96 HCLK HCLK HCLK HCLK
45 I/O I/O I/O I/O 97 I/O I/O I/O I/O
46 VCCA VCCA VCCA VCCA 98 NC NC I/O I/O
47 I/O I/O I/O I/O 99 I/O I/O I/O I/O
48 NC NC I/O I/O 100 I/O I/O I/O I/O
49 I/O I/O I/O I/O 101 I/O I/O I/O I/O
50 I/O I/O I/O I/O 102 NC NC I/O I/O
51 NC NC I/O I/O 103 I/O I/O I/O I/O
52 I/O I/O I/O I/O 104 I/O I/O I/O I/O
Note:
1. Pin 34 in RT54SX16 and RT54SX32-CQ256 are TRST pins.
33
54SX Family FPGAs RadTolerant and HiRel
105 I/O I/O I/O I/O 158 GND GND GND GND
106 NC NC I/O I/O 159 VCCR VCCR VCCR VCCR
107 I/O I/O I/O I/O 160 GND GND GND GND
108 I/O I/O I/O I/O 161 VCCI VCCI VCCI VCCI
109 I/O I/O I/O I/O 162 I/O I/O I/O I/O
110 GND GND GND GND 163 I/O I/O I/O I/O
111 I/O I/O I/O I/O 164 I/O I/O I/O I/O
112 I/O I/O I/O I/O 165 I/O I/O I/O I/O
113 I/O I/O I/O I/O 166 I/O I/O I/O I/O
114 NC NC I/O I/O 167 I/O I/O I/O I/O
115 I/O I/O I/O I/O 168 I/O I/O I/O I/O
116 I/O I/O I/O I/O 169 I/O I/O I/O I/O
117 I/O I/O I/O I/O 170 I/O I/O I/O I/O
118 NC NC I/O I/O 171 I/O I/O I/O I/O
119 I/O I/O I/O I/O 172 I/O I/O I/O I/O
120 I/O I/O I/O I/O 173 I/O I/O I/O I/O
121 I/O I/O I/O I/O 174 VCCA VCCA VCCA VCCA
122 NC NC I/O I/O 175 GND GND GND GND
123 I/O I/O I/O I/O 176 GND GND GND GND
124 I/O I/O I/O I/O 177 I/O I/O I/O I/O
125 NC NC I/O I/O 178 NC NC I/O I/O
126 TDO, I/O TDO, I/O TDO, I/O TDO, I/O 179 I/O I/O I/O I/O
127 NC NC I/O I/O 180 I/O I/O I/O I/O
128 GND GND GND GND 181 NC NC I/O I/O
129 I/O I/O I/O I/O 182 I/O I/O I/O I/O
130 I/O I/O I/O I/O 183 I/O I/O I/O I/O
131 I/O I/O I/O I/O 184 NC NC I/O I/O
132 I/O I/O I/O I/O 185 I/O I/O I/O I/O
133 I/O I/O I/O I/O 186 I/O I/O I/O I/O
134 I/O I/O I/O I/O 187 NC NC I/O I/O
135 I/O I/O I/O I/O 188 I/O I/O I/O I/O
136 I/O I/O I/O I/O 189 GND GND GND GND
137 I/O I/O I/O I/O 190 I/O I/O I/O I/O
138 NC NC I/O I/O 191 NC NC I/O I/O
139 NC NC I/O I/O 192 NC NC I/O I/O
140 NC NC I/O I/O 193 I/O I/O I/O I/O
141 VCCA VCCA VCCA VCCA 194 I/O I/O I/O I/O
142 I/O I/O I/O I/O 195 NC NC I/O I/O
143 I/O I/O I/O I/O 196 I/O I/O I/O I/O
144 I/O I/O I/O I/O 197 I/O I/O I/O I/O
145 I/O I/O I/O I/O 198 I/O I/O I/O I/O
146 I/O I/O I/O I/O 199 I/O I/O I/O I/O
147 I/O I/O I/O I/O 200 NC NC I/O I/O
148 I/O I/O I/O I/O 201 I/O I/O I/O I/O
149 I/O I/O I/O I/O 202 I/O I/O I/O I/O
150 I/O I/O I/O I/O 203 I/O I/O I/O I/O
151 I/O I/O I/O I/O 204 NC NC I/O I/O
152 I/O I/O I/O I/O 205 I/O I/O I/O I/O
153 I/O I/O I/O I/O 206 I/O I/O I/O I/O
154 I/O I/O I/O I/O 207 I/O I/O I/O I/O
155 NC NC I/O I/O 208 NC NC I/O I/O
156 NC NC I/O I/O 209 I/O I/O I/O I/O
157 NC NC I/O I/O 210 I/O I/O I/O I/O
256-Pin CQFP (Continued)
Pin
Number
A54SX16
Function
RT54SX16
Function
A54SX32
Function
RT54SX32
Function
Pin
Number
A54SX16
Function
RT54SX16
Function
A54SX32
Function
RT54SX32
Function
Note:
1. Pin 34 in RT54SX16 and RT54SX32-CQ256 are TRST pins.
34
211 I/O I/O I/O I/O 234 I/O I/O I/O I/O
212 I/O I/O I/O I/O 235 I/O I/O I/O I/O
213 I/O I/O I/O I/O 236 NC NC I/O I/O
214 I/O I/O I/O I/O 237 I/O I/O I/O I/O
215 I/O I/O I/O I/O 238 I/O I/O I/O I/O
216 I/O I/O I/O I/O 239 NC NC I/O I/O
217 I/O I/O I/O I/O 240 GND GND GND GND
218 I/O I/O I/O I/O 241 I/O I/O I/O I/O
219 CLKA CLKA CLKA CLKA 242 I/O I/O I/O I/O
220 CLKB CLKB CLKB CLKB 243 NC NC I/O I/O
221 VCCI VCCI VCCI VCCI 244 I/O I/O I/O I/O
222 GND GND GND GND 245 I/O I/O I/O I/O
223 VCCR VCCR VCCR VCCR 246 I/O I/O I/O I/O
224 GND GND GND GND 247 NC NC I/O I/O
225 PRA, I/O PRA, I/O PRA, I/O PRA, I/O 248 I/O I/O I/O I/O
226 I/O I/O I/O I/O 249 I/O I/O I/O I/O
227 NC NC I/O I/O 250 NC NC I/O I/O
228 I/O I/O I/O I/O 251 I/O I/O I/O I/O
229 I/O I/O I/O I/O 252 I/O I/O I/O I/O
230 I/O I/O I/O I/O 253 NC NC I/O I/O
231 I/O I/O I/O I/O 254 I/O I/O I/O I/O
232 NC NC I/O I/O 255 I/O I/O I/O I/O
233 I/O I/O I/O I/O 256 TCK, I/O TCK, I/O TCK, I/O TCK, I/O
256-Pin CQFP (Continued)
Pin
Number
A54SX16
Function
RT54SX16
Function
A54SX32
Function
RT54SX32
Function
Pin
Number
A54SX16
Function
RT54SX16
Function
A54SX32
Function
RT54SX32
Function
Note:
1. Pin 34 in RT54SX16 and RT54SX32-CQ256 are TRST pins.
35
54SX Family FPGAs RadTolerant and HiRel
Package Mechanical Drawings
208-Pin and 256-Pin CQFP (Cavity Up)
Notes:
1. Outside lead frame holes (from dimension H) are circular.
2. Seal ring and lid are connected to Ground.
3. Lead material is Kovar with minimum 50 microinches gold plate over nickel.
4. Packages are shipped unformed with the ceramic tie bar.
5. CQ256 has a Heat Sink on the back.
A
b
H
D1
D2
E2 E1
F
L1 k
Ceramic
Tie Bar
No. 1
e
A1 t
C
Lead Kovar
Heat Sink
for CQ256
Lid
Top View
Side View
36
Ceramic Quad Flat Pack
CQFP 208 CQFP 256
Dimension Min. Nom. Max. Min. Nom. Max.
A 2.20 2.44 2.67 2.19 2.44 2.69
A1 2.05 2.29 2.52 2.04 2.29 2.50
b 0.18 0.20 0.22 0.18 0.20 0.22
c 0.10 0.15 0.20 0.10 0.15 0.18
D1/E1 28.96 29.21 29.46 35.64 36.00 36.36
D2/E2 25.50 BSC 31.50 BSC
e 0.50 BSC 0.50 BSC
F 6.86 7.75 8.64 7.67 7.75 7.83
H 70.00 BSC 70.00 BSC
K 65.90 BSC 65.90 BSC
L1 74.60 75.00 75.40 74.62 75.00 75.38
t 0.38 0.51 0.64
Notes:
1. All dimensions are in millimeters.
2. BSC equals Basic Spacing between Centers. This is a theoretical true position dimension and so has no tolerance.
54SX Family FPGAs RadTolerant and HiRel
37
List of Changes
The following table lists critical changes that were made in the current version of the document.
Previous version Changes in current version (Preliminary v 1.5.1 (web-only)) Page
Preliminary v1.5
Power up and down sequencing information was modified: damage to the device is
possible when 3.3V is powered up first and when 5.0V is powered down first. 13
The last line of equation 2 was cut off in the previous version. It has been replaced in
the existing version. 14
38
54SX Family FPGAs RadTolerant and HiRel
39
Actel and the Actel logo are registered trademarks of Actel Corporation.
All other trademarks are the property of their owners.
http://www.actel.com
Actel Europe Ltd.
Daneshill House, Lutyens Close
Basingstoke, Hampshire RG24 8AG
United Kingdom
Tel: +44-(0)125-630-5600
Fax: +44-(0)125-635-5420
Actel Corporation
955 East Arques Avenue
Sunnyvale, California 94086
USA
Tel: (408) 739-1010
Fax: (408) 739-1540
Actel Asia-Pacific
EXOS Ebisu Bldg. 4F
1-24-14 Ebisu Shibuya-ku
Tokyo 150 Japan
Tel: +81-(0)3-3445-7671
Fax: +81-90)3-3445-7668
5172141-7/10.00
