TOSHIBA THLY6416G1FG-75,-75L,-80,-80L ABSOLUTE MAXIMUM _ RATINGS SYMBOL ITEM RATING UNIT NOTES Vin Input Voltage -0.3~Vpp + 0.3 Vv 1 Vout Output Valtage -0.3~Vpp + 0.3 Vv 1 Vpp Power Supply Voltage -0.3~46 Vv 1 Topr Operating Temperature 0~ 70 c 1 Tst Storage Temperature -55~ 125 C 1 Pp Power Dissipation 2.4 Ww 1 lout Short-Circuit Output Current 50 mA 1 RECOMMENDED DC OPERATING CONDITIONS (Ta = 0 ~ 70C) SYMBOL PARAMETER MIN TYP. MAX UNIT NOTES Vopp Supply Voltage 3.0 3.3 3.6 Vv 2 Vin LVTTL Input High Voltage 2.0 - Vop + 0.3 V 2 VIL LVTTL Input Low Voltage -0.3 - 0.8 Vv 2 CAPACITANCE (Vpp = 3.3 V,f = 1MHz, Ta = 0 ~ 70C) SYMBOL PARAMETER MIN MAX UNIT CC) Input Capacitance (AO ~A11, BAO, BA1) - TBD pF CG Input Capacitance (RAS, CAS, WE) - TBD pF C3 Input Capacitance (CLKO, CLK1) - TBD pF Ca Input Capacitance (CSO, C51) - TBD pF Cs Input Capacitance (DQMBO ~ DQMB7) - TBD pF Cog \/O Capacitance (DQO0 ~ DQ63) - TBD pF 2000-07-14 4/13TOSHIBA THLY6416G1FG-75,-75L,-80,-80L DC CHARACTERISTICS (Vpp = 3.3V + 0.3V, Ta = 0 ~ 70C) -75/-75L -80/-80L SYMBOL ITEM UNIT | NOTES MIN MAX MIN MAX OPERATING CURRENT Active-Precharge Command Cycling . leet without Burst Operation 1-Bank Operation - 520 - 480 mA 3,5 (tex = trac min) loco | STANDBY CURRENT CKE = Viy - | 36 | - | 320 (tck = min, CS = Vin, mA 3 Vine = Vin (min) / Vi, (max) CKE = Vy IccaP__| Bank: Inactive State) (Power-Down Mode) - 8 - 8 STANDBY CURRENT lccas (CLK = Vi_, CS = Vin, CKE = Vin _ 80 _ 80 oa Vint = Vin (min) /V\_ (max) CKE = Vi, lcc2zps_ | Bank: Inactive State) (Power-Down Mode) 7 8 - 8 lccz__ | NO OPERATING CURRENT CKE = Viy - 400 - 360 (tcc = min, CS = Viq (min) CKEZV mA 3 Icc3p_ | Bank: Active State (4 Banks)) (Power-Down Mode) - 60 - 60 BURST OPERATING CURRENT leca _ . . . - 640 - 600 mA | 3,4,5 (tex = min, CS = Vjy (min) Read/Write Command Cycling) AUTO-REFRESH CURRENT lecs ; ; - 1520 - 1440 | mA 3,5 (tex = min, Auto-Refresh Command Cycling) SELF-REFRESH CURRENT THLY6416G 1FG-75,-80 - 16 - 16 cc6 | (Self-Refresh Mode, CKE = 0.2V mA 3 (Self-Refresh Mode, =02V) |ruLyeai6G1FG-75L,80L | 6.4 - 6.4 INPUT LEAKAGE CURRENT (OV = Vin S Vpp, All Other Pins Not under Test = 0 V) OUTPUT LEAKAGE CURRENT (Dour Is Disabled, 0 V = Vout = Vpp) OUTPUT LEVEL Vou 2.4 - 24 - Vv LVTTL Output H-Level Voltage (lout = 2 mA) OUTPUT LEVEL VoL - 0.4 - 0.4 Vv LVTTL Output L-Level Voltage (loyt = 2 mA) 2000-07-14 5/13TOSHIBA THLY6416G1FG-75,-75L,-80,-80L TENTATIVE TOSHIBA HYBRID DIGITAL INTEGRATED CIRCUIT 16,777,216-WORD BY 64-BIT SYNCHRONOUS DRAM MODULE DESCRIPTION The THLY6416G1FG is a 16,777,216-word by 64-bit synchronous dynamic RAM module consisting of eight TC59SM716FT/FTL DRAMs on a printed circuit board. FEATURES @ 16,777,216-word by 64-bit organization Single power supply of 3.3V 40.3V @ Pipeline architecture -75/-75L |-80/-80L | @ Auto-Refresh and Self-Refresh capability tex Clock Cycle Time (CL = 3) 7.5ns | 10ns | @ All inputs and outputs LVTTL-compatible tras Active-to-Precharge Command e 4096 Refresh cycles per 64ms FAS oeriod (min) 45ns | 48ns | @ Package: 144-pin small-outline DIMM - = (gold contacts) tac Access Time from CLK (CL = 3) 54ns | 68 | 75 751: Based on PC133 SDRAM Unbuffered tec RetiActiverto-Refiactive 65ns | 68ns SO-DIMM Design Specification Rev. 0.01 Command Period (min) e -80,-80L: Based on Intel PC100 SOD Rev.1.0 PIN ASSIGNMENT (TOP VIEW) PIN NAMES FRONT S BAO, BAI Bank Select ~ Data In o1 59. 61 1430 Se IS Eh TOT) LOTT rite Enable ~ B7 CLKO, CLK1 Clock In 1 E I / PD Power (+3.3 Ground BACK 37 Al 1 4 11 45| VDD 47| DQ12 000707EBA2 @ TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the Handling Guide for Semiconductor Devices, or TOSHIBA Semiconductor Reliability Handbook etc.. @ The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (Unintended Usage). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. @ The products described in this document are subject to the foreign exchange and foreign trade laws. @ The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION far any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. @ The information contained herein is subject to change without notice. 2000-07-14 1/13TOSHIBA THLY6416G1FG-75,-75L,-80,-80L SERIAL PRESENCE DETECT Byte -751-75L -80 /-80L Number Function Entry Value Entry Entry Value Entry 0 PRetnes eras oh imormatn winter imeseral | szetye aon | raperes | eon 1 Total # of Bytes in SPD Memory Device 256 bytes 08h 256 bytes 08h 2 (PPM EDO. SDRAM) frome Appendix A SDRAM 04h SDRAM 04h 3 # of Raw Addresses on this Assembly RAO ~ RA11 0Ch RAO ~ RA11 0Ch 4 # of Column Addresses on this Assembly CAO ~ CAB 09h CAO ~ CAB 09h 5 # of Module Banks on this Assembly 2 Bank 02h 2 Bank 02h 6 Data Width of this Assembly... x64 40h x64 40h 7 ..Data Width Continuation x64 00h x64 00h 8 Voltage Interface Standard of this Assembly LVTTL Oth LVTTL Oth 9 ean wee Time at Max. Supported CAS Latency (CL), CL =3, 7.505 75h CL = 3, 8.0ns 80h 10 SDRAM Access from Clock @ CL = X CL = 3, 5-4ns 54h CL = 3, 6.0 ns 60h 11 DIMM Configuration Type (Non-parity, Parity, ECC) Non-Parity 00h Non-Parity 00h 12 Refresh Rate/Type seiner 80h suitor ch 80h 13 SDRAM Width, Primary DRAM x16 10h x16 10h 14 Error Checking SDRAM Data Width NA 00h NA 00h 15 mn Clock Delay, Back-to-Back Random Column 1CLK Oth 1cLK Oth 16 Burst Lengths Supported Full pege 8Fh Full pege 8Fh 17 # of Banks on Each SDRAM Device 4 Banks 04h 4 Banks 04h 18 CAS # Latencies Supported 2,3 06h 2,3 06h 19 CS # Latency Oth Oth 20 WE # Latency Oth Oth 21 SDRAM Module Attributes Unbuffered 00h 00h 22 SDRAM Device Attributes: General OEh OEh 23 Minimum Clock Cycle Time @ CL- X-1 CL = 2, 10 ns AOh CL = 2, 10ns AOh 24 Maximum Data Access Time from Clock @ CL X-1 CL = 2, 6.0ns 60h CL = 2, 6.0ns 60h 25 Minimum Clock Cycle Time @ CL X-2 00h 00h 26 Maximum Data Access Time from Clock @ CL X-2 00h 00h 27 Minimum Row Precharge Time 20 ns 14h 20 ns 14h 28 Minimum Row-Active-ta-Row-Active Delay 15 ns OFh 20 ns 14h 29 Minimum RAS-to-CAS Delay 20 ns 14h 20 ns 14h 30 Minimum RAS Pulse Width 45 ns 2Dh 48 ns 30h 31 Module/Bank Density 64 MB 10h 64 MB 10h 32 Command & Address Signal Input Setup Time 1.5ns 15h 2ns 20h 33 Command & Address Signal Input Hald Time Ins 08h Ins 10h 34 Data Signal Input Setup Time 1.5ns 15h 2ns 20h 35 Data Signal Input Hold Time Ins 08h Ins 10h 36-61 Superset Information (may be used in future) 00h FFh 62 SPD Revision Intel 1.2B 12h Intel 1.2B 12h 63 Check sum for bytes 0 ~ 62 O4A7h A7h 1ED2h D2h OPTIONAL 64 72 Manufacturers JEDEC ID Code (JEP-106E) Place of Manufacture Manufacturer's Part Number Revision Cade Date of Manufacture Serial Number Manufacturer- Data Reserved Reserved Intel Specification Intel Specification 2000-07-14 2/13TOSHIBA THLY6416G1FG-75,-75L,-80,-80L BLOCK DIAGRAM CKEO cso CKE1 $ L>Qm - pameo & LDQM LK CLK c vo. FAW veo WF vol ICKE| M1 vos F-W-2 paz OWA 1/08 M5 'CKE! IRAS| UDQM /- DQMB1 o UDQM | RAS! Bite vaa FW-2 pgs O-W-7_ 1109 ICAS!I le | ne ~ ao 1WE ! AO ~ A11, BSO, BS1 vo1e LEW Dols WH vote AO A11, B50, BS1 We! L>QM -> pamp2 o LDQM LK CLK c vor. FAW spate WF vot ICKE! M2 vos F-W- 0q23, OW 1/08 M6 ICKE! IRAS! UDQM - DQMB3 UDQM | RAS! CLKO o TCAs! vo9 F-Wi-2 pg2a HYWW-_ 1109 CAS! | | bo CLK1 io | ne ~ | wel WE | AO ~ A11,BS0, BS1 voie AM DQ31 WAV] vo16 AO A11,BS0, BS11 Wet LDQM - pamps o LDQM LK CLK c vor FAM? 032 WW 01 ICKE! M3 vos F-W- a39.- OW 1/08 M7 TCKE! 'RAS| UDQM [- DQMB5 0 UDQM | RAS! li cas! vas FW aa OM a9 lcas!| 7 Loe | ee ; ~ | wel \WE | AO ~ A11, BSO, BS1 voig LEW boa7 MW) vo16 A0 ~ A11, BSO, BS1! We! LDQM - Dames LDQM LK CLK c vor FAW peas. OWA 1/01 ICKE! M4 vos FW-2 pass = OWA 1/08 Ms 'CKE! IRAS| UDQM /- DQMB7 0 UDQM | RAS! Ti cas! vas F:W-2vass = OM] 1109 lcasi!| 7 1 7 1 ' : ' : ' ~ pas! \WE | AO A11,BSO, BS1 vo1e LEW bQ63 Ve voig A11, BSO, BS1 | WE! /RAS, ICAS, WE Oo A0~A11, BAO, BA1 Vpp Mi~M8& Vopp @ E2PROM x ci~c8 Fc9~c16= C17~C24 t C25 Vss go 4 I 1 Mi~mg VSS 0 + E2PROM 2 scLo|sc. F?7PROM spat . cpa AO Al A2 WC LTT 777 2000-07-14 3/13TOSHIBA THLY6416G1FG-75,-75L,-80,-80L AC CHARACTERISTICS AND OPERATING CONDITIONS (Vpp = 3.3V + 0.3V, Ta = 0 ~ 70C) (Notes 6, 7, 11) SYMBOL PARAMETER Bit 807-801 UNIT | NOTES MIN MAX MIN MAX tre Ref/Active-Ref/Active Command Period 65 68 tras Active- Precharge Command Period 45 100000 48 100000 ns treo Active-Read/Write Command Delay Time 20 20 9 tee Read/Write(a) -Read/Write(b) 1 1 cycles Command Period trp Precharge-Active Command Period 20 20 trrp Active(a)-Active(b) Command Period 15 20 twr Write Recovery Time cL* =2 10 10 CL* = 3 7.5 8 teK CLK Cycle Time CL* = 2 10 1000 10 1000 CL* = 3 7.5 1000 8 1000 ty CLK High-Level Width 2.5 3 10 te. CLK Low-Level Width 2.5 3 tac Access Time from CLK CL* = 2 6 6 CL* = 3 5.4 6 tou Output Data Hold Time 2.7 3 tuz Output Data High-Ilmpedance Time 2.7 7.5 3 8 8 tiz Output Data Low-Impedance Time 0 0 ns tsp Power-Down Made Entry Time 0 7.5 0 8 tr Transition Time of CLK (Rise and Fall) 0.5 10 0.5 10 tos Data-In Set-up Time 1.5 2 tou Data-In Hold Time 0.8 1 tas Address Set-up Time 1.5 2 taH Address Hold Time 0.8 1 teks CKE Set-up Time 1.5 2 teKH CKE Hold Time 0.8 1 tems Cammand Set-up Time 1.5 2 tomy Command Hold Time 0.8 1 trer Refresh Time 64 64 ms trsc Mode Register Set Cycle Time 16 16 ns 9 * CL is CAS latency. 2000-07-14 6/13TOSHIBA THLY6416G1FG-75,-75L,-80,-80L NOTES: 1. Conditions outside the limits listed under Absolute Maximum Ratings may cause permanent damage to the device. 2. All voltages are referenced to Vss. 3. These parameters depend on the cycle rate and their values are measured at the cycle rate obtained using the minimum values of tcx andtrc. Input signals are changed once during tcK. 4. These parameters depend on the output loading. The specified values are obtained with the output open. 5. These valves are measured with the following conditions. Front side (or back side) : the measuring condtions on the data sheet Back side (or front side) : Stand by (measured with Icce conditions) 6. AC TEST CONDITIONS Reference Level for Output Signals 1AV/1.4AV Output Load See the diagram for AC Test Load (B) below Input Signal Levels 2.4V/0.4V Transition Time (Rise and Fall) of Input Signals 2ns Reference Level of Input Signals 1.4V 3.3V 1.4V 1.2kO q, 2 Output Output T 50 pF 8700 T 50 pF S77 a 7/7 AC Test Load (A) AC Test Load (B) 7. Transition times are measured between the Vi and Viz levels. The transition (rise and fall) of input signals has a fixed slope. 8. tyz defines the time at which the outputs go open circuit and are not reference levels. 9. These parameters are specified for a given number of clock cycles and a given operating frequency. The celation-ship between the number of clock cycles, the timing value and the frequency (a clock period) is as follows: number of clock cycles = specified timing value/clock period (Fractions are rounded up to a whole number. 2000-07-14 7/13TOSHIBA THLY6416G1FG-75,-75L,-80,-80L 10. tcH is the pulse width of CLK measured from the positive edge to the negative edge and referenced to Vyy (min). tcy is the pulse width of CLK measured from the negative edge to the positive edge and referenced to Viz (max). 11. Power-up Sequence Power-up must be performed in the following sequence. 1) Power must be applied to Vpp and VppQ (simultaneously) with all input signals heldin the NOP state. The CLK signal must be started at the same time as power is applied. 2) After power-up a pause of at least 200 useconds is required. Then, DQMB and CKE must be held High (at the Vcc level) to ensure that the DQ output is High-impedance. 3) Both banks must be precharged. 4) The Mode Register Set command must be asserted to initialize the Mode register. 5) An Auto-Refresh operation, consisting of at least eight Auto-Refresh cycles, must be performed. The order in which 4) and 5) are performed is interchangeable. 2000-07-14 8/13TOSHIBA THLY6416G1FG-75,-75L,-80,-80L TIMING DIAGRAMS READ TIMING Read CAS Latency ef \S VWF Wp Lp VS C50 (CS1) was 7] CAS YW 7 AO~AI1 BAO, BA1 teac tac tac _| tuz A ti ton ton DQO-63 VALID VALID A DATA QUT DATA OUT y Read Command I | sdhas Burst Length 2000-07-14 9/13TOSHIBA THLY6416G1FG-75,-75L,-80,-80L COMMAND INPUT TIMING tek tet toy CLKO Viy HE (CLK1) Vi _ \ i \_ \ cf \_F \ \ f tr tr tems. | tomy tomy te CS0 a} (C51) | J Yi te tomy ws ZZ. te tomy te tomy ( v A tas tay AO ~ A111 A BAO, BA1 Vii) a teks} tcKH teks} tcKH teks teKH y \ as KA +A i \ I 4 2000-07-14 10/13TOSHIBA THLY6416G1FG-75,-75L,-80,-80L CONTROL TIMING FOR INPUT DATA (Word Mask) ao_f \_f \+f Ff Ly tomy tems | tcmy tems < <S| DQMBO y \ ~ DQMB7 L_] \ T tos} ton tos} ton tps} toy tps | tpn (Clock Mask) [<__| |_| VALID VALID VALID VALID DQ0 ~ DQ63 DATA IN DATA IN DATA IN DATA IN CLKO (CLK1) } teKH teks | tcKH teks <> CKE _ y \_K l tos} tpH tps | tpy tps} toy tps] tpy ed | <> |~<_>] f<>}~<___>} ee |__| VALID VALID VALID VALID DQd ~ DQ63 A DATA IN VY DATA IN V7 Hp DATA IN VK DATA IN IK CONTROL TIMING FOR OUTPUT DATA (Output Enable) cx) __ FN F VF VF LL tcMH tems} tcmH tems < _ paw yy tac _, ty | Z | tac tou \ ton _| tiz VALID VALID DATA OUT DATA OUT OPEN (Clock Mask) tac tou ' CLKO (CLK1) j tcKH teks | tekH teks << ck i tf tac \ tou \ tou | toH tou VALID VALID DQO ~ DQ63 DATA OUT VALID DATA OUT DATA OUT DQO ~ DQ63 cr fo 2000-07-14TOSHI BA THLY6416G1FG-75,-75L,-80,-80L MODE REGISTER SET CYCLE CLKO (CLK1) j tems} temH G0 (CS1) ao trsc "IT was 7 tems} tomy A / tems| tomy cs Soe VW tems} tcmH WE YH; i tas tay <] A0~ All : BAO, BAI Set Register Data Next Command AO Burst A2 Al uential Interleaved A1 | Burst Length fe 71 0 __o 1 1 A? 0 0 2 0 1 4 A3 | Addressing Mode 0 | 8 1 0 A4 1 0 Reserved CAS L 1 7 Reserved AS atency 1 1 Full A6 A3 Addressing Mode A7 | 0 | (Test Mode) 0 Sequential 1 Interleaved A8 | 0 Reserved CAS AIS Write Mode Reserved Reserved A10| 0 2 BAO] o Reserved 3 4 BA1]| 0 . AQ Single Write Mode 0 Burst Read and Burst Write Burst Read and Single Write 2000-07-14 12/13TOSHIBA THLY6416G1FG-75,-75L,-80,-80L PACKAGE DIMENSIONS (THLY6416G1FG) Unit: mm FRONT >|_< 3:80 max _ - | _ c s| |= aL oOo in $i 2 S . oo] co] o N st - |e e}e ae lol +t] w ~ 3.30 40.13 | 23.20 4.60 32.80 | | 1.00 +0.10 2.00 + 0.13 63.60 REF 2-@ 1.80 BACK 3.70 + 0.13 nn | oT | 2.10 Oo ea a eee i mo Oe Oo a | i CONTACT DIMENSIONS @THLY6416G1FG \ Full R ' u I he, ! FRONT ; | | | tT c Fi i x = 1 E S E I in m . N i + i 0.600.051 | 1.50+0.10 ; 0.80 I 2.50 I 4.60 Contacts: gold Weight : 8.6g (typ.) 2000-07-14 13/13