CY7C2562XV18/CY7C2564XV18
72-Mbit QDR® II+ Xtreme SRAM Two-Word
Burst Architecture (2.5 Cycle Read Latency) with ODT
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 001-70204 Rev. *F Revised May 12, 2016
72-Mbit QDR® II+ Xtre me SRAM Two-Word Burst Architecture (2 .5 Cycle Read Latency) with ODT
Features
■Separate independent read and write data ports
❐Supports concurrent transactions
■450 MHz clock for high bandwidth
■Two-word burst for reducing address bus frequency
■Double data rate (DDR) interfaces on both read and write ports
(data transferred at 900 MHz) at 450 MHz
■Available in 2.5 clock cycle latency
■Two input clocks (K and K) for precise DDR timing
❐SRAM uses rising edges only
■Echo clocks (CQ and CQ) simplify data capture in high-speed
systems
■Data valid pin (QVLD) to indicate valid data on the output
■On-Die Termination (ODT) feature
❐Supported for D[x:0], BWS[x:0], and K/K inputs
■Single multiplexed address input bus latches address inputs
for both read and write ports
■Separate port selects for depth expansion
■Synchronous internally self-timed writes
■QDR™-II+ Xtreme operates with 2.5 cycle read latency when
DOFF is asserted HIGH
■Operates similar to QDR I device with 1 cycle read latency when
DOFF is asserted LOW
■Available in × 18, and × 36 configurations
■Full data coherency, providing most current data
■Core VDD = 1.8 V ± 0.1 V; VDDQ = 1.4 V to 1.6 V
❐Supports 1.5 V I/O supply
■HSTL inputs and variable drive HSTL output buffers
■Available in 165-ball FBGA package (13 × 15 × 1.4 mm)
■CY7C2564XV18 offered in both Pb-free and non Pb-free
packages and CY7C2562XV18 offered in Pb-free package
only.
■JTAG 1149.1 compatible test access port
■Phase-locked loop (PLL) for accurate data placement
Configurations
With Read Cycle Latency of 2.5 cycles:
CY7C2562XV18 – 4M × 18
CY7C2564XV18 – 2M × 36
Functional Description
The CY7C2562XV18 and CY7C2564XV18 are 1.8 V
Synchronous Pipelined SRAMs, equipped with QDR™-II+
architecture. Similar to QDR II architecture, QDR II+ architecture
consists of two separate ports: the read port and the write port to
access the memory array. The read port has dedicated data
outputs to support read operations and the write port has
dedicated data inputs to support write operations. QDR II+
architecture has separate data inputs and data outputs to
completely eliminate the need to “turnaround” the data bus that
exists with common devices. Access to each port is through a
common address bus. Addresses for read and write addresses
are latched on alternate rising edges of the input (K) clock.
Accesses to the QDR II+ read and write ports are completely
independent of one another. To maximize data throughput, both
read and write ports are equipped with DDR interfaces. Each
address location is associated with two 18-bit words
(CY7C2562XV18), or 36-bit words (CY7C2564XV18) that burst
sequentially into or out of the device. Because data can be
transferred into and out of the device on every rising edge of both
input clocks (K and K), memory bandwidth is maximized while
simplifying system design by eliminating bus “turnarounds”.
These devices have an on-die termination (ODT) feature
supported for D[x:0], BWS[x:0], and K/K inputs, which helps
eliminate external termination resistors, reduce cost, reduce
board area, and simplify board routing.
Depth expansion is accomplished with port selects, which
enables each port to operate independently.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the K or K input clocks. Writes are
conducted with on-chip synchronous self-timed write circuitry.
For a complete list of related documentation, click here.
Selection Guide
Description 450 MHz 366 MHz Unit
Maximum Operating Frequency 450 366 MHz
Maximum Operating Current × 18 1205 970 mA
× 36 1445 1165
CY7C2562XV18/CY7C2564XV18
Document Number: 001-70204 Rev. *F Page 2 of 29
Logic Block Diagram – CY7C2562XV18
Logic Block Diagram – CY7C2564XV18
2M x 18 Array
CLK
A(20:0)
Gen.
K
K
Control
Logic
Address
Register
D[17:0]
Read Add. Decode
Read Data Reg.
RPS
WPS
Control
Logic
Address
Register
Reg.
Reg.
Reg.
18
21
36
18
BWS[1:0]
VREF
Write Add. Decode
Write
Reg
18
A(20:0)
21
CQ
CQ
DOFF
Q[17:0]
18
18
Write
Reg
2M x 18 Array
18
QVLD
1M x 36 Array
CLK
A(19:0)
Gen.
K
K
Control
Logic
Address
Register
D[35:0]
Read Add. Decode
Read Data Reg.
RPS
WPS
Control
Logic
Address
Register
Reg.
Reg.
Reg.
36
20
72
36
BWS[3:0]
VREF
Write Add. Decode
Write
Reg
36
A(19:0)
20
CQ
CQ
DOFF
Q[35:0]
36
36
Write
Reg
1M x 36 Array
36
QVLD
CY7C2562XV18/CY7C2564XV18
Document Number: 001-70204 Rev. *F Page 3 of 29
Contents
Pin Configurations ...........................................................4
Pin Definitions ..................................................................5
Functional Overview ........................................................6
Read Operations ......................................................... 6
Write Operations ......................................................... 7
Byte Write Operations ................................................. 7
Concurrent Transactions ............................................. 7
Depth Expansion .........................................................7
Programmable Impedance .......................................... 7
Echo Clocks ................................................................ 7
Valid Data Indicator (QVLD) ........................................ 7
On-Die Termination (ODT) .......................................... 7
PLL ..............................................................................7
Application Example ........................................................8
Truth Table ........................................................................ 9
Write Cycle Descriptions .................................................9
Write Cycle Descriptions ...............................................10
IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 11
Disabling the JTAG Feature ......................................11
Test Access Port .......................................................11
Performing a TAP Reset ...........................................11
TAP Registers ........................................................... 11
TAP Instruction Set ...................................................11
TAP Controller State Diagram .......................................13
TAP Controller Block Diagram ......................................14
TAP Electrical Characteristics ...................................... 14
TAP AC Switching Characteristics ...............................15
TAP Timing and Test Conditions .................................. 16
Identification Register Definitions ................................ 17
Scan Register Sizes .......................................................17
Instruction Codes ........................................................... 17
Boundary Scan Order .................................................... 18
Power Up Sequence in QDR II+ Xtreme SRAM ............ 19
Power Up Sequence ................................................. 19
PLL Constraints ......................................................... 19
Maximum Ratings ........................................................... 20
Operating Range ............................................................. 20
Neutron Soft Error Immunity ......................................... 20
Electrical Characteristics ............................................... 20
DC Electrical Characteristics ..................................... 20
AC Electrical Characteristics ..................................... 21
Capacitance .................................................................... 22
Thermal Resistance ........................................................ 22
AC Test Loads and Waveforms ..................................... 22
Switching Characteristics .............................................. 23
Switching Waveforms .................................................... 24
Read/Write/Deselect Sequence ................................ 24
Ordering Information ...................................................... 25
Ordering Code Definitions ......................................... 25
Package Diagram ............................................................ 26
Acronyms ........................................................................ 27
Document Conventions ................................................. 27
Units of Measure ....................................................... 27
Document History Page ................................................. 28
Sales, Solutions, and Legal Information ...................... 29
Worldwide Sales and Design Support ....................... 29
Products .................................................................... 29
PSoC® Solutions ...................................................... 29
Cypress Developer Community ................................. 29
Technical Support ..................................................... 29
CY7C2562XV18/CY7C2564XV18
Document Number: 001-70204 Rev. *F Page 4 of 29
Pin Configurations
The pin configuration for CY7C2562XV18 and CY7C2564XV18 follow. [1]
Figure 1. 165-ball FBGA (13 × 15 × 1.4 mm) pinout
CY7C2562XV18 (4M × 18)
12345678910 11
ACQ NC/144M A WPS BWS1KNC/288M RPS AACQ
BNC Q9 D9 A NC K BWS0ANCNCQ8
CNC NC D10 VSS AAAV
SS NC Q7 D8
DNC D11 Q10 VSS VSS VSS VSS VSS NC NC D7
ENC NC Q11 VDDQ VSS VSS VSS VDDQ NC D6 Q6
FNC Q12 D12 VDDQ VDD VSS VDD VDDQ NC NC Q5
GNC D13 Q13 VDDQ VDD VSS VDD VDDQ NC NC D5
HDOFF VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ
JNC NC D14 VDDQ VDD VSS VDD VDDQ NC Q4 D4
KNC NC Q14 VDDQ VDD VSS VDD VDDQ NC D3 Q3
LNC Q15 D15 VDDQ VSS VSS VSS VDDQ NC NC Q2
MNC NC D16 VSS VSS VSS VSS VSS NC Q1 D2
NNC D17 Q16 VSS AAAV
SS NC NC D1
PNC NC Q17 A A QVLD A A NC D0 Q0
RTDOTCKAAAODTAAATMSTDI
CY7C2564XV18 (2M × 36)
12345678910 11
ACQ NC/288M A WPS BWS2KBWS1RPS A NC/144M CQ
BQ27 Q18 D18 A BWS3KBWS
0AD17Q17Q8
CD27 Q28 D19 VSS AAAV
SS D16 Q7 D8
DD28 D20 Q19 VSS VSS VSS VSS VSS Q16 D15 D7
EQ29 D29 Q20 VDDQ VSS VSS VSS VDDQ Q15 D6 Q6
FQ30 Q21 D21 VDDQ VDD VSS VDD VDDQ D14 Q14 Q5
GD30 D22 Q22 VDDQ VDD VSS VDD VDDQ Q13 D13 D5
HDOFF VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ
JD31 Q31 D23 VDDQ VDD VSS VDD VDDQ D12 Q4 D4
KQ32 D32 Q23 VDDQ VDD VSS VDD VDDQ Q12 D3 Q3
LQ33 Q24 D24 VDDQ VSS VSS VSS VDDQ D11 Q11 Q2
MD33 Q34 D25 VSS VSS VSS VSS VSS D10 Q1 D2
ND34 D26 Q25 VSS AAAV
SS Q10 D9 D1
PQ35 D35 Q26 A A QVLD A A Q9 D0 Q0
RTDOTCKAAAODTAAATMSTDI
Note
1. NC/144M and NC/288M are not connected to the die and can be tied to any voltage level.
CY7C2562XV18/CY7C2564XV18
Document Number: 001-70204 Rev. *F Page 5 of 29
Pin Definitions
Pin Name I/O Pin Description
D[x:0] Input-
Synchronous
Data Input Signals. Sampled on the rising edge of K and K clocks during valid write operations.
CY7C2562XV18 D[17:0]
CY7C2564XV18 D[35:0]
WPS Input-
Synchronous
Write Port Select Active LOW. Sampled on the rising edge of the K clock. When asserted active, a
write operation is initiated. Deasserting deselects the write port. Deselecting the write port ignores D[x:0].
BWS0,
BWS1,
BWS2,
BWS3
Input-
Synchronous
Byte Write Select 0, 1, 2, and 3 Active LOW. Sampled on the rising edge of the K and K clocks during
write operations. Used to select which byte is written into the device during the current portion of the
write operations. Bytes not written remain unaltered.
CY7C2562XV18 BWS0 controls D[8:0] and BWS1 controls D[17:9].
CY7C2564XV18 BWS0 controls D[8:0], BWS1 controls D[17:9], BWS2 controls D[26:18] and BWS3
controls D[35:27].
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select
ignores the corresponding byte of data and it is not written into the device.
A Input-
Synchronous
Address Inputs. Sampled on the rising edge of the K (read address) and K (write address) clocks during
active read and write operations. These address inputs are multiplexed for both read and write
operations. Internally, the device is organized as 4M × 18 (2 arrays each of 2M × 18) for CY7C2562XV18,
and 2M × 36 (2 arrays each of 1M × 36) for CY7C2564XV18. Therefore, only 21 address inputs are
needed to access the entire memory array for CY7C2562XV18, and 20 address inputs for
CY7C2564XV18. These inputs are ignored when the appropriate port is deselected. The Address pins
(A) can be assigned any bit order.
Q[x:0] Output-
Synchronous
Data Output Signals. These pins drive out the requested data during a read operation. Valid data is
driven out on the rising edge of the K and K clocks during read operations. When the read port is
deselected, Q[x:0] are automatically tristated.
CY7C2562XV18 Q[17:0]
CY7C2564XV18 Q[35:0]
RPS Input-
Synchronous
Read Port Select Active LOW. Sampled on the rising edge of positive input clock (K). When active,
a read operation is initiated. Deasserting deselects the read port. When deselected, the pending access
is allowed to complete and the output drivers are automatically tristated following the next rising edge of
the K clock. Each read access consists of a burst of two sequential transfers.
QVLD Valid output
indicator
Valid Output Indicator. The Q Valid indicates valid output data. QVLD is edge aligned with CQ and CQ.
ODT [2] On-Die
Termination
input pin
On-Die Termination Input. This pin is used for on-die termination (ODT) of the input signals. ODT range
selection is made during power up initialization. A LOW on this pin selects a low range that follows
RQ/3.33 for 175 < RQ < 350(where RQ is the resistor tied to ZQ pin)A HIGH on this pin selects a
high range that follows RQ/1.66 for 175 < RQ < 250 (where RQ is the resistor tied to ZQ pin). When
left floating, a high range termination value is selected by default.
K Input Clock Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device
and to drive out data through Q[x:0]. All accesses are initiated on the rising edge of K.
KInput Clock Negative Input Clock Input. K is used to capture synchronous inputs being presented to the device
and to drive out data through Q[x:0].
CQ Echo Clock Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the input clock
(K) of the QDR II+. The timing for the echo clocks is shown in Switching Characteristics on page 23.
CQ Echo Clock Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the input clock
(K) of the QDR II+. The timing for the echo clocks is shown in the Switching Characteristics on page 23.
Note
2. On-die termination (ODT) feature is supported for D[x:0], BWS[x:0], and K/K inputs.
CY7C2562XV18/CY7C2564XV18
Document Number: 001-70204 Rev. *F Page 6 of 29
Functional Overview
The CY7C2562XV18, and CY7C2564XV18 are synchronous
pipelined Burst SRAMs equipped with a read port and a write
port. The read port is dedicated to read operations and the write
port is dedicated to write operations. Data flows into the SRAM
through the write port and flows out through the read port. These
devices multiplex the address inputs to minimize the number of
address pins required. By having separate read and write ports,
the QDR II+ completely eliminates the need to “turn around” the
data bus and avoids any possible data contention, thereby
simplifying system design. Each access consists of two 18-bit
data transfers in the case of CY7C2562XV18, and two 36-bit
data transfers in the case of CY7C2564XV18 in one clock cycle.
These devices operate with a read latency of two and half cycles
when DOFF pin is tied HIGH. When DOFF pin is set LOW or
connected to VSS then the device behaves in QDR I mode with
a read latency of one clock cycle.
Accesses for both ports are initiated on the rising edge of the
positive input clock (K). All synchronous input and output timing
are referenced from the rising edge of the input clocks (K and K).
All synchronous data inputs (D[x:0]) pass through input registers
controlled by the input clocks (K and K). All synchronous data
outputs (Q[x:0]) pass through output registers controlled by the
rising edge of the input clocks (K and K) as well.
All synchronous control (RPS, WPS, BWS[x:0]) inputs pass
through input registers controlled by the rising edge of the input
clocks (K and K).
CY7C2562XV18 is described in the following sections. The
same basic descriptions apply to CY7C2564XV18.
Read Operations
The CY7C2562XV18 is organized internally as two arrays of
2M × 18. Accesses are completed in a burst of two sequential
18-bit data words. Read operations are initiated by asserting
RPS active at the rising edge of the positive input clock (K). The
address is latched on the rising edge of the K clock. The address
presented to the address inputs is stored in the read address
register. Following the next two K clock rise, the corresponding
lowest order 18-bit word of data is driven onto the Q[17:0] using
K as the output timing reference. On the subsequent rising edge
of K, the next 18-bit data word is driven onto the Q[17:0]. The
requested data is valid 0.45 ns from the rising edge of the input
clock (K and K).
When the read port is deselected, the CY7C2562XV18 first
completes the pending read transactions. Synchronous internal
circuitry automatically tristates the outputs following the next
rising edge of the negative input clock (K). This enables for a
seamless transition between devices without the insertion of wait
states in a depth expanded memory.
ZQ Input Output Impedance Matching Input. This input is used to tune the device outputs to the system data
bus impedance. CQ, CQ, and Q[x:0] output impedance are set to 0.2 × RQ, where RQ is a resistor
connected between ZQ and ground. Alternatively, connect this pin directly to VDDQ, which enables the
minimum impedance mode. This pin cannot be connected directly to GND or left unconnected.
DOFF Input PLL Turn Off Active LOW. Connecting this pin to ground turns off the PLL inside the device. The
timing in the operation with the PLL turned off differs from those listed in this data sheet. For normal
operation, connect this pin to a pull up through a 10 k or less pull up resistor. The device behaves in
QDR I mode when the PLL is turned off. In this mode, the device can be operated at a frequency of up
to 167 MHz with QDR I timing.
TDO Output TDO Pin for JTAG.
TCK Input TCK Pin for JTAG.
TDI Input TDI Pin for JTAG.
TMS Input TMS Pin for JTAG.
NC N/A Not Connected to the Die. Can be tied to any voltage level.
NC/144M Input Not Connected to the Die. Can be tied to any voltage level.
NC/288M Input Not Connected to the Die. Can be tied to any voltage level.
VREF Input-
Reference
Reference Voltage Input. Static input used to set the reference level for HSTL inputs, outputs, and AC
measurement points.
VDD Power Supply Power Supply Inputs to the Core of the Device.
VSS Ground Ground for the Device.
VDDQ Power Supply Power Supply Inputs for the Outputs of the Device.
Pin Definitions (continued)
Pin Name I/O Pin Description
CY7C2562XV18/CY7C2564XV18
Document Number: 001-70204 Rev. *F Page 7 of 29
Write Operations
Write operations are initiated by asserting WPS active at the
rising edge of the positive input clock (K). On the same K clock
rise the data presented to D[17:0] is latched and stored into the
lower 18-bit write data register, provided BWS[1:0] are both
asserted active. On the subsequent rising edge of the negative
input clock (K), the address is latched and the information
presented to D[17:0] is also stored into the write data register,
provided BWS[1:0] are both asserted active. The 36 bits of data
are then written into the memory array at the specified location.
When deselected, the write port ignores all inputs after the
pending write operations have been completed.
Byte Write Operations
Byte write operations are supported by the CY7C2562XV18. A
write operation is initiated as described in the Write Operations
section. The bytes that are written are determined by BWS0 and
BWS1, which are sampled with each set of 18-bit data words.
Asserting the appropriate Byte Write Select input during the data
portion of a write latches the data being presented and writes it
into the device. Deasserting the Byte Write Select input during
the data portion of a write enables the data stored in the device
for that byte to remain unaltered. This feature can be used to
simplify read, modify, or write operations to a byte write
operation.
Concurrent Transactions
The read and write ports on the CY7C2562XV18 operate
completely independently of one another. As each port latches
the address inputs on different clock edges, the user can read or
write to any location, regardless of the transaction on the other
port. The user can start reads and writes in the same clock cycle.
If the ports access the same location at the same time, the SRAM
delivers the most recent information associated with the
specified address location. This includes forwarding data from a
write cycle that was initiated on the previous K clock rise.
Depth Expansion
The CY7C2562XV18 has a port select input for each port. This
enables for easy depth expansion. Both port selects are sampled
on the rising edge of the positive input clock only (K). Each port
select input can deselect the specified port. Deselecting a port
does not affect the other port. All pending transactions (read and
write) are completed before the device is deselected.
Programmable Impedance
An external resistor, RQ, must be connected between the ZQ pin
on the SRAM and VSS to enable the SRAM to adjust its output
driver impedance. The value of RQ must be 5 × the value of the
intended line impedance driven by the SRAM. The allowable
range of RQ to guarantee impedance matching with a tolerance
of ±15% is between 175 and 350 , with VDDQ =1.5V. The
output impedance is adjusted every 1024 cycles upon power up
to account for drifts in supply voltage and temperature.
Echo Clocks
Echo clocks are provided on the QDR II+ to simplify data capture
on high-speed systems. Two echo clocks are generated by the
QDR II+. CQ is referenced with respect to K and CQ is
referenced with respect to K. These are free running clocks and
are synchronized to the input clock of the QDR II+. The timing
for echo clocks is shown in Switching Characteristics on page 23.
Valid Data Indicator (QVLD)
QVLD is provided on the QDR II+ to simplify data capture on high
speed systems. The QVLD is generated by the QDR II+ device
along with data output. This signal is also edge-aligned with the
echo clock and follows the timing of any data pin. This signal is
asserted half a cycle before valid data arrives.
On-Die Termination (ODT)
These devices have an On-Die Termination feature for Data
inputs (D[x:0]), Byte Write Selects (BWS[x:0]), and Input Clocks (K
and K). The termination resistors are integrated within the chip.
The ODT range selection is enabled through ball R6 (ODT pin).
The ODT termination tracks value of RQ where RQ is the resistor
tied to the ZQ pin. ODT range selection is made during power-up
initialization. A LOW on this pin selects a low range that follows
RQ/3.33 for 175 < RQ < 350 (where RQ is the resistor tied
to ZQ pin)A HIGH on this pin selects a high range that follows
RQ/1.66 for 175 < RQ < 250 (where RQ is the resistor tied
to ZQ pin). When left floating, a high range termination value is
selected by default. For a detailed description on the ODT
implementation, refer to the application note, On-Die Termination
for QDRII+/DDRII+ SRAMs.
PLL
These chips use a PLL that is designed to function between
120 MHz and the specified maximum clock frequency. During
power up, when the DOFF is tied HIGH, the PLL is locked after
100 s of stable clock. The PLL can also be reset by slowing or
stopping the input clocks K and K for a minimum of 30 ns.
However, it is not necessary to reset the PLL to lock to the
desired frequency. The PLL automatically locks 100 s after a
stable clock is presented. The PLL may be disabled by applying
ground to the DOFF pin. When the PLL is turned off, the device
behaves in QDR I mode with one cycle latency and a longer
access time). For information, refer to the application note, PLL
Considerations in QDRII/DDRII/QDRII+/DDRII+.
CY7C2562XV18/CY7C2564XV18
Document Number: 001-70204 Rev. *F Page 8 of 29
Application Example
Figure 2 shows two QDR II+ used in an application.
Figure 2. Application Example (Width Expansion)
D[x:0]
ARPSWPS BWS KK
Q[x:0]
ZQ
SRAM#1 CQ/CQ
D[x:0]
ARPSWPS BWS KK
Q[x:0]
ZQ
SRAM#2 CQ/CQ
DATA IN[2x:0]
DATA OUT [2x:0]
ADDRESS
RPS
WPS
BWS
CLKIN1/CLKIN1
CLKIN2/CLKIN2
SOURCE K
SOURCE K
FPGA / ASIC
RQ RQ
CY7C2562XV18/CY7C2564XV18
Document Number: 001-70204 Rev. *F Page 9 of 29
Truth Table
The truth table for CY7C2562XV18, and CY7C2564XV18 follow. [3, 4, 5, 6, 7, 8]
Operation KRPS WPS DQ DQ
Write Cycle:
Load address on the rising edge of K;
input write data on K and K rising edges.
L–H X L D(A) at K(t) D(A + 1) at K(t)
Read Cycle: (2.5 cycle Latency)
Load address on the rising edge of K;
wait two and half cycles; read data on K and K rising edges.
L–H L X Q(A) at K(t + 2) Q(A + 1) at K(t + 3)
NOP: No Operation L–H H H D = X
Q = High Z
D = X
Q = High Z
Standby: Clock Stopped Stopped X X Previous State Previous State
Write Cycle Descriptions
The write cycle description table for CY7C2562XV18 follow. [3, 9]
BWS0BWS1KKComments
L L L–H – During the data portion of a write sequence
CY7C2562XV18 both bytes (D[17:0]) are written into the device.
L L – L–H During the data portion of a write sequence:
CY7C2562XV18 both bytes (D[17:0]) are written into the device.
L H L–H – During the data portion of a write sequence:
CY7C2562XV18 only the lower byte (D[8:0]) is written into the device, D[17:9] remains unaltered.
L H – L–H During the data portion of a write sequence
CY7C2562XV18 only the lower byte (D[8:0]) is written into the device, D[17:9] remains unaltered.
H L L–H – During the data portion of a write sequence
CY7C2562XV18 only the upper byte (D[17:9]) is written into the device, D[8:0] remains unaltered.
H L – L–H During the data portion of a write sequence
CY7C2562XV18 only the upper byte (D[17:9]) is written into the device, D[8:0] remains unaltered.
H H L–H – No data is written into the devices during this portion of a write operation.
H H – L–H No data is written into the devices during this portion of a write operation.
Notes
3. X = “Don't Care,” H = Logic HIGH, L = Logic LOW, represents rising edge.
4. Device powers up deselected with the outputs in a tristate condition.
5. “A” represents address location latched by the devices when transaction was initiated. A + 1 represents the internal address sequence in the burst.
6. “t” represents the cycle at which a Read/Write operation is started. t + 1, and t + 2 are the first, and second clock cycles respectively succeeding the “t” clock cycle.
7. Data inputs are registered at K and K rising edges. Data outputs are delivered on K and K rising edges as well.
8. Ensure that when clock is stopped K = K and C = C = HIGH. This is not essential, but permits most rapid restart by overcoming transmission line charging symmetrically.
9. Is based on a write cycle that was initiated in accordance with the Truth Table. BWS0, BWS1, BWS2 and BWS3 can be altered on different portions of a write cycle,
as long as the setup and hold requirements are achieved.
CY7C2562XV18/CY7C2564XV18
Document Number: 001-70204 Rev. *F Page 10 of 29
Write Cycle Descriptions
The write cycle description table for CY7C2564XV18 follow. [10, 11]
BWS0BWS1BWS2BWS3K K Comments
LLLLL–H–During the data portion of a write sequence, all four bytes (D
[35:0]) are written into
the device.
LLLL–L–HDuring the data portion of a write sequence, all four bytes (D
[35:0]) are written into
the device.
L H H H L–H – During the data portion of a write sequence, only the lower byte (D[8:0]) is written
into the device. D[35:9] remains unaltered.
L H H H – L–H During the data portion of a write sequence, only the lower byte (D[8:0]) is written
into the device. D[35:9] remains unaltered.
H L H H L–H – During the data portion of a write sequence, only the byte (D[17:9]) is written into
the device. D[8:0] and D[35:18] remains unaltered.
H L H H – L–H During the data portion of a write sequence, only the byte (D[17:9]) is written into
the device. D[8:0] and D[35:18] remains unaltered.
H H L H L–H – During the data portion of a write sequence, only the byte (D[26:18]) is written into
the device. D[17:0] and D[35:27] remains unaltered.
H H L H – L–H During the data portion of a write sequence, only the byte (D[26:18]) is written into
the device. D[17:0] and D[35:27] remains unaltered.
H H H L L–H – During the data portion of a write sequence, only the byte (D[35:27]) is written into
the device. D[26:0] remains unaltered.
H H H L – L–H During the data portion of a write sequence, only the byte (D[35:27]) is written into
the device. D[26:0] remains unaltered.
HHHHL–H–No data is written into the device during this portion of a write operation.
HHHH–L–HNo data is written into the device during this portion of a write operation.
Notes
10. X = “Don't Care,” H = Logic HIGH, L = Logic LOW, represents rising edge.
11. Is based on a write cycle that was initiated in accordance with the Truth Table on page 9. BWS0, BWS1, BWS2 and BWS3 can be altered on different portions of a
write cycle, as long as the setup and hold requirements are achieved.
CY7C2562XV18/CY7C2564XV18
Document Number: 001-70204 Rev. *F Page 11 of 29
IEEE 1149.1 Serial Boundary Scan (JTAG)
These SRAMs incorporate a serial boundary scan Test Access
Port (TAP) in the FBGA package. This part is fully compliant with
IEEE Standard #1149.1-2001. The TAP operates using JEDEC
standard 1.8 V logic levels.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are
internally pulled up and may be unconnected. They may
alternatively be connected to VDD through a pull up resistor. TDO
must be left unconnected. Upon power up, the device comes up
in a reset state, which does not interfere with the operation of the
device.
Test Access Port
Test Clock
The test clock is used only with the TAP controller. All inputs are
captured on the rising edge of TCK. All outputs are driven from
the falling edge of TCK.
Test Mode Select (TMS)
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. This pin may be left
unconnected if the TAP is not used. The pin is pulled up
internally, resulting in a logic HIGH level.
Test Data-In (TDI)
The TDI pin is used to serially input information into the registers
and can be connected to the input of any of the registers. The
register between TDI and TDO is chosen by the instruction that
is loaded into the TAP instruction register. For information about
loading the instruction register, see the TAP Controller State
Diagram on page 13. TDI is internally pulled up and can be
unconnected if the TAP is unused in an application. TDI is
connected to the most significant bit (MSB) on any register.
Test Data-Out (TDO)
The TDO output pin is used to serially clock data out from the
registers. The output is active, depending upon the current state
of the TAP state machine (see Instruction Codes on page 17).
The output changes on the falling edge of TCK. TDO is
connected to the least significant bit (LSB) of any register.
Performing a TAP Reset
A Reset is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This Reset does not affect the operation of the
SRAM and can be performed while the SRAM is operating. At
power up, the TAP is reset internally to ensure that TDO comes
up in a High Z state.
TAP Registers
Registers are connected between the TDI and TDO pins to scan
the data in and out of the SRAM test circuitry. Only one register
can be selected at a time through the instruction registers. Data
is serially loaded into the TDI pin on the rising edge of TCK. Data
is output on the TDO pin on the falling edge of TCK.
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the TDI
and TDO pins, as shown in TAP Controller Block Diagram on
page 14. Upon power up, the instruction register is loaded with
the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state, as described
in the previous section.
When the TAP controller is in the Capture-IR state, the two least
significant bits are loaded with a binary “01” pattern to allow for
fault isolation of the board level serial test path.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between TDI
and TDO pins. This enables shifting of data through the SRAM
with minimal delay. The bypass register is set LOW (VSS) when
the BYPASS instruction is executed.
Boundary Scan Register
The boundary scan register is connected to all of the input and
output pins on the SRAM. Several No Connect (NC) pins are also
included in the scan register to reserve pins for higher density
devices.
The boundary scan register is loaded with the contents of the
RAM input and output ring when the TAP controller is in the
Capture-DR state and is then placed between the TDI and TDO
pins when the controller is moved to the Shift-DR state. The
EXTEST, SAMPLE/PRELOAD, and SAMPLE Z instructions can
be used to capture the contents of the input and output ring.
The Boundary Scan Order on page 18 shows the order in which
the bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected to
TDI, and the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired into
the SRAM and can be shifted out when the TAP controller is in
the Shift-DR state. The ID register has a vendor code and other
information described in Identification Register Definitions on
page 17.
TAP Instruction Set
Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in Instruction
Codes on page 17. Three of these instructions are listed as
RESERVED and must not be used. The other five instructions
are described in this section in detail.
Instructions are loaded into the TAP controller during the Shift-IR
state when the instruction register is placed between TDI and
TDO. During this state, instructions are shifted through the
instruction register through the TDI and TDO pins. To execute
the instruction after it is shifted in, the TAP controller must be
moved into the Update-IR state.
CY7C2562XV18/CY7C2564XV18
Document Number: 001-70204 Rev. *F Page 12 of 29
IDCODE
The IDCODE instruction loads a vendor-specific, 32-bit code into
the instruction register. It also places the instruction register
between the TDI and TDO pins and shifts the IDCODE out of the
device when the TAP controller enters the Shift-DR state. The
IDCODE instruction is loaded into the instruction register at
power up or whenever the TAP controller is supplied a
Test-Logic-Reset state.
SAMPLE Z
The SAMPLE Z instruction connects the boundary scan register
between the TDI and TDO pins when the TAP controller is in a
Shift-DR state. The SAMPLE Z command puts the output bus
into a High Z state until the next command is supplied during the
Update IR state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the input and output pins is captured
in the boundary scan register.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because there
is a large difference in the clock frequencies, it is possible that
during the Capture-DR state, an input or output undergoes a
transition. The TAP may then try to capture a signal while in
transition (metastable state). This does not harm the device, but
there is no guarantee as to the value that is captured.
Repeatable results may not be possible.
To guarantee that the boundary scan register captures the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller’s capture setup plus hold
times (tCS and tCH). The SRAM clock input might not be captured
correctly if there is no way in a design to stop (or slow) the clock
during a SAMPLE/PRELOAD instruction. If this is an issue, it is
still possible to capture all other signals and simply ignore the
value of the CK and CK captured in the boundary scan register.
After the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the boundary
scan register between the TDI and TDO pins.
PRELOAD places an initial data pattern at the latched parallel
outputs of the boundary scan register cells before the selection
of another boundary scan test operation.
The shifting of data for the SAMPLE and PRELOAD phases can
occur concurrently when required, that is, while the data
captured is shifted out, the preloaded data can be shifted in.
BYPASS
When the BYPASS instruction is loaded in the instruction register
and the TAP is placed in a Shift-DR state, the bypass register is
placed between the TDI and TDO pins. The advantage of the
BYPASS instruction is that it shortens the boundary scan path
when multiple devices are connected together on a board.
EXTEST
The EXTEST instruction drives the preloaded data out through
the system output pins. This instruction also connects the
boundary scan register for serial access between the TDI and
TDO in the Shift-DR controller state.
EXTEST OUTPUT BUS TRISTATE
IEEE Standard 1149.1 mandates that the TAP controller be able
to put the output bus into a tristate mode.
The boundary scan register has a special bit located at bit #108.
When this scan cell, called the “extest output bus tristate,” is
latched into the preload register during the Update-DR state in
the TAP controller, it directly controls the state of the output
(Q-bus) pins, when the EXTEST is entered as the current
instruction. When HIGH, it enables the output buffers to drive the
output bus. When LOW, this bit places the output bus into a
High Z condition.
This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that cell,
during the Shift-DR state. During Update-DR, the value loaded
into that shift-register cell latches into the preload register. When
the EXTEST instruction is entered, this bit directly controls the
output Q-bus pins. Note that this bit is pre-set LOW to enable the
output when the device is powered up, and also when the TAP
controller is in the Test-Logic-Reset state.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
CY7C2562XV18/CY7C2564XV18
Document Number: 001-70204 Rev. *F Page 13 of 29
TAP Controller State Diagram
The state diagram for the TAP controller follows. [12]
TEST-LOGIC
RESET
TEST-LOGIC/
IDLE
SELECT
DR-SCAN
CAPTURE-DR
SHIFT-DR
EXIT1-DR
PAUSE-DR
EXIT2-DR
UPDATE-DR
1
0
1
1
0
1
0
1
0
0
0
1
1
1
0
10
10
0
0
1
0
1
1
0
1
0
0
1
1
0
SELECT
IR-SCAN
CAPTURE-IR
SHIFT-IR
EXIT1-IR
PAUSE-IR
EXIT2-IR
UPDATE-IR
Note
12. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.
CY7C2562XV18/CY7C2564XV18
Document Number: 001-70204 Rev. *F Page 14 of 29
TAP Controller Block Diagram
0
012..29
3031
Boundary Scan Register
Identification Register
012..
.
.108
012
Instruction Register
Bypass Register
Selection
Circuitry
Selection
Circuitry
TAP Controller
TDI TDO
TCK
TMS
TAP Electrical Characteristics
Over the Operating Range
Parameter [13, 14, 15] Description Test Conditions Min Max Unit
VOH1 Output HIGH voltage IOH =–2.0 mA 1.4 – V
VOH2 Output HIGH voltage IOH = –100 A1.6–V
VOL1 Output LOW voltage IOL = 2.0 mA – 0.4 V
VOL2 Output LOW voltage IOL = 100 A–0.2V
VIH Input HIGH voltage 0.65 × VDD VDD + 0.3 V
VIL Input LOW voltage –0.3 0.35 × VDD V
IXInput and Output load current GND VI VDD –5 5 A
Notes
13. These characteristics pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics on page 20.
14. Overshoot: VIH(AC) < VDD + 0.35 V (Pulse width less than tTCYC/2), Undershoot: VIL(AC) > 0.3 V (Pulse width less than tTCYC/2).
15. All Voltage referenced to Ground.
CY7C2562XV18/CY7C2564XV18
Document Number: 001-70204 Rev. *F Page 15 of 29
TAP AC Switching Characteristics
Over the Operating Range
Parameter [16, 17] Description Min Max Unit
tTCYC TCK clock cycle time 50 – ns
tTF TCK clock frequency – 20 MHz
tTH TCK clock HIGH 20 – ns
tTL TCK clock LOW 20 – ns
Setup Times
tTMSS TMS setup to TCK clock rise 5 – ns
tTDIS TDI setup to TCK clock rise 5 – ns
tCS Capture setup to TCK rise 5 – ns
Hold Times
tTMSH TMS Hold after TCK clock rise 5 – ns
tTDIH TDI Hold after clock rise 5 – ns
tCH Capture Hold after clock rise 5 – ns
Output Times
tTDOV TCK clock LOW to TDO valid –10 ns
tTDOX TCK clock LOW to TDO invalid 0 – ns
Notes
16. tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register.
17. Test conditions are specified using the load in TAP AC Test Conditions. tR/tF = 1 V/ns.
CY7C2562XV18/CY7C2564XV18
Document Number: 001-70204 Rev. *F Page 16 of 29
TAP Timing and Test Conditions
Figure 3 shows the TAP timing and test conditions. [18]
Figure 3. TAP Timing and Test Conditions
t
TL
t
TH
(a)
TDO
C
L
= 20 pF
Z
0
= 50
GND
0.9V
50
1.8V
0V
ALL INPUT PULSES
0.9V
Test Clock
Test Mode Select
TCK
TMS
Test Data In
TDI
Test Data Out
t
TCYC
t
TMSH
t
TMSS
t
TDIS
t
TDIH
t
TDOV
t
TDOX
TDO
Slew Rate = 1 V/ns
Note
18. Test conditions are specified using the load in TAP AC Test Conditions. tR/tF = 1 V/ns.
CY7C2562XV18/CY7C2564XV18
Document Number: 001-70204 Rev. *F Page 17 of 29
Identification Register Definitions
Instruction Field Value Description
CY7C2562XV18 CY7C2564XV18
Revision Number (31:29) 000 000 Version number.
Cypress Device ID (28:12) 11010010000010100 11010010000100100 Defines the type of SRAM.
Cypress JEDEC ID (11:1) 00000110100 00000110100 Allows unique identification of
SRAM vendor.
ID Register Presence (0) 1 1 Indicates the presence of an
ID register.
Scan Register Sizes
Register Name Bit Size
Instruction 3
Bypass 1
ID 32
Boundary Scan 109
Instruction Codes
Instruction Code Description
EXTEST 000 Captures the input and output ring contents.
IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO.
This operation does not affect SRAM operation.
SAMPLE Z 010 Captures the input and output contents. Places the boundary scan register between TDI and
TDO. Forces all SRAM output drivers to a High Z state.
RESERVED 011 Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD 100 Captures the input and output contents. Places the boundary scan register between TDI and
TDO. Does not affect the SRAM operation.
RESERVED 101 Do Not Use: This instruction is reserved for future use.
RESERVED 110 Do Not Use: This instruction is reserved for future use.
BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM
operation.
CY7C2562XV18/CY7C2564XV18
Document Number: 001-70204 Rev. *F Page 18 of 29
Boundary Scan Order
Bit # Bump ID Bit # Bump ID Bit # Bump ID Bit # Bump ID
0 6R 28 10G 56 6A 84 1J
16P299G575B852J
2 6N 30 11F 58 5A 86 3K
3 7P 31 11G 59 4A 87 3J
47N 329F 605C 882K
5 7R 33 10F 61 4B 89 1K
6 8R 34 11E 62 3A 90 2L
7 8P 35 10E 63 2A 91 3L
8 9R 36 10D 64 1A 92 1M
9 11P 37 9E 65 2B 93 1L
10 10P 38 10C 66 3B 94 3N
11 10N 39 11D 67 1C 95 3M
12 9P 40 9C 68 1B 96 1N
13 10M 41 9D 69 3D 97 2M
14 11N 42 11B 70 3C 98 3P
15 9M 43 11C 71 1D 99 2N
16 9N 44 9B 72 2C 100 2P
17 11L 45 10B 73 3E 101 1P
18 11M 46 11A 74 2D 102 3R
19 9L 47 10A 75 2E 103 4R
20 10L 48 9A 76 1E 104 4P
21 11K 49 8B 77 2F 105 5P
22 10K 50 7C 78 3F 106 5N
23 9J 51 6C 79 1G 107 5R
24 9K 52 8A 80 1F 108 Internal
25 10J 53 7A 81 3G
26 11J 54 7B 82 2G
27 11H 55 6B 83 1H
CY7C2562XV18/CY7C2564XV18
Document Number: 001-70204 Rev. *F Page 19 of 29
Power Up Sequence in QDR II+ Xtreme SRAM
QDR II+ Xtreme SRAMs must be powered up and initialized in a
predefined manner to prevent undefined operations.
Power Up Sequence
■Apply power and drive DOFF either HIGH or LOW (All other
inputs can be HIGH or LOW).
❐Apply VDD before VDDQ.
❐Apply VDDQ before VREF or at the same time as VREF
.
❐Drive DOFF HIGH.
■Provide stable DOFF (HIGH), power and clock (K, K) for 100 s
to lock the PLL
PLL Constraints
■PLL uses K clock as its synchronizing input. The input must
have low phase jitter, which is specified as tKC Var.
■The PLL functions at frequencies down to 120 MHz.
■If the input clock is unstable and the PLL is enabled, then the
PLL may lock onto an incorrect frequency, causing unstable
SRAM behavior. To avoid this, provide 100 s of stable clock
to relock to the desired clock frequency.
Figure 4. Power Up Waveforms
CY7C2562XV18/CY7C2564XV18
Document Number: 001-70204 Rev. *F Page 20 of 29
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage Temperature ............................... –65 °C to +150 °C
Supply Voltage on VDD Relative to GND .....–0.5 V to +2.9 V
Supply Voltage on VDDQ Relative to GND .... –0.5 V to +VDD
DC Applied to Outputs in High Z ...... –0.5 V to VDDQ + 0.3 V
DC Input Voltage [19] ........................... –0.5 V to VDD + 0.3 V
Current into Outputs (LOW) ........................................ 20 mA
Static Discharge Voltage
(MIL-STD-883, M. 3015) ......................................... > 2001V
Latch up Current ................................................... > 200 mA
Maximum Junction Temperature .............................. 125 °C
Operating Range
Range Ambient
Temperature (TA)VDD [20] VDDQ [20]
Commercial 0 °C to +70 °C 1.8 ± 0.1 V 1.4 V to 1.6 V
Industrial -40 °C to +85 °C
Neutron Soft Error Immunity
Parameter Description Test
Conditions Typ Max* Unit
LSBU Logical
Single-Bit
Upsets
25 °C 260 271 FIT/
Mb
LMBU Logical
Multi-Bit
Upsets
25 °C 0 0.01 FIT/
Mb
SEL Single Event
Latch up
85 °C 0 0.1 FIT/
Dev
* No LMBU or SEL events occurred during testing; this column represents a
statistical 2, 95% confidence limit calculation. For more details refer to
Application Note AN54908 “Accelerated Neutron SER Testing and Calculation of
Terrestrial Failure Rates”.
Electrical Characteristics
Over the Operating Range
DC Electrical Characteristics
Over the Operating Range
Parameter [21] Description Test Conditions Min Typ Max Unit
VDD Power supply voltage 1.7 1.8 1.9 V
VDDQ Supply voltage 1.4 1.5 1.6 V
VOH Output HIGH voltage Note 22 VDDQ/2 – 0.12 – VDDQ/2 + 0.12 V
VOL Output LOW voltage Note 23 VDDQ/2 – 0.12 – VDDQ/2 + 0.12 V
VOH(LOW) Output HIGH voltage IOH =0.1 mA, Nominal Impedance VDDQ – 0.2 – VDDQ V
VOL(LOW) Output LOW voltage IOL = 0.1 mA, Nominal Impedance VSS –0.2 V
VIH Input HIGH voltage VREF + 0.1 – VDDQ + 0.15 V
VIL Input LOW voltage –0.15 – VREF – 0.1 V
IXInput leakage current GND VI VDDQ 2 – 2 A
IOZ Output leakage current GND VI VDDQ, Output Disabled 2 – 2 A
VREF Input reference voltage Typical Value = 0.75 V 0.68 0.75 0.86 V
IDD [24] VDD Operating Supply VDD = Max,
IOUT = 0 mA,
f = fMAX = 1/tCYC
450 MHz (× 18) – – 1205 mA
(× 36) – – 1445
366 MHz (× 18) – – 970 mA
(× 36) – – 1165
Notes
19. Overshoot: VIH(AC) < VDDQ + 0.35 V (Pulse width less than tCYC/2), Undershoot: VIL(AC) > 0.3 V (Pulse width less than tCYC/2).
20. Power up: Assumes a linear ramp from 0 V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
21. All Voltage referenced to Ground.
22. Output are impedance controlled. IOH = (VDDQ/2)/(RQ/5) for values of 175 ohms < RQ < 350 ohms.
23. Output are impedance controlled. IOL = (VDDQ/2)/(RQ/5) for values of 175 ohms < RQ < 350 ohms.
24. The operation current is calculated with 50% read cycle and 50% write cycle.
CY7C2562XV18/CY7C2564XV18
Document Number: 001-70204 Rev. *F Page 21 of 29
ISB1 Automatic Power down Current Max VDD,
Both Ports
Deselected,
VIN VIH or
VIN VIL,
f = fMAX = 1/tCYC,
Inputs Static
450 MHz (× 18) – – 1205 mA
(× 36) – – 1445
366 MHz (× 18) – – 970 mA
(× 36) – – 1165
Electrical Characteristics (continued)
Over the Operating Range
DC Electrical Characteristics (continued)
Over the Operating Range
Parameter [21] Description Test Conditions Min Typ Max Unit
AC Electrical Characteristics
Over the Operating Range
Parameter [25] Description Test Conditions Min Typ Max Unit
VIH Input HIGH voltage VREF + 0.2 – VDDQ + 0.24 V
VIL Input LOW voltage –0.24 – VREF – 0.2 V
Note
25. Overshoot: VIH(AC) < VDDQ + 0.35 V (Pulse width less than tCYC/2), Undershoot: VIL(AC) > 0.3 V (Pulse width less than tCYC/2).
CY7C2562XV18/CY7C2564XV18
Document Number: 001-70204 Rev. *F Page 22 of 29
Capacitance
Parameter [26] Description Test Conditions Max Unit
CIN Input capacitance TA = 25 C, f = 1 MHz, VDD = 1.8 V, VDDQ = 1.5 V 4 pF
COOutput capacitance 4pF
Thermal Resistance
Parameter [26] Description Test Conditions 165-ball FBGA
Package Unit
JA (0 m/s) Thermal resistance
(junction to ambient)
Socketed on a 170 × 220 × 2.35 mm, eight-layer printed circuit
board
14.43 °C/W
JA (1 m/s) 13.40 °C/W
JA (3 m/s) 12.66 °C/W
JB Thermal resistance
(junction to board)
11.38 °C/W
JC Thermal resistance
(junction to case)
3.30 °C/W
AC Test Loads and Waveforms
Figure 5. AC Test Loads and Waveforms
1.25 V
0.25V
R = 50
5pF
INCLUDING
JIG AND
SCOPE
ALL INPUT PULSES
DEVICE RL= 50
Z0= 50
VREF = 0.75 V
VREF = 0.75 V
[27]
0.75 V
UNDER
TEST
0.75 V
DEVICE
UNDER
TEST
OUTPUT
0.75 V
VREF
VREF
OUTPUT
ZQ
ZQ
(a)
SLEW RATE= 2 V/ns
RQ =
250
(b)
RQ =
250
Notes
26. Tested initially and after any design or process change that may affect these parameters.
27. Unless otherwise noted, test conditions are based on signal transition time of 2 V/ns, timing reference levels of 0.75 V, Vref = 0.75 V, RQ = 250 , VDDQ = 1.5 V, input
pulse levels of 0.25 V to 1.25 V, and output loading of the specified IOL/IOH and load capacitance shown in (a) of Figure 5.
CY7C2562XV18/CY7C2564XV18
Document Number: 001-70204 Rev. *F Page 23 of 29
Switching Characteristics
Over the Operating Range
Parameter [28, 29]
Description
450 MHz 366 MHz
Unit
Cypress
Parameter
Consortium
Parameter Min Max Min Max
tPOWER VDD(typical) to the first access [30] 1 – 1 – ms
tCYC tKHKH K clock cycle time 2.2 8.4 2.73 8.4 ns
tKH tKHKL Input clock (K/K) HIGH 0.4 –0.4 –ns
tKL tKLKH Input clock (K/K) LOW 0.4 –0.4 –ns
tKHKHtKHKHK clock rise to K clock rise (rising edge to rising edge) 0.94 –1.16 –ns
Setup Times
tSA tAVKH Address setup to K clock rise 0.275 –0.4 –ns
tSC tIVKH Control setup to K clock rise (RPS, WPS)0.275 –0.4 –ns
tSCDDR tIVKH DDR control setup to clock (K/K) rise (BWS0, BWS1, BWS2,
BWS3)
0.275 –0.4 –ns
tSD tDVKH D[X:0] setup to clock (K/K) rise 0.275 –0.4 –ns
Hold Times
tHA tKHAX Address hold after K clock rise 0.275 –0.4 –ns
tHC tKHIX Control hold after K clock rise (RPS, WPS)0.275 –0.4 –ns
tHCDDR tKHIX DDR control hold after clock (K/K) rise (BWS0, BWS1, BWS2,
BWS3)
0.275 –0.4 –ns
tHD tKHDX D[X:0] hold after clock (K/K) rise 0.275 –0.4 –ns
Output Times
tCCQO tCHCQV K/K clock rise to echo clock valid –0.45 –0.45 ns
tCQOH tCHCQX Echo clock hold after K/K clock rise –0.45 ––0.45 –ns
tCQD tCQHQV Echo clock high to data valid –0.13 –0.15 ns
tCQDOH tCQHQX Echo clock high to data invalid –0.13 ––0.15 –ns
tCQH tCQHCQL Output clock (CQ/CQ) HIGH [31] 1.02 –1.285 –ns
tCQHCQHtCQHCQHCQ clock rise to CQ clock rise (rising edge to rising edge) [31] 1.02 –1.285 –ns
tCHZ tCHQZ Clock (K/K) rise to high Z (active to high Z) [32, 33] –0.45 –0.45 ns
tCLZ tCHQX1 Clock (K/K) rise to low Z [32, 33] –0.45 ––0.45 –ns
tQVLD tCQHQVLD Echo clock high to QVLD valid [34] –0.15 0.15 –0.20 0.20 ns
PLL Timing
tKC Var tKC Var Clock phase jitter –0.15 –0.15 ns
tKC lock tKC lock PLL lock time (K) 100 –100 –s
tKC Reset tKC Reset K static to PLL reset [35] 30 –30 –ns
Notes
28. Unless otherwise noted, test conditions are based on signal transition time of 2 V/ns, timing reference levels of 0.75 V, Vref = 0.75 V, RQ = 250 , VDDQ = 1.5 V, input
pulse levels of 0.25 V to 1.25 V, and output loading of the specified IOL/IOH and load capacitance shown in (a) of Figure 5 on page 22.
29. When a part with a maximum frequency above 366 MHz is operating at a lower clock frequency, it requires the input timings of the frequency range in which it is being
operated and outputs data with the output timings of that frequency range.
30. This part has a voltage regulator internally; tPOWER is the time that the power must be supplied above VDD minimum initially before initiating a read or write operation.
31. These parameters are extrapolated from the input timing parameters (tCYC/2 – 80 ps, where 80 ps is the internal jitter). These parameters are only guaranteed by design
and are not tested in production.
32. tCHZ, tCLZ, are specified with a load capacitance of 5 pF as in part (b) of Figure 5 on page 22. Transition is measured 100 mV from steady state voltage.
33. At any given voltage and temperature tCHZ is less than tCLZ .
34. tQVLD spec is applicable for both rising and falling edges of QVLD signal.
35. Hold to >VIH or <VIL.
CY7C2562XV18/CY7C2564XV18
Document Number: 001-70204 Rev. *F Page 24 of 29
Switching Waveforms
Read/Write/Deselect Sequence
Figure 6. Waveform for 2.5 Cycle Read Latency [36, 37, 38]
Notes
36. Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, that is, A0 + 1.
37. Outputs are disabled (High Z) one clock cycle after a NOP.
38. In this example, if address A0 = A1, then data Q00 = D10 and Q01 = D11. Write data is forwarded immediately as read results. This note applies to the whole diagram.
CY7C2562XV18/CY7C2564XV18
Document Number: 001-70204 Rev. *F Page 25 of 29
Ordering Information
The following table contains only the parts that are currently available. If you do not see what you are looking for, contact your local
sales representative. For more information, visit the Cypress website at www.cypress.com and refer to the product summary page at
http://www.cypress.com/products
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office
closest to you, visit us at http://www.cypress.com/go/datasheet/offices.
Ordering Code Definitions
Speed
(MHz) Ordering Code
Package
Diagram Package Type
Operating
Range
450 CY7C2564XV18-450BZC 51-85180 165-ball FBGA (13 × 15 × 1.4 mm) Commercial
CY7C2562XV18-450BZXC 165-ball FBGA (13 × 15 × 1.4 mm) Pb-free
CY7C2564XV18-450BZXC
CY7C2564XV18-450BZXI Industrial
366 CY7C2564XV18-366BZC 51-85180 165-ball FBGA (13 × 15 × 1.4 mm) Commercial
CY7C2562XV18-366BZXC 165-ball FBGA (13 × 15 × 1.4 mm) Pb-free
CY7C2564XV18-366BZXC
Temperature Range: X = C or I
C = Commercial; I = Industrial
Pb-free
Package Type:
BZ = 165-ball FBGA
Frequency Range: XXX = 450 MHz or 366 MHz
V18 = 1.8 V
Die Revision
Part Identifier: 256X = 2562 or 2564
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
7CY 256X X - XXX BZ XV18C X
CY7C2562XV18/CY7C2564XV18
Document Number: 001-70204 Rev. *F Page 26 of 29
Package Diagram
Figure 7. 165-ball FBGA (13 × 15 × 1.4 mm) BB165D/BW165D (0.5 Ball Diameter) Package Outline, 51-85180
51-85180 *G
CY7C2562XV18/CY7C2564XV18
Document Number: 001-70204 Rev. *F Page 27 of 29
Acronyms Document Conventions
Units of Measure
Acronym Description
DDR Double Data Rate
FBGA Fine-Pitch Ball Grid Array
HSTL High-Speed Transceiver Logic
I/O Input/Output
JTAG Joint Test Action Group
LSB Least Significant Bit
LMBU Logical Multi-Bit Upsets
LSBU Logical Single-Bit Upsets
MSB Most Significant Bit
ODT On-Die Termination
PLL Phase-Locked Loop
QDR Quad Data Rate
SEL Single Event Latch-up
SRAM Static Random Access Memory
TAP Test Access Port
TCK Test Clock
TMS Test Mode Select
TDI Test Data-In
TDO Test Data-Out
Symbol Unit of Measure
°C degree Celsius
kkilohm
MHz megahertz
µA microampere
µs microsecond
mA milliampere
mV millivolt
mm millimeter
ms millisecond
ns nanosecond
ohm
% percent
pF picofarad
ps picosecond
Vvolt
Wwatt
CY7C2562XV18/CY7C2564XV18
Document Number: 001-70204 Rev. *F Page 28 of 29
Document History Page
Document Title: CY7C2562XV18/CY7C2564XV18, 72-Mbit QDR® II+ Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle
Read Latency) with ODT
Document Number: 001-70204
Rev. ECN No. Orig. of
Change
Submission
Date Description of Change
** 3302894 OSN 07/05/2011 New data sheet.
*A 3532349 PRIT 02/22/2012 Changed status from Preliminary to Final.
*B 3639849 PRIT 06/08/2012 No technical updates.
Completing Sunset Review.
*C 3781737 PRIT 10/24/2012 Updated Application Example (Updated Figure 2).
Updated TAP Electrical Characteristics (Updated Note 14).
Updated TAP AC Switching Characteristics (Updated Note 17).
Updated TAP Timing and Test Conditions (Updated Note 18 and updated
Figure 3).
Updated Thermal Resistance (Changed value of JA parameter from
23.94 °C/W to 14.84 °C/W (for Test Condition “With Still Air (0 m/s)”) for
165-ball FBGA Package, changed value of JA parameter from 20.07 °C/W to
13.68 °C/W (for Test Condition “With Air flow (1 m/s)”) for 165-ball FBGA
Package, changed value of JC parameter from 3.0 °C/W to 5.1 °C/W for
165-ball FBGA Package).
Updated Package Diagram (spec 51-85180 (Changed revision from *E to *F)).
*D 4380995 PRIT 05/15/2014 Updated Application Example:
Updated Figure 2.
Updated Thermal Resistance:
Updated values of JA parameter.
Included JB parameter and its details.
Updated to new template.
Completing Sunset Review.
*E 4574060 PRIT 11/19/2014 Updated Functional Description:
Added “For a complete list of related documentation, click here.” at the end.
*F 5269064 PRIT 05/12/2016 Added Industrial Temperature Range related information in all instances across
the document.
Updated Ordering Information:
Updated part numbers.
Updated Package Diagram:
spec 51-85180 – Changed revision from *F to *G.
Updated to new template.
Document Number: 001-70204 Rev. *F Revised May 12, 2016 Page 29 of 29
QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, IDT, NEC, Renesas, and Samsung.
CY7C2562XV18/CY7C2564XV18
© Cypress Semiconductor Corporation 2011-2016. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you under its copyright rights in the Software, a personal, non-exclusive, nontransferable license (without the right to sublicense) (a) for Software provided in source code form, to modify
and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either
directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units. Cypress also grants you a personal, non-exclusive, nontransferable, license (without the right
to sublicense) under those claims of Cypress's patents that are infringed by the Software (as provided by Cypress, unmodified) to make, use, distribute, and import the Software solely to the minimum
extent that is necessary for you to exercise your rights under the copyright license granted in the previous sentence. Any other use, reproduction, modification, translation, or compilation of the Software
is prohibited.
CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes to this document without further notice. Cypress does not
assume any liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or
programming code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application
made of this information and any resulting product. Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of
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and hold Cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress
products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United
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