M1N1G64TU8HA2B-37B (Green) 1GB : 128M x 64 PC2-4200 Unbuffered DDR2 SO-DIMM 200 pin Unbuffered DDR2 SO-DIMM Based on 64Mx8 DDR2 SDRAM Features * 200-Pin Small Outline Dual In-Line Memory Module (SO-DIMM) * 128Mx64 Unbuffered DDR2 SO-DIMM based on 64Mx8 DDR2 SDRAM devices. * Performance: * DRAM DLL aligns DQ and DQS transitions with clock transitions. * Address and control signals are fully synchronous to positive clock edge * Programmable Operation: - DIMM Latency: 4 - Burst Type: Sequential or Interleave - Burst Length: 4, 8 - Operation: Burst Read and Write * Auto Refresh (CBR) and Self Refresh Modes * Automatic and controlled precharge commands * 14/10/2 Addressing * 7.8 s Max. Average Periodic Refresh Interval * Serial Presence Detect * Gold contacts * SDRAMs in 60-ball FBGA Package * RoHS Compliant PC2-4200 Speed Sort DIMM Latency 37B Unit 4 fCK Clock Frequency 266 tCK Clock Cycle 3.75 MHz ns fDQ DQ Burst Frequency 533 MHz * Intended for 266MHz applications * Inputs and outputs are SSTL-18 compatible * VDD = VDDQ = 1.8V 0.1V * SDRAMs have 4 internal banks for concurrent operation * Module has one physical bank * Differential clock inputs * Data is read or written on both clock edges Description M1N1G64TUH8A2B is unbuffered 200-Pin Double Data Rate 2 (DDR2) Synchronous DRAM Small Outline Dual In-Line Memory Module (SO-DIMM), organized as two ranks of 128Mx64 high-speed memory array. Modules use sixteen 64Mx8 60-ball FBGA packaged devices. The DIMM is manufactured using raw cards developed for broad industry use as reference designs. The use of these common design files minimizes electrical variation between suppliers. All NANYA DDR2 SDRAM DIMMs provide a high-performance, flexible 8-byte interface in a 2.66" long space-saving footprint. The DIMM is intended for use in applications operating up to 266MHz clock speeds and achieves high-speed data transfer rates of up to 533MHz. Prior to any access operation, the device latency and burst/length/operation type must be programmed into the DIMM by address inputs A0-A13 and I/O inputs BA0 and BA1 using the mode register set cycle. The DIMM uses serial presence-detect implemented via a serial EEPROM using a standard IIC protocol. The first 128 bytes of serial PD data are programmed and locked during module assembly. The remaining 128 bytes are available for use by the customer. Ordering Information Part Number M1N1G64TU8HA2B-37B REV 1.0 04/2006 Speed DDR2-533 PC2-4200 266MHz (3.75ns @ CL = 4) Organization Power Leads Note 128Mx64 1.8V Gold Green 1 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. M1N1G64TU8HA2B-37B (Green) 1GB : 128M x 64 PC2-4200 Unbuffered DDR2 SO-DIMM Pin Description CK0, Differential Clock Inputs CKE0, CKE1 DQ0-DQ63 Clock Enable Row Address Strobe Bidirectional data strobes - Column Address Strobe Differential data strobes DM0-DM7 Write Enable , Data input/output DQS0-DQS7 Chip Selects Input Data Masks VDD Power (1.8V) VREF Ref. Voltage for SSTL_18 inputs A0-A13 Row Address Inputs A0-A9 Column Address Inputs VSS Column Address Input/Auto-precharge SCL Serial Presence Detect Clock Input BA0, BA1 SDRAM Bank Address Inputs SDA Serial Presence Detect Data input/output ODT0, ODT1 Active termination control lines SA0, SA1 A10/AP NC VDDSPD Serial EEPROM positive power supply Ground Serial Presence Detect Address Inputs No Connect Pinout Pin Front 1 VREF 2 VSS 51 3 VSS 4 DQ4 53 5 DQ0 6 DQ5 7 DQ1 8 VSS 9 VSS 10 DM0 11 Pin Back Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back DQS2 52 DM2 101 A1 102 A0 151 DQ42 152 DQ46 VSS 54 VSS 103 VDD 104 VDD 153 DQ43 154 DQ47 55 DQ18 56 DQ22 105 A10/AP 106 BA1 155 VSS 156 VSS 57 DQ19 58 DQ23 107 BA0 108 157 DQ48 158 DQ52 59 VSS 60 VSS 109 110 159 DQ49 160 DQ53 12 VSS 61 DQ24 62 DQ28 111 112 VDD 161 VSS 162 VSS 13 DQS0 14 DQ6 63 DQ25 64 DQ29 113 114 ODT0 163 NC 164 CK1 15 VSS 16 DQ7 65 VSS 66 VSS 115 116 A13 165 VSS 166 17 DQ2 18 VSS 67 DM3 68 117 VDD 118 VDD 167 168 VSS 19 DQ3 20 DQ12 69 NC 70 DQS3 119 ODT1 120 NC 169 DQS6 170 DM6 21 VSS 22 DQ13 71 VSS 72 VSS 121 VSS 122 VSS 171 VSS 172 VSS 23 DQ8 24 VSS 73 DQ26 74 DQ30 123 DQ32 124 DQ36 173 DQ50 174 DQ54 25 DQ9 26 DM1 75 DQ27 76 DQ31 125 DQ33 126 DQ37 175 DQ51 176 DQ55 27 VSS 28 VSS 77 VSS 78 VSS 127 VSS 128 VSS 177 VSS 178 VSS 30 CK0 79 CKE0 80 CKE1 129 130 DM4 179 DQ56 180 DQ60 29 VDD 31 DQS1 32 81 VDD 82 VDD 131 DQS4 132 VSS 181 DQ57 182 DQ61 33 VSS 34 VSS 83 NC 84 NC 133 VSS 134 DQ38 183 VSS 184 VSS 35 DQ10 36 DQ14 85 NC 86 NC 135 DQ34 136 DQ39 185 DM7 186 37 DQ11 38 DQ15 87 VDD 88 VDD 137 DQ35 138 VSS 187 VSS 188 DQS7 39 VSS 40 VSS 89 A12 90 A11 139 VSS 140 DQ44 189 DQ58 190 VSS 41 VSS 42 VSS 91 A9 92 A7 141 DQ40 142 DQ45 191 DQ59 192 DQ62 43 DQ16 44 DQ20 93 A8 94 A6 143 DQ41 144 VSS 193 VSS 194 DQ63 45 DQ17 46 DQ21 95 VDD 96 VDD 145 VSS 146 195 SDA 196 VSS 47 VSS 48 VSS 97 A5 98 A4 147 DM5 148 DQS5 197 SCL 198 SA0 50 NC 99 A3 100 A2 149 VSS 150 VSS 199 VDDSPD 200 SA1 49 Note: All pin assignments are consistent for all 8-byte unbuffered versions. REV 1.0 04/2006 2 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. M1N1G64TU8HA2B-37B (Green) 1GB : 128M x 64 PC2-4200 Unbuffered DDR2 SO-DIMM Input/Output Functional Description Symbol Type Polarity Function - (SSTL) Cross Point The system clock inputs. All the DDR2 SDRAM address and control inputs are sampled on the cross point of the rising edge of CK and falling edge of CKE0, CKE1 (SSTL) Active High Activates the SDRAM CK signal when high and deactivates the CK signal when low. By deactivating the clocks, CKE low initiates the Power Down mode, or the Self Refresh mode. , (SSTL) Active Low Enables the associated SDRAM command decoder when low and disables the command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. (SSTL) Active Low When sampled at the positive rising edge of the clock, to be executed by the SDRAM. CK0 - CK2, , , VREF Supply , , define the operation Reference voltage for SSTL-18 inputs ODT0, ODT1 Input Active High BA0, BA1 (SSTL) - Selects which SDRAM bank is to be active. During a Bank Activate command cycle, defines the row address when sampled at the cross point of the rising edge of CK and falling edge of . During a Read or Write command cycle, defines the column address when sampled at the cross point of the rising edge of CK and falling edge of . In addition to the column address, AP is used to invoke autoprecharge operation at the end of the burst read or write cycle. If AP is high, autoprecharge is selected and BA0-BA1 defines the bank to be precharged. If AP is low, autoprecharge is disabled. During a precharge command cycle, AP is used in conjunction with BA0-BA1 to control which bank(s) to precharge. If AP is high, all banks will be precharged regardless of the state of BA0-BA1 inputs. If AP is low, BA0-BA1 are used to define which bank to precharge. A0 - A9 A10/AP A11 - A13 (SSTL) - DQ0 - DQ63 (SSTL) Active High VDD, VSS Supply DQS0 - DQS7 - (SSTL) DM0 - DM7 Input On-Die Termination control signals Data and Check Bit Input/Output pins. Power and ground for the DDR2 SDRAM input buffers and core logic Negative and Data strobe for input and output data Positive Edge Active High The data write masks, associated with one data byte. In Write mode, DM operates as a byte mask by allowing input data to be written if it is low but blocks the write operation if it is high. In Read mode, DM lines have no effect. DM8 is associated with check bits CB0-CB7, and is not used on x64 modules. SA0 - SA2 - Address inputs. Connected to either VDD or VSS on the system board to configure the Serial Presence Detect EEPROM address. SDA - This bi-directional pin is used to transfer data into or out of the SPD EEPROM. A resistor must be connected from the SDA bus line to VDD to act as a pull-up. SCL - This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected from the SCL bus time to VDD to act as a pull-up. VDDSPD REV 1.0 04/2006 Supply Serial EEPROM positive power supply. 3 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. M1N1G64TU8HA2B-37B (Green) 1GB : 128M x 64 PC2-4200 Unbuffered DDR2 SO-DIMM Functional Block Diagram (1GB, 2Ranks, 64Mx8 DDR2 SDRAMs) / / * * * / * * * / / / / 8 8 8 8 * / / 8 8 * * / / 8 8 7 / / /* / // / /8 / 7 * * 7 * / / / 8 8 * 8 * 8 8 / /7 * 7 * * ** * * * * * */ * *8 * * *7 8 / / / * / / 8 8 / 8 8 * * / / 8 8 8 * * / / 8 8 7 8 8 8* 8 3 $+2 2 3 3 3 4 3 3 * / REV 1.0 04/2006 !" #$%& '($!" ) (!$ &% + $ ! (, $ #$!$! ) $ ( $ ** (# - . 01 01 1 1 $ (# - . )) $!)' ! + $ ** (# - . $, / $+2 ! 5 62 * * 4 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. M1N1G64TU8HA2B-37B (Green) 1GB : 128M x 64 PC2-4200 Unbuffered DDR2 SO-DIMM Serial Presence Detect (Part 1 of 2) Serial PD Data Entry (Hexadecimal) SPD Entry Value Byte Description PC2-4200 Note 37B 0 Number of Serial PD Bytes Written during Production 128 80 1 Total Number of Bytes in Serial PD device 2 Fundamental Memory Type 256 08 3 Number of Row Addresses on Assembly 4 Number of Column Addresses on Assembly 5 Number of DIMM Ranks 6 Data Width of Assembly 7 Reserved 8 Voltage Interface Level of this Assembly SSTL_1.8 05 9 DDR2 SDRAM Device Cycle Time at CL=5 3.75ns 3D 10 DDR2 SDRAM Device Access Time from Clock at CL=5 0.5ns 50 11 DIMM Configuration Type 12 Refresh Rate/Type 13 DDR2-SDRAM 08 14 0E 10 0A 2 rank, Height = 30mm 61 X64 40 Undefined 00 Non-Parity 00 SR/1x(7.8us) 82 Primary DDR2 SDRAM Width X8 08 14 Error Checking DDR2 SDRAM Device Width NA 00 15 Reserved 16 DDR2 SDRAM Device Attributes: Burst Length Supported 17 18 19 DIMM Mechanical Characteristics 20 DDR2 SDRAM DIMM Type Information 21 DDR2 SDRAM Module Attributes: 22 DDR2 SDRAM Device Attributes: General 23 Undefined 00 4,8 0C DDR2 SDRAM Device Attributes: Number of Device Banks 4 04 DDR2 SDRAM Device Attributes: CAS Latencies Supported 3/4/5 38 <4.10mm 01 Regular SODIMM (67.6mm) 04 Normal DIMM 00 Support weak driver 01 Minimum Clock Cycle at CL=4 3.75ns 3D 24 Maximum Data Access Time from Clock at CL=4 0.5ns 50 25 Minimum Clock Cycle Time at CL=3 5ns 50 26 Maximum Data Access Time from Clock at CL=3 0.6ns 60 27 Minimum Row Precharge Time (tRP) 15ns 3C 28 Minimum Row Active to Row Active delay (tRRD) 7.5ns 1E 29 Minimum RAS to CAS delay (tRCD) 15ns 3C 30 Minimum RAS Pulse Width (tRAS) 45ns 2D 31 Module Bank Density 512MB 80 32 Address and Command Setup Time Before Clock (tIS) 0.25 ns 25 33 Address and Command Hold Time After Clock (tIH) 0.375 ns 37 34 Data Input Setup Time Before Clock (tDS) 0.10 ns 10 35 Data Input Hold Time After Clock (tDH) 0.225ns 22 36 Write Recovery Time (tWR) 15ns 3C 37 Internal Write to Read Command delay (tWTR) 7.5 ns 1E 38 Internal Read to Precharge delay (tRTP) 39 Reserved 40 Extension of Byte 41 tRC and Byte 42 tRFC 41 Minimum Core Cycle Time (tRC) REV 1.0 04/2006 7.5ns 1E Undefined 00 The number below a decimal point of tRC and tRFC are 0, tRFC is less than 256ns 00 60ns 3C 5 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. M1N1G64TU8HA2B-37B (Green) 1GB : 128M x 64 PC2-4200 Unbuffered DDR2 SO-DIMM Serial Presence Detect (Part 2 of 2) Serial PD Data Entry (Hexadecimal) SPD Entry Value Byte Description PC2-4200 Note 37B 42 Min. Auto Refresh Command Cycle Time (tRFC) 43 Maximum Clock Cycle Time (tCK) 8ns 80 44 Max. DQS-DQ Skew Factor (tDQS) 0.30ns 1E 45 Read Data Hold Skew Factor (tQHS) 0.40ns 28 46 PLL Relock Time N/A 00 47 Tcasemax 1C 51 48 Thermal Resistance of DRAM Package from Top (Case) to Ambient (Psi T-A DRAM) 122C/W 7A 49 DRAM Case Temperature Rise from Ambient due to Activate-Precharge/Mode Bits (DT0/Mode Bits) 18C 4B 50 DRAM Case Temperature Rise from Ambient due to Precharge/Quiet Standby (DT2N/DT2Q) 47C 2E 51 DRAM Case Temperature Rise from Ambient due to precharge Power-Down (DT2P) 39C 27 52 DRAM Case Temperature Rise from Ambient due to Active Standby (DT3N) 33C 21 53 DRAM Case Temperature Rise from Ambient due to Active Power-Down with Fast PDN Exit (DT3P fast) 37C 25 54 DRAM Case Temperature Rise from Ambient due to Active Power-Down with Slow PDN Exit (DT3P slow) 23C 17 55 DRAM Case Temperature Rise from Ambient due to Page Open Burst Read/DT4R4W Mode Bit (DT4R/DT4R4W Mode Bit) 26C 34 56 DRAM Case Temperature Rise from Ambient due to Burst Refresh (DT5B) 35C 23 57 DRAM Case Temperature Rise from Ambient due to Bank Interleave Reads with Auto-Precharge (DT7) 37C 25 58 Thermal Resistance of PLL Package from Top (Case) to Ambient (Psi T-A PLL) 00 00 59 Thermal Resistance of Register Package from Top (Case) to Ambient (Psi T-A Register) 00 00 60 PLL Case Temperature Rise from Ambient due to PLL Active (DT PLL Active) 00 00 61 Resister Case Temperature Rise from Ambient due to Register Active/Mode Bit (DT Register Active/Mode Bit) 00 00 62 SPD Revision 1.2 12 63 Checksum for Byte 0-62 Checksum Data FA 64-71 Manufacturer's JEDEC ID Code NANYA 7F7F7F0B00000000 72 105ns Module Manufacturing Location 73-91 Module Part Number 92-255 Reserved Note1: M1N1G64TUH8A2B-37B REV 1.0 04/2006 69 Manufacturing code -- Module Part Number in ASCII -- Undefined -- 1 4D314E31473634545538484132462D33374220 6 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. M1N1G64TU8HA2B-37B (Green) 1GB : 128M x 64 PC2-4200 Unbuffered DDR2 SO-DIMM Absolute Maximum Ratings Symbol VIN, VOUT VDD Rating Units Voltage on I/O pins relative to Vss Parameter -0.5 to +2.3 V Voltage on VDD pins relative to Vss -1.0 to +2.3 V Voltage on VDDQ pins relative to Vss -0.5 to +2.3 V VDDL Voltage on VDDL pins relative to Vss -0.5 to +2.3 V TSTG Storage Temperature (Plastic) -55 to +100 C VDDQ Note: Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Operating temperature Conditions Symbol TCASE Note: 1. 2. Parameter Operating Temperature (Ambient) Rating Units Note 0 to 95 C 1 Case temperature is measured at top and center side of any DRAMs. tREFI = 3.9 9s tCASE > 85C DC Electrical Characteristics and Operating Conditions Symbol Parameter Min Max Units Notes VDD Supply Voltage 1.7 1.9 V 1 VDDL DLL Supply Voltage 1.7 1.9 V 1 VDDQ Output Supply Voltage 1.7 1.9 V 1 0 0 V 0.49VDDQ 0.51VDDQ V 1, 2 VREF - 0.04 VREF + 0.04 V 3 VSS, VSSQ VREF VTT Supply Voltage, I/O Supply Voltage Input Reference Voltage Termination Voltage Note: 1. Inputs are not recognized as valid until VREF stabilizes. 2. VREF is expected to be equal to 0.5 V DDQ of the transmitting device, and to track variations in the DC level of the same. Peak-to-peak noise on VREF may not exceed 2% of the DC value. 3. VTT of transmitting device must track VREF of receiving device. Input AC/DC logic level Symbol VIH (AC) Parameter Input High (Logic1) Voltage Min Max Units Notes VREF + 0.250 - V 1 1 VIL (AC) Input Low (Logic0) Voltage - VREF - 0.250 V VIH (DC) Input High (Logic1) Voltage VREF + 0.125 VDDQ + 0.3 V VIL (DC) Input Low (Logic0) Voltage -0.3 VREF - 0.125 V REV 1.0 04/2006 1 7 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. M1N1G64TU8HA2B-37B (Green) 1GB : 128M x 64 PC2-4200 Unbuffered DDR2 SO-DIMM Operating, Standby, and Refresh Currents TCASE = 0 C ~ 85 C; VDDQ = VDD = 1.8V 0.1V (1GB, 2 Ranks, 64Mx8 DDR2 SDRAMs) Symbol Parameter/Condition PC2-4200 Unit Notes (37B) IDD0 Operating Current: one bank; active/precharge; tRC = tRC (MIN); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle 800 mA 1 IDD1 Operating Current: one bank; active/read/precharge; Burst = 4; tRC = tRC (MIN); CL= 4; tCK = tCK (MIN); IOUT = 0mA; address and control inputs changing once per clock cycle 880 mA 1 IDD2P Precharge Power-Down Standby Current: all banks idle; power-down mode; CKE VIL (MAX); tCK = tCK (MIN) 80 mA 1 IDD2Q Precharge Quiet Stand by Current 640 mA 1 Idle Standby Current: CS VIH (MIN); all banks idle; CKE VIH (MIN); tCK = tCK (MIN); IDD2N address and control inputs changing once per clock cycle 480 mA 1 IDD3PF Active Power-Down Standby Current: one bank active; power-down mode; CKE VIL (MAX); tCK = tCK (MIN); Fast PDN Exit MRS(12) = 0mA 256 mA 1 IDD3PS Active Power-Down Standby Current: one bank active; power-down mode; CKE VIL (MAX); tCK = tCK (MIN); Slow PDN Exit MRS(12) = 1mA 80 mA 1 IDD3N Active Standby Current: one bank; active/precharge; CS VIH (MIN); CKE VIH (MIN); tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle 336 mA 1 Operating Current: one bank; Burst = 4; reads; continuous burst; address IDD4R and control inputs changing once per clock cycle; DQ and DQS outputs changing twice per clock cycle; CL = 4; tCK = tCK (MIN); IOUT = 0mA 960 mA 1 Operating Current: one bank; Burst = 4; writes; continuous burst; address IDD4W and control inputs changing once per clock cycle; DQ and DQS inputs changing twice per clock cycle; CL= 4; tCK = tCK (MIN) 1000 mA 1 1536 mA 1 80 mA 1 1520 mA 1 IDD5 Auto-Refresh Current: tRC = tRFC (MIN) IDD6 Self-Refresh Current: CKE 0.2V IDD7 Operating Current: four bank; four bank interleaving with BL = 4, address and control inputs randomly changing; 50% of data changing at every transfer; tRC = tRC (min); IOUT = 0mA. Note: 1. REV 1.0 04/2006 Module IDD was calculated from component IDD. It may different from the actual measurement. 8 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. M1N1G64TU8HA2B-37B (Green) 1GB : 128M x 64 PC2-4200 Unbuffered DDR2 SO-DIMM AC Timing Specifications for DDR2 SDRAM Devices Used on Module (TCASE = 0 C ~ 85 C; VDDQ = 1.8V 0.1V; VDD = 1.8V 0.1V, See AC Characteristics) (Part 1 of 2) Symbol tAC Max. DQ output access time from CK/ -0.5 +0.5 Unit -0.45 +0.45 ns tCH 0.45 0.55 tCK tCL CK low-level width 0.45 0.55 tCK tHP Minimum half clk period for any given cycle; defined by clk high (tCH) or clk low (tCL) time tCH or tCL - tCK tCK Clock Cycle Time 3.75 8 ns tDH DQ and DM input hold time 225 - ps tDS DQ and DM input setup time 100 - ps tIPW Input pulse width 0.6 - tCK DQ and DM input pulse width (each input) 0.35 - tCK - tAC max ns tHZ Data-out high-impedance time from CK/ tLZ(DQ) Data-out low-impedance time from CK/ 2tAC min tAC max ns tLZ(DQS) DQS low-impedance time from CK/ tAC min tAC max ns DQS-DQ skew (DQS & associated DQ signals) - 0.30 ns tQHS Data hold Skew Factor - 0.4 ns tQH Data output hold time from DQS tHP tQHS - ns Write command to 1st DQS latching transition -0.25 0.25 tCK DQS input low (high) pulse width (write cycle) 0.35 - tCK tDSS DQS falling edge to CK setup time (write cycle) 0.2 - tCK tDSH DQS falling edge hold time from CK (write cycle) 0.2 - tCK tMRD Mode register set command cycle time 2 - tCK tWPST Write postamble 0.40 0.60 tCK tWPRE Write preamble 0.35 - tCK tDQSQ tDQSS tDQSL,(H) tIH Address and control input hold time 375 - ps tIS Address and control input setup time 0.25 - ns tRPRE Read preamble 0.9 1.1 tCK tRPST Read postamble 0.4 0.6 tCK tIS + tCK + tIH - ns tDelay Minimum time clocks remains ON after CKE asynchronously drops Low tRFC Refresh to active/Refresh command time 105 ns Average Periodic Refresh Interval (85C < TCASE : 95C) 3.9 9s Average Periodic Refresh Interval (0C : TCASE : 85C) 7.8 9s tREFI tRRD Active bank A to Active bank B command 7.5 - Notes ns DQS output access time from CK/ tDIPW 04/2006 Min. CK high-level width tDQSCK REV 1.0 -37B Parameter ns 9 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. M1N1G64TU8HA2B-37B (Green) 1GB : 128M x 64 PC2-4200 Unbuffered DDR2 SO-DIMM AC Timing Specifications for DDR2 SDRAM Devices Used on Module (TCASE = 0 C ~ 85 C; VDDQ = 1.8V 0.1V; VDD = 1.8V 0.1V, See AC Characteristics) (Part 2 of 2) Symbol tCCD -37B Parameter Min. to Max. 2 tWR Write recovery time WR Write recovery time with Auto-Precharge 15 Unit tCK - tWR/tCK ns ns tDAL Auto precharge write recovery + precharge time WR +tRP tWTR Internal write to read command delay 7.5 tRTP Internal read to precharge command delay 7.5 ns tXSNR Exit self refresh to a Non-read command tRFC +10 ns tXSRD Exit self refresh to a Read command 200 tCK - tCK - ns Exit precharge power down to any Non- read command 2 - tCK tXARD Exit active power down to read command 2 - tCK tXARDS Exit active power down to read command 6-AL - tCK tXP Notes tCKE CKE minimum pulse width 3 - tCK tOIT OCD drive mode output delay 0 12 ns 2 2 tCK tAC tAC ODT tAOND tAON tAONPD ODT turn-on delay ODT turn-on (min) ODT turn-on (Power down mode) 2tCK + tAC(min) tAC(max) +2 +1 ns ns 2.5 2.5 tCK ODT turn-off tAC(min) tAC(max) +0.6 ns tAOFPD ODT turn-off (Power down mode) 2.5tCK + tAC(min) t +2 AC(max) +1 ns tANPD ODT to power down entry latency 3 tCK tAXPD ODT power down exit latency 8 tCK tAOFD tAOF ODT turn-off delay (max) +1 Speed Grade Definition REV 1.0 04/2006 tRAS Row Active Time 45 70000 ns tRCD RAS to CAS delay 15 - ns tRC Row Cycle Time 60 - ns tRP Row Precharge Time 15 - ns 10 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. M1N1G64TU8HA2B-37B (Green) 1GB : 128M x 64 PC2-4200 Unbuffered DDR2 SO-DIMM Package Dimensions (1GB, 2Ranks, 64Mx8 DDR2 SDRAMs) FRONT 67.60 30.00 20.00 6.00 4.00 63.60 (2X) 1.80 1 2.15 39 41 11.40 199 Detail A Detail B 4.20 47.40 2.70 2.45 BACK SIDE 3.80 MAX 1.00+/- 0.10 Detail B 0.45 0.60 1.00+/- 0.1 2.55 4.00+/-0.10 0.25 MAX Detail A Note: All dimensions are typical with tolerances of +/- 0.15 unless otherwise stated. Units: Millimeters (Inches) REV 1.0 04/2006 11 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. M1N1G64TU8HA2B-37B (Green) 1GB : 128M x 64 PC2-4200 Unbuffered DDR2 SO-DIMM Revision Log Rev Date 1.0 04/2006 Modification Official release. Nanya Technology Corporation Hwa Ya Technology Park 669 Fu Hsing 3rd Rd., Kueishan, Taoyuan, 333, Taiwan, R.O.C. Tel: +886-3-328-1688 Please visit our home page for more information: www.elixir-memory.com Printed in Taiwan (c)2006 REV 1.0 04/2006 12 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice.