IBM043610ULAB4M x 1612/10, 3.3VMMDM15DSU-021044922. Preliminary IBM041810ULAB IBM043610ULAB 32K X 36 & 64K X 18 SRAM Features * 32K x 36 or 64K x 18 Organizations * 0.45 Micron CMOS Technology * Synchronous Flow Thru Mode of Operation with Self-Timed Late Write * Single Differential PECL Clock compatible with LVTTL Levels * Single +3.3V Power Supply and Ground * Common I/O * 3.3V and 2.5V LVTTL I/O Compatible * Registered Addresses, Write Enables, Synchronous Select, and Data Ins * Asynchronous Output Enable and Power Down Inputs * Boundary Scan using limited set of JTAG 1149.1 functions * Byte Write Capability & Global Write Enable * 7 X 17 Bump Ball Grid Array Package with SRAM JEDEC Standard Pinout and Boundary SCAN Order Description The IBM043610ULAB and IBM041810ULAB 1Mb SRAMS are Synchronous Flowthru Mode, high-performance CMOS Static Random Access Memories that are versatile, have wide I/O, and achieve 6ns cycle time. Differential K clocks are used to initiate the read/write operation, and all internal operations are self-timed. At the rising edge of the K clock, all 88H5752.T2 11/98 Addresses, Write-Enables, Sync Select, and Data Ins are registered internally. An internal Write buffer allows write data to follow one cycle after addresses and controls. The chip is operated with a single +3.3V power supply and is compatible with LVTTL I/O interfaces. (c)IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 1 of 22 IBM041810ULAB IBM043610ULAB 32K X 36 & 64K X 18 SRAM Preliminary X36 BGA Pinout (Top View) 1 2 3 4 5 6 7 A VDDQ SA8 B NC NC SA7 NC SA4 SA3 VDDQ NC NC NC NC NC C NC SA9 SA6 VDD SA5 SA2 NC D DQ23 DQ18 VSS NC VSS DQ17 DQ12 E DQ19 DQ24 VSS SS VSS DQ11 DQ16 F VDDQ DQ20 VSS G VSS DQ15 VDDQ G DQ21 DQ25 SBWc NC SBWb DQ10 DQ14 H DQ26 DQ22 VSS NC VSS DQ13 DQ9 J VDDQ VDD NC VDD NC VDD VDDQ K DQ27 DQ31 VSS K VSS DQ4 DQ8 L DQ32 DQ28 SBWd K SBWa DQ7 DQ3 M VDDQ DQ33 VSS SW VSS DQ2 VDDQ N DQ34 DQ29 VSS SA1 VSS DQ6 DQ1 P DQ30 DQ35 VSS SA0 VSS DQ0 DQ5 M2* SA10 NC SA11 NC ZZ NC VDDQ R NC SA14 M1* VDD T NC NC SA13 SA12 U VDDQ TMS TDI TCK TDO Note: * M1 and M2 are read protocol mode pins. For this application, M1 and M2 must be connected to VSS and VSS, respectively. X18 BGA Pinout (Top View) 1 2 3 4 5 6 7 A VDDQ SA8 SA7 NC SA4 SA3 VDDQ B NC NC NC NC NC NC NC C NC SA9 SA6 VDD SA5 SA2 NC D DQ9 NC VSS NC VSS DQ8 NC E NC DQ10 VSS SS VSS NC DQ7 F VDDQ NC VSS G VSS DQ6 VDDQ G NC DQ11 SBWb NC NC NC DQ5 H DQ12 NC VSS NC VSS DQ4 NC J VDDQ VDD NC VDD NC VDD VDDQ K VSS NC DQ3 K SBWa DQ2 NC NC VDDQ DQ1 NC K NC DQ13 VSS L DQ14 NC NC M VDDQ DQ15 VSS SW VSS N DQ16 NC VSS SA1 VSS P NC DQ17 VSS SA0 VSS NC DQ0 R NC SA15 M1 VDD M2 SA11 NC T NC SA13 SA14 NC SA12 SA10 ZZ U VDDQ TMS TDI TCK TDO NC VDDQ Note: * M1 and M2 are read protocol mode pins. For this application, M1 and M2 must be connected to VSS and VSS, respectively. (c)IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 2 of 22 88H5752.T2 11/98 IBM041810ULAB IBM043610ULAB 32K X 36 & 64K X 18 SRAM Preliminary Pin Description SA0-SA15 Address Input DQ0-DQ35 Data I/O TDO SS IEEE 1149 Test Output Synchronous Select K, K Differential PECL CLocks (LVTTL Compatible) SW Write Enable, global VDD Power Supply (+3.3V) SBWa Write Enable, Byte a (DQ0 to DQ8) VSS Ground SBWb Write Enable, Byte b (DQ9 to DQ17) VDDQ SBWc Write Enable, Byte c (DQ18 to DQ26) G Asynchronous Output Enable SBWd Write Enable, Byte d (DQ27 to DQ35) ZZ Asynchronous Sleep Mode IEEE 1149 Test Inputs NC No Connect TMS,TDI,TCK M1, M2 Mode Inputs- Selects Read Protocol Operation Output Power Supply Block Diagram WR Add Register 2:1 MUX RD Add Register Latch ZZ SW SW Register SW Register SBW Register SBW Register Row Decode SA0-SA15 K SS 32Kx36 or 64K x18 Array Column Decode Read/Write Amp SBW Latch Match 2:1 MUX Write Buffer SS Register SS Register Data Out Latch G DQ0-DQ35 88H5752.T2 11/98 (c)IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 3 of 22 IBM041810ULAB IBM043610ULAB 32K X 36 & 64K X 18 SRAM Preliminary SRAM Features Late Write Late Write function allows for write data to be registered one cycle after addresses and controls. This feature eliminates one bus-turnaround cycle necessary when going from a Read to a Write operation. Late Write is accomplished by buffering write addresses and data so that the write operation occurs during the next write cycle. In case a read cycle occurs after a write cycle, the address and write data information are stored temporarily in holding registers. During the first write cycle preceded by a read cycle, the SRAM array will be updated with the address and data from the holding registers. Read cycle addresses are monitored to determine if read data is to be supplied from the SRAM array or the write buffer. The bypassing of the SRAM array data occurs on a byte-by-byte basis. When one byte is written during a write cycle, read data from the last written address will have new byte data from the write buffer and remaining bytes from the SRAM array. Mode Control Mode control pins M1 and M2 are used to select four different JEDEC standard read protocols. The SRAM supports the following protocols: * Single Clock, Flow-Thru (M1 = VSS, M2 = VSS) * Pipeline (M1 = VSS, M2 = VDD) * Flow Thru (M1 = VDD, M2 = VSS) This datasheet only describes Flow Thru functionality. Mode control inputs must be set with power-up and must not change during SRAM operation. Sleep Mode Sleep Mode is accomplished by switching asynchronous signal ZZ high. When the SRAM is in Sleep Mode, the outputs will go to a High-Z state and the SRAM will draw standby current. SRAM data will not be preserved and a recovery time (tZZR) followed by four "K-clock" cycles are required before the SRAM resumes normal operation. Power-Up Requirements In order to guarantee the optimum internally regulated supply voltage, the SRAM requires 4s of power-up time after VDD reaches its operating range. Power-Up/Power-Down Sequencing The Power supplies need to be powered up in the following manner: GND, VDD, VDDQ, and Inputs. The power-down sequencing must be the reverse. VDDQ must never be allowed to exceed VDD. Ordering Information Part Number Organization IBM041810ULAB - 6F IBM041810ULAB - 6 64K x 18 IBM043610ULAB - 6F IBM043610ULAB - 6 Leads 7.0ns Access / 6.0ns Cycle 6.0ns Access / 6.0ns Cycle 32K x 36 (c)IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 4 of 22 Speed 6.0ns Access / 6.0ns Cycle 7 X 17 BGA 7.0ns Access / 6.0ns Cycle 88H5752.T2 11/98 IBM041810ULAB IBM043610ULAB 32K X 36 & 64K X 18 SRAM Preliminary Clock Truth Table K ZZ SS SW SBWa SBWb SBWc SBWd DQ (n) DQ (n+1) Mode LH L L H X X X X DOUT 0-35 X Read Cycle All Bytes LH L L L L H H H X DIN 0-8 Write Cycle 1st Byte LH L L L H L H H X DIN 9-17 Write Cycle 2nd Byte LH L L L H H L H X DIN 18-26 Write Cycle 3rd Byte LH L L L H H H L X DIN 27-35 Write Cycle 4th Byte LH L L L L L L L X DIN 0-35 Write Cycle All Bytes LH L L L H H H H High-Z X Abort Write Cycle LH L H X X X X X High-Z X Deselect Cycle X H X X X X X X High-Z High-Z Sleep Mode Output Enable Truth Table Operation G DQ Read L DOUT 0-35 Read H High-Z Sleep (ZZ=H) X High-Z Write (SW=L) X High-Z Deselect (SS=H) X High-Z 88H5752.T2 11/98 (c)IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 5 of 22 IBM041810ULAB IBM043610ULAB 32K X 36 & 64K X 18 SRAM Preliminary Absolute Maximum Ratings Item Symbol Rating Units Notes VDD -0.5 to 4.0 V 1 VDDQ -0.5 to 4.0 V 1 VIN -0.5 to VDD+0.5 V 1 VOUT -0.5 to VDD+0.5 V 1 Operating Temperature TA 0 to +70 C 1 Junction Temperature TJ 110 C 1 Storage Temperature TSTG -55 to +125 C 1 Short Circuit Output Current IOUT 25 mA 1 ILI >200 mA Power Supply Voltage Output Power Supply Voltage Input Voltage Output Voltage Latchup Current 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. (c)IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 6 of 22 88H5752.T2 11/98 IBM041810ULAB IBM043610ULAB 32K X 36 & 64K X 18 SRAM Preliminary Recommended DC Operating Conditions Parameter (TA = 0 to 70C) Symbol Min. Typ. Max. Units Notes VDD 3.135 3.3 3.465 V 1 VDDQ 2.375 2.5 3.465 V 1 Input High Voltage VIH 2.0 -- VDD+0.3 V 1, 2, 4 Input Low Voltage VIL -0.3 -- 0.8 V 1, 3, 4 DQ Input High Voltage VIHdQ 1.85 -- VDD+0.3 V 1, 2 DQ Input Low Voltage VILDQ -0.3 -- 1.15 V 1, 3 PECL Clock Input High Voltage VIH - PECL 2.135 -- 2.420 V 1, 2 PECL Clock Input Low Voltage VIL - PECL 1.490 -- 1.825 V 1, 3 Iout -- 5 8 mA Core Supply Voltage Output Driver Supply Voltage Output Current 1. 2. 3. 4. All voltages referenced to VSS. All VDD, VDDQ, and VSS pins must be connected. VIH(Max)DC = VDD + 0.3 V, VIH(Max)AC = VDD + 1.5 V (pulse width 4.0ns). VIL(Min)DC = - 0.3 V, VIL(Min)AC = -1.5 V (pulse width 4.0ns). It does not include DQs. DC Electrical Characteristics (TA = 0 to +70C, VDD = 3.3V 5%) Symbol Min. Max. Units Notes Average Power Supply Operating Current - X36 (IOUT = 0, VIN = VIH or VIL , ZZ & SS = VIL) IDD6 -- 475 mA 1 Average Power Supply Operating Current - X18 (IOUT = 0, VIN = VIH or VIL, ZZ & SS = VIL) IDD6 -- 450 mA 1 Power Supply Standby Current (SS = VIH, and ZZ = VIH All other inputs = VIH or VIL, IOUT = 0) ISB -- 25 mA 1 Input Leakage Current, any input, except TDI, TMS, TCK (VIN = VSS or VDD) ILI -2 +2 A Output Leakage Current (VOUT = VSS or VDD, DQ in High-Z) ILO -2 +2 A Output High "H" Level Voltage (IOH=-8mA @ 2.4V) for VDDQ=3.3V. VOH 2.4 -- V Output Low "L" Level Voltage (IOL=+8mA @ 0.4V) for VDDQ=3.3V. VOL -- 0.4 V Output High "H" Level Voltage (IOH=-8mA @ 1.6V) for VDDQ=2.5V. VOH 1.6 -- V Output Low "L" Level Voltage (IOL=+8mA @ 0.4V) for VDDQ=2.5V. VOL -- 0.4 V Parameter 1. IOUT = Chip Output Current. 88H5752.T2 11/98 (c)IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 7 of 22 IBM041810ULAB IBM043610ULAB 32K X 36 & 64K X 18 SRAM Preliminary Capacitance (TA = 0 to +70C, VDD = 3.3V 5%, f = 1MHz) Parameter Input Capacitance Data I/O Capacitance (DQ0-DQ35) Symbol Test Condition Max Units CIN VIN = 0V 4 pF COUT VOUT = 0V 5 pF AC Test Conditions (TA = 0 to +70C, VDD = 3.3V 5%, VDDQ = 3.3V -5%, +5%) Parameter Symbol Conditions Units Input High Level for 3.3V I/O VIH(3.3V) 3.0 V Input Low Level for 3.3V I/O VIL(3.3V) 0.0 V Input High Level for 2.5V I/O VIH(2.5V) 2.25 V 2, 3 Input Low Level for 2.5V I/O VIL(2.5V) 0.25 V 2, 3 DQ Input High Level VDQIH(2.5V) 1.85 V 2 DQ Input Low Level VDQIL(2.5V) 1.15 V 2 PECL Clock Input High Voltage VIH-PECL 2.4 V PECL Clock Input Low Voltage VIL-PECL 1.5 V Input Rise Time TR 1.0 ns Input Fall Time TF 1.0 ns PECL Clock Input Rise Time TR-PECL 0.5 ns PECL Clock Input Fall Time TF-PECL 0.5 ns 1.5 V K and K Cross Point V Input and Output Timing Reference Level (except K,K) PECL Clock Reference Level Output Load Conditions Notes 1 1. See AC Test Loading on page 11. 2. Tested with tDVKH = 0.5ns, without guardbands. 3. Does not include DQs. (c)IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 8 of 22 88H5752.T2 11/98 IBM041810ULAB IBM043610ULAB 32K X 36 & 64K X 18 SRAM Preliminary AC Test Loading 50 16.7 50 16.7 1.25V 5pF DQ 50 16.7 50 1.25V 5pF 1.25V 88H5752.T2 11/98 (c)IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 9 of 22 IBM041810ULAB IBM043610ULAB 32K X 36 & 64K X 18 SRAM Preliminary AC Characteristics (TA = 0 to +70C, VDD = 3.3V 5%, VDDQ = 3.3V -5%, +5%) Parameter Symbol -6F -6 Min. Max. Min. Max. Units Notes Cycle Time tKHKH 6.0 -- 6.0 -- ns Clock High Pulse Width tKHKL 2.0 -- 2.0 -- ns Clock Low Pulse Width tKLKH 2.0 -- 2.0 -- ns Clock High to Output Valid tKHQV -- 6.0 -- 7.0 ns Address Setup Time tAVKH 0.5 -- 0.5 -- ns Address Hold Time tKHAX 1.0 -- 1.0 -- ns Sync Select Setup Time tSVKH 0.5 -- 0.5 -- ns Sync Select Hold Time tKHSX 1.0 -- 1.0 -- ns Write Enables Setup Time tWVKH 0.5 -- 0.5 -- ns Write Enables Hold Time tKHWX 1.0 -- 1.0 -- ns Data In Setup Time tDVKH 0.5 -- 0.5 -- ns Data In Hold Time tKHDX 1.0 -- 1.0 -- ns Clock High to Data Out Hold Time tKHQX 2.0 -- 2.0 -- ns 1 Clock High to Output Active tKHQX4 2.0 -- 2.0 -- ns 1 Clock High to Output High-Z tKHQZ -- 2.5 -- 3.0 ns 1 Output Enable to High-Z tGHQZ -- 3.0 -- 3.0 ns 1 Output Enable to Low-Z tGLQX 2.5 -- 2.5 -- ns 1 Output Enable to Output Valid 1 tGLQV -- 2.5 -- 2.5 ns Sleep Mode Recovery TIme tZZR 100 -- 100 -- ns Sleep Mode Enable TIme tZZE -- 6.0 -- 6.0 ns 1 1. See AC Test Loading on page 11. (c)IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 10 of 22 88H5752.T2 11/98 IBM041810ULAB IBM043610ULAB 32K X 36 & 64K X 18 SRAM Preliminary Timing Diagram (Read and Deselect Cycles) tKLKH tKHKL tKHKH K tAVKH A1 SA A2 A3 A3 A4 tKHSX tKHAX SS tWVKH tSVKH SW tGLQV tKHWX tKHQZ tKHQV G tGHQZ Q3 Q2 DQ tGLQX Q4 tKHQX tKHQZ tKHQX4 tKHQV tKHQV tKHQV 88H5752.T2 11/98 (c)IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 11 of 22 IBM041810ULAB IBM043610ULAB 32K X 36 & 64K X 18 SRAM Preliminary Timing Diagram (Read and Write Cycles) tKLKH tKHKH tKHKL K tAVKH SA A2 A1 A3 A2 A4 tKHAX tSVKH SS tKHSX tKHWX tKHWX SW tWVKH tWVKH tKHWX tKHWX SBW tWVKH tWVKH tKHQV G tGHQZ tKHQZ tKHQX4 Q1 DQ D2 tKHQV Q3 D4 Q2 tKHDX tKHQV tDVKH tDVKH tKHDX NOTES: 1. D2 is the input data written in memory location A2. 2. Q2 is output data read from the write buffer, as a result of address A2 being a match from the last write cycle address. (c)IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 12 of 22 88H5752.T2 11/98 IBM041810ULAB IBM043610ULAB 32K X 36 & 64K X 18 SRAM Preliminary Timing Diagram (Sleep Mode) tKHKH K ZZ tZZR tZZE DQ 88H5752.T2 11/98 (c)IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 13 of 22 IBM041810ULAB IBM043610ULAB 32K X 36 & 64K X 18 SRAM Preliminary IEEE 1149.1 TAP AND BOUNDARY SCAN The SRAM provides a limited set of JTAG functions intended to test the interconnection between SRAM I/Os and printed circuit board traces or other components. There is no multiplexer in the path from I/O pins to the RAM core. In conformance with IEEE std. 1149.1, the SRAM contains a TAP controller, Instruction register, Boundary Scan register, Bypass register, and ID register. The TAP controller has a standard 16-state machine that resets internally upon power-up; therefore, TRST signal is not required. Signal List * * * * TCK: TMS: TDI: TDO: Test Clock Test Mode Select Test Data In Test Data Out Caution: TCK, TMS, TDI inputs must be biased to a valid logic level, even if JTAG is not used. JTAG Recommended DC Operating Conditions (TA = 0 to 70C) Parameter Symbol Min. Max. Units Notes JTAG Input High Voltage VIH1 2.2 VDD+0.3 V 1 JTAG Input Low Voltage VIL1 -0.3 0.8 V 1 JTAG Output High Level VOH1 2.4 -- V 1, 2 JTAG Output Low Level VOL1 -- 0.4 V 1, 3 JTAG Input Leakage Current (VIN = VSS or VDD) IJTAG -- +50 A 4 1. 2. 3. 4. All JTAG Inputs/Outputs are LVTTL Compatible only. IOH1 = -8mA at 2.4V. IOL1 = +8mA at 0.4V. If JTAG is not used, signals TCK, TMS, and TDI may be left floating. These inputs are defaulted to VDD. JTAG AC Test Conditions (TA = 0 to +70C, VDD = 3.3V -5% +10%) Parameter Symbol Conditions Units Input Pulse High Level VIH1 3.0 V Input Pulse Low Level VIL1 0.0 V Input Rise Time TR1 2.0 ns Input Fall Time TF1 2.0 ns 1.5 V Input and Output Timing Reference Level Notes 1 1. See AC Test Loading on page 11. (c)IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 14 of 22 88H5752.T2 11/98 IBM041810ULAB IBM043610ULAB 32K X 36 & 64K X 18 SRAM Preliminary JTAG AC Characteristics (TA = 0 to +70C, VDD = 3.3V -5% +10%) Symbol Min. Max. Units TCK Cycle Time Parameter tTHTH 20 -- ns TCK High Pulse Width tTHTL 7 -- ns TCK Low Pulse Width tTLTH 7 -- ns TMS Setup tMVTH 4 -- ns TMS Hold tTHMX 4 -- ns TDI Setup tDVTH 4 -- ns TDI Hold tTHDX 4 -- ns TCK Low to Valid Data tTLOV -- 7 ns Notes 1 1. See AC Test Loading on page 11. JTAG Timing Diagram tTHTL tTHTH tTLTH TCK tTHMX TMS tTHDX tMVTH TDI tDVTH TDO tTLOV 88H5752.T2 11/98 (c)IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 15 of 22 IBM041810ULAB IBM043610ULAB 32K X 36 & 64K X 18 SRAM Preliminary Scan Register Definition Register Name Bit Size X18 Bit Size X36 Instruction 3 3 Bypass 1 1 ID 32 32 Boundary Scan1,2 51 70 1. The Boundary Scan chain consists of the following bits: * 36 or 18 bits for Data Inputs depending on X18 or X36 Configuration * 15 bits for SA0 - SA14 for X36, 16 bits for SA0 - SA15 for X18 * 4 bits for SBWa - SBWd in X36, 2 bits for SBWa and SBWb in X18 * 8 bits for K, K, SS, G, SW, ZZ, M1 and M2 * 7 bits for Place Holders 2. K and K clocks connect to a differential receiver that generates a single-ended clock signal. This signal and its inverted value are used for Boundary Scan sampling. ID Register Definition Field Bit Number and Description Part Revision Number (31:28) Device Density and Configuration (27:18) Vendor Definition (17:12) Manufacture JEDEC Code (11:1) Start Bit(0) 64K X 18 TBD 001 000 0011 TBD 000 101 001 00 1 32K X 36 TBD 000 110 0100 TBD 000 101 001 00 1 Instruction Set Code Instruction Notes 000 SAMPLE-Z 1 001 IDCODE 1 010 SAMPLE-Z 1 011 PRIVATE 5 100 SAMPLE 4 101 PRIVATE 5 110 PRIVATE 5 111 BYPASS 3 1. Places DQs in High-Z in order to sample all input data regardless of other SRAM inputs. 2. TDI is sampled as an input to the first ID register to allow for the serial shift of the external TDI data. 3. BYPASS register is initiated to VSS when BYPASS instruction is invoked. The BYPASS register also holds the last serially loaded TDI when exiting the Shift DR state. 4. SAMPLE instruction does not place DQs in High-Z. 5. This instruction is reserved for the exclusive use of IBM. Invoking this instruction will cause improper SRAM functionality. List of IEEE 1149.1 standard violations: * 7.2.1.b, e * 7.7.1.a-f * 10.1.1.b, e * 0.7.1.a-d (c)IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 16 of 22 88H5752.T2 11/98 IBM041810ULAB IBM043610ULAB 32K X 36 & 64K X 18 SRAM Preliminary Boundary Scan Order (X36) (PH =Place Holder) Exit Order Signal Bump # Exit Order Signal Bump # Exit Order Signal Bump # 1 M2 5R 25 DQ15 6F 49 DQ22 2H 2 SA0 4P 26 DQ16 7E 50 DQ26 1H 3 SA12 4T 27 DQ11 6E 51 SBWc 3G 4 SA10 6R 28 DQ12 7D 52 PH1 4D 5 SA11 5T 29 DQ17 6D 53 SS 4E 6 ZZ 7T 30 SA3 6A 54 PH1 4G 7 DQ0 6P 31 SA2 6C 55 PH2 4H 8 DQ5 7P 32 SA5 5C 56 SW 4M 9 DQ6 6N 33 SA4 5A 57 SBWd 3L 10 DQ1 7N 34 PH1 6B 58 DQ27 1K 11 DQ2 6M 35 PH1 5B 59 DQ31 2K 12 DQ7 6L 36 PH1 3B 60 DQ32 1L 13 DQ3 7L 37 PH1 2B 61 DQ28 2L 14 DQ4 6K 38 SA7 3A 62 DQ33 2M 15 DQ8 7K 39 SA6 3C 63 DQ34 1N 16 SBWa 5L 40 SA9 2C 64 DQ29 2N 17 K 4L 41 SA8 2A 65 DQ30 1P 18 K 4K 42 DQ18 2D 66 DQ35 2P 19 G 4F 43 DQ23 1D 67 SA13 3T 20 SBWb 5G 44 DQ24 2E 68 SA14 2R 21 DQ9 7H 45 DQ19 1E 69 SA1 4N 22 DQ13 6H 46 DQ20 2F 70 M1 3R 23 DQ14 7G 47 DQ25 2G 24 DQ10 6G 48 DQ21 1G 1. Input of PH register connected to VSS. 2. Input of PH register connected to VDD. 88H5752.T2 11/98 (c)IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 17 of 22 IBM041810ULAB IBM043610ULAB 32K X 36 & 64K X 18 SRAM Preliminary Boundary Scan Order (X18) Exit Order Signal Bump # Exit Order Signal Bump # 1 M2 5R 27 PH1 2B 2 SA10 6T 28 SA7 3A 3 SA0 4P 29 SA6 3C 4 SA11 6R 30 SA9 2C 5 SA12 5T 31 SA8 2A 6 ZZ 7T 32 DQ9 1D 7 DQ0 7P 33 DQ10 2E 8 DQ1 6N 34 DQ11 2G 9 DQ2 6L 35 DQ12 1H 10 DQ3 7K 36 SBWb 3G 11 SBWa 5L 37 PH1 4D 12 K 4L 38 SS 4E 13 K 4K 39 PH1 4G 14 G 4F 40 PH2 4H 15 DQ4 6H 41 SW 4M 16 DQ5 7G 42 DQ13 2K 17 DQ6 6F 43 DQ14 1L 18 DQ7 7E 44 DQ15 2M 19 DQ8 6D 45 DQ16 1N 20 SA3 6A 46 DQ17 2P 21 SA2 6C 47 SA14 3T 22 SA5 5C 48 SA15 2R 23 SA4 5A 49 SA1 4N 24 PH1 6B 50 SA13 2T 25 PH1 5B 51 M1 3R 26 PH1 3B 1. Input of PH register connected to VSS. 2. Input of PH register connected to VDD. (c)IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 18 of 22 88H5752.T2 11/98 IBM041810ULAB IBM043610ULAB 32K X 36 & 64K X 18 SRAM Preliminary TAP Controller State Machine 1 Test Logic Reset 0 0 Run Test Idle 1 1 Select DR 0 0 1 1 Select IR 1 Capture IR Capture DR 0 0 0 Shift IR 0 Shift DR 1 1 1 1 Exit1 IR Exit1 DR 0 0 0 0 Pause DR Pause IR 1 1 Exit2 DR Exit2 IR 0 1 1 88H5752.T2 11/98 1 Update DR 0 0 Update IR 1 0 (c)IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 19 of 22 IBM041810ULAB IBM043610ULAB 32K X 36 & 64K X 18 SRAM Preliminary 7 x 17 BGA Dimensions 20.32 0.84 REF (119X) 0.75 0.15 Solder Ball 0.030" 0.006 7 6 3.19 REF 5 4 3 2 1 U T R P N M L K 7.62 1.27 J H G F E D C B A 12.00 0.25 14.00 22.00 Indicates A0 Location 20 0.25 1 0.25 Feature is for Lead Pin IDENTIFICATION Overmold 0.66 0.05 1.0 0.1 0.600 0.10 Typ 2.26 0.15 (c)IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 20 of 22 88H5752.T2 11/98 IBM041810ULAB IBM043610ULAB 32K X 36 & 64K X 18 SRAM Preliminary 11/98 Revision Log Revision Contents of Modification 9/3/98 Initial Release. 11/98 Changed part numbers from Rev A to B. 88H5752.T2 11/98 (c)IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 21 of 22 International Business Machines Corp.1998 Copyright Printed in the United States of America All rights reserved IBM and the IBM logo are registered trademarks of the IBM Corporation. This document may contain preliminary information and is subject to change by IBM without notice. IBM assumes no responsibility or liability for any use of the information contained herein. Nothing in this document shall operate as an express or implied license or indemnity under the intellectual property rights of IBM or third parties. The products described in this document are not intended for use in implantation or other direct life support applications where malfunction may result in direct physical harm or injury to persons. NO WARRANTIES OF ANY KIND, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, ARE OFFERED IN THIS DOCUMENT. For more information contact your IBM Microelectronics sales representative or visit us on World Wide Web at http://www.chips.ibm.com IBM Microelectronics manufacturing is ISO 9000 compliant.