IBM043610ULAB-6 - IBM Microelectronics

88H5752.T2

Use is further subject to the provisions at the end of this document.

Page 1 of 22

IBM041810ULAB

IBM043610ULAB

Preliminary 32K X 36 & 64K X 18 SRAM

Features

• 32K x 36 or 64K x 18 Organizations

• 0.45 Micron CMOS Technology

• Synchronous Flow Thru Mode of Operation with

Self-Timed Late Write

• Single Differential PECL Clock compatible with

LVTTL Levels

• Single +3.3V Power Supply and Ground

• Common I/O

• 3.3V and 2.5V LVTTL I/O Compatible

• Registered Addresses, Write Enables, Synchro-

nous Select, and Data Ins

• Asynchronous Output Enable and Power Down

Inputs

• Boundary Scan using limited set of JTAG 1149.1

functions

• Byte Write Capability & Global Write Enable

• 7 X 17 Bump Ball Grid Array Package with

SRAM JEDEC Standard Pinout and Boundary

SCAN Order

Description

The IBM043610ULAB and IBM041810ULAB 1Mb

SRAMS are Synchronous Flowthru Mode, high-per-

formance CMOS Static Random Access Memories

that are versatile, have wide I/O, and achieve 6ns

cycle time. Differential K clocks are used to initiate

the read/write operation, and all internal operations

are self-timed. At the rising edge of the K clock, all

Addresses, Write-Enables, Sync Select, and Data

Ins are registered internally. An internal Write buffer

allows write data to follow one cycle after addresses

and controls. The chip is operated with a single

+3.3V power supply and is compatible with LVTTL

I/O interfaces.

IBM043610ULAB4M x 1612/10, 3.3VMMDM15DSU-021044922.

IBM041810ULAB

IBM043610ULAB

32K X 36 & 64K X 18 SRAM Preliminary

Use is further subject to the provisions at the end of this document.

Page 2 of 22

88H5752.T2

11/98

X36 BGA Pinout (Top View)

1234567

AVDDQ SA8 SA7 NC SA4 SA3 VDDQ

BNC NC NC NC NC NC NC

CNC SA9 SA6 VDD SA5 SA2 NC

DDQ23 DQ18 VSS NC VSS DQ17 DQ12

EDQ19 DQ24 VSS SS VSS DQ11 DQ16

FVDDQ DQ20 VSS GVSS DQ15 VDDQ

GDQ21 DQ25 SBWc NC SBWb DQ10 DQ14

HDQ26 DQ22 VSS NC VSS DQ13 DQ9

JVDDQ VDD NC VDD NC VDD VDDQ

KDQ27 DQ31 VSS KVSS DQ4 DQ8

LDQ32 DQ28 SBWd K SBWa DQ7 DQ3

MVDDQ DQ33 VSS SW VSS DQ2 VDDQ

NDQ34 DQ29 VSS SA1 VSS DQ6 DQ1

PDQ30 DQ35 VSS SA0 VSS DQ0 DQ5

RNC SA14 M1* VDD M2* SA10 NC

TNC NC SA13 SA12 SA11 NC ZZ

UVDDQ TMS TDI TCK TDO NC VDDQ

Note: * M1 and M2 are read protocol mode pins. For this application, M1 and M2 must be connected to VSS and VSS, respec-

tively.

X18 BGA Pinout (Top View)

1234567

AVDDQ SA8 SA7 NC SA4 SA3 VDDQ

BNC NC NC NC NC NC NC

CNC SA9 SA6 VDD SA5 SA2 NC

DDQ9 NC VSS NC VSS DQ8 NC

ENC DQ10 VSS SS VSS NC DQ7

FVDDQ NC VSS GVSS DQ6 VDDQ

GNC DQ11 SBWb NC NC NC DQ5

HDQ12 NC VSS NC VSS DQ4 NC

JVDDQ VDD NC VDD NC VDD VDDQ

KNC DQ13 VSS KVSS NC DQ3

LDQ14 NC NC K SBWa DQ2 NC

MVDDQ DQ15 VSS SW VSS NC VDDQ

NDQ16 NC VSS SA1 VSS DQ1 NC

PNC DQ17 VSS SA0 VSS NC DQ0

RNC SA15 M1 VDD M2 SA11 NC

TNC SA13 SA14 NC SA12 SA10 ZZ

UVDDQ TMS TDI TCK TDO NC VDDQ

Note: * M1 and M2 are read protocol mode pins. For this application, M1 and M2 must be connected to VSS and VSS, respec-

tively.

IBM041810ULAB

IBM043610ULAB

Preliminary 32K X 36 & 64K X 18 SRAM

88H5752.T2

Use is further subject to the provisions at the end of this document.

Page 3 of 22

Pin Description

SA0-SA15 Address Input TDO IEEE 1149 Test Output

DQ0-DQ35 Data I/O SS Synchronous Select

K, K Differential PECL CLocks (LVTTL Compati-

ble) M1, M2 Mode Inputs- Selects Read Protocol Operation

SW Write Enable, global VDD Power Supply (+3.3V)

SBWa Write Enable, Byte a (DQ0 to DQ8) VSS Ground

SBWb Write Enable, Byte b (DQ9 to DQ17) VDDQ Output Power Supply

SBWc Write Enable, Byte c (DQ18 to DQ26) G Asynchronous Output Enable

SBWd Write Enable, Byte d (DQ27 to DQ35) ZZ Asynchronous Sleep Mode

TMS,TDI,TCK IEEE 1149 Test Inputs NC No Connect

Block Diagram

32Kx36

64K x18

Buffer

Write

Column Decode

Read/Write Amp

Row Decode

2:1 MUX

Data Out

Latch

DQ0-DQ35

WR Add

RD Add

Match

Latch

SA0-SA15

SBW SBW

Array

IBM041810ULAB

IBM043610ULAB

32K X 36 & 64K X 18 SRAM Preliminary

Use is further subject to the provisions at the end of this document.

Page 4 of 22

88H5752.T2

11/98

SRAM Features

Late Write

Late Write function allows for write data to be registered one cycle after addresses and controls. This feature

eliminates one bus-turnaround cycle necessary when going from a Read to a Write operation. Late Write is

accomplished by buffering write addresses and data so that the write operation occurs during the next write

cycle. In case a read cycle occurs after a write cycle, the address and write data information are stored tem-

porarily in holding registers. During the first write cycle preceded by a read cycle, the SRAM array will be

updated with the address and data from the holding registers. Read cycle addresses are monitored to deter-

mine if read data is to be supplied from the SRAM array or the write buffer. The bypassing of the SRAM array

data occurs on a byte-by-byte basis. When one byte is written during a write cycle, read data from the last

written address will have new byte data from the write buffer and remaining bytes from the SRAM array.

Mode Control

Mode control pins M1 and M2 are used to select four different JEDEC standard read protocols. The SRAM

supports the following protocols:

• Single Clock, Flow-Thru (M1 = VSS, M2 = VSS)

• Pipeline (M1 = VSS, M2 = VDD)

• Flow Thru (M1 = VDD, M2 = VSS)

This datasheet only describes Flow Thru functionality. Mode control inputs must be set with power-up and

must not change during SRAM operation.

Sleep Mode

Sleep Mode is accomplished by switching asynchronous signal ZZ high. When the SRAM is in Sleep Mode,

the outputs will go to a High-Z state and the SRAM will draw standby current. SRAM data will not be pre-

served and a recovery time (tZZR) followed by four “K-clock” cycles are required before the SRAM resumes

normal operation.

Power-Up Requirements

In order to guarantee the optimum internally regulated supply voltage, the SRAM requires 4µs of power-up

time after VDD reaches its operating range.

Power-Up/Power-Down Sequencing

The Power supplies need to be powered up in the following manner: GND, VDD, VDDQ, and Inputs. The

power-down sequencing must be the reverse. VDDQ must never be allowed to exceed VDD.

Ordering Information

Part Number Organization Speed Leads

IBM041810ULAB - 6F 64K x 18 6.0ns Access / 6.0ns Cycle

7 X 17 BGA

IBM041810ULAB - 6 7.0ns Access / 6.0ns Cycle

IBM043610ULAB - 6F 32K x 36 6.0ns Access / 6.0ns Cycle

IBM043610ULAB - 6 7.0ns Access / 6.0ns Cycle

IBM041810ULAB

IBM043610ULAB

Preliminary 32K X 36 & 64K X 18 SRAM

88H5752.T2

Use is further subject to the provisions at the end of this document.

Page 5 of 22

Clock Truth Table

KZZ SS SW SBWa SBWb SBWc SBWd DQ (n) DQ (n+1) Mode

L→HLLHXXXX

DOUT 0-35 X Read Cycle All Bytes

L→HLLL LHHH X

DIN 0-8 Write Cycle 1st Byte

L→HLLLHLHHX

DIN 9-17 Write Cycle 2nd Byte

L→HLLLHHLHX

DIN 18-26 Write Cycle 3rd Byte

L→HLLLHHHL X

DIN 27-35 Write Cycle 4th Byte

L→HLLLLLLLX

DIN 0-35 Write Cycle All Bytes

L→HL L L H H H H High-Z X Abort Write Cycle

L→HL H X X X X X High-Z X Deselect Cycle

X H X X X X X X High-Z High-Z Sleep Mode

Output Enable Truth Table

Operation GDQ

Read LDOUT 0-35

Read H High-Z

Sleep (ZZ=H) X High-Z

Write (SW=L) X High-Z

Deselect (SS=H) X High-Z

IBM041810ULAB

IBM043610ULAB

32K X 36 & 64K X 18 SRAM Preliminary

Use is further subject to the provisions at the end of this document.

Page 6 of 22

88H5752.T2

11/98

Absolute Maximum Ratings

Item Symbol Rating Units Notes

Power Supply Voltage VDD -0.5 to 4.0 V 1

Output Power Supply Voltage VDDQ -0.5 to 4.0 V 1

Input Voltage VIN -0.5 to VDD+0.5 V1

Output Voltage VOUT -0.5 to VDD+0.5 V1

Operating Temperature TA0 to +70 °C1

Junction Temperature TJ110 °C1

Storage Temperature TSTG -55 to +125 °C1

Short Circuit Output Current IOUT 25 mA 1

Latchup Current ILI >200 mA

1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a

stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational

sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reli-

ability.

IBM041810ULAB

IBM043610ULAB

Preliminary 32K X 36 & 64K X 18 SRAM

88H5752.T2

Use is further subject to the provisions at the end of this document.

Page 7 of 22

Recommended DC Operating Conditions (TA = 0 to 70°C)

Parameter Symbol Min. Typ. Max. Units Notes

Core Supply Voltage VDD 3.135 3.3 3.465 V 1

Output Driver Supply Voltage VDDQ 2.375 2.5 3.465 V 1

Input High Voltage VIH 2.0 — VDD+0.3 V1, 2, 4

Input Low Voltage VIL -0.3 — 0.8 V 1, 3, 4

DQ Input High Voltage VIHdQ 1.85 — VDD+0.3 V1, 2

DQ Input Low Voltage VILDQ -0.3 — 1.15 V 1, 3

PECL Clock Input High Voltage VIH - PECL 2.135 — 2.420 V 1, 2

PECL Clock Input Low Voltage VIL - PECL 1.490 — 1.825 V 1, 3

Output Current Iout —5 8 mA

1. All voltages referenced to VSS. All VDD, VDDQ, and VSS pins must be connected.

2. VIH(Max)DC = VDD + 0.3 V, VIH(Max)AC = VDD + 1.5 V (pulse width ≤ 4.0ns).

3. VIL(Min)DC = - 0.3 V, VIL(Min)AC = -1.5 V (pulse width ≤4.0ns).

4. It does not include DQs.

DC Electrical Characteristics (TA = 0 to +70°C, VDD = 3.3V ±5%)

Parameter Symbol Min. Max. Units Notes

Average Power Supply Operating Current - X36

(IOUT = 0, VIN = VIH or VIL , ZZ & SS = VIL)IDD6 — 475 mA 1

Average Power Supply Operating Current - X18

(IOUT = 0, VIN = VIH or VIL, ZZ & SS = VIL)IDD6 — 450 mA 1

Power Supply Standby Current

(SS = VIH, and ZZ = VIH

All other inputs = VIH or VIL, IOUT = 0) ISB —25mA1

Input Leakage Current, any input, except TDI, TMS, TCK

(VIN = VSS or VDD)ILI -2 +2 µA

Output Leakage Current

(VOUT = VSS or VDD, DQ in High-Z) ILO -2 +2 µA

Output High “H” Level Voltage (IOH=-8mA @ 2.4V) for VDDQ=3.3V. VOH 2.4 — V

Output Low “L” Level Voltage (IOL=+8mA @ 0.4V) for VDDQ=3.3V. VOL — 0.4 V

Output High “H” Level Voltage (IOH=-8mA @ 1.6V) for VDDQ=2.5V. VOH 1.6 — V

Output Low “L” Level Voltage (IOL=+8mA @ 0.4V) for VDDQ=2.5V. VOL — 0.4 V

1. IOUT = Chip Output Current.

IBM041810ULAB

IBM043610ULAB

32K X 36 & 64K X 18 SRAM Preliminary

Use is further subject to the provisions at the end of this document.

Page 8 of 22

88H5752.T2

11/98

Capacitance (TA = 0 to +70°C, VDD = 3.3V ±5%, f = 1MHz)

Parameter Symbol Test Condition Max Units

Input Capacitance CIN VIN = 0V 4pF

Data I/O Capacitance (DQ0-DQ35) COUT VOUT = 0V 5pF

AC Test Conditions (TA = 0 to +70°C, VDD = 3.3V ±5%, VDDQ = 3.3V -5%, +5%)

Parameter Symbol Conditions Units Notes

Input High Level for 3.3V I/O VIH(3.3V) 3.0 V

Input Low Level for 3.3V I/O VIL(3.3V) 0.0 V

Input High Level for 2.5V I/O VIH(2.5V) 2.25 V 2, 3

Input Low Level for 2.5V I/O VIL(2.5V) 0.25 V 2, 3

DQ Input High Level VDQIH(2.5V) 1.85 V 2

DQ Input Low Level VDQIL(2.5V) 1.15 V 2

PECL Clock Input High Voltage VIH-PECL 2.4 V

PECL Clock Input Low Voltage VIL-PECL 1.5 V

Input Rise Time TR1.0 ns

Input Fall Time TF1.0 ns

PECL Clock Input Rise Time TR-PECL 0.5 ns

PECL Clock Input Fall Time TF-PECL 0.5 ns

Input and Output Timing Reference Level (except K,K) 1.5 V

PECL Clock Reference Level K and K Cross Point V

Output Load Conditions 1

1. See AC Test Loading on page 11.

2. Tested with tDVKH = 0.5ns, without guardbands.

3. Does not include DQs.

IBM041810ULAB

IBM043610ULAB

Preliminary 32K X 36 & 64K X 18 SRAM

88H5752.T2

Use is further subject to the provisions at the end of this document.

Page 9 of 22

AC Test Loading

1.25V

50 Ω

16.7 Ω

5pF

1.25V

50 Ω

16.7 Ω

5pF

1.25V

IBM041810ULAB

IBM043610ULAB

32K X 36 & 64K X 18 SRAM Preliminary

Use is further subject to the provisions at the end of this document.

Page 10 of 22

88H5752.T2

11/98

AC Characteristics (TA = 0 to +70°C, VDD = 3.3V ±5%, VDDQ = 3.3V -5%, +5%)

Parameter Symbol -6F -6 Units Notes

Min. Max. Min. Max.

Cycle Time tKHKH 6.0 — 6.0 — ns

Clock High Pulse Width tKHKL 2.0 — 2.0 — ns

Clock Low Pulse Width tKLKH 2.0 — 2.0 — ns

Clock High to Output Valid tKHQV — 6.0 — 7.0 ns 1

Address Setup Time tAVKH 0.5 — 0.5 — ns

Address Hold Time tKHAX 1.0 — 1.0 — ns

Sync Select Setup Time tSVKH 0.5 — 0.5 — ns

Sync Select Hold Time tKHSX 1.0 — 1.0 — ns

Write Enables Setup Time tWVKH 0.5 — 0.5 — ns

Write Enables Hold Time tKHWX 1.0 — 1.0 — ns

Data In Setup Time tDVKH 0.5 — 0.5 — ns

Data In Hold Time tKHDX 1.0 — 1.0 — ns

Clock High to Data Out Hold Time tKHQX 2.0 — 2.0 — ns 1

Clock High to Output Active tKHQX4 2.0 — 2.0 — ns 1

Clock High to Output High-Z tKHQZ — 2.5 — 3.0 ns 1

Output Enable to High-Z tGHQZ — 3.0 — 3.0 ns 1

Output Enable to Low-Z tGLQX 2.5 — 2.5 — ns 1

Output Enable to Output Valid tGLQV — 2.5 — 2.5 ns 1

Sleep Mode Recovery TIme tZZR 100 — 100 — ns

Sleep Mode Enable TIme tZZE — 6.0 — 6.0 ns

1. See AC Test Loading on page 11.

IBM041810ULAB

IBM043610ULAB

Preliminary 32K X 36 & 64K X 18 SRAM

88H5752.T2

Use is further subject to the provisions at the end of this document.

Page 11 of 22

Timing Diagram (Read and Deselect Cycles)

tKHKH

Q2 Q3 Q4

tKLKH

tKHKL

tAVKH

tKHAX

tSVKH

tKHSX

tKHWX

tWVKH

tKHQV

tGHQZ

tGLQX

tGLQV

tKHQX

tKHQV

tKHQZ

A1 A3 A3 A4

tKHQV

tKHQX4

tKHQZ

IBM041810ULAB

IBM043610ULAB

32K X 36 & 64K X 18 SRAM Preliminary

Use is further subject to the provisions at the end of this document.

Page 12 of 22

88H5752.T2

11/98

Timing Diagram (Read and Write Cycles)

tKHKH

D2 Q3 D4

tKLKH

tKHKL

tKHQV

tAVKH

tKHAX

tSVKH

tKHSX tKHWX

tWVKH

tKHQZ

tGHQZ

SBW

tDVKH

tKHDX

tKHQV

A1 A2 A2 A4

NOTES:

1. D2 is the input data written in memory location A2.

2. Q2 is output data read from the write buffer, as a result of address A2 being a match

from the last write cycle address.

tKHWX

tWVKH tWVKH

tKHWX

tWVKH

tDVKH tKHDX

tKHQX4 tKHQV

IBM041810ULAB

IBM043610ULAB

Preliminary 32K X 36 & 64K X 18 SRAM

88H5752.T2

Use is further subject to the provisions at the end of this document.

Page 13 of 22

Timing Diagram (Sleep Mode)

tKHKH

tZZR tZZE

IBM041810ULAB

IBM043610ULAB

32K X 36 & 64K X 18 SRAM Preliminary

Use is further subject to the provisions at the end of this document.

Page 14 of 22

88H5752.T2

11/98

IEEE 1149.1 TAP AND BOUNDARY SCAN

The SRAM provides a limited set of JTAG functions intended to test the interconnection between SRAM I/Os

and printed circuit board traces or other components. There is no multiplexer in the path from I/O pins to the

RAM core.

In conformance with IEEE std. 1149.1, the SRAM contains a TAP controller, Instruction register, Boundary

Scan register, Bypass register, and ID register.

The TAP controller has a standard 16-state machine that resets internally upon power-up; therefore, TRST

signal is not required.

Signal List

• TCK: Test Clock

• TMS: Test Mode Select

• TDI: Test Data In

• TDO: Test Data Out

Caution: TCK, TMS, TDI inputs must be biased to a valid logic level, even if JTAG is not used.

JTAG Recommended DC Operating Conditions (TA = 0 to 70°C)

Parameter Symbol Min. Max. Units Notes

JTAG Input High Voltage VIH1 2.2 VDD+0.3 V1

JTAG Input Low Voltage VIL1 -0.3 0.8 V 1

JTAG Output High Level VOH1 2.4 — V 1, 2

JTAG Output Low Level VOL1 — 0.4 V 1, 3

JTAG Input Leakage Current

(VIN = VSS or VDD)IJTAG — +50 µA4

1. All JTAG Inputs/Outputs are LVTTL Compatible only.

2. IOH1 = -8mA at 2.4V.

3. IOL1 = +8mA at 0.4V.

4. If JTAG is not used, signals TCK, TMS, and TDI may be left ﬂoating. These inputs are defaulted to VDD.

JTAG AC Test Conditions (TA = 0 to +70°C, VDD = 3.3V -5% +10%)

Parameter Symbol Conditions Units Notes

Input Pulse High Level VIH1 3.0 V

Input Pulse Low Level VIL1 0.0 V

Input Rise Time TR1 2.0 ns

Input Fall Time TF1 2.0 ns

Input and Output Timing Reference Level 1.5 V 1

1. See AC Test Loading on page 11.

IBM041810ULAB

IBM043610ULAB

Preliminary 32K X 36 & 64K X 18 SRAM

88H5752.T2

Use is further subject to the provisions at the end of this document.

Page 15 of 22

JTAG AC Characteristics (TA = 0 to +70°C, VDD = 3.3V -5% +10%)

Parameter Symbol Min. Max. Units Notes

TCK Cycle Time tTHTH 20 — ns

TCK High Pulse Width tTHTL 7— ns

TCK Low Pulse Width tTLTH 7— ns

TMS Setup tMVTH 4— ns

TMS Hold tTHMX 4— ns

TDI Setup tDVTH 4— ns

TDI Hold tTHDX 4— ns

TCK Low to Valid Data tTLOV — 7 ns 1

1. See AC Test Loading on page 11.

JTAG Timing Diagram

TCK

TMS

TDI

TDO

tTHTL tTLTH tTHTH

tTHMX

tMVTH

tDVTH

tTHDX

tTLOV

IBM041810ULAB

IBM043610ULAB

32K X 36 & 64K X 18 SRAM Preliminary

Use is further subject to the provisions at the end of this document.

Page 16 of 22

88H5752.T2

11/98

List of IEEE 1149.1 standard violations:

• 7.2.1.b, e

• 7.7.1.a-f

• 10.1.1.b, e

• 0.7.1.a-d

Scan Register Deﬁnition

Instruction 3 3

Bypass 1 1

ID 32 32

Boundary Scan1,2 51 70

1. The Boundary Scan chain consists of the following bits:

• 36 or 18 bits for Data Inputs depending on X18 or X36 Conﬁguration

• 15 bits for SA0 - SA14 for X36, 16 bits for SA0 - SA15 for X18

• 4 bits for SBWa - SBWd in X36, 2 bits for SBWa and SBWb in X18

• 8 bits for K, K, SS, G, SW, ZZ, M1 and M2

• 7 bits for Place Holders

2. K and K clocks connect to a differential receiver that generates a single-ended clock signal. This signal and its inverted value are

used for Boundary Scan sampling.

ID Register Deﬁnition

Part

Field Bit Number and Description

Revision Number

(31:28) Device Density and

Conﬁguration (27:18) Vendor Deﬁnition

(17:12) Manufacture JEDEC

Code (11:1) Start

Bit(0)

64K X 18 TBD 001 000 0011 TBD 000 101 001 00 1

32K X 36 TBD 000 110 0100 TBD 000 101 001 00 1

Instruction Set

Code Instruction Notes

000 SAMPLE-Z 1

001 IDCODE 1

010 SAMPLE-Z 1

011 PRIVATE 5

100 SAMPLE 4

101 PRIVATE 5

110 PRIVATE 5

111 BYPASS 3

1. Places DQs in High-Z in order to sample all input data regardless of other SRAM inputs.

2. TDI is sampled as an input to the ﬁrst ID register to allow for the serial shift of the external TDI data.

3. BYPASS register is initiated to VSS when BYPASS instruction is invoked. The BYPASS register also holds the last serially loaded

TDI when exiting the Shift DR state.

4. SAMPLE instruction does not place DQs in High-Z.

5. This instruction is reserved for the exclusive use of IBM. Invoking this instruction will cause improper SRAM functionality.

IBM041810ULAB

IBM043610ULAB

Preliminary 32K X 36 & 64K X 18 SRAM

88H5752.T2

Use is further subject to the provisions at the end of this document.

Page 17 of 22

Boundary Scan Order (X36) (PH =Place Holder)

Exit Order Signal Bump # Exit Order Signal Bump # Exit Order Signal Bump #

1M2 5R 25 DQ15 6F 49 DQ22 2H

2SA0 4P 26 DQ16 7E 50 DQ26 1H

3SA12 4T 27 DQ11 6E 51 SBWc 3G

4SA10 6R 28 DQ12 7D 52 PH14D

5SA11 5T 29 DQ17 6D 53 SS 4E

6ZZ 7T 30 SA3 6A 54 PH14G

7DQ0 6P 31 SA2 6C 55 PH24H

8DQ5 7P 32 SA5 5C 56 SW 4M

9DQ6 6N 33 SA4 5A 57 SBWd 3L

10 DQ1 7N 34 PH16B 58 DQ27 1K

11 DQ2 6M 35 PH15B 59 DQ31 2K

12 DQ7 6L 36 PH13B 60 DQ32 1L

13 DQ3 7L 37 PH12B 61 DQ28 2L

14 DQ4 6K 38 SA7 3A 62 DQ33 2M

15 DQ8 7K 39 SA6 3C 63 DQ34 1N

16 SBWa 5L 40 SA9 2C 64 DQ29 2N

17 K4L

41 SA8 2A 65 DQ30 1P

18 K4K42 DQ18 2D 66 DQ35 2P

19 G4F43 DQ23 1D 67 SA13 3T

20 SBWb 5G 44 DQ24 2E 68 SA14 2R

21 DQ9 7H 45 DQ19 1E 69 SA1 4N

22 DQ13 6H 46 DQ20 2F 70 M1 3R

23 DQ14 7G 47 DQ25 2G

24 DQ10 6G 48 DQ21 1G

1. Input of PH register connected to VSS.

2. Input of PH register connected to VDD.

IBM041810ULAB

IBM043610ULAB

32K X 36 & 64K X 18 SRAM Preliminary

Use is further subject to the provisions at the end of this document.

Page 18 of 22

88H5752.T2

11/98

Boundary Scan Order (X18)

Exit Order Signal Bump # Exit Order Signal Bump #

1M2 5R 27 PH12B

2SA10 6T 28 SA7 3A

3SA0 4P 29 SA6 3C

4SA11 6R 30 SA9 2C

5SA12 5T 31 SA8 2A

6ZZ 7T 32 DQ9 1D

7DQ0 7P 33 DQ10 2E

8DQ1 6N 34 DQ11 2G

9DQ2 6L 35 DQ12 1H

10 DQ3 7K 36 SBWb 3G

11 SBWa 5L 37 PH14D

12 K4L

38 SS 4E

13 K4K

39 PH14G

14 G4F40 PH24H

15 DQ4 6H 41 SW 4M

16 DQ5 7G 42 DQ13 2K

17 DQ6 6F 43 DQ14 1L

18 DQ7 7E 44 DQ15 2M

19 DQ8 6D 45 DQ16 1N

20 SA3 6A 46 DQ17 2P

21 SA2 6C 47 SA14 3T

22 SA5 5C 48 SA15 2R

23 SA4 5A 49 SA1 4N

24 PH16B 50 SA13 2T

25 PH15B 51 M1 3R

26 PH13B

1. Input of PH register connected to VSS.

2. Input of PH register connected to VDD.

IBM041810ULAB

IBM043610ULAB

Preliminary 32K X 36 & 64K X 18 SRAM

88H5752.T2

Use is further subject to the provisions at the end of this document.

Page 19 of 22

TAP Controller State Machine

Test Logic Reset

Run Test Idle Select DR

Capture DR

Shift DR

Exit1 DR

Pause DR

Exit2 DR

Update DR

Select IR

Capture IR

Shift IR

Exit1 IR

Pause IR

Exit2 IR

Update IR

IBM041810ULAB

IBM043610ULAB

32K X 36 & 64K X 18 SRAM Preliminary

Use is further subject to the provisions at the end of this document.

Page 20 of 22

88H5752.T2

11/98

7 x 17 BGA Dimensions

14.00

12.00 ± 0.25

22.00

Overmold

0.600 ± 0.10 Typ

1.0 ± 0.1

20 ± 0.25

7.62

1.27

20.32

(119X)∅ 0.75 ± 0.15 Solder Ball

0.84 REF

UTRPNML K J H FGEDCB

0.030” 0.006

3.19 REF

1± 0.25

Feature is for Lead Pin IDENTIFICATION

0.66 ± 0.05

2.26 ± 0.15

Indicates A0 Location

IBM041810ULAB

IBM043610ULAB

Preliminary 32K X 36 & 64K X 18 SRAM

88H5752.T2

Use is further subject to the provisions at the end of this document.

Page 21 of 22

11/98

Revision Log

Revision Contents of Modiﬁcation

9/3/98 Initial Release.

11/98 Changed part numbers from Rev A to B.

International Business Machines Corp.1998

Printed in the United States of America

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This document may contain preliminary information and is subject to change by IBM without notice. IBM assumes no responsibility or

liability for any use of the information contained herein. Nothing in this document shall operate as an express or implied license or

indemnity under the intellectual property rights of IBM or third parties. The products described in this document are not intended for

use in implantation or other direct life support applications where malfunction may result in direct physical harm or injury to persons.

NO WARRANTIES OF ANY KIND, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY

OR FITNESS FOR A PARTICULAR PURPOSE, ARE OFFERED IN THIS DOCUMENT.

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