19-5235; Rev 0; 6/10 Stereo Audio CODEC with FLEXSOUND Technology Features S 100dB DR Stereo DAC (8kHz < fS < 96kHz) S 91dB DR Stereo ADC (8kHz < fS < 96kHz) S Stereo Low EMI Class D Amplifiers 950mW/Channel (8I, VSPKVDD_ = 4.2V) S Stereo DirectDrive Headphone Amplifiers S Differential Receiver Amplifier S 2 Stereo Single-Ended/Mono Differential Line Inputs S 3 Differential Microphone Inputs S FLEXSOUND Technology 5-Band Parametric EQ Automatic Level Control (ALC) Excursion Limiter Speaker Power Limiter Speaker Distortion Limiter Microphone Automatic Gain Control and Noise Gate S Dual I2S/PCM/TDM Digital Audio Interfaces S Asynchronous Digital Mixing S Supports Master Clock Frequencies from 10MHz to 60MHz S RF Immune Analog Inputs and Outputs S Extensive Click-and-Pop Reduction Circuitry S I2C Control Interface S 63 WLP Package (3.80mm x 3.30mm, 0.4mm Pitch) The MAX9888 is a full-featured audio CODEC whose high performance and low power consumption make it ideal for portable applications. Class D speaker amplifiers provide efficient amplification for two speakers. Low radiated emissions enable completely filterless operation. Integrated bypass switches optionally connect an external amplifier to the transducer when the Class D amplifiers are disabled. DirectDrive(R) headphone amplifiers provide a true ground-referenced output, eliminating the need for large DC-blocking capacitors. 1.8V headphone operation ensures low power consumption. The device also includes a differential receiver amplifier. Three differential analog microphone inputs are available as well as support for two PDM digital microphones. Integrated switches allow microphone signals to be routed out to external devices. Two flexible single-ended or differential line inputs may be connected to an FM radio or other sources. Integrated FLEXSOUNDK technology improves loudspeaker performance by optimizing the signal level and frequency response while limiting the maximum distortion and power at the output to prevent speaker damage. Automatic gain control (AGC) and a noise gate optimize the signal level of microphone input signals to make best use of the ADC dynamic range. Ordering Information The device is fully specified over the -40NC to +85NC extended temperature range. PART TEMP RANGE PIN-PACKAGE MAX9888EWY+ -40NC to +85NC 63 WLP +Denotes lead(Pb)-free/RoHS-compliant package. DirectDrive is a registered trademark and FLEXSOUND is a trademark of Maxim Integrated Products, Inc. Simplified Block Diagram I2C I2S/PCM I2S/PCM CONTROL DIGITAL AUDIO INTERFACE DIGITAL AUDIO INTERFACE RECEIVER AMP DIGITAL MICROPHONE INPUT SPEAKER AMP FLEXSOUND TECHNOLOGY ADC MIX LINEIN A1 ADC LINEIN A2 + LINEIN B1 * 5-BAND PARAMETRIC EQ * AUTOMATIC LEVEL CONTROL * LOUDSPEAKER PROCESSING * EXCURSION LIMITER * THD LIMITER * POWER LIMITER * MICROPHONE PROCESSING * AUTOMATIC GAIN CONTROL * NOISE GATE * ASYNCHRONOUS DIGITAL MIXING DAC SPEAKER AMP MIX DAC HEADPHONE AMP MAX9888 HEADPHONE AMP LINEIN B2 + ________________________________________________________________ Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com. MAX9888 General Description MAX9888 Stereo Audio CODEC with FLEXSOUND Technology Table of Contents General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Simplified Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Functional Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Digital Input/Output Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Input Clock Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Audio Interface Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Digital Microphone Timing Characterstics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 I2C Timing Characterstics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Typical Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Microphone to ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Line to ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Digital Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Analog Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 DAC to Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Line to Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 DAC to Speaker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Line to Speaker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 DAC to Headphone . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Line to Headphone . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Speaker Bypass Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 I2C Slave Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Microphone Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Line Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 ADC Input Mixers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Record Path Signal Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Microphone AGC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Noise Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 2 Stereo Audio CODEC with FLEXSOUND Technology ADC Record Level Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Sidetone . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Digital Audio Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Clock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Passband Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Playback Path Signal Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Automatic Level Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Parametric Equalizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Playback Level Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 DAC Input Mixers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Preoutput Signal Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Preoutput Mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Preoutput PGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Receiver Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Receiver Output Volume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Receiver Output Mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Speaker Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Speaker Output Volume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Speaker Output Mixers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Speaker Amplifier Signal Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Excursion Limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Power Limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Distortion Limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Headphone Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Headphone Output Mixers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Headphone Output Volume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Output Bypass Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Click-and-Pop Reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Jack Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Jack Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Accessory Button Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Jack Removal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 3 MAX9888 TABLE OF CONTENTS (continued) MAX9888 Stereo Audio CODEC with FLEXSOUND Technology TABLE OF CONTENTS (continued) Battery Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Device Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Device Revision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 I2C Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Bit Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 START and STOP Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Early STOP Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Slave Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Write Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Read Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Typical Operating Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Analog Microphones and Bypass Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Digital Microphones and Receiver Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Filterless Class D Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 RF Susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Startup/Shutdown Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Component Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Optional Ferrite Bead Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Input Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Charge-Pump Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Charge-Pump Flying Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Charge-Pump Holding Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Unused Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Recommended PCB Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Supply Bypassing, Layout, and Grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 WLP Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 4 C8 INB2 D8 INB1 D9 INA2/EXTMICN E9 INA1/EXTMICP G9 MIC2N F9 MIC2P MIC2BYP MIC1N/ F8 DIGMICCLK MIC1P/ E8 DIGMICDATA G8 MICBIAS D6 JACKSNS INABYP MBEN JDETEN JACK DETECTION I2C REG EXTMIC EXTMIC + + PA2EN: 0/20/30dB PGAINB: +20dB TO -6dB INBDIFF PGAINB: +20dB TO -6dB PGAINA: +20dB TO -6dB INADIFF PGAINA: +20dB TO -6dB PGAM2: +20dB TO 0dB PA1EN: 0/20/30dB PGAM1: +20dB TO 0dB PSCLK CLOCK CONTROL E2 D1 MIXOUT3 MIX MIXOUT2 MIX MIXOUT1 MIX MIXADR MIX MIXADL MIX MAS1 DAI1 SEL1 ADREN ADCR ADCL ADLEN BCLKS1 D2 E4 LBEN2 MIX MUX AVRG: 0/6/12/18dB AVR: 3dB TO -2dB PREOUT3 PGAOUT3: 0dB TO -23dB PREOUT2 PGAOUT2: 0dB TO -23dB LTEN1 DATA INPUT F2 + + PORT S2 EQ2EN DV1: 0dB TO -15dB G3 HIZOFF2 SDINS2 MODE1 DVFLT AUDIO/ VOICE FILTERS DCB2 AUDIO/ FILTERS FLEXSOUND TECHNOLOGY DATA OUTPUT MAS2 DVEQ2: 0dB TO -15dB LBEN1 DV2: 0dB TO -15dB EXCURSION LIMITER G1 SDOUTS2 FRAME CLOCK LRCLK2 5-BAND PARAMETRIC EQ DVEQ1: 0dB TO -15dB MULTI BAND ALC EQ1EN F3 LRCLKS2 BIT CLOCK BCLK2 DV1G: 0/6/12/18dB MAS2 DAI2 SEL2 5-BAND PARAMETRIC EQ DVST: 0dB TO -60dB MODE1 AVFLT AUDIO/ VOICE FILTERS E1 DVDDS1 BCLKS2 HIZOFF1 DATA OUTPUT AVLG: 0/6/12/18dB AVL: 3dB TO -12dB PREOUT1 D4 SDINS1 NOISE GATE DSTS SIDETONE SDOUT1 MAS1 PORT S1 SDOUTS1 FRAME CLOCK PGAOUT1: 0dB TO -23dB BIT CLOCK LRCLK1 AUTOMATIC GAIN CONTROL LRCLKS1 BCLK1 MCLK SDIN1 E5 SDOUT2 F5 MIXDAR MIX MIXDAL MIX DATA INPUT +9dB +9dB +9dB DAREN DACR DALEN DACL G4 DVDD G2 DVDDS2 SDIN2 F4 G5 MIX SPVOLL: +8dB TO -62dB RECVOL: +8dB TO -62dB AGND G7 DGND F1 MIX MIXHPR MIX MIXHPL RECEN 0dB B8 HPVSS C1N B7 C1P HPVOLR: +3dB TO -67dB HPVOLL: +3dB TO -67dB CHARGE PUMP HPREN HPLEN SPREN +6dB A9 SPKBYP RECBYP BIAS POWER/ DISTORTION LIMITER SPLEN +6dB BATTERY ADC MAX9888 MIXSPR SPVOLR: +8dB TO -62dB MIX MIXSPL MIX MIXREC AVDD F6 HPGND HPVDD HPR HPSNS HPL SPKRGND SPKRN SPKRP SPKRVDD SPKLGND SPKLN SPKLP SPKLVDD RECN/ RXINN A8 A7 C9 C6 B9 A2, B2 A1, B1 C1, C2 C3, D3 C4, C5 A5, B5 A4, B4 A3, B3 B6 A6 G6 REG RECP/ RXINP F7 REF PREG Functional Diagram 5 MAX9888 SDA SCL IRQ Stereo Audio CODEC with FLEXSOUND Technology MAX9888 Stereo Audio CODEC with FLEXSOUND Technology Absolute Maximum Ratings REG, INA1, INA2, INB1, INB2, MIC1P/DIGMICDATA, MIC1N/DIGMICCLK, MIC2P, MIC2N................-0.3V to +2.2V HPSNS................................ (HPGND - 0.3V) to (HPGND + 0.3V) HPL, HPR............................. (HPVSS - 0.3V) to (HPVDD + 0.3V) RECP, RECN...............(SPKLGND - 0.3V) to (SPKLVDD + 0.3V) SPKLP, SPKLN............(SPKLGND - 0.3V) to (SPKLVDD + 0.3V) SPKRP, SPKRN..........(SPKRGND - 0.3V) to (SPKRVDD + 0.3V) Continuous Power Dissipation (TA = +70NC) 63-Bump WLP (derate 25.6mW/NC above +70NC).........2.05W Operating Temperature Range........................... -40NC to +85NC Storage Temperature Range............................. -65NC to +150NC Soldering Temperature (reflow).......................................+260NC (Voltages with respect to AGND.) DVDD, AVDD, HPVDD..........................................-0.3V to +2.2V SPKLVDD, SPKRVDD, DVDDS1, DVDDS2...........-0.3V to +6.0V DGND, HPGND, SPKLGND, SPKRGND...............-0.1V to +0.1V HPVSS................................ (HPGND - 2.2V) to (HPGND + 0.3V) C1N..................................... (HPVSS - 0.3V) to (HPGND + 0.3V) C1P......................................(HPGND - 0.3V) to (HPVDD + 0.3V) PREG...................................................... -0.3V to (AVDD + 0.3V) REF, MICBIAS.................................. -0.3V to (SPKLVDD + 0.3V) MCLK, SDINS1, SDINS2, JACKSNS, SDA, SCL, IRQ..................................................-0.3V to +6.0V LRCLKS1, BCLKS1, SDOUTS1.......... -0.3V to (DVDDS1 + 0.3V) LRCLKS2, BCLKS2, SDOUTS2.......... -0.3V to (DVDDS2 + 0.3V) Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Electrical Characteristics (VAVDD = VHPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to GND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CPREG = CREG = 1FF, CC1N-C1P = 1FF, CHPVSS = 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB, AVPGAIN_ = 0dB, AVPGAOUT_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.) (Note 1) PARAMETER POWER SUPPLY SYMBOL Supply Voltage Range CONDITIONS Guaranteed by PSRR Full-duplex 8kHz mono, receiver output (Note 3) VSPKLVDD, VSPKRVDD 2.8 VDVDD, VAVDD, VHPVDD 1.65 VDVDDS1, VDVDDS2 1.65 IVDD MAX UNITS 5.5 1.8 2.0 V 3.6 Analog 6.37 10 1.98 3.5 Digital 1.49 3 Analog 2.71 4 1.65 2.5 2.93 4.5 Analog DAC playback 48kHz stereo, Speaker speaker outputs (Note 3) Digital 1.85 3 8.22 16 2.94 5 Analog Full-duplex 48kHz stereo, microphone inputs, Speaker headphone outputs (Note 3) Digital 12.75 18 1.7 3 Stereo line playback, IN_DIF = 0, INA1 to HPL, INA2 to HPR, VMCLK = 0V 6 TYP Speaker DAC playback 48kHz stereo, Speaker headphone outputs (Note 3) Digital Total Supply Current (Note 2) MIN 3.75 5.5 Analog 5.11 7 Speaker 0.58 1 Digital 0.03 0.06 mA Stereo Audio CODEC with FLEXSOUND Technology (VAVDD = VHPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to GND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CPREG = CREG = 1FF, CC1N-C1P = 1FF, CHPVSS = 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB, AVPGAIN_ = 0dB, AVPGAOUT_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.) (Note 1) PARAMETER SYMBOL Shutdown Supply Current (Note 2) CONDITIONS TA = +25NC TYP MAX Analog MIN 0.2 2 Speaker 0.1 1 1 5 Digital UNITS FA REF Voltage 2.5 PREG Voltage 1.6 V REG Voltage 0.7 V Shutdown to Full Operation SLEW = 0 30 SLEW = 1 17 V ms MICROPHONE TO ADC PATH Dynamic Range (Note 4) Total Harmonic Distortion + Noise Common-Mode Rejection Ratio DR THD+N CMRR fS = 8kHz, MODE = 0 (IIR voice), AVMICPRE_ = 0dB Path Phase Delay PSRR 88 VIN = 0.1VP-P, MCLK = 12.288MHz, fS = 8kHz, f = 1kHz -77 AVMICPRE_ = 0dB, VIN = 1VP-P, f = 1kHz -82 AVMICPRE_ = +30dB, VIN = 32mVP-P, f = 1kHz -71 VIN = 100mVP-P, f = 217Hz 65 VAVDD = 1.65V to 2.0V, input referred, MIC inputs floating Power-Supply Rejection Ratio 75 60 -65 dB dB 100 f = 217Hz, VRIPPLE = 100mVP-P, AVADC = 0dB, input referred 100 f = 1kHz, VRIPPLE = 100mVP-P, AVADC = 0dB, input referred 91 f = 10kHz, VRIPPLE = 100mVP-P, AVADC = 0dB, input referred 70 1kHz, 0dB input, highpass filter disabled measured from analog input to digital output dB dB MODE = 0 (IIR voice) 8kHz 2.2 MODE = 0 (IIR voice) 16kHz 1.1 MODE = 1 (FIR audio) 8kHz 4.5 MODE = 1 (FIR audio) 48kHz 0.76 ms 7 MAX9888 ELECTRICAL CHARACTERISTICS (continued) MAX9888 Stereo Audio CODEC with FLEXSOUND Technology ELECTRICAL CHARACTERISTICS (continued) (VAVDD = VHPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to GND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CPREG = CREG = 1FF, CC1N-C1P = 1FF, CHPVSS = 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB, AVPGAIN_ = 0dB, AVPGAOUT_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS MICROPHONE PREAMP AVMICPRE_ = 0dB Full-Scale Input 1.05 PA1EN/PA2EN = 01 Preamplifier Gain PGA Gain MIC Input Resistance AVMICPRE_ (Note 5) AVMICPGA_ (Note 5) RIN_MIC PA1EN/PA2EN = 10 VP-P 0 19.5 20 20.5 PA1EN/PA2EN = 11 29.4 30 30.5 PGAM1/PGAM2 = 0x00 19.5 20 20.5 PGAM1/PGAM2 = 0x14 All gain settings, measured at MIC1P/MIC1N/ MIC2P/MIC2N 0 30 50 2.14 dB dB kI MICROPHONE BIAS MICBIAS Output Voltage VMICBIAS Load Regulation 2.2 2.25 V ILOAD = 1mA to 2mA ILOAD = 1mA 0.5 11 mV VSPKLVDD = 2.8V to 5.5V 100 f = 217Hz, VRIPPLE (SPKLVDD) = 100mVP-P 92 f = 10kHz, VRIPPLE (SPKLVDD) = 100mVP-P 83 A-weighted, f = 20Hz to 20kHz 3.8 P-weighted, f = 20Hz to 4kHz 2.1 f = 1kHz 33 IMIC1_ = 100mA, INABYP = MIC2BYP = 1, VMIC2_ = VINA_ = (0V, VAVDD) 3.5 VIN = 2VP-P, VCM = 0.9V, RL = 10kI, f = 1kHz, INABYP = MIC2BYP = 1 -80 dB Off-Isolation VIN = 2VP-P, VCM = 0.9V, RL = 10kI, f = 1kHz 60 dB Off-Leakage Current VMIC1_ = (0V, VAVDD), VMIC2_/VINA_ = (VAVDD, 0V) Line Regulation Ripple Rejection Noise Voltage FV dB FVRMS nV/Hz MICROPHONE BYPASS SWITCH On-Resistance Total Harmonic Distortion + Noise RON THD+N -2.5 20 +2.5 I FA LINE INPUT TO ADC PATH Dynamic Range (Note 4) Total Harmonic Distortion + Noise Gain Error 8 DR THD+N fS = 48kHz, MCLK = 12.288MHz, MODE = 1 (FIR audio) 91 dB VIN = 1VP-P, f = 1kHz -77 dB DC accuracy 1 5 % Stereo Audio CODEC with FLEXSOUND Technology (VAVDD = VHPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to GND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CPREG = CREG = 1FF, CC1N-C1P = 1FF, CHPVSS = 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB, AVPGAIN_ = 0dB, AVPGAOUT_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS LINE INPUT PREAMP Full-Scale Input Level Adjust Gain VIN AVPGAIN_ AVPGAIN_ = 0dB 1 AVPGAIN_ = -6dB 1.4 PGAINA/PGAINB = 0x0 19 20 21 PGAINA/PGAINB = 0x1 13 14 15 2 3 4 PGAINA/PGAINB = 0x2 (Note 5) PGAINA/PGAINB = 0x3 TA = +25NC PGAINA/PGAINB = 0x4 -4 -3 -2 PGAINA/PGAINB = 0x5, 0x6, 0x7 -7 -6 -5 14.6 21 27.4 AVPGAIN_ = +20dB RIN 20 AVPGAIN_ = +3dB 20 AVPGAIN_ = 0dB 7.3 AVPGAIN_ = -3dB RIN_FB INAEXT/INBEXT = 1 10 13.7 kI 20 AVPGAIN_ = -6dB Feedback Resistance dB 0 AVPGAIN_ = +14dB Input Resistance VP-P 20 TA = +25NC 18.5 TA = TMIN to TMAX 17.5 20 21.5 23 kI ADC LEVEL CONTROL ADC Level Adjust Range AVADCLVL AVL/AVR = 0xF to 0x0 (Note 5) -12 ADC Level Adjust Step Size ADC Gain Adjust Range +3 1 AVADCGAIN AVLG/AVRG = 00 to 11 (Note 5) 0 ADC Gain Adjust Step Size dB dB 18 6 dB dB ADC DIGITAL FILTERS VOICE MODE IIR LOWPASS FILTER (MODE1 = 0) Passband Cutoff Stopband Attenuation (Note 6) 0.441 x fs -3dB cutoff 0.449 x fs fPLP Passband Ripple Stopband Cutoff Ripple limit cutoff f < fPLP -0.1 fSLP f > fSLP 74 Hz +0.1 dB 0.47 x fs Hz dB 9 MAX9888 ELECTRICAL CHARACTERISTICS (continued) MAX9888 Stereo Audio CODEC with FLEXSOUND Technology ELECTRICAL CHARACTERISTICS (continued) (VAVDD = VHPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to GND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CPREG = CREG = 1FF, CC1N-C1P = 1FF, CHPVSS = 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB, AVPGAIN_ = 0dB, AVPGAOUT_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS VOICE MODE IIR HIGHPASS FILTER (MODE1 = 0) Passband Cutoff (-3dB from Peak) Stopband Cutoff (-30dB from Peak) DC Attenuation fAHPPB fAHPSB DCATTEN AVFLT = 0x1 (elliptical tuned for fs = 16kHz + 217Hz notch) 0.0161 x fs AVFLT = 0x2 (500Hz Butterworth tuned for fs = 16kHz) 0.0319 x fs AVFLT = 0x3 (elliptical tuned for fs = 8kHz + 217Hz notch) 0.0321 x fs AVFLT = 0x4 (500Hz Butterworth tuned for fs = 8kHz) 0.0632 x fs AVFLT = 0x5 (fs/240 Butterworth) 0.0043 x fs AVFLT = 0x1 (elliptical tuned for fs = 16kHz + 217Hz notch) 0.0139 x fs AVFLT = 0x2 (500Hz Butterworth tuned for fs = 16kHz) 0.0156 x fs AVFLT = 0x3 (elliptical tuned for fs = 8kHz + 217Hz notch) 0.0279 x fs AVFLT = 0x4 (500Hz Butterworth tuned for fs = 8kHz) 0.0312 x fs AVFLT = 0x5 (fs/240 Butterworth) 0.002 x fs AVFLT 000 Hz Hz 90 dB STEREO AUDIO MODE FIR LOWPASS FILTER (MODE1 = 1, DHF1 = 0, LRCLK < 50kHz) Passband Cutoff fPLP Passband Ripple Stopband Cutoff Ripple limit cutoff 0.43 x fs -3dB cutoff 0.48 x fs -6.02dB cutoff 0.5 x fs f < fPLP -0.1 fSLP Stopband Attenuation (Note 6) f < fSLP 60 Hz +0.1 dB 0.58 x fs Hz dB ADC STEREO AUDIO MODE FIR LOWPASS FILTER (MODE1 = 1, DHF1 = 1, LRCLK > 50kHz) Passband Cutoff 10 Ripple limit cutoff 0.208 x fs -3dB cutoff 0.28 x fs fPLP Hz Stereo Audio CODEC with FLEXSOUND Technology (VAVDD = VHPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to GND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CPREG = CREG = 1FF, CC1N-C1P = 1FF, CHPVSS = 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB, AVPGAIN_ = 0dB, AVPGAOUT_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.) (Note 1) PARAMETER SYMBOL Passband Ripple Stopband Cutoff CONDITIONS f < fPLP MIN TYP -0.1 fSLP Stopband Attenuation f < fSLP MAX UNITS +0.1 dB 0.417 x fs Hz 60 dB ADC STEREO AUDIO MODE DC-BLOCKING HIGHPASS FILTER (MODE1 = 1) Passband Cutoff (-3dB from Peak) fAHPPB AVFLT 000 DC Attenuation DCAtten AVFLT 000 0.000125 x fs 90 Hz dB MICROPHONE AUTOMATIC GAIN CONTROL AGC Hold Duration AGC Attack Time AGC Release Time AGC Threshold Level AGCHLD = 01 50 AGCHLD = 11 400 AGCATK = 00 2 AGCATK = 11 123 AGCRLS = 000 0.078 AGCRLS = 111 10 ms ms s AGCTH = 0x0 to 0xF -3 (Note 5) 0 20 dB -64 -16 dB 0 12 dB AGC Threshold Step Size +18 1 AGC Gain dB dB ADC NOISE GATE NG Threshold Level ANTH = 0x3 to 0xF, referred to 0dBFS NG Attenuation (Note 5) ADC-TO-DAC DIGITAL SIDETONE (MODE = 0) Sidetone Gain Adjust Range AVSTGA DVST = 0x01 -0.5 DVST = 0x1F -60.5 Sidetone Gain Adjust Step Size dB 2 1kHz, 0dB input, highpass 8kHz filter disabled 16kHz Sidetone Path Phase Delay dB 2.2 ms 1.1 ADC-TO-DAC DIGITAL LOOP-THROUGH PATH Dynamic Range (Note 4) DR Total Harmonic Distortion THD fS = 48kHz, MCLK = 12.288MHz, MODE = 1 (FIR audio) 89 f = 1kHz, fS = 48kHz, MCLK = 12.288MHz, MODE = 1 (FIR audio) -71 dB -66 dB 0 dB DAC LEVEL CONTROL DAC Attenuation Range AVDACATTN DV1DV2 = 0xF to 0x0 (Note 5) -15 DAC Attenuation Step Size DAC Gain Adjust Range DAC Gain Adjust Step Size 1 AVDACGAIN DV1G = 00 to 11 (Note 5) 0 dB 18 6 dB dB 11 MAX9888 ELECTRICAL CHARACTERISTICS (continued) MAX9888 Stereo Audio CODEC with FLEXSOUND Technology ELECTRICAL CHARACTERISTICS (continued) (VAVDD = VHPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to GND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CPREG = CREG = 1FF, CC1N-C1P = 1FF, CHPVSS = 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB, AVPGAIN_ = 0dB, AVPGAOUT_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DAC DIGITAL FILTERS VOICE MODE IIR LOWPASS FILTER (MODE1 = 0) Passband Cutoff 0.448 x fs -3dB cutoff 0.451 x fs fPLP Passband Ripple Stopband Cutoff Ripple limit cutoff f < fPLP Hz -0.1 fSLP Stopband Attenuation (Note 6) f > fSLP +0.1 dB 0.476 x fs Hz 75 dB VOICE MODE IIR HIGHPASS FILTER (MODE1 = 0) Passband Cutoff (-3dB from Peak) Stopband Cutoff (-30dB from Peak) DC Attenuation 12 fDHPPB fDHPSB DCATTEN DVFLT = 0x1 (elliptical tuned for fs = 16kHz + 217Hz notch) 0.0161 x fs DVFLT = 0x2 (500Hz Butterworth tuned for fs = 16kHz) 0.0312 x fs DVFLT = 0x3 (elliptical tuned for fs = 8kHz + 217Hz notch) 0.0321 x fs DVFLT = 0x4 (500Hz Butterworth tuned for fs = 8kHz) 0.0625 x fs DVFLT = 0x5 (fs/240 Butterworth) 0.0042 x fs DVFLT = 0x1 (elliptical tuned for fs = 16kHz + 217Hz notch) 0.0139 x fs DVFLT = 0x2 (500Hz Butterworth tuned for fs = 16kHz) 0.0156 x fs DVFLT = 0x3 (elliptical tuned for fs = 8kHz + 217Hz notch) 0.0279 x fs DVFLT = 0x4 (500Hz Butterworth tuned for fs = 8kHz) 0.0312 x fs DVFLT = 0x5 (fs/240 Butterworth) 0.002 x fs DVFLT 000 Hz Hz 85 dB Stereo Audio CODEC with FLEXSOUND Technology (VAVDD = VHPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to GND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CPREG = CREG = 1FF, CC1N-C1P = 1FF, CHPVSS = 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB, AVPGAIN_ = 0dB, AVPGAOUT_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS STEREO AUDIO MODE FIR LOWPASS FILTER (MODE1 = 1, DHF1/DHF2 = 0, LRCLK < 50kHz) Passband Cutoff fPLP Passband Ripple Stopband Cutoff Ripple limit cutoff 0.43 x fs -3dB cutoff 0.47 x fs -6.02dB cutoff 0.5 x fs f < fPLP -0.1 Hz fSLP Stopband Attenuation (Note 6) f > fSLP +0.1 dB 0.58 x fs Hz 60 dB STEREO AUDIO MODE FIR LOWPASS FILTER (MODE1 = 1, DHF1/DHF2 = 1 for LRCLK > 50kHz) Passband Cutoff 0.24 x fs -3dB cutoff 0.31 x fs f < fPLP -0.1 fPLP Passband Ripple Stopband Cutoff Ripple limit cutoff Hz fSLP Stopband Attenuation (Note 6) f < fSLP +0.1 dB 0.477 x fs Hz 60 dB STEREO AUDIO MODE DC-BLOCKING HIGHPASS FILTER Passband Cutoff (-3dB from Peak) 0.000104 x fs fDHPPB DVFLT 000 (DAI1), DCB2 = 1 (DAI2) DCATTEN DVFLT 000 (DAI1), DCB2 = 1 (DAI2) 90 dB Dual Band Lowpass Corner Frequency ALCMB = 1 5 kHz Dual Band Highpass Corner Frequency ALCMB = 1 5 kHz DC Attenuation Hz AUTOMATIC LEVEL CONTROL Gain Range Low Signal Threshold Release Time ALCTH = 111 to 001 0 12 dB -48 -12 dBFS ALCRLS = 101 0.25 ALCRLS = 000 8 s PARAMETRIC EQUALIZER Number of Bands 5 Per Band Gain Range Preattenuator Gain Range Preattenuator Step Size (Note 5) Bands -12 +12 dB -15 0 dB 1 dB 13 MAX9888 ELECTRICAL CHARACTERISTICS (continued) MAX9888 Stereo Audio CODEC with FLEXSOUND Technology ELECTRICAL CHARACTERISTICS (continued) (VAVDD = VHPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to GND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CPREG = CREG = 1FF, CC1N-C1P = 1FF, CHPVSS = 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB, AVPGAIN_ = 0dB, AVPGAOUT_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DAC-TO-RECEIVER AMPLIFIER PATH Dynamic Range (Note 4) Total Harmonic Distortion + Noise Click and Pop Level DR THD+N KCP fS = 48kHz, MCLK = 12.288MHz, f = 1kHz 96 f = 1kHz, POUT = 25mW, RREC = 32I -70 Peak voltage, A-weighted, 32 samples per second, AVREC = 0dB Into shutdown -70 Out of shutdown -73 dB -63 dB dBV PREOUTPUT MIXERS Level Adjust Gain AVPGAOUT_ (Note 5) PGAOUTA/PGAOUTB/ PGAOUTC = 0x0 PGAOUTA/PGAOUTB/ PGAOUTC = 0xC 0 dB -25 Level Adjust Step Size Mute Attenuation f = 1kHz -23.4 -22 2 dB 85 dB 92 dB -70 dB LINE INPUT-TO-RECEIVER AMPLIFIER PATH Dynamic Range (Note 4) Total Harmonic Distortion + Noise DR Referenced to full-scale output level THD+N VSPKLVDD = 2.8V to 5.5V Power-Supply Rejection Ratio PSRR 54 -63 f = 1kHz, VRIPPLE = 100mVP-P -63 f = 10kHz, VRIPPLE = 100mVP-P Click-and-Pop Level KCP 89 f = 217Hz, VRIPPLE = 100mVP-P Peak voltage, A-weighted, 32 samples per second, AVREC = 0dB dB -65 Into shutdown -57 Out of shutdown -55 dBV RECEIVER AMPLIFIER Output Power POUT Full-Scale Output Volume Control AVREC Volume Control Step Size Mute Attenuation Output Offset Voltage Capacitive Drive Capability 14 RREC = 32I, f = 1kHz, THD = 1% (Note 7) VOS (Note 5) 100 mW 1 VRMS RECVOL = 0x00 -65 -62 -58 RECVOL = 0x1F +7.5 +8 +8.5 +8dB to +6dB 0.5 +6dB to +0dB 1 0dB to -14dB 2 -14dB to -38dB 3 -38dB to -62dB 4 f = 1kHz 95 AVREC = -62dB No sustained oscillations TA = +25NC 0.13 RREC = 32I 500 RREC = J 100 dB dB dB 1 mV pF Stereo Audio CODEC with FLEXSOUND Technology (VAVDD = VHPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to GND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CPREG = CREG = 1FF, CC1N-C1P = 1FF, CHPVSS = 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB, AVPGAIN_ = 0dB, AVPGAOUT_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DAC-TO-SPEAKER AMPLIFIER PATH Total Harmonic Distortion + Noise f = 1kHz, POUT = 250mW, ZSPK = 8I + 68FH -71 dB Crosstalk SPL to SPR and SPKR to SPKL, POUT = 640mW, f = 1kHz -75 dB Output Noise A-weighted 43 FVRMS Click-and-Pop Level THD+N KCP Peak voltage, A-weighted, 32 samples per second, AVSPK_ = 0dB Into shutdown -65 Out of shutdown -65 dBV LINE INPUT-TO-SPEAKER AMPLIFIER PATH Total Harmonic Distortion + Noise THD+N Output Noise f = 1kHz, POUT = 200mW, ZSPK = 8I + 68FH A-weighted VSPKLVDD = VRIPPLE = 2.8V to 5.5V Power-Supply Rejection Ratio PSRR 43 KCP dB 56 FVRMS 60 f = 217Hz, VRIPPLE = 100mV 75 f = 1kHz, VRIPPLE = 100mV 73 f = 10kHz, VRIPPLE = 100mV Click-and-Pop Level -66 Peak voltage, A-weighted, 32 samples per second, AVSPK_ = 0dB dB 50 Into shutdown -48 Out of shutdown -50 dBV SPEAKER AMPLIFIER Output Power POUT Full-Scale Output Volume Control (Note 5) Volume Control Step Size f = 1kHz, THD = 1%, ZSPK = 8I + 68FH VSPKLVDD = VSPKRVDD = 5.0V 1370 VSPKLVDD = VSPKRVDD = 4.2V 954 VSPKLVDD = VSPKRVDD = 3.7V 733 VSPKLVDD = VSPKRVDD = 3.2V 544 mW (Note 7) AVSPK_ 2 VRMS SPVOLL/SPVOLR = 0x00 -69 -64 -59 SPVOLL/SPVOLR = 0x1F +7.5 +8 +8.5 +8dB to +6dB 0.5 +6dB to +0dB 1 0dB to -14dB 2 -14dB to -38dB 3 -38dB to -64dB 4 dB dB 15 MAX9888 ELECTRICAL CHARACTERISTICS (continued) MAX9888 Stereo Audio CODEC with FLEXSOUND Technology ELECTRICAL CHARACTERISTICS (continued) (VAVDD = VHPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to GND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CPREG = CREG = 1FF, CC1N-C1P = 1FF, CHPVSS = 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB, AVPGAIN_ = 0dB, AVPGAOUT_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.) (Note 1) PARAMETER SYMBOL Mute Attenuation Output Offset Voltage CONDITIONS MIN f = 1kHz VOS TYP MAX UNITS 1.25 mV 1000 Hz 86 0.25 AVSPK_ = -64dB, TA = +25NC dB EXCURSION LIMITER Upper-Corner Frequency Range DHPUCF = 001 to 100 Lower-Corner Frequency DHPLCF = 01 to 10 400 DHPUCF = 000 (fixed mode) 100 DHPUCF = 001 200 DHPUCF = 010 300 DHPUCF = 011 400 DHPUCF = 100 500 Biquad Minimum Corner Frequency ZSPK = 8I + 68FH, VSPKLVDD = VSPKRVDD = 5.5V, AVSPK_ = +8dB Threshold Voltage Release Time 400 DHPTH = 000 0.34 DHPTH = 111 4.95 ALCRLS = 101 0.25 ALCRLS = 000 4 Hz Hz VP s POWER LIMITER Attenuation -64 ZSPK = 8I + 68FH, VSPKLVDD = VSPKRVDD = 5.5V, AVSPK_ = +8dB Threshold Time Constant 1 tPWR1 Time Constant 2 tPWR2 Weighting Factor kPWR PWRTH = 0x1 0.05 PWRTH = 0xF 1.80 PWRT1 = 0x1 0.5 PWRT1 = 0xF 8.7 PWRT2 = 0x1 to 0xF 0.5 PWRT2 = 0xF 8.7 PWRK = 000 to 111 12.5 dB W s min 100 % DISTORTION LIMITER Distortion Limit Release Time Constant THDCLP = 0x1 <1 THDCLP = 0xF 24 THDT1 = 000 0.76 THDT1 = 111 6.2 % s DAC-TO-HEADPHONE AMPLIFIER PATH Dynamic Range (Note 4) Total Harmonic Distortion + Noise 16 DR THD+N fS = 48kHz, MCLK = Master or slave mode 12.288MHz Slave mode fS = 48kHz, MCLK = 12.288MHz, f = 1kHz, POUT = 20mW 100 RHP = 16I -71 RHP = 32I -75 fS = 48kHz, MCLK = 12.288MHz, f = 1kHz, VOUT = 1VRMS, RHP = 10kI dB 94 -79 -64 dB Stereo Audio CODEC with FLEXSOUND Technology (VAVDD = VHPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to GND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CPREG = CREG = 1FF, CC1N-C1P = 1FF, CHPVSS = 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB, AVPGAIN_ = 0dB, AVPGAOUT_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.) (Note 1) PARAMETER SYMBOL Crosstalk CONDITIONS MIN PSRR -82 dB -82 dB 60 f = 217Hz, VRIPPLE = 100mV, AVVOL = 0dB 92 91 f = 10kHz, VRIPPLE = 100mV, AVVOL = 0dB 57 MODE = 0 (voice) 8kHz 2.2 MODE = 0 (voice) 16kHz 1.1 MODE = 1 (music) 8kHz 4.5 MODE = 1 (music) 48kHz 0.76 Peak voltage, A-weighted, 32 samples per second, AVHP_ = 0dB dB ms Channel Gain Mismatch KCP 84 f = 1kHz, VRIPPLE = 100mV, AVVOL = 0dB Gain Error Click-and-Pop Level UNITS f = 1kHz, Input = -1dBFS, RHP = 10kI 1kHz, 0dB input, highpass filter disabled measured from digital input to analog output DAC Path Phase Delay MAX HPL to HPR and HPR to HPL, POUT = 5mW, f = 1kHz, RHP = 32I VAVDD = VHPVDD = 1.65V to 2.0V Power-Supply Rejection Ratio TYP 1 % 0.5 % Into shutdown -66 Out of shutdown -67 dBV LINE INPUT-TO-HEADPHONE AMPLIFIER PATH Total Harmonic Distortion + Noise Dynamic Range (Note 4) THD+N VIN = 1VP-P, f =1kHz, RHP = 32I DR VAVDD = VHPVDD = 1.65V to 2.0V Power-Supply Rejection Ratio PSRR 42 dB 91 dB 66 f = 217Hz, VRIPPLE = 100mVP-P 62 f = 1kHz, VRIPPLE = 100mVP-P 57 f = 10kHz, VRIPPLE = 100mVP-P Click and Pop Level -70 KCP Peak voltage, A-weighted, 32 samples per second, AVHP_ = 0dB POUT f = 1kHz, THD = 1% dB 41 Into shutdown -62 Out of shutdown -60 dBV HEADPHONE AMPLIFIER Output Power Full-Scale Output Volume Control RHP = 32I 32 RHP = 16I 40 (Note 7) AVHP_ TA = +25NC (Note 5) mW 1 VRMS HPVOL_ = 0x00 -71 -67 -66 HPVOL_ = 0x1F 2.4 3 3.5 dB 17 MAX9888 ELECTRICAL CHARACTERISTICS (continued) MAX9888 Stereo Audio CODEC with FLEXSOUND Technology ELECTRICAL CHARACTERISTICS (continued) (VAVDD = VHPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to GND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CPREG = CREG = 1FF, CC1N-C1P = 1FF, CHPVSS = 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB, AVPGAIN_ = 0dB, AVPGAOUT_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.) (Note 1) PARAMETER SYMBOL Volume Control Step Size Mute Attenuation Output Offset Voltage MIN VOS +1dB to -5dB 1 -5dB to -19dB 2 -19dB to -43dB 3 -43dB to -67dB 4 AVHP_ = -67dB No sustained oscillations fCP TYP 0.5 f = 1kHz Capacitive Drive Capability Charge Pump Oscillator Frequency CONDITIONS +3dB to +1dB MAX dB 82 0.2 TA = +25NC dB 1 2 TA = TMIN to TMAX RHP = 32I 500 RHP = J 100 300 667 Slow mode 74 ISPKL_ = 100mA, SPKBYP = 1, VRXIN_ = [0V, VSPKLVDD] 2.8 UNITS mV pF 900 kHz SPEAKER BYPASS SWITCH On-Resistance Total Harmonic Distortion + Noise RON THD+N VIN = 2VP-P, VCM = VSPKLVDD/2, ZSPK = 8I + 68FH, f = 1kHz, SPKBYP = 1 Off-Isolation VIN = 2VP-P, VCM = VSPKLVDD/2, ZL = 8I + 68FH, f = 1kHz Off-Leakage Current VRXIN_ = [0V, VSPKLVDD], VSPKL_ = [VSPKLVDD, 0V] RS = 10I -77 RS = 0I -60 4.5 dB 96 -1 I dB +1 FA 2 I RECEIVER BYPASS SWITCH IRECP = 100mA, RECBYP = 1, VRECN = [0V, VSPKLVDD] 1.2 VIN = 2VP-P, VCM = VSPKLVDD/2, RL = 32I, f = 1kHz, RECBYP = 1 -66 % Off-Isolation VIN = 2VP-P, VCM = VSPKLVDD/2, RL = 32I, f = 1kHz 80 dB Off-Leakage Current VRECP = [0V, VSPKLVDD], VRECN = [VSPKLVDD, 0V] On-Resistance Total Harmonic Distortion + Noise 18 RON THD+N -15 +15 FA Stereo Audio CODEC with FLEXSOUND Technology (VAVDD = VHPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to GND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CPREG = CREG = 1FF, CC1N-C1P = 1FF, CHPVSS = 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB, AVPGAIN_ = 0dB, AVPGAOUT_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS JACK DETECTION MICBIAS enabled JACKSNS High Threshold VTH1 MICBIAS disabled MICBIAS enabled JACKSNS Low Threshold VTH2 MICBIAS disabled 0.95 x 0.98 x 0.92 x VMICBIAS VMICBIAS VMICBIAS 0.92 x 0.10 x 0.17 x 0.06 x VMICBIAS VMICBIAS VMICBIAS 0.06 x VSENSE MICBIAS disabled RSENSE MICBIAS disabled, JDWK = 0 1.7 IWPU MICBIAS disabled, JDWK = 1 2 tGLITCH V 0.17 x 0.10 x V VSPKLVDD VSPKLVDD VSPKLVDD JACKSNS Sense Voltage JACKSNS Deglitch Period 0.98 x VSPKLVDD VSPKLVDD VSPKLVDD JACKSNS Sense Resistance JACKSNS Weak Pullup Current 0.95 x VSPKLVDD V 2.4 2.9 kI 5 9.5 FA JDEB = 00 25 JDEB = 11 200 ms BATTERY ADC Input Voltage Range 2.8 LSB Size 5.5 0.1 V V Digital Input/Output Characteristics (VAVDD = VHPVDD = VDVDD = VDVDDS1 = VDVDDS2 = 1.65V to 2.0V, VSPKLVDD = VSPKRVDD = 3.7V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 0.6 V +1 FA MCLK Input High Voltage VIH Input Low Voltage VIL Input Leakage Current IIH, IIL 1.2 VDVDD = 2.0V, VIN = 0V, 5.5V, TA = +25C V -1 Input Capacitance 10 pF SDINS1, BCLKS1, LRCLKS1--INPUT Input High Voltage VIH Input Low Voltage VIL 0.7 x DVDDS1 0.29 x DVDDS1 Input Hysteresis Input Leakage Current Input Capacitance V 200 IIH, IIL VDVDDS1 = 3.6V, VIN = 0V, 3.6V; TA = +25C -1 mV +1 10 V FA pF 19 MAX9888 ELECTRICAL CHARACTERISTICS (continued) MAX9888 Stereo Audio CODEC with FLEXSOUND Technology Digital Input/Output Characteristics (continued) (VAVDD = VHPVDD = VDVDD = VDVDDS1 = VDVDDS2 = 1.65V to 2.0V, VSPKLVDD = VSPKRVDD = 3.7V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 0.4 V BCLKS1, LRCLKS1, SDOUTS1--OUTPUT Output Low Voltage Output High Voltage Input Leakage Current VOL VOH IIH, IIL VDVDDS1 = 1.65V, IOL = 3mA VDVDDS1 = 1.65V, IOH = 3mA VDVDD = 2.0V, VIN = 0V, 5.5V; TA = +25C, high-impedance state DVDDS1 - 0.4 V -1 +1 FA SDINS2, BCLKS2, LRCLKS2--INPUT Input High Voltage VIH Input Low Voltage VIL 0.7 x DVDDS2 0.29 x DVDDS2 Input Hysteresis Input Leakage Current V 200 IIH, IIL VDVDDS2 = 3.6V, VIN = 0V, 3.6V; TA = +25C -1 Input Capacitance V mV +1 10 FA pF BCLKS2, LRCLKS2, SDOUTS2--OUTPUT Output Low Voltage Output High Voltage Input Leakage Current VOL VOH IIH, IIL VDVDDS2 = 1.65V, IOL = 3mA VDVDDS2 = 1.65V, IOH = 3mA VDVDD = 2.0V, VIN = 0V, 5.5V; TA = +25NC, high-impedance state 0.4 DVDDS2 - 0.4 V V -1 +1 FA SDA, SCL--INPUT Input High Voltage VIH Input Low Voltage VIL 0.7 x DVDD 0.3 x DVDD Input Hysteresis Input Leakage Current V 210 IIH, IIL VDVDD = 2.0V, VIN = 0V, 5.5V, TA = +25NC -1 Input Capacitance V mV +1 10 FA pF SDA, IRQ--OUTPUT Output High Current IOH VOUT = 5.5V, TA = +25C Output Low Voltage VOL VDVDD = 1.65V, IOL = 3mA 1 mA 0.2 x DVDD V DIGMICDATA--INPUT Input High Voltage VIH Input Low Voltage VIL 0.65 x DVDD 0.35 x DVDD Input Hysteresis Input Leakage Current Input Capacitance 20 V 125 IIH, IIL VDVDD = 2.0V, VIN = 0V, 2.0V; TA = +25C -25 mV +25 10 V FA pF Stereo Audio CODEC with FLEXSOUND Technology (VAVDD = VHPVDD = VDVDD = VDVDDS1 = VDVDDS2 = 1.65V to 2.0V, VSPKLVDD = VSPKRVDD = 3.7V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 0.4 V DIGMICCLK--OUTPUT Output Low Voltage VOL VDVDD = 1.65V, IOL = 1mA Output High Voltage VOH VDVDD = 1.65V, IOH = 1mA DVDD 0.4 V Input Clock Characteristics (VAVDD = VHPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.) (Note 1) PARAMETER MCLK Input Frequency MCLK Input Duty Cycle SYMBOL CONDITIONS MIN DAI1 LRCLK Average Frequency Error (Note 9) MHz PSCLK = 10 or 11 30 60 DHF_ = 0 8 48 DHF_ = 1 48 96 70 100 FREQ1 = 0x8 to 0xF FREQ1 = 0x0 0 0 +0.025 -0.025 +0.025 Rapid lock mode 2 7 Nonrapid lock mode 12 25 100 10 % psRMS -0.025 Maximum LRCLK Jitter to Maintain PLL Lock Soft-Start/Stop Time UNITS 60 40 DAI2 LRCLK Average Frequency Error (Note 9) PLL Lock Time 50 MAX PSCLK = 01 Maximum MCLK Input Jitter LRCLK Sample Rate (Note 8) TYP 10 fMCLK kHz % % ms ns ms 21 MAX9888 Digital Input/Output Characteristics (continued) MAX9888 Stereo Audio CODEC with FLEXSOUND Technology Audio Interface Timing Characteristics (VAVDD = VHPVDD = VDVDD = VDVDDS1 = VDVDDS2 = 1.65V, VSPKLVDD = VSPKRVDD = 2.8V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS BCLK Cycle Time tBCLK Slave mode 90 ns BCLK High Time tBCLKH Slave mode 20 ns BCLK Low Time tBCLKL Slave mode 20 ns 20 ns 20 ns tR, tF BCLK or LRCLK Rise and Fall Time SDIN to BCLK Setup Time Master mode, CL = 15pF ns tSETUP LRCLK to BCLK Setup Time tSYNCSET SDIN to BCLK Hold Time Slave mode tHOLD tSYNCHOLD Slave mode LRCLK to BCLK Hold Time Minimum Delay Time from LSB BCLK Falling Edge to High-Impedance State tHIZOUT Master mode, TDM_ = 1 LRCLK Rising Edge to SDOUT MSB Delay tSYNCTX CL = 30pF, TDM_ = 1, FSW_ = 1 BCLK to SDOUT Delay tCLKTX CL = 30pF Delay Time from BCLK to LRCLK tCLKSYNC Master mode Delay Time from LRCLK to BCLK After LSB tENDSYNC Master mode ns 42 ns 50 TDM_ = 1, BCLK rising edge 50 50 TDM_ = 1 -15 ns ns +15 0.8 x tBCLKL TDM_ = 0 TDM_ = 1, FSW_ = 1 20 tBCLKH BCLK (INPUT) tCLKSYNC tBCLKL tSYNCSET LRCLK (INPUT) tCLKTX tHIZOUT SDOUT (OUTPUT) LSB SDIN (INPUT) LSB tCLKTX tHIZOUT HI-Z tSETUP MSB tHOLD MSB MASTER MODE Figure 1. Non-TDM Audio Interface Timing Diagrams (TDM_ = 0) SDOUT (OUTPUT) LSB SDIN (INPUT) LSB ns ns tBCLK LRCLK (OUTPUT) 22 ns 20 TDM_ = 0 tF t BCLK R (OUTPUT) 20 HI-Z tSETUP MSB tHOLD MSB SLAVE MODE Stereo Audio CODEC with FLEXSOUND Technology MAX9888 tBCLK tF tR tBCLKH BCLK (OUTPUT) tBCLKL BCLK (INPUT) tCLKSYNC tSYNCSET tCLKSYNC LRCLK (OUTPUT) tSYNCHOLD LRCLK (INPUT) tCLKTX tHIZOUT SDOUT (OUTPUT) LSB SDOUT (OUTPUT) MSB HI-Z tCLKTX tHIZOUT LSB HI-Z MSB tSETUP tHOLD SDIN (INPUT) LSB tSETUP tHOLD SDIN (INPUT) MSB LSB MSB MASTER MODE SLAVE MODE Figure 2. TDM Audio Interface Timing Diagram (TDM_ = 1, FSW_ = 0) tBCLK tF tR tBCLKH BCLK (OUTPUT) tENDSYNC tCLKSYNC LRCLK (OUTPUT) LRCLK (INPUT) tSYNCTX tCLKTX HI-Z MSB tHIZOUT SDOUT (OUTPUT) tBCLKL BCLK (INPUT) LSB tHIZOUT SDOUT (OUTPUT) LSB tSYNCTX tCLKTX HI-Z MSB tSETUP tHOLD SDIN (INPUT) LSB tSETUP tHOLD SDIN (INPUT) MSB MASTER MODE LSB MSB SLAVE MODE Figure 3. TDM Audio Interface Timing Diagram (TDM_ = 1, FSW_ = 1) Digital Microphone Timing Characterstics (VAVDD = VHPVDD = VDVDD = VDVDDS1 = VDVDDS2 = 2.0V, VSPKLVDD = VSPKRVDD = 2.8V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MICCLK = 00 MCLK/8 MICCLK = 01 MCLK/6 MAX UNITS DIGMICCLK Frequency fMICCLK DIGMICDATA to DIGMICCLK Setup Time tSU,MIC Either clock edge 20 ns DIGMICDATA to DIGMICCLK Hold Time tHD,MIC Either clock edge 0 ns MHz 23 MAX9888 Stereo Audio CODEC with FLEXSOUND Technology 1/fMICCLK tHD,MIC tSU,MIC tHD,MIC tSU,MIC LEFT RIGHT LEFT RIGHT Figure 4. Digital Microphone Timing Diagram I2C Timing Characterstics (VAVDD = VHPVDD = VDVDD = VDVDDS1 = VDVDDS2 = 1.65V to 2.0V, VSPKLVDD = VSPKRVDD = 3.7V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.) (Note 1) PARAMETER SYMBOL CONDITIONS Guaranteed by SCL pulse-width low and high MIN 0 TYP MAX UNITS 400 kHz Serial-Clock Frequency fSCL Bus Free Time Between STOP and START Conditions tBUF 1.3 Fs tHD,STA 0.6 Fs SCL Pulse-Width Low tLOW 1.3 Fs SCL Pulse-Width High tHIGH 0.6 Fs Setup Time for a Repeated START Condition tSU,STA 0.6 Fs Data Hold Time Data Setup Time tHD,DAT tSU,DAT Hold Time (Repeated) START Condition RPU = 475I, CB = 100pF, 400pF 0 900 100 ns ns SDA and SCL Receiving Rise Time tR (Note 10) 20 + 0.1CB 300 ns SDA and SCL Receiving Fall Time tF (Note 10) 20 + 0.1CB 300 ns SDA Transmitting Fall Time tF RPU = 475I, CB = 100pF, 400pF (Note 10) 20 + 0.05CB 250 ns 400 pF 50 ns Setup Time for STOP Condition tSU,STO Bus Capacitance CB Pulse Width of Suppressed Spike tSP 24 0.6 Guaranteed by SDA transmitting fall time 0 Fs Stereo Audio CODEC with FLEXSOUND Technology MAX9888 SDA tSU,STA tSU,DAT tLOW tBUF tHD,STA tSP tHD,DAT tSU,STO tHIGH SCL tHD,STA tR tF START CONDITION REPEATED START CONDITION STOP CONDITION START CONDITION Figure 5. I2C Interface Timing Diagram Note 1: The IC is 100% production tested at TA = +25NC. Specifications over temperature limits are guaranteed by design. Note 2: Analog supply current = IAVDD + IHPVDD. Speaker supply current = ISPKLVDD + ISPKRVDD. Digital supply current = IDVDD + IDVDDS1 + IDVDDS2. Note 3: Clocking all zeros into the DAC. Slave mode. Note 4: Dynamic range measured using the EIAJ method. -60dBFS, 1kHz output signal, A-weighted and normalized to 0dBFS. f = 20Hz to 20kHz. Note 5: Gain measured relative to the 0dB setting. Note 6: The filter specification is accurate only for synchronous clocking modes, where NI is a multiple of 0x1000. Note 7: 0dBFS for DAC input. 1VP-P for INA/INB inputs. Note 8: LRCLK may be any rate in the indicated range. Asynchronous or noninteger MCLK/LRCLK ratios may exhibit some fullscale performance degradation compared to synchronous integer related MCLK/LRCLK ratios. Note 9: In master-mode operation, the accuracy of the MCLK input proportionally determines the accuracy of the sample clock rate. Note 10: CB is in pF. Power Consumption (VAVDD = VHPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V) IAVDD (mA) IHPVDD (mA) ISPKLVDD + ISPKRVDD (mA) IDVDD (mA) DAC Playback 48kHz Stereo HP DAC a HP 24-bit, music filters 1.35 1.37 1.65 2.91 0.02 16.25 DAC Playback 48kHz Stereo HP DAC a HP 24-bit, music filters, 0.1mW/channel, RHP = 32I 1.35 4.19 1.65 3.02 0.02 21.55 DAC Playback 48kHz Stereo HP DAC a HP 24-bit, music filters, ALC enabled 1.35 1.37 1.65 2.96 0.02 16.36 MODE IDVDDS1 + IDVDDS2 POWER (mA) (mW) 25 MAX9888 Stereo Audio CODEC with FLEXSOUND Technology Power Consumption (continued) (VAVDD = VHPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V) IAVDD (mA) IHPVDD (mA) ISPKLVDD + ISPKRVDD (mA) IDVDD (mA) DAC Playback 48kHz Stereo HP DAC a HP 24-bit, music filters, EQ enabled 1.35 1.36 1.65 3.27 0.02 16.90 DAC Playback 48kHz Stereo HP DAC a HP 24-bit, music filters, digital mixing 1.34 1.36 1.65 2.91 0.02 16.27 DAC Playback 44.1kHz Stereo HP DAC a HP 24-bit, music filters 1.35 1.37 1.69 2.85 0.02 16.29 DAC Playback 8kHz Stereo HP DAC a HP 16-bit, voice filters 1.35 1.37 1.65 1.46 0.01 13.65 DAC Playback 8kHz Mono HP DAC a HP 16-bit, voice filters 1.00 0.71 1.01 1.36 0.01 9.27 DAC Playback 48kHz Stereo SPK DAC a SPK 24-bit, music filters 1.83 0.02 8.22 2.92 0.02 39.09 DAC Playback 48kHz Mono SPK DAC a SPK 24-bit, music filters 1.25 0.02 4.31 2.82 0.02 23.32 Line Stereo Record 48kHz INA a ADC 16-bit, music filters 9.91 0.02 0.39 1.62 0.11 22.48 Line Stereo Record 48kHz, Stereo HP INA a ADC INA a HP 16-bit, music filters 10.64 2.65 0.66 1.63 0.11 29.51 Line Stereo Record 48kHz, Stereo SPK INA a ADC INA a SPK 16-bit, music filters 10.97 0.03 7.15 1.63 0.12 49.50 Differential Line Record 48kHz INA a ADCL INB a ADCR Differential input 10.49 0.02 0.39 1.63 0.16 23.58 Microphone Stereo Record 48kHz MIC1/2 a ADC 16-bit, music filters 10.88 0.03 0.69 1.62 0.17 25.43 Microphone Stereo Record 8kHz MIC1/2 a ADC 16-bit, voice filters 10.77 0.02 0.64 1.03 0.06 23.78 MODE 26 IDVDDS1 + IDVDDS2 POWER (mA) (mW) Stereo Audio CODEC with FLEXSOUND Technology IAVDD (mA) IHPVDD (mA) ISPKLVDD + ISPKRVDD (mA) IDVDD (mA) Microphone Mono Record 48kHz MIC1/2 a ADC 16-bit, music filters 6.01 0.02 0.66 1.37 0.10 15.97 Microphone Mono Record 8kHz MIC1/2 a ADC 16-bit, voice filters 5.95 0.02 0.64 0.98 0.04 14.94 Microphone Mono Record 8kHz MIC1/2 a ADC 16-bit, voice filters, AGC 5.95 0.02 0.64 0.98 0.04 15.00 Microphone Mono Record 8kHz MIC1/2 a ADC 16-bit, voice filters, AGC, noise gate 5.96 0.02 0.64 0.98 0.04 14.98 Full-Duplex 48kHz Stereo HP MIC1/2 a ADC DAC a HP 24-bit, music filters 11.38 1.37 1.70 3.56 0.19 36.06 Full-Duplex 8kHz Mono RCV MIC1 a ADC DAC a REC 16-bit, voice filters 6.35 0.02 1.98 1.47 0.03 21.47 Full-Duplex 8kHz Mono HP MIC1 a ADC DAC a HP 16-bit, voice filters 6.09 0.71 1.01 1.46 0.03 18.72 Full-Duplex 8kHz Stereo HP MIC1/2 a ADC DAC a HP 16-bit, voice filters 10.92 1.37 1.09 1.51 0.05 28.95 Line Playback Stereo HP INA a HP Single-ended inputs 1.89 2.65 0.58 0.03 0.01 10.41 Line Playback Stereo SPK INA a SPK Single-ended inputs 2.21 0.02 7.05 0.04 0.02 30.19 Line Playback Mono SPK INA a SPK Single-ended inputs 1.68 0.02 3.70 0.03 0.02 16.90 Differential Line Playback Stereo HP INA a HPL INB a HPR Differential input 2.46 2.65 0.58 0.03 0.01 11.42 MODE IDVDDS1 + IDVDDS2 POWER (mA) (mW) 27 MAX9888 Power Consumption (continued) (VAVDD = VHPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V) Typical Operating Characteristics (VAVDD = VHPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to GND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CPREG = CREG = 1FF, CC1N-C1P = 1FF, CHPVSS = 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB, AVPGAIN_ = 0dB, AVPGAOUT_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. TA = +25NC, unless otherwise noted.) Microphone to ADC -40 -50 -60 -70 -40 -50 -60 -30 -50 -60 -70 -80 -90 -80 -90 -90 100 1000 10,000 100,000 10 1000 10,000 100,000 TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY (MIC TO ADC) TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY (MIC TO ADC) 0 -50 -60 -70 MCLK = 13MHz LRCLK = 8kHz FREQ MODE VIN = 0.1VP-P AVMICPRE_ = +20dB -10 -20 -30 0 -40 -50 -60 -70 -20 -30 -40 -50 -60 -70 -80 -90 -90 -90 -100 -100 -100 1000 FREQUENCY (Hz) 10,000 100,000 MCLK = 13MHz LRCLK = 8kHz FREQ MODE VIN = 0.032VP-P AVMICPRE_ = +30dB -10 -80 100 MAX9888 toc06 TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY (MIC TO ADC) -40 10 100 FREQUENCY (Hz) THD+N RATIO (dB) -30 100 FREQUENCY (Hz) THD+N RATIO (dB) -20 -100 10 FREQUENCY (Hz) MCLK = 12.288MHz LRCLK = 96kHz NI MODE VIN = 1VP-P AVMICPRE_ = 0dB -10 10,000 MAX9888 toc04 0 1000 MAX9888 toc03 -40 -70 10 MCLK = 12.288MHz LRCLK = 48kHz NI MODE VIN = 1VP-P AVMICPRE_ = 0dB -20 -80 -100 28 -30 0 -10 THD+N RATIO (dB) -20 TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY (MIC TO ADC) MAX9888 toc05 THD+N RATIO (dB) -30 MCLK = 13MHz LRCLK = 44.1kHz PLL MODE VIN = 1VP-P AVMICPRE_ = 0dB -10 THD+N RATIO (dB) MCLK = 13MHz LRCLK = 8kHz FREQ MODE VIN = 1VP-P AVMICPRE_ = 0dB -20 0 MAX9888 toc01 0 -10 TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY (MIC TO ADC) MAX9888 toc02 TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY (MIC TO ADC) THD+N RATIO (dB) MAX9888 Stereo Audio CODEC with FLEXSOUND Technology -80 10 100 1000 FREQUENCY (Hz) 10,000 10 100 1000 FREQUENCY (Hz) 10,000 Stereo Audio CODEC with FLEXSOUND Technology (VAVDD = VHPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to GND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CPREG = CREG = 1FF, CC1N-C1P = 1FF, CHPVSS = 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB, AVPGAIN_ = 0dB, AVPGAOUT_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. TA = +25NC, unless otherwise noted.) COMMON-MODE REJECTION RATIO vs. FREQUENCY (MIC TO ADC) 60 -35 MCLK = 13MHz LRCLK = 8kHz FREQ MODE VIN = 1VP-P AVMICPRE_ = 0dB -55 -65 -75 MODE = 0 40 AVMICPRE_ = 0dB 30 20 VOUT, DIFF = 0dBFS 0 10 100 1000 10,000 10 FREQUENCY (Hz) 10,000 100,000 10 -80 -40 -60 -80 -40 -60 -80 -120 -120 -120 -140 FREQUENCY (Hz) 100,000 MCLK = 13MHz LRCLK = 44.1kHz PLL MODE AVMICPRE_ = 0dB -20 -100 500 1000 1500 2000 2500 3000 3500 4000 10,000 FFT, 0dBFS (MIC TO ADC) -100 -140 1000 0 -100 0 100 FREQUENCY (Hz) AMPLITUDE (dBV) -60 MCLK = 13MHz LRCLK = 8kHz FREQ MODE AVMICPRE_ = 0dB -20 AMPLITUDE (dBV) AMPLITUDE (dBV) -40 -120 1000 FFT, -60dBFS (MIC TO ADC) 0 MAX9888 toc10 MCLK = 13MHz LRCLK = 8kHz FREQ MODE AVMICPRE_ = 0dB -20 100 RIPPLE ON SPKLVDD, SPKRVDD FREQUENCY (Hz) FFT, 0dBFS (MIC TO ADC) 0 RIPPLE ON AVDD, DVDD, HPVDD -100 10 -85 -60 -80 MAX9888 toc11 -45 -40 AVMICPRE_ = +20dB 50 VRIPPLE = 200mVP-P INPUTS AC GROUNDED -20 PSRR (dB) -25 MAX9888 toc09 AVMICPRE_ = +30dB 70 0 MAX9888 toc08 80 CMRR (dB) NORMALIZED GAIN (dB) MODE = 1 -15 90 MAX9888 toc07 5 -5 POWER-SUPPLY REJECTION RATIO vs. FREQUENCY (MIC TO ADC) MAX9888 toc12 GAIN vs. FREQUENCY (MIC TO ADC) -140 0 500 1000 1500 2000 2500 3000 3500 4000 FREQUENCY (Hz) 0 5000 10,000 15,000 20,000 FREQUENCY (Hz) 29 MAX9888 Typical Operating Characteristics (continued) Typical Operating Characteristics (continued) (VAVDD = VHPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to GND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CPREG = CREG = 1FF, CC1N-C1P = 1FF, CHPVSS = 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB, AVPGAIN_ = 0dB, AVPGAOUT_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. TA = +25NC, unless otherwise noted.) -60 -80 MCLK = 12.288MHz LRCLK = 48kHz NI MODE AVMICPRE_ = 0dB -20 AMPLITUDE (dBV) -40 MAX9888 toc13 MCLK = 13MHz LRCLK = 44.1kHz PLL MODE AVMICPRE_ = 0dB -20 -40 -60 -80 -100 -100 -120 -120 -140 -140 0 5000 10,000 15,000 20,000 0 5000 FREQUENCY (Hz) FFT, -60dBFS (MIC TO ADC) MCLK = 12.288MHz LRCLK = 48kHz NI MODE AVMICPRE_ = 0dB -20 -60 -80 -40 -60 -80 -100 -100 -120 -120 -140 -140 0 5000 10,000 FREQUENCY (Hz) 30 20,000 MCLK = 12.288MHz LRCLK = 96kHz NI MODE AVMICPRE_ = 0dB -20 AMPLITUDE (dBV) -40 15,000 FFT, 0dBFS (MIC TO ADC) 0 MAX9888 toc15 0 10,000 FREQUENCY (Hz) MAX9888 toc16 AMPLITUDE (dBV) FFT, 0dBFS (MIC TO ADC) 0 MAX9888 toc14 FFT, -60dBFS (MIC TO ADC) 0 AMPLITUDE (dBV) MAX9888 Stereo Audio CODEC with FLEXSOUND Technology 15,000 20,000 0 5000 10,000 FREQUENCY (Hz) 15,000 20,000 Stereo Audio CODEC with FLEXSOUND Technology (VAVDD = VHPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to GND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CPREG = CREG = 1FF, CC1N-C1P = 1FF, CHPVSS = 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB, AVPGAIN_ = 0dB, AVPGAOUT_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. TA = +25NC, unless otherwise noted.) FFT, -60dBFS (MIC TO ADC) MCLK = 12.288MHz LRCLK = 96kHz NI MODE AVMICPRE_ = 0dB AMPLITUDE (dBV) -20 -40 ADC ENABLE/DISABLE RESPONSE (MIC TO ADC) MAX9888 toc17 0 MAX9888 toc18 SCL 2V/div -60 ADC OUTPUT 0.5V/div -80 -100 -120 -140 0 5000 10,000 15,000 20,000 FREQUENCY (Hz) 10ms/div SOFTWARE TURN-ON/OFF RESPONSE (MIC TO ADC) MAX9888 toc19 SCL 2V/div ADC OUTPUT 0.5V/div 10ms/div 31 MAX9888 Typical Operating Characteristics (continued) Typical Operating Characteristics (continued) (VAVDD = VHPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to GND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CPREG = CREG = 1FF, CC1N-C1P = 1FF, CHPVSS = 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB, AVPGAIN_ = 0dB, AVPGAOUT_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. TA = +25NC, unless otherwise noted.) Line to ADC -40 -50 -60 -30 -40 -20 -50 -60 -70 -40 -50 -60 -70 -80 -80 -80 -90 -90 -100 -100 10 100 1000 10,000 100,000 100 10 FREQUENCY (Hz) 1000 10,000 MCLK = 12.288MHz LRCLK = 48kHz NI MODE VIN = 1VRMS -30 POWER-SUPPLY REJECTION RATIO vs. FREQUENCY (LINE TO ADC) 0 EXTERNAL GAIN MODE RIN = 56kI, CIN = 1F -40 -50 -60 VRIPPLE = 200mVP-P INPUTS AC GROUNDED -20 -40 PSRR (dB) THD+N RATIO (dB) -20 1000 FREQUENCY (Hz) FREQUENCY (Hz) MAX9888 toc23 0 -10 100 10 100,000 TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY (LINE TO ADC) -60 RIPPLE ON AVDD, DVDD, HPVDD -80 -70 -80 -100 RIPPLE ON SPKLVDD, SPKRVDD -90 -100 -120 10 100 1000 FREQUENCY (Hz) 32 -30 -70 -90 MCLK = 12.288MHz LRCLK = 48kHz NI MODE VIN = 0.1VP-P AVPGAIN_ = +20dB 10,000 MAX9888 toc22 -20 0 -10 MAX9888 toc24 -30 MCLK = 12.288MHz LRCLK = 48kHz NI MODE VIN = 1VP-P CIN = 1F AVPGAIN_ = 0dB THD+N RATIO (dB) -20 0 -10 THD+N RATIO (dB) MCLK = 12.288MHz LRCLK = 48kHz NI MODE VIN = 1.4VP-P AVPGAIN_ = -6dB CIN = 1F MAX9888 toc20 0 -10 TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY (LINE TO ADC) TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY (LINE TO ADC) MAX9888 toc21 TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY (LINE TO ADC) THD+N RATIO (dB) MAX9888 Stereo Audio CODEC with FLEXSOUND Technology 100,000 10 100 1000 FREQUENCY (Hz) 10,000 100,000 10,000 100,000 Stereo Audio CODEC with FLEXSOUND Technology (VAVDD = VHPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to GND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CPREG = CREG = 1FF, CC1N-C1P = 1FF, CHPVSS = 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB, AVPGAIN_ = 0dB, AVPGAOUT_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. TA = +25NC, unless otherwise noted.) Digital Loopback MCLK = 12.288MHz LRCLK = 48kHz NI MODE -60 -80 -100 -120 -40 -60 -80 -100 -120 -140 -140 -160 -160 -180 MCLK = 12.288MHz LRCLK = 48kHz NI MODE -20 AMPLITUDE (dBFS) AMPLITUDE (dBFS) -40 0 MAX9888 toc25 0 -20 FFT, -60dBFS (SDINS1 TO SDOUTS2 DIGITAL LOOPBACK) MAX9888 toc26 FFT, 0dBFS (SDINS1 TO SDOUTS2 DIGITAL LOOPBACK) -180 0 5000 10,000 FREQUENCY (Hz) 15,000 20,000 0 5000 10,000 15,000 20,000 FREQUENCY (Hz) 33 MAX9888 Typical Operating Characteristics (continued) Typical Operating Characteristics (continued) (VAVDD = VHPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to GND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CPREG = CREG = 1FF, CC1N-C1P = 1FF, CHPVSS = 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB, AVPGAIN_ = 0dB, AVPGAOUT_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. TA = +25NC, unless otherwise noted.) Analog Loopback -60 -70 -40 POUT = 0.025W -50 -60 -80 POUT = 0.01W -90 100 1000 10,000 100,000 -80 -140 10 100 1000 10,000 0 100,000 5000 10,000 15,000 20,000 FREQUENCY (Hz) FREQUENCY (Hz) FREQUENCY (Hz) FFT, -60dBFS (LINE TO ADC TO DAC TO HEADPHONE) FFT, 0dBFS (LINE TO ADC TO DAC TO HEADPHONE) FFT, -60dBFS (LINE TO ADC TO DAC TO HEADPHONE) -20 -60 -80 MCLK = 12.288MHz LRCLK = 48kHz NI MODE RHP = 32I -20 AMPLITUDE (dBV) -40 0 -40 0 -60 -80 -40 -60 -80 -100 -100 -100 -120 -120 -120 -140 -140 0 5000 10,000 FREQUENCY (Hz) 15,000 20,000 MCLK = 12.288MHz LRCLK = 48kHz NI MODE RHP = 32I -20 AMPLITUDE (dBV) MCLK = 13MHz LRCLK = 44.1kHz PLL MODE RHP = 32I MAX9888 toc30 0 MAX9888 toc29 -60 -120 POUT = 0.01W -90 10 -40 -100 -70 -80 34 -30 MCLK = 13MHz LRCLK = 44.1kHz PLL MODE RHP = 32I -20 MAX9888 toc32 POUT = 0.025W 0 AMPLITUDE (dBV) -40 -50 -20 FFT, 0dBFS (LINE TO ADC TO DAC TO HEADPHONE) MAX9888 toc31 THD+N RATIO (dB) -30 MCLK = 12.288MHz LRCLK = 48kHz NI MODE RHP = 32I, CIN = 1F -10 THD+N RATIO (dB) MCLK = 13MHz LRCLK = 44.1kHz PLL MODE RHP = 32I, CIN = 1F -20 0 MAX9888 toc27 0 -10 TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY (LINE TO ADC TO DAC TO HEADPHONE ) MAX9888 toc28 TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY (LINE TO ADC TO DAC TO HEADPHONE) AMPLITUDE (dBV) MAX9888 Stereo Audio CODEC with FLEXSOUND Technology -140 0 5000 10,000 FREQUENCY (Hz) 15,000 20,000 0 5000 10,000 FREQUENCY (Hz) 15,000 20,000 Stereo Audio CODEC with FLEXSOUND Technology (VAVDD = VHPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to GND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CPREG = CREG = 1FF, CC1N-C1P = 1FF, CHPVSS = 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB, AVPGAIN_ = 0dB, AVPGAOUT_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. TA = +25NC, unless otherwise noted.) DAC to Receiver f = 3000Hz f = 1000Hz -60 -70 POUT = 0.05W -50 -60 -80 f = 100Hz -90 0.04 0.06 0.08 2 100 10 1000 POWER CONSUMPTION vs. OUTPUT POWER (DAC TO RECEIVER) 1 0 -1 -2 -3 110 THD+N = 1% 100 90 MCLK = 13MHz LRCLK = 8kHz FREQ MODE RREC = 32I AVREC = +8dB 80 70 2.5 3.0 0.15 0.10 100 1000 FREQUENCY (Hz) 10,000 4.5 5.0 5.5 0 VRIPPLE = 200mVP-P ALL ZEROS AT INPUT -20 -40 RIPPLE ON SPKLVDD, SPKRVDD -60 -80 0.05 10 4.0 POWER-SUPPLY REJECTION RATIO vs. FREQUENCY (DAC TO RECEIVER) RIPPLE ON AVDD, DVDD, HPVDD -4 -5 3.5 SUPPLY VOLTAGE (V) MCLK = 13MHz LRCLK = 8kHz FREQ MODE RREC = 32I AVREC = +8dB 0.20 THD+N = 10% 120 60 GAIN vs. FREQUENCY (DAC TO RECEIVER) 0.25 130 10,000 FREQUENCY (Hz) POWER CONSUMPTION (W) 3 -90 0.12 OUTPUT POWER (W) MCLK = 13MHz LRCLK = 8kHz FREQ MODE RREC = 32I 4 0.10 PSRR (dB) 5 0.02 MAX9888 toc36 0 POUT = 0.025W MAX9888 toc35 MAX9888 toc34 -40 -70 -80 NORMALIZED GAIN (dB) -30 140 OUTPUT POWER PER CHANNEL (mW) -40 -50 -20 OUTPUT POWER vs. SUPPLY VOLTAGE (DAC TO RECEIVER) MAX9888 toc37 THD+N RATIO (dB) -30 MCLK = 13MHz LRCLK = 8kHz FREQ MODE RREC = 32I -10 THD+N RATIO (dB) MCLK = 13MHz LRCLK = 8kHz FREQ MODE RREC = 32I AVREC = +8dB -20 0 MAX9888 toc33 0 -10 TOTAL HARMONIC DISTORTION vs. FREQUENCY (DAC TO RECEIVER) MAX9888 toc38 TOTAL HARMONIC DISTORTION vs. OUTPUT POWER (DAC TO RECEIVER) 0 -100 0 0.02 0.04 0.06 0.08 OUTPUT POWER (W) 0.10 0.12 10 100 1000 10,000 100,000 FREQUENCY (Hz) 35 MAX9888 Typical Operating Characteristics (continued) Typical Operating Characteristics (continued) (VAVDD = VHPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to GND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CPREG = CREG = 1FF, CC1N-C1P = 1FF, CHPVSS = 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB, AVPGAIN_ = 0dB, AVPGAOUT_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. TA = +25NC, unless otherwise noted.) SOFTWARE TURN-ON/OFF RESPONSE (DAC TO RECEIVER, VSEN = 1) MAX9888 toc39 SCL 2V/div FFT, 0dBFS (DAC TO RECEIVER) MAX9888 toc40 0 SCL 2V/div AMPLITUDE (dBV) RECEIVER OUTPUT 1V/div MCLK = 13MHz LRCLK = 8kHz FREQ MODE RREC = 32I -20 RECEIVER OUTPUT 1V/div -40 MAX9888 toc41 SOFTWARE TURN-ON/OFF RESPONSE (DAC TO RECEIVER, VSEN = 0) -60 -80 -100 -120 -140 10ms/div 0 10ms/div 5000 10,000 15,000 20,000 FREQUENCY (Hz) -60 -80 -100 -40 -60 -80 -100 -120 -140 0 5000 10,000 FREQUENCY (Hz) 36 -20 AMPLITUDE (dBm) -40 MCLK = 13MHz LRCLK = 8kHz PLL MODE RREC = 32I 15,000 20,000 0 MCLK = 13MHz LRCLK = 8kHz PLL MODE RREC = 32I -20 AMPLITUDE (dBm) -20 0 MAX9888 toc43 MCLK = 13MHz LRCLK = 8kHz FREQ MODE RREC = 32I MAX9888 toc42 0 WIDEBAND FFT, -60dBFS (DAC TO RECEIVER) MAX9888 toc44 WIDEBAND FFT, 0dBFS (DAC TO RECEIVER) FFT, -60dBFS (DAC TO RECEIVER) AMPLITUDE (dBV) MAX9888 Stereo Audio CODEC with FLEXSOUND Technology -40 -60 -80 -100 -120 -120 0 1 10 100 FREQUENCY (kHz) 1000 10,000 0 1 10 100 FREQUENCY (kHz) 1000 10,000 Stereo Audio CODEC with FLEXSOUND Technology (VAVDD = VHPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to GND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CPREG = CREG = 1FF, CC1N-C1P = 1FF, CHPVSS = 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB, AVPGAIN_ = 0dB, AVPGAOUT_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. TA = +25NC, unless otherwise noted.) Line to Receiver TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER (LINE TO RECEIVER) -10 0 -20 THD+N RATIO (dB) -40 f = 6000Hz -50 -60 -30 -40 -50 POUT = 0.05W -60 -70 -70 -80 f = 1000Hz f = 100Hz -80 0 0.02 0.04 0.06 0.08 POUT = 0.025W -90 0.10 10 100 OUTPUT POWER (W) 3 100,000 VRIPPLE = 200mVP-P INPUT AC GROUNDED -20 2 1 PSRR (dB) NORMALIZED GAIN (dB) 0 MAX9888 toc47 RREC = 32I CIN = 1F 4 10,000 POWER-SUPPLY REJECTION RATIO vs. FREQUENCY (LINE TO RECEIVER) GAIN vs. FREQUENCY (LINE TO RECEIVER) 5 1000 FREQUENCY (Hz) MAX9888 toc48 THD+N RATIO (dB) -30 RREC = 32I CIN = 1F AVREC = +8dB -10 -20 MAX9888 toc46 RREC = 32I AVREC = +8dB MAX9888 toc45 0 TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY (LINE TO RECEIVER) 0 -1 -40 RIPPLE ON SPKLVDD, SPKRVDD -60 -2 -3 -80 RIPPLE ON AVDD, DVDD, HPVDD -4 -5 10 100 1000 FREQUENCY (Hz) 10,000 100,000 -100 10 100 1000 10,000 100,000 FREQUENCY (Hz) 37 MAX9888 Typical Operating Characteristics (continued) Typical Operating Characteristics (continued) (VAVDD = VHPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to GND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CPREG = CREG = 1FF, CC1N-C1P = 1FF, CHPVSS = 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB, AVPGAIN_ = 0dB, AVPGAOUT_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. TA = +25NC, unless otherwise noted.) DAC to Speaker -40 -20 f = 6000Hz -50 f = 1000Hz -60 -40 -80 -50 -90 0 0.2 0.4 0.6 0.8 1.0 -40 f = 6000Hz -50 f = 1000Hz -70 f = 100Hz -80 1.2 -30 -60 f = 1000Hz -70 f = 100Hz VSPK_VDD = 3.V MCLK = 12.288MHz, LRCLK = 48kHz NI MODE ZSPK = 8I + 68H AVSPK_ = +8dB -10 -20 f = 6000Hz -60 -70 0 f = 100Hz -80 0.2 0.4 0.6 0.8 1.0 0 0.1 0.2 0.3 0.4 0.5 0.6 OUTPUT POWER (W) OUTPUT POWER (W) OUTPUT POWER (W) TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER (DAC TO SPEAKER) TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER (DAC TO SPEAKER) TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER (DAC TO SPEAKER) f = 6000Hz -40 -50 f = 1000Hz -60 -20 -70 -30 f = 6000Hz -40 -50 f = 1000Hz -60 -70 -80 0 0.5 1.0 1.5 OUTPUT POWER (W) 2.0 2.5 VSPK_VDD = 3V MCLK = 12.288MHz, LRCLK = 48kHz NI MODE ZSPK = 4I + 33H AVSPK_ = +8dB -10 -20 -30 -40 f = 6000Hz -50 f = 1000Hz -60 -70 -80 f = 100Hz -90 MAX9888 toc54 -10 0 THD+N RATIO (dB) -30 VSPK_VDD = 3.7V MCLK = 12.288MHz, LRCLK = 48kHz NI MODE ZSPK = 4I + 33H AVSPK_ = +8dB MAX9888 toc53 -20 0 THD+N RATIO (dB) VSPK_VDD = 4.2V MCLK = 12.288MHz, LRCLK = 48kHz NI MODE ZSPK = 4I + 33H AVSPK_ = +8dB MAX9888 toc52 0 -10 38 -30 0 THD+N RATIO (dB) -30 -10 THD+N RATIO (dB) THD+N RATIO (dB) -20 VSPK_VDD = 3.7V MCLK = 12.288MHz, LRCLK = 48kHz NI MODE ZSPK = 8I + 68H AVSPK_ = +8dB TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER (DAC TO SPEAKER) MAX9888 toc50 VSPK_VDD = 4.2V MCLK = 12.288MHz, LRCLK = 48kHz NI MODE ZSPK = 8I + 68H AVSPK_ = +8dB -10 0 MAX9888 toc49 0 TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER (DAC TO SPEAKER) MAX9888 toc51 TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER (DAC TO SPEAKER) THD+N RATIO (dB) MAX9888 Stereo Audio CODEC with FLEXSOUND Technology -80 f = 100Hz -90 0 f = 100Hz -90 0.5 1.0 OUTPUT POWER (W) 1.5 2.0 0 0.2 0.4 0.6 0.8 1.0 OUTPUT POWER (W) 1.2 1.4 Stereo Audio CODEC with FLEXSOUND Technology (VAVDD = VHPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to GND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CPREG = CREG = 1FF, CC1N-C1P = 1FF, CHPVSS = 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB, AVPGAIN_ = 0dB, AVPGAOUT_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. TA = +25NC, unless otherwise noted.) -40 -50 -60 POUT = 0.25W -70 -40 MAX9888 toc56 -50 -60 0 POUT = 0.25W -20 10 100 1000 10,000 -40 POUT = 1.0W -50 -60 POUT = 0.5W -80 POUT = 0.55W -90 100,000 -30 -70 -80 POUT = 0.55W -90 VSPK_VDD = 4.2V MCLK = 12.288MHz, LRCLK = 48kHz NI MODE ZSPK = 4I + 33H -10 -70 -80 10 100 -90 1000 100,000 10,000 10 100 1000 100,000 10,000 FREQUENCY (Hz) FREQUENCY (Hz) FREQUENCY (Hz) TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY (DAC TO SPEAKER) OUTPUT POWER vs. SUPPLY VOLTAGE (DAC TO SPEAKER) OUTPUT POWER vs. SUPPLY VOLTAGE (DAC TO SPEAKER) -30 POUT = 1.0W -40 -50 -60 POUT = 0.5W -70 -80 -90 10 100 1000 FREQUENCY (Hz) 10,000 100,000 MCLK = 12.288MHz, LRCLK = 48kHz NI MODE ZSPK = 8I + 68H 2000 1800 1600 THD+N = 10% 1400 1200 1000 800 THD+N = 1% 600 400 3500 MAX9888 toc60 -20 2200 OUTPUT POWER PER CHANNEL (mW) VSPK_VDD = 3.7V MCLK = 12.288MHz, LRCLK = 48kHz NI MODE ZSPK = 4I + 33H OUTPUT POWER PER CHANNEL (mW) MAX9888 toc58 0 -10 THD+N RATIO (dB) -30 TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY (DAC TO SPEAKER) THD+N RATIO (dB) -30 -20 MAX9888 toc59 THD+N RATIO (dB) -20 VSPK_VDD = 3.7V MCLK = 12.288MHz, LRCLK = 48kHz NI MODE ZSPK = 8I + 68H AVSPK_ = +8dB -10 THD+N RATIO (dB) VSPK_VDD = 4.2V MCLK = 12.288MHz, LRCLK = 48kHz NI MODE ZSPK = 8I + 68H AVSPK_ = +8dB -10 0 MAX9888 toc55 0 TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY (DAC TO SPEAKER) MAX9888 toc57 TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY (DAC TO SPEAKER) MCLK = 12.288MHz, LRCLK = 48kHz NI MODE ZSPK = 4I + 33H 3000 2500 2000 1500 THD+N = 1% 1000 THD+N = 10% 500 0 2.5 3.0 3.5 4.0 4.5 SUPPLY VOLTAGE (V) 5.0 5.5 2.5 3.0 3.5 4.0 4.5 5.0 5.5 SUPPLY VOLTAGE (V) 39 MAX9888 Typical Operating Characteristics (continued) Typical Operating Characteristics (continued) (VAVDD = VHPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to GND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CPREG = CREG = 1FF, CC1N-C1P = 1FF, CHPVSS = 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB, AVPGAIN_ = 0dB, AVPGAOUT_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. TA = +25NC, unless otherwise noted.) GAIN vs. FREQUENCY (DAC TO SPEAKER) -1 70 60 30 -3 20 -4 10 -5 0 1000 10,000 100,000 VSPK_VDD = 4.2V MCLK = 12.288MHz, LRCLK = 48kHz NI MODE AVSPK_ = +8dB 15 10 1.0 1.5 3.5 4.0 4.5 2.0 VRIPPLE = 200mVP-P -20 MAX9888 toc63 VSPK_VDD = 3.7V MCLK = 12.288MHz, LRCLK = 48kHz NI MODE AVSPK_ = +8dB 20 10 0 2.5 5.0 SPK_VDD SUPPLY VOLTAGE (V) 5.5 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 OUTPUT POWER PER CHANNEL (W) POWER-SUPPLY REJECTION RATIO vs. SUPPLY VOLTAGE (DAC TO SPEAKER) RIPPLE ON SPKLVDD, SPKRVDD -40 -60 -80 5 0 40 0.5 0 PSRR (dB) MCLK = 12.288MHz, LRCLK = 48kHz ZSPK = 8I + 68H NI MODE AVSPK_ = +8dB ALL ZEROS AT INPUT 3.0 ZSPK = 8I + 68H 40 POWER-SUPPLY REJECTION RATIO vs. FREQUENCY (DAC TO SPEAKER) MAX9888 toc64 30 2.5 ZSPK = 4I + 33H 50 OUTPUT POWER PER CHANNEL (W) SUPPLY CURRENT vs. SUPPLY VOLTAGE (DAC TO SPEAKER) 20 60 0 0 FREQUENCY (Hz) 25 70 30 0 RIPPLE ON SPKLVDD, SPKRVDD VRIPPLE = 200mVP-P f = 1kHz -20 PSRR (dB) 100 ZSPK = 8I + 68H 40 -2 10 4I ++ 33H 33H ZZSPK SPK == 4I 50 80 MAX9888 toc66 0 MAX9888 toc62 80 90 EFFICIENCY (%) 1 100 MAX9888 toc65 2 90 EFFICIENCY (%) NORMALIZED GAIN (dB) 3 100 MAX9888 toc61 MCLK = 12.288MHz, LRCLK = 48kHz NI MODE ZSPK = 8I + 68H 4 EFFICIENCY vs. OUTPUT POWER (DAC TO SPEAKER) EFFICIENCY vs. OUTPUT POWER (DAC TO SPEAKER) 5 SPK_VDD SUPPLY CURRENT (mA) MAX9888 Stereo Audio CODEC with FLEXSOUND Technology -40 -60 -80 RIPPLE ON AVDD, DVDD, HPVDD -100 -100 10 100 1000 FREQUENCY (Hz) 10,000 100,000 2.5 3.0 3.5 4.0 4.5 SUPPLY VOLTAGE (V) 5.0 5.5 Stereo Audio CODEC with FLEXSOUND Technology (VAVDD = VHPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to GND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CPREG = CREG = 1FF, CC1N-C1P = 1FF, CHPVSS = 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB, AVPGAIN_ = 0dB, AVPGAOUT_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. TA = +25NC, unless otherwise noted.) CROSSTALK (dB) MAX9888 toc67 MCLK = 12.288MHz, LRCLK = 48kHz NI MODE ZSPK = 8I + 68H -20 -30 MAX9888 toc69 MAX9888 toc68 0 -10 SOFTWARE TURN-ON/OFF RESPONSE (DAC TO SPEAKER, VSEN = 1) SOFTWARE TURN-ON/OFF RESPONSE (DAC TO SPEAKER, VSEN = 0) CROSSTALK vs. FREQUENCY (DAC TO SPEAKER) -40 -50 SCL 2V/div SCL 2V/div SPEAKER OUTPUT 1V/div SPEAKER OUTPUT 1V/div -60 -70 -80 -90 10 100 1000 10,000 10ms/div 10ms/div FFT, -60dBFS (DAC TO SPEAKER) WIDEBAND FFT (DAC TO SPEAKER) 100,000 FFT, -60dBFS (DAC TO SPEAKER) -60 -80 -40 -120 -120 -140 0 5000 10,000 FREQUENCY (Hz) 15,000 20,000 MAX9888 toc71 -80 -100 MCLK = 13MHz, LRCLK = 44.1kHz PLL MODE ZSPK = 8I + 68H 10 0 -60 -100 20 AMPLITUDE (dBm) AMPLITUDE (dBV) -40 MCLK = 13MHz, LRCLK = 44.1kHz PLL MODE ZSPK = 8I + 68H -20 AMPLITUDE (dbV) MCLK = 12.288MHz, LRCLK = 48kHz NI MODE ZSPK = 8I + 68H -20 0 MAX9888 toc70 0 MAX9888 toc72 FREQUENCY (Hz) -10 -20 -30 -40 -50 -140 -60 0 5000 10,000 FREQUENCY (Hz) 15,000 20,000 1 10 100 FREQUENCY (MHz) 41 MAX9888 Typical Operating Characteristics (continued) Typical Operating Characteristics (continued) (VAVDD = VHPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to GND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CPREG = CREG = 1FF, CC1N-C1P = 1FF, CHPVSS = 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB, AVPGAIN_ = 0dB, AVPGAOUT_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. TA = +25NC, unless otherwise noted.) Line to Speaker THD+N RATIO (dB) f = 6000Hz -50 -30 -40 -60 -70 -70 -80 f = 100Hz f = 1000Hz 0 POUT = 0.55W -50 -60 -80 0.4 0.6 100 1000 10 100 FREQUENCY (Hz) VRIPPLE = 200mVRMS INPUT AC GROUNDED 0 RIPPLE ON AVDD, DVDD, HPVDD -60 ZSPK = 8I + 68H -10 -20 CROSSTALK (dB) -20 MAX9888 toc75 1000 FREQUENCY (Hz) CROSSTALK vs. FREQUENCY (LINE TO SPEAKER) MAX9888 toc76 0 PSRR (dB) -2 100,000 10,000 POWER-SUPPLY REJECTION RATIO vs. FREQUENCY (LINE TO SPEAKER) -40 0 -1 -5 10 0.8 1 -4 -90 0.2 2 -3 POUT = 0.25W OUTPUT POWER (W) -30 -40 -50 -60 -70 -80 RIPPLE ON SPKLVDD, SPKRVDD -100 10 100 1000 FREQUENCY (Hz) 42 3 MAX9888 toc77 -40 ZSPK = 8I + 68H CIN = 1F 4 NORMALIZED GAIN (dB) -20 -20 -30 ZSPK = 8I + 68H CIN = 1F AVSPK_ = +8dB -10 5 MAX9888 toc74 ZSPK = 8I + 68H AVSPK_ = +8dB -10 0 MAX9888 toc73 0 GAIN vs. FREQUENCY (LINE TO SPEAKER) TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY (LINE TO SPEAKER) TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER (LINE TO SPEAKER) THD+N RATIO (dB) MAX9888 Stereo Audio CODEC with FLEXSOUND Technology 10,000 -80 -90 100,000 10 100 1000 FREQUENCY (Hz) 10,000 100,000 10,000 100,000 Stereo Audio CODEC with FLEXSOUND Technology (VAVDD = VHPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to GND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CPREG = CREG = 1FF, CC1N-C1P = 1FF, CHPVSS = 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB, AVPGAIN_ = 0dB, AVPGAOUT_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. TA = +25NC, unless otherwise noted.) DAC to Headphone -40 f = 1000Hz f = 3000Hz -50 -60 -70 -40 f = 1000Hz -50 MAX9888 toc79 f = 6000Hz -60 -20 0 0.01 0.02 0.03 0.04 -40 -50 f = 1000Hz -60 f = 6000Hz -80 f = 100Hz -90 0.05 -30 -70 -80 f = 100Hz -90 MCLK = 12.288MHz LRCLK = 48kHz NI MODE RHP = 32I AVHP_ = +3dB -10 -70 -80 0 0.01 0.02 0.03 0.04 f = 100Hz -90 0.05 0 0.01 0.02 0.03 0.04 0.05 OUTPUT POWER (W) OUTPUT POWER (W) TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER (DAC TO HEADPHONE) TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER (DAC TO HEADPHONE) TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY (LINE TO SPEAKER) -40 -50 f = 1000Hz -60 -20 f = 6000Hz -70 -30 -40 f = 6000Hz f = 1000Hz -50 -60 -70 -80 0 0.01 0.02 0.03 OUTPUT POWER (W) 0.04 0.05 MCLK = 13MHz LRCLK = 8kHz FREQ MODE RHP = 32I AVHP_ = +3dB -10 -20 -30 -40 -50 -60 POUT = 0.01W -70 -80 f = 100Hz -90 0 THD+N RATIO (dB) -30 MCLK = 12.288MHz LRCLK = 48kHz NI MODE RHP = 16I AVHP_ = +3dB -10 THD+N RATIO (dB) MCLK = 12.288MHz LRCLK = 96kHz NI MODE RHP = 32I AVHP_ = +3dB -20 0 MAX9888 toc81 0 MAX9888 toc83 OUTPUT POWER (W) -10 THD+N RATIO (dB) -30 0 THD+N RATIO (dB) -30 -20 TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER (DAC TO HEADPHONE) MAX9888 toc82 THD+N RATIO (dB) -20 MCLK = 13MHz LRCLK = 44.1kHz PLL MODE RHP = 32I AVHP_ = +3dB -10 THD+N RATIO (dB) MCLK = 13MHz LRCLK = 8kHz FREQ MODE RHP = 32I AVHP_ = +3dB -10 0 MAX9888 toc78 0 TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER (DAC TO HEADPHONE) MAX9888 toc80 TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER (DAC TO HEADPHONE) f = 100Hz -90 -80 POUT = 0.02W -90 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 OUTPUT POWER (W) 10 100 1000 10,000 FREQUENCY (Hz) 43 MAX9888 Typical Operating Characteristics (continued) Typical Operating Characteristics (continued) (VAVDD = VHPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to GND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CPREG = CREG = 1FF, CC1N-C1P = 1FF, CHPVSS = 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB, AVPGAIN_ = 0dB, AVPGAOUT_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. TA = +25NC, unless otherwise noted.) -40 -50 -60 POUT = 0.025W -70 -40 POUT = 0.025W -70 -20 1000 10,000 -100 100,000 10 100 1000 10,000 FREQUENCY (Hz) FREQUENCY (Hz) TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY (DAC TO HEADPHONE) GAIN vs. FREQUENCY (DAC TO HEADPHONE) MCLK = 12.288MHz LRCLK = 48kHz NI MODE RHP = 16I -20 -30 -40 -50 POUT = 0.01W -60 -70 -80 -90 10 100 1000 FREQUENCY (Hz) 10,000 100,000 -60 POUT = 0.025W -70 POUT = 0.01W -20 -30 MODE = 0 -40 MCLK = 13MHz LRCLK = 8kHz NI MODE RHP = 32I -50 -70 10 100 100 1000 10,000 100,000 HPVDD INPUT CURRENT vs. OUTPUT POWER (DAC TO HEADPHONE) MODE = 1 -10 10 FREQUENCY (Hz) 0 -60 POUT = 0.0.25W -50 100,000 10 MAX9888 toc87 0 -10 -40 -100 120 HPVDD INPUT CURRENT (mA) 100 -30 -90 POUT = 0.01W MAX9888 toc88 10 MCLK = 12.288MHz LRCLK = 96kHz NI MODE RHP = 32I AVHP_ = +3dB -80 -90 POUT = 0.1W -90 MAX9888 toc86 MAX9888 toc85 -50 -60 0 -10 -80 -80 44 -30 TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY (DAC TO HEADPHONE) THD+N RATIO (dB) -30 -20 NORMALIZED GAIN (dB) THD+N RATIO (dB) -20 MCLK = 12.288MHz LRCLK = 48kHz NI MODE RHP = 32I AVHP_ = +3dB -10 THD+N RATIO (dB) MCLK = 13MHz LRCLK = 44.1kHz PLL MODE RHP = 32I AVHP_ = +3dB -10 0 MAX9888 toc84 0 TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY (DAC TO HEADPHONE) MAX9888 toc89 TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY (DAC TO HEADPHONE) THD+N RATIO (dB) MAX9888 Stereo Audio CODEC with FLEXSOUND Technology MCLK = 12.288MHz LRCLK = 48kHz NI MODE 100 80 60 40 RHP = 16I 20 RHP = 32I 0 1000 FREQUENCY (Hz) 10,000 100,000 0.01 0.1 1 10 OUTPUT POWER PER CHANNEL (mW) 100 Stereo Audio CODEC with FLEXSOUND Technology (VAVDD = VHPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to GND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CPREG = CREG = 1FF, CC1N-C1P = 1FF, CHPVSS = 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB, AVPGAIN_ = 0dB, AVPGAOUT_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. TA = +25NC, unless otherwise noted.) POWER-SUPPLY REJECTION RATIO vs. FREQUENCY (DAC TO HEADPHONE) -40 RIPPLE ON SPKLVDD, SPKRVDD -80 100 1000 10,000 HEADPHONE OUTPUT 0.5V/div -70 -80 -100 100,000 10 100 FREQUENCY (Hz) SOFTWARE TURN-ON/OFF RESPONSE (DAC TO HEADPHONE, VSEN = 1) 10,000 100,000 0 MCLK = 13MHz, LRCLK = 8kHz FREQ MODE RHP = 32I AMPLITUDE (dBV) -20 -40 FFT, -60dBFS (DAC TO HEADPHONE) 0 MCLK = 13MHz, LRCLK = 8kHz FREQ MODE RHP = 32I -20 -40 -60 -80 -100 -60 -80 -100 -120 -120 10ms/div 10ms/div FFT, 0dBFS (DAC TO HEADPHONE) MAX9888 toc93 SCL 2V/div HEADPHONE OUTPUT 0.5V/div 1000 FREQUENCY (Hz) MAX9888 toc95 10 -60 -90 RIPPLE ON AVDD, DVDD, HPVDD -100 MAX9888 toc91 -50 SCL 2V/div AMPLITUDE (dBV) -60 MCLK = 12.288MHz LRCLK = 48kHz NI MODE RHP = 32I MAX9888 toc94 PSRR (dB) -20 CROSSTALK (dB) VRIPPLE = 200mVP-P INPUT ALL ZEROS SOFTWARE TURN-ON/OFF RESPONSE (DAC TO HEADPHONE, VSEN = 0) MAX9888 toc92 -40 MAX9888 toc90 0 CROSSTALK vs. FREQUENCY (DAC TO HEADPHONE) -140 -140 -160 0 5000 10,000 FREQUENCY (Hz) 15,000 20,000 0 5000 10,000 15,000 20,000 FREQUENCY (Hz) 45 MAX9888 Typical Operating Characteristics (continued) Typical Operating Characteristics (continued) (VAVDD = VHPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to GND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CPREG = CREG = 1FF, CC1N-C1P = 1FF, CHPVSS = 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB, AVPGAIN_ = 0dB, AVPGAOUT_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. TA = +25NC, unless otherwise noted.) FFT, -60dBFS (DAC TO HEADPHONE) FFT, 0dBFS (DAC TO HEADPHONE) MCLK = 13MHz, LRCLK = 44.1kHz PLL MODE RHP = 32I -20 -40 AMPLITUDE (dBV) -40 -60 -80 -100 -60 -80 -100 -120 -120 -140 -160 -140 0 5000 10,000 15,000 5000 0 20,000 10,000 FREQUENCY (Hz) FREQUENCY (Hz) FFT, 0dBFS (DAC TO HEADPHONE) MCLK = 12.288MHz LRCLK = 48kHz NI MODE RHP = 32I -20 AMPLITUDE (dBV) MAX9888 toc98 0 -40 -60 -80 -100 -120 -140 0 5000 10,000 FREQUENCY (Hz) 46 MAX9888 toc97 MCLK = 13MHz, LRCLK = 44.1kHz PLL MODE RHP = 32I -20 0 MAX9888 toc96 0 AMPLITUDE (dBV) MAX9888 Stereo Audio CODEC with FLEXSOUND Technology 15,000 20,000 15,000 20,000 Stereo Audio CODEC with FLEXSOUND Technology (VAVDD = VHPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to GND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CPREG = CREG = 1FF, CC1N-C1P = 1FF, CHPVSS = 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB, AVPGAIN_ = 0dB, AVPGAOUT_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. TA = +25NC, unless otherwise noted.) -40 -80 -100 FFT, -60dBFS (DAC TO HEADPHONE) MAX9888 toc100 -60 -80 -160 10,000 15,000 20,000 5000 0 FREQUENCY (Hz) 10,000 15,000 20,000 -160 5000 0 FREQUENCY (Hz) 20 MAX9888 toc102 -40 -60 MCLK = 13MHz LRCLK = 44.1kHz PLL MODE AVHP_ = -3dB RHP = 32I 0 AMPLITUDE (dBm) MCLK = 13MHz LRCLK = 44.1kHz PLL MODE AVHP_ = -3dB RHP = 32I -20 15,000 20,000 WIDEBAND FFT, -60dBFS (DAC TO HEADPHONE) 20 0 10,000 FREQUENCY (Hz) WIDEBAND FFT, 0dBFS (DAC TO HEADPHONE) AMPLITUDE (dBm) -100 MAX9888 toc103 5000 -80 -140 -140 0 -60 -120 -120 -140 MCLK = 2.288MHz LRCLK = 96kHz NI MODE RHP = 32I -20 -40 -100 -120 0 AMPLITUDE (dBV) -60 MCLK = 12.288MHz LRCLK = 96kHz NI MODE RHP = 32I -20 AMPLITUDE (dbV) -40 AMPLITUDE (dBV) MAX9888 toc99 MCLK = 12.288MHz LRCLK = 48kHz NI MODE RHP = 32I -20 FFT, 0dBFS (DAC TO HEADPHONE) 0 MAX9888 toc101 FFT, -60dBFS (DAC TO HEADPHONE) 0 -20 -40 -60 -80 -80 -100 -100 0 1 10 100 FREQUENCY (kHz) 1000 10,000 0 1 10 100 1000 10,000 FREQUENCY (kHz) 47 MAX9888 Typical Operating Characteristics (continued) Typical Operating Characteristics (continued) (VAVDD = VHPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to GND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CPREG = CREG = 1FF, CC1N-C1P = 1FF, CHPVSS = 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB, AVPGAIN_ = 0dB, AVPGAOUT_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. TA = +25NC, unless otherwise noted.) Line to Headphone -40 f = 6000Hz f = 1000Hz -60 -30 -40 -50 POUT = 0.01W -60 f = 100Hz 0 0.01 0.02 0.03 0.04 1 0 -1 -2 -4 POUT = 0.025W -90 0.05 2 -3 -80 -80 10 100 1000 -5 10,000 100,000 10 100 1000 10,000 100,000 OUTPUT POWER (W) FREQUENCY (Hz) FREQUENCY (Hz) POWER-SUPPLY REJECTION RATIO vs. FREQUENCY (LINE TO HEADPHONE) CROSSTALK vs. FREQUENCY (LINE TO HEADPHONE) COMMON-MODE REJECTION RATIO vs. FREQUENCY (LINE TO HEADPHONE) -60 RIPPLE ON SPKLVDD, SPKRVDD 50 -30 -40 -50 -60 MAX9888 toc109 -20 VOUT = -6dBV CIN = 1F RHP = 32I 60 CMRR (dB) RIPPLE ON AVDD, DVDD, HPVDD RHP = 32I -10 70 MAX9888 toc108 -20 CROSSTALK (dB) VRIPPLE = 200mVP-P -40 0 MAX9888 toc107 0 AVPGAIN_ = 0dB 40 30 AVPGAIN_ = 20dB 20 -70 -80 10 -80 -100 10 100 1000 FREQUENCY (Hz) 48 3 -70 -70 RHP = 32I CIN = 1F 4 NORMALIZED GAIN (dB) -30 -50 -20 THD+N RATIO (dB) THD+N RATIO (dB) -20 RHP = 32I CIN = 1F -10 5 MAX9888 toc105 RHP = 32I AVHP_ = +3dB -10 0 MAX9888 toc104 0 GAIN vs. FREQUENCY (LINE TO HEADPHONE) TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY (LINE TO HEADPHONE) MAX9888 toc106 TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER (LINE TO HEADPHONE) PSRR (dB) MAX9888 Stereo Audio CODEC with FLEXSOUND Technology 10,000 100,000 0 -90 10 100 1000 FREQUENCY (Hz) 10,000 100,000 10 100 1000 FREQUENCY (Hz) 10,000 100,000 Stereo Audio CODEC with FLEXSOUND Technology (VAVDD = VHPVDD = VDVDD = VDVDDS1 = VDVDDS2 = +1.8V, VSPKLVDD = VSPKRVDD = 3.7V. Speaker loads (ZSPK) connected between SPK_P and SPK_N. Receiver load (RREC) connected between RECP and RECN. Headphone loads (RHP) connected from HPL or HPR to GND. RHP = J, RREC = J, ZSPK = J, CREF = 2.2FF, CMICBIAS = CPREG = CREG = 1FF, CC1N-C1P = 1FF, CHPVSS = 1FF. AVMICPRE_ = +20dB, AVMICPGA_ = 0dB, AVDACATTN = 0dB, AVDACGAIN = 0dB, AVADCLVL = 0dB, AVADCGAIN = 0dB, AVPGAIN_ = 0dB, AVPGAOUT_ = 0dB, AVHP_ = 0dB, AVREC = 0dB, AVSPK_ = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. TA = +25NC, unless otherwise noted.) Speaker Bypass Switch TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER (SPEAKER BYPASS SWITCH) RECEIVER AMPLIFIER DRIVING LOUDSPEAKER ZSPK = 8I + 68H -10 3.0 RON (I) -40 -50 ISW = 20mA 3.5 -30 2.5 2.0 VSPK_VDD = 3.0V VSPK_VDD = 3.7V 1.5 f = 6000Hz VSPK_VDD = 4.2V 1.0 -60 -70 f = 1000Hz f = 100Hz VSPK_VDD = 5.0V 0.5 0 -80 0.05 0.10 0.15 1 0 0.20 2 3 4 5 6 VCOM (V) OUTPUT POWER (W) OFF-ISOLATION vs. FREQUENCY (SPEAKER BYPASS SWITCH) 0 SPEAKER AMP DRIVING LOUDSPEAKER SPEAKER BYPASS SWITCH OPEN MEASURED AT RXIN_ -20 MAX9888 toc112 0 OFF-ISOLATION (dB) THD+N RATIO (dB) -20 4.0 MAX9888 toc110 0 MAX9888 toc111 ON RESISTANCE vs. VCOM (SPEAKER BYPASS SWITCH) -40 50I LOAD ON RXIN_ -60 -80 RECEIVER AMP DRIVING RXIN_ -100 -120 10 100 1000 10,000 100,000 FREQUENCY (Hz) 49 MAX9888 Typical Operating Characteristics (continued) Stereo Audio CODEC with FLEXSOUND Technology MAX9888 Pin Configuration TOP VIEW (BUMP SIDE DOWN) 1 2 3 4 5 6 7 8 9 A SPKRN SPKRGND SPKLVDD SPKLP SPKLN RECP/ RXINP HPVDD HPGND HPVSS B SPKRN SPKRGND SPKLVDD SPKLP SPKLN RECN/ RXINN C1P C1N HPL C SPKRP SPKRP SPKRVDD SPKLGND SPKLGND HPSNS N.C. INB2 HPR MAX9888 D BCLKS1 LRCLKS1 SPKRVDD SDINS1 N.C. JACKSNS N.C. INB1 INA2/ EXTMICN E DVDDS1 MCLK N.C. SDOUTS1 IRQ N.C. N.C. MIC1P/ DIGMICDATA INA1/ EXTMICP F DGND BCLKS2 LRCLKS2 SDA SCL REG REF DIGMICCLK MIC2P G SDOUTS2 DVDDS2 SDINS2 DVDD AVDD PREG AGND MICBIAS MIC2N 50 MIC1N/ Stereo Audio CODEC with FLEXSOUND Technology PIN NAME A1, B1 SPKRN FUNCTION A2, B2 SPKRGND Right-Speaker Ground A3, B3 SPKLVDD Left-Speaker, REF, Receiver Amplifier Power Supply. Bypass to SPKLGND with a 1FF and a 10FF capacitor. Negative Right-Channel Class D Speaker Output A4, B4 SPKLP Positive Left-Channel Class D Speaker Output A5, B5 SPKLN Negative Left-Channel Class D Speaker Output A6 RECP/RXINP Positive Receiver Amplifier Output. Can be positive bypass switch input when receiver amp is shut down. A7 HPVDD Headphone Power Supply. Bypass to HPGND with a 1FF capacitor. A8 HPGND Headphone Ground A9 HPVSS Inverting Charge-Pump Output. Bypass to HPGND with a 1FF ceramic capacitor. B6 RECN/RXINN B7 C1P Charge-Pump Flying Capacitor Positive Terminal. Connect a 1FF ceramic capacitor between C1N and C1P. B8 C1N Charge-Pump Flying Capacitor Negative Terminal. Connect a 1FF ceramic capacitor between C1N and C1P. B9 HPL Left-Channel Headphone Output Negative Receiver Amplifier Output. Can be negative bypass switch input when receiver amp is shut down. C1, C2 SPKRP C3, D3 SPKRVDD Positive Right-Channel Class D Speaker Output Right-Speaker Power Supply. Bypass to SPKRGND with a 1FF capacitor. C4, C5 SPKLGND Left-Speaker Ground C6 HPSNS C7, D5, D7, E3, E6, E7 N.C. No Connection C8 INB2 Single-Ended Line Input B2. Also positive differential line input B. C9 HPR Right-Channel Headphone Output D1 BCLKS1 S1 Digital Audio Bit Clock Input/Output. BCLKS1 is an input when the MAX9888 is in slave mode and an output when in master mode. The input/output voltage is referenced to DVDDS1. D2 LRCLKS1 S1 Digital Audio Left-Right Clock Input/Output. LRCLKS1 is the audio sample rate clock and determines whether S1 audio data is routed to the left or right channel. In TDM mode, LRCLKS1 is a frame sync pulse. LRCLKS1 is an input when the MAX9888 is in slave mode and an output when in master mode. The input/output voltage is referenced to DVDDS1. D4 SDINS1 D6 JACKSNS D8 INB1 D9 INA2/ EXTMICN Headphone Amplifier Ground Sense. Connect to the headphone jack ground terminal or connect to ground. S1 Digital Audio Serial-Data DAC Input. The input voltage is referenced to DVDDS1. Jack Sense. Detects the insertion of a jack. See the Headset Detection section. Single-Ended Line Input B1. Also negative differential line input B. Single-Ended Line Input A2. Also positive differential line input A or negative differential external microphone input. 51 MAX9888 Pin Description Stereo Audio CODEC with FLEXSOUND Technology MAX9888 Pin Description (continued) PIN NAME E1 DVDDS1 E2 MCLK E4 SDOUTS1 E5 E8 Master Clock Input. Acceptable input frequency range is 10MHz to 60MHz. S1 Digital Audio Serial-Data ADC Output. The output voltage is referenced to DVDDS1. Hardware Interrupt Output. IRQ can be programmed to pull low when bits in status register 0x00 change state. Read status register 0x00 to clear IRQ once set. Repeat faults have no effect on IRQ until it is cleared by reading the I2C status register 0x00. Connect a 10kI pullup resistor to DVDD for full output swing. MIC1P/ Positive Differential Microphone 1 Input. AC-couple a microphone with a series 1FF capacitor. Can DIGMICDATA be retasked as a digital microphone data input. E9 INA1/ EXTMICP F1 DGND F2 BCLKS2 S2 Digital Audio Bit Clock Input/Output. BCLKS2 is an input when the IC is in slave mode and an output when in master mode. The input/output voltage is referenced to DVDDS2. F3 LRCLKS2 S2 Digital Audio Left-Right Clock Input/Output. LRCLKS2 is the audio sample rate clock and determines whether audio data on S2 is routed to the left or right channel. In TDM mode, LRCLKS2 is a frame sync pulse. LRCLKS2 is an input when the IC is in slave mode and an output when in master mode. The input/output voltage is referenced to DVDDS2. Single-Ended Line Input A1. Also negative differential line input A or positive differential external microphone input. Digital Ground F4 SDA I2C Serial-Data Input/Output. Connect a pullup resistor to DVDD for full output swing. F5 SCL I2C Serial-Clock Input F6 REG Common-Mode Voltage Reference. Bypass to AGND with a 1FF capacitor. F7 REF Converter Reference. Bypass to AGND with a 2.2FF capacitor. F8 52 IRQ FUNCTION S1 Digital Audio Interface Power-Supply Input. Bypass to DGND with a 1FF capacitor. MIC1N/ Negative Differential Microphone 1 Input. AC-couple a microphone with a series 1FF capacitor. Can DIGMICCLK be retasked as a digital microphone clock output. F9 MIC2P G1 SDOUTS2 Positive Differential Microphone 2 Input. AC-couple a microphone with a series 1FF capacitor. S2 Digital Audio Serial-Data ADC Output. The output voltage is referenced to DVDDS2. G2 DVDDS2 S2 Digital Audio Interface Power-Supply Input. Bypass to DGND with a 1FF capacitor. G3 SDINS2 S2 Digital Audio Serial-Data DAC Input. The input voltage is referenced to DVDDS2. G4 DVDD Digital Power Supply. Supply for the digital core and I2C interface. Bypass to DGND with a 1FF capacitor. G5 AVDD Analog Power Supply. Bypass to AGND with a 1FF capacitor. G6 PREG Positive Internal Regulated Supply. Bypass to AGND with a 1FF capacitor. G7 AGND Analog Ground G8 MICBIAS G9 MIC2N Low-Noise Bias Voltage. Outputs a 2.2V microphone bias. An external resistor in the 2.2kI to 1kI range should be used to set the microphone current. Negative Differential Microphone 2 Input. AC-couple a microphone with a series 1FF capacitor. Stereo Audio CODEC with FLEXSOUND Technology The MAX9888 is a fully integrated stereo audio codec with FLEXSOUND technology and integrated amplifiers. Two differential microphone amplifiers can accept signals from three analog inputs. One input can be retasked to support two digital microphones. Any combination of two microphones (analog or digital) can be recorded simultaneously. The analog signals are amplified up to 50dB and recorded by the stereo ADC. The digital record path supports voice filtering with selectable preset highpass filters and high stopband attenuation at fS/2. An automatic gain control (AGC) circuit monitors the digitized signal and automatically adjusts the analog microphone gain to make best use of the ADC's dynamic range. A noise gate attenuates signals below the user-defined threshold to minimize the noise output by the ADC. The IC includes two analog line inputs. One of the line inputs can be optionally retasked as a third analog microphone input. Both line inputs support either stereo singleended input signals or mono differential signals. The line inputs are preamplified and then routed either to the ADC for recording or to the output amplifiers for playback. Integrated analog switches allow two differential microphone signals to be routed out the third microphone input to an external device. This eliminates the need for an external analog switch in systems that have two devices recording signals from the same microphone. Through two digital audio interfaces, the device can transmit one stereo audio signal and receive two stereo audio signals in a wide range of formats including I2S, PCM, and up to four mono slots in TDM. Each interface can be connected to either of two audio ports (S1 and S2) for communication with external devices. Both audio interfaces support 8kHz to 96kHz sample rates. Each input signal is independently equalized using 5-band parametric equalizers. A multiband automatic level control (ALC) boosts signals by up to 12dB. One signal path additionally supports the same voiceband filtering as the ADC path. The IC includes a differential receiver amplifier, stereo Class D speaker amplifiers, and DirectDrive true ground stereo headphone amplifiers. When the receiver amplifier is disabled, analog switches allow RECP/RXINP and RECN/RXINN to be reused for signal routing. In systems where a single transducer is used for both the loudspeaker and receiver, an external receiver amplifier can be routed to the left speaker through RECP/RXINP and RECN/RXINN, bypassing the Class D amplifier, to connect to the loudspeaker. If the internal receiver amplifier is used, then leave RECP/ RXINP and RECN/RXINN unconnected. In systems where an external amplifier drives both the receiver and the MAX9888's input, one of the differential signals can be disconnected from the receiver when not needed by passing it through the analog switch that connects RECP/RXINP to RECN/RXINN. The stereo Class D amplifier provides efficient amplification for two speakers. The amplifier includes active emissions limiting to minimize the radiated emissions (EMI) traditionally associated with Class D. In most systems, no output filtering is required to meet standard EMI limits. To optimize speaker sound quality, the IC includes an excursion limiter, a distortion limiter, and a power limiter. The excursion limiter is a dynamic highpass filter with variable corner frequency that increases in response to high signal levels. Low-frequency energy typically causes more distortion than useful sound at high signal levels, so attenuating low frequencies allows the speaker to play louder without distortion or damage. At lower signal levels, the filter corner frequency reduces to pass more low frequency energy when the speaker can handle it. The distortion limiter reduces the volume when the output signal exceeds a preset distortion level. This ensures that regardless of input signal and battery voltage, excessive distortion is never heard by the user. The power limiter monitors the continuous power into the loudspeaker and lowers the signal level if the speaker is at risk of overheating. The stereo DirectDrive headphone amplifier uses an inverting charge pump to generate a ground-referenced output signal. This eliminates the need for DC-blocking capacitors or a midrail bias for the headphone jack ground return. Ground sense reduces output noise caused by ground return current. The IC integrates jack detection allowing the detection of insertion and removal of accessories as well as button presses. 53 MAX9888 Detailed Description MAX9888 Stereo Audio CODEC with FLEXSOUND Technology I2C Slave Address Configure the MAX9888 using the I2C control bus. The IC uses a slave address of 0x20 or 00100000 for write operations and 0x21 or 00100001 for read operations. See the I2C Serial Interface section for a complete interface description. Registers Table 1 lists all of the registers, their addresses, and power-on-reset states. Registers 0x00 to 0x03 and 0xFF are read-only while all of the other registers are read/ write. Write zeros to all unused bits in the register table when updating the register, unless otherwise noted. Table 1. Register Map REGISTER B7 B6 B5 B4 B3 B2 B1 B0 CLD SLD ULK -- -- -- JDET -- ADDRESS DEFAULT R/W PAGE STATUS Status Microphone AGC/NG NG Jack Status AGC JKSNS -- -- Battery Voltage -- -- -- Interrupt Enable ICLD ISLD IULK -- -- -- -- VBAT 0 0x00 -- R 103 0x01 -- R 65 0x02 -- R 101 0x03 -- R/W 102 0 0 IJDET 0 0x0F 0x00 R/W 103 0 0 0 0 0x10 0x00 R/W 76 0x11 0x00 R/W 76 MASTER CLOCK CONTROL Master Clock 0 0 PSCLK DAI1 CLOCK CONTROL Clock Mode Any Clock Control SR1 FREQ1 PLL1 NI1[14:8] NI1[7:1] 0x12 0x00 R/W 77 NI1[0] 0x13 0x00 R/W 77 WS1 0x14 0x00 R/W 71 0x15 0x00 R/W 72 0x16 0x00 R/W 72 0x17 0x00 R/W 73 0x18 0x00 R/W 79 DAI1 CONFIGURATION Format MAS1 WCI1 BCI1 DLY1 0 0 0 Clock OSR1 0 I/O Configuration SEL1 LTEN1 Time-Division Multiplex SLOTL1 Filters FSW1 BSEL1 LBEN1 DMONO1 HIZOFF1 SDOEN1 SDIEN1 SLOTR1 MODE1 TDM1 SLOTDLY1 AVFLT1 DHF1 DVFLT1 DAI2 CLOCK CONTROL Clock Mode Any Clock Control SR2 0 PLL2 0 0 0 0x19 0x00 R/W 76 0x1A 0x00 R/W 77 NI2[0] 0x1B 0x00 R/W 77 WS2 0x1C 0x00 R/W 71 0x1D 0x00 R/W 72 0x1E 0x00 R/W 72 NI2[14:8] NI2[7:1] DAI2 CONFIGURATION Format MAS2 WCI2 BCI2 DLY2 0 Clock 0 0 0 0 0 I/O Configuration 54 SEL2 0 TDM2 FSW2 BSEL2 LBEN2 DMONO2 HIZOFF2 SDOEN2 SDIEN2 Stereo Audio CODEC with FLEXSOUND Technology REGISTER B7 Time-Division Multiplex Filters B6 B5 SLOTL2 0 B4 B3 SLOTR2 0 0 B2 B1 B0 SLOTDLY2 0 DHF2 0 0 DCB2 ADDRESS DEFAULT R/W PAGE 0x1F 0x00 R/W 73 0x20 0x00 R/W 79 0x21 0x00 R/W 85 MIXERS DAC Mixer MIXDAL MIXDAR Left ADC Mixer MIXADL 0x22 0x00 R/W 64 Right ADC Mixer MIXADR 0x23 0x00 R/W 64 Preoutput 1 Mixer 0 0 0 0 MIXOUT1 0x24 0x00 R/W 86 Preoutput 2 Mixer 0 0 0 0 MIXOUT2 0x25 0x00 R/W 86 Preoutput 3 Mixer 0 0 0 0 MIXOUT3 0x26 0x00 R/W 86 MIXHPR 0x27 0x00 R/W 97 MIXREC 0x28 0x00 R/W 88 MIXSPR 0x29 0x00 R/W 90 0x2A 0x00 R/W 69 DV1 0x2B 0x00 R/W 84 Headphone Amplifier Mixer Receiver Amplifier Mixer MIXHPL 0 0 Speaker Amplifier Mixer 0 0 MIXSPL LEVEL CONTROL Sidetone DSTS 0 DVST DAI1 Playback Level DV1M 0 DAI1 Playback Level 0 0 0 EQCLP1 DVEQ1 0x2C 0x00 R/W 83 DAI2 Playback Level DV2M 0 0 0 DV2 0x2D 0x00 R/W 84 DAI2 Playback Level 0 0 0 EQCLP2 DVEQ2 0x2E 0x00 R/W 83 Left ADC Level 0 0 AVLG AVL 0x2F 0x00 R/W 68 Right ADC Level 0 0 AVRG AVR 0x30 0x00 R/W 68 Microphone 1 Input Level 0 0x31 0x00 R/W 61 DV1G PA1EN PGAM1 55 MAX9888 Table 1. Register Map (continued) MAX9888 Stereo Audio CODEC with FLEXSOUND Technology Table 1. Register Map (continued) REGISTER B7 Microphone 2 Input Level B6 B5 B4 B3 0 INA Input Level 0 INAEXT 0 0 0 INB Input Level 0 INBEXT 0 0 0 Preoutput 1 Level 0 0 0 0 Preoutput 2 Level 0 0 0 Preoutput 3 Level 0 0 0 Left Headphone Amplifier Volume Control HPLM 0 0 Right Headphone Amplifier Volume Control HPRM 0 Receiver Amplifier Volume Control RECM Left Speaker Amplifier Volume Control Right Speaker Amplifier Volume Control PA2EN B2 B1 B0 PGAM2 ADDRESS DEFAULT R/W PAGE 0x32 0x00 R/W 61 PGAINA 0x33 0x00 R/W 63 PGAINB 0x34 0x00 R/W 63 PGAOUT1 0x35 0x00 R/W 87 0 PGAOUT2 0x36 0x00 R/W 87 0 PGAOUT3 0x37 0x00 R/W 87 HPVOLL 0x38 0x00 R/W 97 0 HPVOLR 0x39 0x00 R/W 97 0 0 RECVOL 0x3A 0x00 R/W 88 SPLM 0 0 SPVOLL 0x3B 0x00 R/W 90 SPRM 0 0 SPVOLR 0x3C 0x00 R/W 90 MICROPHONE AGC Configuration AGCSRC AGCRLS Threshold AGCATK ANTH AGCHLD AGCTH 0x3D 0x00 R/W 65 0x3E 0x00 R/W 66 0x3F 0x00 R/W 92 SPEAKER SIGNAL PROCESSING Excursion Limiter Filter 0 Excursion Limiter Threshold 0 ALC 56 ALCEN DHPUCF 0 0 ALCRLS 0 0 0 DHPLCF 0 DHPTH 0x40 0x00 R/W 92 ALCMB ALCTH 0x41 0x00 R/W 82 Stereo Audio CODEC with FLEXSOUND Technology REGISTER B7 B6 B5 Power Limiter PWRTH Power Limiter PWRT2 Distortion Limiter B4 B3 B2 0 B1 B0 PWRK 0x42 0x00 R/W 93 0x43 0x00 R/W 94 0x44 0x00 R/W 95 0x45 0x00 R/W 63 0x46 0x00 R/W 61 EQ1EN 0x47 0x00 R/W 99, 83 PWRT1 THDCLP 0 ADDRESS DEFAULT R/W PAGE THDT1 CONFIGURATION Audio Input INADIFF INBDIFF Microphone MICCLK 0 0 DIGMICL DIGMICR 0 0 0 0 0 0 EXTMIC Level Control VS2EN VSEN ZDEN 0 0 0 Bypass Switches EQ2EN INABYP 0 0 MIC2BYP 0 0 RECBYP SPKBYP 0x48 0x00 R/W 62, 98 Jack Detection JDETEN 0 0 0 0 0 JDEB 0x49 0x00 R/W 101 POWER MANAGEMENT INAEN INBEN 0 0 MBEN 0 ADLEN ADREN 0x4A 0x00 R/W 59 Output Enable HPLEN Input Enable HPREN SPLEN SPREN RECEN 0 DALEN DAREN 0x4B 0x00 R/W 59 System Enable VBATEN 0 0 0 0 JDWK 0 0x4C 0x00 R/W 59 K_1[15:8] 0x50/0x82 0xXX R/W 82 SHDN DSP COEFFICIENTS EQ Band 1 (DAI1/DAI2) EQ Band 2 (DAI1/DAI2) K_1[7:0] 0x51/0x83 0xXX R/W 82 K1_1[15:8] 0x52/0x84 0xXX R/W 82 K1_1[7:0] 0x53/0x85 0xXX R/W 82 K2_1[15:8] 0x54/0x86 0xXX R/W 82 K2_1[7:0] 0x55/0x87 0xXX R/W 82 c1_1[15:8] 0x56/0x88 0xXX R/W 82 c1_1[7:0] 0x57/0x89 0xXX R/W 82 c2_1[15:8] 0x58/0x8A 0xXX R/W 82 c2_1[7:0] 0x59/0x8B 0xXX R/W 82 K_2[15:8] 0x5A/0x8C 0xXX R/W 82 K_2[7:0] 0x5B/0x8D 0xXX R/W 82 K1_2[15:8] 0x5C/0x8E 0xXX R/W 82 K1_2[7:0] 0x5D/0x8F 0xXX R/W 82 K2_2[15:8] 0x5E/0x90 0xXX R/W 82 K2_2[7:0] 0x5F/0x91 0xXX R/W 82 c1_2[15:8] 0x60/0x92 0xXX R/W 82 c1_2[7:0] 0x61/0x93 0xXX R/W 82 c2_2[15:8] 0x62/0x94 0xXX R/W 82 c2_2[7:0] 0x63/0x95 0xXX R/W 82 57 MAX9888 Table 1. Register Map (continued) MAX9888 Stereo Audio CODEC with FLEXSOUND Technology Table 1. Register Map (continued) REGISTER EQ Band 3 (DAI1/DAI2) EQ Band 4 (DAI1/DAI2) EQ Band 5 (DAI1/DAI2) Excursion Limiter Biquad (DAI1/DAI2) B7 B6 B5 B4 B3 B2 B1 B0 ADDRESS DEFAULT R/W PAGE K_3[15:8] 0x64/0x96 0xXX R/W 82 K_3[7:0] 0x65/0x97 0xXX R/W 82 K1_3[15:8] 0x66/0x98 0xXX R/W 82 K1_3[7:0] 0x67/0x99 0xXX R/W 82 K2_3[15:8] 0x68/0x9A 0xXX R/W 82 K2_3[7:0] 0x69/0x9B 0xXX R/W 82 c1_3[15:8] 0x6A/0x9C 0xXX R/W 82 c1_3[7:0] 0x6B/0x9D 0xXX R/W 82 c2_3[15:8] 0x6C/0x9E 0xXX R/W 82 c2_3[7:0] 0x6D/0x9F 0xXX R/W 82 K_4[15:8] 0x6E/0xA0 0xXX R/W 82 K_4[7:0] 0x6F/0xA1 0xXX R/W 82 K1_4[15:8] 0x70/0xA2 0xXX R/W 82 K1_4[7:0] 0x71/0xA3 0xXX R/W 82 K2_4[15:8] 0x72/0xA4 0xXX R/W 82 K2_4[7:0] 0x73/0xA5 0xXX R/W 82 c1_4[15:8] 0x74/0xA6 0xXX R/W 82 c1_4[7:0] 0x75/0xA7 0xXX R/W 82 c2_4[15:8] 0x76/0xA8 0xXX R/W 82 c2_4[7:0] 0x77/0xA9 0xXX R/W 82 K_5[15:8] 0x78/0xAA 0xXX R/W 82 K_5[7:0] 0x79/0xAB 0xXX R/W 82 K1_5[15:8] 0x7A/0xAC 0xXX R/W 82 K1_5[7:0] 0x7B/0xAD 0xXX R/W 82 K2_5[15:8] 0x7C/0xAE 0xXX R/W 82 K2_5[7:0] 0x7D/0xAF 0xXX R/W 82 c1_5[15:8] 0x7E/0xB0 0xXX R/W 82 c1_5[7:0] 0x7F/0xB1 0xXX R/W 82 c2_5[15:8] 0x80/0xB2 0xXX R/W 82 c2_5[7:0] 0x81/0xB3 0xXX R/W 82 a1[15:8] 0xB4/0xBE 0xXX R/W 91 a1[7:0] 0xB5/0xBF 0xXX R/W 91 a2[15:8] 0xB6/0xC0 0xXX R/W 91 a2[7:0] 0xB7/0xC1 0xXX R/W 91 b0[15:8] 0xB8/0xC2 0xXX R/W 91 b0[7:0] 0xB9/0xC3 0xXX R/W 91 b1[15:8] 0xBA/0xC4 0xXX R/W 91 b1[7:0] 0xBB/0xC5 0xXX R/W 91 b2[15:8] 0xBC/0xC6 0xXX R/W 91 b2[7:0] 0xBD/0xC7 0xXX R/W 91 REV 0xFF 0x43 R 104 REVISION ID Rev ID 58 Stereo Audio CODEC with FLEXSOUND Technology Table 2. Power Management Registers REGISTER BIT NAME 7 SHDN 6 VBATEN 1 JDWK 7 INAEN 6 INBEN 3 MBEN 1 ADLEN 0 ADREN 7 HPLEN 6 HPREN 5 SPLEN 4 SPREN 3 RECEN 1 DALEN 0 DAREN 0x4C 0x4A 0x4B DESCRIPTION Global Shutdown Disables everything except the headset detection circuitry, which is controlled separately. 0 = Device shutdown 1 = Device enabled See the Battery Measurement section. See the Headset Detection section. Line Input A Enable 0 = Disabled 1 = Enabled Line Input B Enable 0 = Disabled 1 = Enabled Microphone Bias Enable 0 = Disabled 1 = Enabled Left ADC Enable 0 = Disabled 1 = Enabled Right ADC Enable 0 = Disabled 1 = Enabled Left Headphone Enable 0 = Disabled 1 = Enabled Right Headphone Enable 0 = Disabled 1 = Enabled Left Speaker Enable 0 = Disabled 1 = Enabled Right Speaker Enable 0 = Disabled 1 = Enabled Receiver Enable 0 = Disabled 1 = Enabled Left DAC Enable 0 = Disabled 1 = Enabled Right DAC Enable 0 = Disabled 1 = Enabled 59 MAX9888 Power Management The IC includes comprehensive power management to allow the disabling of all unused circuits, minimizing supply current. MAX9888 Stereo Audio CODEC with FLEXSOUND Technology Microphone Inputs The device includes three differential microphone inputs and a low-noise microphone bias for powering the microphones (Figure 6). One microphone input can also be configured as a digital microphone input accepting signals from up to two digital microphones. Two microphones, analog or digital, can be recorded simultaneously. In the typical application, one microphone input is used for the handset microphone and the other is used as an accessory microphone. In systems using a background noise microphone, INA can be retasked as another microphone input. In systems where the codec is not the only device recording microphone signals, connect microphones to MIC2P/MIC2N and EXTMICP/EXTMICN. MIC1P/MIC1N then become outputs that route the microphone signals to an external device as needed. Two devices can then record microphone signals without needing external analog switches. Analog microphone signals are amplified by two stages of gain and then routed to the ADCs. The first stage offers selectable 0dB, 20dB, or 30dB settings. The second stage is a programmable-gain amplifier (PGA) adjustable from 0dB to 20dB in 1dB steps. To maximize the signalto-noise ratio, use the gain in the first stage whenever possible. Zero-crossing detection is included on the PGA to minimize zipper noise while making gain changes. MCLK MICBIAS PSCLK REG CLOCK CONTROL MBEN MIC1P/ DIGMICDATA PGAM1: +20dB TO 0dB MIC1N/ DIGMICCLK EXTMIC MIC2BYP PA1EN: 0/20/30dB ADLEN MIC2P MIX ADCL MIC2N EXTMIC INABYP PA2EN: 0/20/30dB PGAM1: +20dB TO 0dB MIXADL PGAINA: +20dB TO -6dB MIX INA1/EXTMICP INADIFF PGAINA: +20dB TO -6dB Figure 6. Microphone Input Block Diagram 60 ADREN MIXADR INA2/EXTMICN ADCR Stereo Audio CODEC with FLEXSOUND Technology REGISTER BIT NAME 6 PA1EN/PA2EN 5 3 0x31/0x32 PGAM1/PGAM2 1 0 7 MICCLK 6 5 GAIN (dB) VALUE 0x00 +20 0x0B +9 0x01 +19 0x0C +8 0x02 +18 0x0D +7 0x03 +17 0x0E +6 0x04 +16 0x0F +5 0x05 +15 0x10 +4 +14 0x11 +3 0x07 +13 0x12 +2 0x08 +12 0x13 +1 0x09 +11 0x14 to 0x1F 0 0x0A +10 Digital Microphone Clock Frequency Select a frequency that is within the digital microphone's clock frequency range. Set OSR1 = 1 when using a digital microphone. 00 = PCLK/8 01 = PCLK/6 10 = 64 x LRCLK 11 = Reserved DIGMICR Right Digital Microphone Enable Set PAR1EN = 00 for proper operation. 0 = Disabled 1 = Enabled EXTMIC GAIN (dB) 0x06 DIGMICL 1 0 VALUE Left Digital Microphone Enable Set PAL1EN = 00 for proper operation. 0 = Disabled 1 = Enabled 0x46 4 DESCRIPTION MIC1/MIC2 Preamplifier Gain Course microphone gain adjustment. 00 = Preamplifier disabled 01 = 0dB 10 = 20dB 11 = 30dB MIC1/MIC2 PGA Fine microphone gain adjustment. 4 2 MAX9888 Table 3. Microphone Input Registers External Microphone Connection Routes INA_/EXTMIC_ to the microphone preamplifiers. Set INAEN = 0 when using INA_/EXTMIC_ as a microphone input. 00 = Disabled 01 = MIC1 input 10 = MIC2 input 11 = Reserved 61 MAX9888 Stereo Audio CODEC with FLEXSOUND Technology Table 3. Microphone Input Registers (continued) REGISTER BIT NAME 7 INABYP 4 MIC2BYP 1 RECBYP 0x48 DESCRIPTION INA_/EXTMIC_ to MIC1_ Bypass Switch 0 = Disabled 1 = Enabled MIC1_ to MIC2_ Bypass Switch 0 = Disabled 1 = Enabled See the Output Bypass Switches section. 0 SPKBYP Line Inputs The device includes two sets of line inputs (Figure 7). Each set can be configured as a stereo single-ended input or as a mono differential input. Each input includes adjustable gain to match a wide range of input signal levels. If a custom gain is needed, the external gain mode provides a trimmed feedback resistor. Set the gain by choosing the appropriate input resistor and using the following formula: AVPGAIN = 20 x log (20K/RIN) The external gain mode also allows summing multiple signals into a single input, by connecting multiple input resistors as show in Figure 8, and inputting signals larger than 1VP-P. INABYP INA1/ EXTMICP PGAINA: +20dB TO -6dB INADIFF INA2/ EXTMICN PGAINA: +20dB TO -6dB MIX MIXOUT1 PGAINB: +20dB TO -6dB MIX INB1 INBDIFF PGAINB: +20dB TO -6dB MIXOUT2 LEFT INPUT 1 LEFT INPUT 2 20kI INA1/EXTMICP VCM RIGHT INPUT 1 RIGHT INPUT 2 20kI INA2/EXTMICN VCM MIX INB2 MIXOUT3 Figure 7. Line Input Block Diagram 62 Figure 8. Summing Multiple Input Signals into INA/INB Stereo Audio CODEC with FLEXSOUND Technology REGISTER BIT 6 0x33/0x34 NAME DESCRIPTION INAEXT/INBEXT 2 1 PGAINA/PGAINB 0 7 INADIFF 6 INBDIFF 0x45 Line Input A/B External Gain Switches out the internal input resistor and selects a trimmed 20kI feedback resistor. Use an external input resistor to set the gain of the line input. 0 = Disabled 1 = Enabled Line Input A/B Internal Gain Settings 000 = +20dB 001 = +14dB 010 = +3dB 011 = 0dB 100 = -3dB 101 = -6dB 110 = -6dB 111 = -6dB Line Input A Differential Enable 0 = Stereo single-ended input 1 = Mono differential input Line Input B Differential Enable 0 = Stereo single-ended input 1 = Mono differential input ADC Input Mixers The device's stereo ADC accepts input from the microphone amplifiers and line inputs. The ADC mixer routes any combination of the six audio inputs to the left and right ADCs (Figure 9). PGAM1: +20dB TO 0dB PA1EN: 0/20/30dB ADLEN MIX ADCL PGAM2: +20dB TO 0dB MIXADL PA2EN: 0/20/30dB MIX INADIFF + ADCR ADREN PGAINA: +20dB TO -6dB MIXADR PGAINA: +20dB TO -6dB PGAINB: +20dB TO -6dB INBDIFF + PGAINB: +20dB TO -6dB Figure 9. ADC Input Mixer Block Diagram 63 MAX9888 Table 4. Line Input Registers Table 5. ADC Input Mixer Register REGISTER BIT NAME DESCRIPTION 7 6 5 0x22/0x23 4 3 MIXADL/MIXADR 2 1 0 Left/Right ADC Input Mixer Selects which analog inputs are recorded by the left/right ADC. 1xxxxxxx = MIC1 x1xxxxxx = MIC2 xx1xxxxx = Reserved xxx1xxxx = Reserved xxxx1xxx = INA1 xxxxx1xx = INA2 (INADIFF = 0) or INA2 - INA1 (INADIFF = 1) xxxxxx1x = INB1 xxxxxxx1 = INB2 (INBDIFF = 0) or INB2 - INB1 (INBDIFF = 1) Record Path Signal Processing The device's record signal path includes both automatic gain control (AGC) for the microphone inputs and a digital noise gate at the output of the ADC (Figure 10). Microphone AGC The IC's AGC monitors the signal level at the output of the ADC and then adjusts the MIC1 and MIC2 analog PGA settings automatically. When the signal level is below the predefined threshold, the gain is increased up to its maximum (20dB). If the signal exceeds the threshold, the gain is reduced to prevent the output signal level exceeding the threshold. When AGC is enabled, the microphone PGA is not user programmable. The AGC provides a more constant signal level and improves the available ADC dynamic range. Noise Gate Since the AGC increases the levels of all signals below a user-defined threshold, the noise floor is effectively increased by 20dB. To counteract this, the noise gate reduces the gain at low signal levels. Unlike typical noise gates that completely silence the output below a defined level, the noise gate in the IC applies downward expansion. The noise gate attenuates the output at a rate of 1dB for each 2dB the signal is below the threshold. The noise gate can be used in conjunction with the AGC or on its own. When the AGC is enabled, the noise gate reduces the output level only when the AGC has set the gain to the maximum setting. Figure 11 shows the gain response resulting from using the AGC and noise gate. AGC AND NOISE GATE AMPLITUDE RESPONSE PGAM1: +20dB TO -6dB 0 NOISE GATE AUTOMATIC GAIN CONTROL PA1EN: 0/20/30dB PGAM2: +20dB TO 0dB AGC ONLY AUDIO/ VOICE FILTERS ADLEN MIX MODE1 AVFLT ADCL AVLG: 0/6/12/18dB AVL: 3dB TO -12dB MIXADL PA2EN: 0/20/30dB MIX MIXADR AGC AND NOISE GATE -40 -60 AGC AND NOISE GATE DISABLED -80 NOISE GATE ONLY ADCR ADREN -20 OUTPUT AMPLITUDE (dBFS) MAX9888 Stereo Audio CODEC with FLEXSOUND Technology -100 AVRG: 0/6/12/18dB AVR: 3dB TO -2dB -120 -120 -100 -80 -60 -40 -20 0 INPUT AMPLITUDE (dBFS) Figure 10. Record Path Signal Processing Block Diagram 64 Figure 11. AGC and Noise Gate Input vs. Output Gain Stereo Audio CODEC with FLEXSOUND Technology REGISTER BIT NAME 7 6 NG 5 0x01 3 AGC 1 0 7 GAIN (dB) VALUE GAIN (dB) 0x00 +20 0x0B +9 0x01 +19 0x0C +8 0x02 +18 0x0D +7 0x03 +17 0x0E +6 0x04 +16 0x0F +5 0x05 +15 0x10 +4 0x06 +14 0x11 +3 0x07 +13 0x12 +2 0x08 +12 0x13 +1 0x09 +11 0x14 to 0x1F 0 0x0A +10 AGCSRC AGCRLS AGC Release Time Defined as the duration from start to finish of gain increase in the region shown in Figure 12. Release times are longer for low AGC threshold levels. 000 = 78ms 001 = 156ms 010 = 312ms 011 = 625ms 100 = 1.25s 101 = 2.5s 110 = 5s 111 = 10s 6 4 VALUE AGC/Noise Gate Signal Source Determines which ADC channel the AGC and noise gates analyze. Gain is adjusted on both channels regardless of the AGCSRC setting. 0 = Left ADC output 1 = Maximum of either the left or right ADC output 0x3D 5 DESCRIPTION Noise Gate Attenuation Reports the current noise gate attenuation. 000 = 0dB 001 = 1dB 010 = 2dB 011 = 3dB to 5dB 100 = 6dB to 7dB 101 = 8dB to 9dB 110 = 10dB to 11dB 111 = 12dB AGC Gain Reports the current AGC gain setting. 4 2 MAX9888 Table 6. Record Path Signal Processing Registers 65 MAX9888 Stereo Audio CODEC with FLEXSOUND Technology Table 6. Record Path Signal Processing Registers (continued) REGISTER BIT NAME DESCRIPTION AGCATK AGC Attack Time Defined as the time required to reduce gain by 63% of the total gain reduction (one time constant of the exponential response). Attack times are longer for low AGC threshold levels. See Figure 12 for details. 00 = 2ms 01 = 7.2ms 10 = 31ms 11 = 123ms 3 2 0x3D 1 AGCHLD 0 AGC Hold Time The delay before the AGC release begins. The hold time counter starts whenever the signal drops below the AGC threshold and is reset by any signal that exceeds the threshold. Set AGCHLD to enable the AGC circuit. See Figure 12 for details. 00 = AGC disabled 01 = 50ms 10 = 100ms 11 = 400ms Noise Gate Threshold Gain is reduced for signals below the threshold to quiet noise. The thresholds are relative to the ADC's full-scale output voltage. 7 6 ANTH 5 4 0x3E VALUE THRESHOLD (dBFS) 0x0 Noise gate disabled 0x8 -45 0x1 Reserved 0x9 -41 0x2 Reserved 0xA -38 0x3 -64 0xB -34 0x4 -62 0xC -30 0x5 -58 0xD -27 0x6 -53 0xE -22 0x7 -50 0xF -16 VALUE 2 AGCTH 0 66 THRESHOLD (dBFS) AGC Threshold Gain is reduced when signals exceed the threshold to prevent clipping. The thresholds are relative to the ADC's full-scale voltage. 3 1 VALUE THRESHOLD (dBFS) VALUE THRESHOLD (dBFS) 0x0 -3 0x8 -11 0x1 -4 0x9 -12 0x2 -5 0xA -13 0x3 -6 0xB -14 0x4 -7 0xC -15 0x5 -8 0xD -16 0x6 -9 0xE -17 0x7 -10 0xF -18 Stereo Audio CODEC with FLEXSOUND Technology MAX9888 ATTACK TIME HOLD TIME RELEASE TIME Figure 12. AGC Timing ADC Record Level Control The IC includes separate digital level control for the left and right ADC outputs (Figure 13). To optimize dynamic range, use analog gain to adjust the signal level and set the digital level control to 0dB whenever possible. Digital level control is primarily used when adjusting the record level for digital microphones. NOISE GATE AUTOMATIC GAIN CONTROL AUDIO/ VOICE FILTERS MODE1 AVFLT1 ADLEN ADCL AVLG: 0/6/12/18dB AVL: 3dB TO -12dB ADCR ADREN AVRG: 0/6/12/18dB AVR: 3dB TO -2dB Figure 13. ADC Record Level Control Block Diagram 67 MAX9888 Stereo Audio CODEC with FLEXSOUND Technology Table 7. ADC Record Level Control Register REGISTER BIT NAME DESCRIPTION Left/Right ADC Gain 00 = 0dB 01 = 6dB 10 = 12dB 11 = 18dB 5 AVLG/AVRG 4 Left/Right ADC Level 3 0x2F/0x30 2 1 AVL/AVR 0 VALUE GAIN (dB) VALUE GAIN (dB) 0x0 +3 0x8 -5 0x1 +2 0x9 -6 0x2 +1 0xA -7 0x3 0 0xB -8 0x4 -1 0xC -9 0x5 -2 0xD -10 0x6 -3 0xE -11 0x7 -4 0xF -12 Sidetone used in telephony to allow the speaker to hear himself speak, providing a more natural user experience. The IC implements sidetone digitally. Doing so helps prevent unwanted feedback into the playback signal path and better matches the playback audio signal. Enable sidetone during full-duplex operation to add a low-level copy of the recorded audio signal to the playback audio signal (Figure 14). Sidetone is commonly DV1G: 0/6/12/18dB DVST: 0dB TO -60dB SIDETONE + MIX DSTS MULTIBAND ALC NOISE GATE AUTOMATIC GAIN CONTROL AUDIO/ VOICE FILTERS MODE1 AVFLT ADLEN ADCL AVLG: 0/6/12/18dB AVL: 3dB TO -12dB DVEQ1: 0dB TO -15dB 5-BAND PARAMETRIC EQ DVEQ2: 0dB TO -15dB 5-BAND PARAMETRIC EQ EQ1EN EQ2EN DV2: 0dB TO -15dB ADCR ADREN AVRG: 0/6/12/18dB AVR: 3dB TO -2dB Figure 14. Sidetone Block Diagram 68 MIXDAL EXCURSION LIMITER DV1: 0dB TO -15dB MIX DACL DALEN AUDIO/ FILTERS DCB2 AUDIO/ VOICE FILTERS MODE1 DVFLT MIXDAR MIX DACR DAREN Stereo Audio CODEC with FLEXSOUND Technology REGISTER BIT NAME 7 DSTS 6 3 0x2A 1 0 DESCRIPTION Sidetone Source Selects which ADC output is fed back as sidetone. When mixing the left and right ADC outputs, each is attenuated by 6dB to prevent full-scale signals from clipping. 00 = Sidetone disabled 01 = Left ADC 10 = Right ADC 11 = Left + Right ADC Sidetone Level Adjusts the sidetone signal level. All levels are referenced to the ADC's full-scale output. 4 2 MAX9888 Table 8. Sidetone Register DVST VALUE LEVEL (dB) VALUE LEVEL (dB) 0x00 Sidetone disabled 0x10 -30.5 0x01 -0.5 0x11 -32.5 0x02 -2.5 0x12 -34.5 0x03 -4.5 0x13 -36.5 0x04 -6.5 0x14 -38.5 0x05 -8.5 0x15 -40.5 0x06 -10.5 0x16 -42.5 0x07 -12.5 0x17 -44.5 0x08 -14.5 0x18 -46.5 0x09 -16.5 0x19 -48.5 0x0A -18.5 0x1A -50.5 0x0B -20.5 0x1B -52.5 0x0C -22.5 0x1C -54.5 0x0D -24.5 0x1D -56.6 0x0E -26.5 0x1E -58.5 0x0F -28.5 0x1F -60.5 Digital Audio Interfaces The IC includes two separate playback signal paths and one record signal path. Digital audio interface 1 (DAI1) is used to transmit the recorded stereo audio signal and receive a stereo audio signal for playback. Digital audio interface 2 (DAI2) is used to receive a second stereo audio signal. Use DAI1 for all full-duplex operations and for all voice signals. Use DAI2 for music and to mix two playback audio signals. The digital audio interfaces are separate from the audio ports to enable either interface to communicate with any external device connected to the audio ports. Each audio interface can be configured in a variety of formats including left justified, I2S, PCM, and time division multiplexed (TDM). TDM mode supports up to 4 mono audio slots in each frame. The IC can use up to 2 mono slots per interface, leaving the remaining two slots available for another device. Table 9 shows how to configure the device for common digital audio formats. Figures 16 and 17 show examples of common audio formats. By default, SDOUTS1 and SDOUTS2 are set high impedance when the IC is not outputting data to facilitate sharing the bus. Configure the interface in TDM mode using only slot 1 to transmit and receive mono PCM voice data. The IC's digital audio interfaces support both ADC to DAC loop-through and digital loopback. Loop-through allows the signal converted by the ADC to be routed to the DAC for playback. The signal is routed from the record path to the playback path in the digital audio interface to allow the IC's full complement of digital signal processing to be used. Loopback allows digital 69 data input to either SDINS1 or SDINS2 to be routed from one interface to the other for output on SDOUTS2 or SDOUTS1. Both interfaces must be configured for the same sample rate, but the interface format need LRCLKS1 BCLKS1 SDOUTS1 SDINS1 not be the same. This allows the IC to route audio data from one device to another, converting the data format as needed. Figure 15 shows the available digital signal routing options. DVDDS1 BCLKS2 LRCLKS2 SDOUTS2 PORT S1 SDINS2 DVDDS2 PORT S1 DAI1 SDIN2 SDOUT2 LRCLK2 BCLK2 SDIN1 SDOUT1 SEL2 LRCLK1 SEL1 BCLK1 MAX9888 Stereo Audio CODEC with FLEXSOUND Technology DAI2 MAS1 MAS1 BIT CLOCK FRAME CLOCK HIZOFF1 DATA OUTPUT MAS2 DATA INPUT MAS2 BIT CLOCK FRAME CLOCK HIZOFF2 DATA OUTPUT DATA INPUT LBEN1 MUX LBEN2 + LTEN1 DAI1 RECORD PATH DAI1 PLAYBACK PATH DAI2 PLAYBACK PATH Figure 15. Digital Audio Signal Routing Table 9. Common Digital Audio Formats MODE WCI1/WCI2 BCI1/BCI2 DLY1/DLY2 TDM1/TDM2 Left Justified Set as desired Set as desired 0 0 X X I2S 1 0 1 0 X X 0 PCM X 1 X 1 TDM X 1 X 1 X = Don't care. 70 SLOTL1/SLOTL2 SLOTR1/SLOTR2 0 Set as desired Stereo Audio CODEC with FLEXSOUND Technology REGISTER BIT 7 6 5 NAME 4 2 1 0 DESCRIPTION MAS1/MAS2 DAI1/DAI2 Master Mode In master mode, DAI1/DAI2 outputs LRCLK and BCLK. In slave mode, DAI1/DAI2 accept LRCLK and BCLK as inputs. 0 = Slave mode 1 = Master mode WCI1/WCI2 DAI1/DAI2 Word Clock Invert TDM1/TDM2 = 0: 0 = Left-channel data is transmitted while LRCLK is low. 1 = Right-channel data is transmitted while LRCLK is low. TDM1/TDM2 = 1: Always set WCI = 0. BCI1/BCI2 DAI1/DAI2 Bit Clock Invert BCI1/BCI2 must be set to 1 when TDM1/TDM2 = 1. 0 = SDIN is accepted on the rising edge of BCLK. SDOUT is valid on the rising edge of BCLK. 1 = SDIN is accepted on the falling edge of BCLK. SDOUT is valid on the falling edge of BCLK. Master Mode: 0 = LRCLK transitions on the falling edge of BCLK. 1 = LRCLK transitions on the rising edge of BCLK. DLY1/DLY2 DAI1/DAI2 Data Delay DLY1/DLY2 has no effect when TDM1/TDM2 = 1. 0 = The most significant data bit is clocked on the first active BCLK edge after an LRCLK transition. 1 = The most significant data bit is clocked on the second active BCLK edge after an LRCLK transition. TDM1/TDM2 DAI1/DAI2 Time-Division Multiplex Mode (TDM Mode) Set TDM1/TDM2 when communicating with devices that use a frame synchronization pulse on LRCLK instead of a square wave. 0 = Disabled 1 = Enabled (BCI1/BCI2 must be set to 1) FSW1/FSW2 DAI1/DAI2 Wide Frame Sync Pulse Increases the width of the frame sync pulse to the full data width when TDM1/TDM2 = 1. FSW1/FSW2 has no effect when TDM1/TDM2 = 0. 0 = Disabled 1 = Enabled 0x14/0x1C WS1/WS2 MAX9888 Table 10. Digital Audio Interface Registers DAI1/DAI2 Audio Data Bit Depth Determines the maximum bit depth of audio being transmitted and received. Data is always 16 bit when TDM1/TMD2 = 0. 0 = 16 bits 1 = 24 bits 71 MAX9888 Stereo Audio CODEC with FLEXSOUND Technology Table 10. Digital Audio Interface Registers (continued) REGISTER BIT NAME 7 OSR1 6 0x15/0x1D 2 1 BSEL1/ BSEL2 0 7 SEL1/SEL2 6 5 3 72 DAI1/DAI2 BCLK Output Frequency When operating in master mode, BSEL1/BSEL2 set the frequency of BCLK. When operating in slave mode, BSEL1/BSEL2 have no effect. Select the lowest BCLK frequency that clocks all data input to the DAC and output by the ADC. 000 = BCLK disabled 001 = 64 x LRCLK 010 = 48 x LRCLK 011 = 128 x LRCLK (invalid for DHF1/DHF2 = 1) 100 = PCLK/2 101 = PCLK/4 110 = PCLK/8 111 = PCLK/16 DAI1/DAI2 Audio Port Selector Selects which port is used by DAI1/DAI2. 00 = None 01 = Port S1 10 = Port S2 11 = Reserved LTEN1 DAI1 Digital Loopthrough Connects the output of the record signal path to the input of the playback path. Data input to DAI1 from an external device is mixed with the recorded audio signal. 0 = Disabled 1 = Enabled LBEN1/ LBEN2 DAI1/DAI2 Digital Audio Interface Loopback LBEN1 routes the digital audio input to DAI1 back out on DAI2. LBEN2 routes the digital audio input to DAI2 back out on DAI1. Selecting LBEN2 disables the ADC output data. 0 = Disabled 1 = Enabled 0x16/0x1E 4 DESCRIPTION ADC Oversampling Ratio Use the higher setting for maximum performance. Use the lower setting for reduced power consumption at the expense of performance. 00 = 96x 01 = 64x 10 = Reserved 11 = Reserved DMONO1/ DMONO2 DAI1/DAI2 DAC Mono Mix Mixes the left and right digital input to mono and routes the combined signal to the left and right playback paths. The left and right input data is attenuated by 6dB prior to the mono mix. 0 = Disabled 1 = Enabled Stereo Audio CODEC with FLEXSOUND Technology REGISTER BIT NAME DESCRIPTION 2 HIZOFF1/ HIZOFF2 Disable DA1/DAI2 Output High-Impedance Mode Normally SDOUT is set high impedance between data words. Set HIZOFF1/HIZOFF2 to force a level on SDOUT at all times. 0 = Disabled 1 = Enabled 1 SDOEN1/ SDOEN2 DAI1/DAI2 Record Path Output Enable DAI2 outputs data only if LBEN1 = 1. 0 = Disabled 1 = Enabled 0 SDIEN1/ SDIEN2 DAI1/DAI2 Playback Path Input Enable 0 = Disabled 1 = Enabled 0x16/0x1E 7 SLOTL1/ SLOTL2 6 5 SLOTR1/ SLOTR2 0x17/0x1F 4 3 2 1 0 SLOTDLY1/ SLOTDLY2 TDM Left Time Slot Selects which of the four slots is used for left data on DAI1/DAI2. If the same slot is selected for left and right audio, left audio is placed in the slot. 00 = Slot 1 01 = Slot 2 10 = Slot 3 11 = Slot 4 TDM Right Time Slot Selects which of the four slots is used for right data on DAI1/DAI2. If the same slot is selected for left and right audio, left audio is placed in the slot. 00 = Slot 1 01 = Slot 2 10 = Slot 3 11 = Slot 4 TDM Slot Delay Adds 1 BCLK cycle delay to the data in the specified TDM slot. 1xxx = Slot 4 delayed x1xx = Slot 3 delayed xx1x = Slot 2 delayed xxx1 = Slot 1 delayed 73 MAX9888 Table 10. Digital Audio Interface Registers (continued) MAX9888 Stereo Audio CODEC with FLEXSOUND Technology WCI_ = 0, BCI_ = 0, DLY_ = 0, TDM_ = 0, FSW_ = 0, WS_ = 0, HIZOFF_ = 1, SLOTL_ = 0, SLOTR_ = 0 LRCLK SDOUT RIGHT LEFT D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 BCLK SDIN WCI_ = 1, BCI_ = 0, DLY_ = 0, TDM_ = 0, FSW_ = 0, WS_ = 0, HIZOFF_ = 1, SLOTL_ = 0, SLOTR_ = 0 LRCLK SDOUT LEFT RIGHT D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 BCLK SDIN WCI_ = 0, BCI_ = 1, DLY_ = 0, TDM_ = 0, FSW_ = 0, WS_ = 0, HIZOFF_ = 1, SLOTL_ = 0, SLOTR_ = 0 LRCLK SDOUT RIGHT LEFT D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 BCLK SDIN WCI_ = 0, BCI_ = 0, DLY_ = 1, TDM_ = 0, FSW_ = 0, WS_ = 0, HIZOFF_ = 1, SLOTL_ = 0, SLOTR_ = 0 LRCLK SDOUT LEFT RIGHT D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 BCLK SDIN Figure 16. Non-TDM Data Format Examples 74 Stereo Audio CODEC with FLEXSOUND Technology MAX9888 WCI_ = 0, BCI_ = 1, DLY_ = 0, TDM_ = 1, FSW_ = 0, WS_ = 0, HIZOFF_ = 0, SLOTL_ = 0, SLOTR_ = 1 LRCLK SDOUT HI-Z L15 L14 L13 L12 L11 L10 L9 L8 L7 L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 HI-Z BCLK SDIN L6 L5 WCI_ = 0, BCI_ = 1, DLY_ = 0, TDM_ = 1, FSW_ = 1, WS_ = 0, HIZOFF_ = 0, SLOTL_ = 0, SLOTR_ = 1 LRCLK SDOUT HI-Z L15 L14 L13 L12 L11 L10 L9 L8 L7 L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 HI-Z BCLK SDIN L6 L5 WCI_ = 0, BCI_ = 1, DLY_ = 0, TDM_ = 1, FSW_ = 0, WS_ = 0, HIZOFF_ = 1, SLOTL_ = 0, SLOTR_ = 1 LRCLK SDOUT L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 BCLK SDIN WCI_ = 0, BCI_ = 1, DLY_ = 0, TDM_ = 1, FSW_ = 0, WS_ = 0, HIZOFF_ = 0, SLOTL_ = 2, SLOTR_ = 3 LRCLK HI-Z SDOUT 32 CYCLES L15 L14 L13 L12 L11 L10 L9 L8 L7 L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 HI-Z BCLK SDIN L6 L5 WCI_ = 0, BCI_ = 1, DLY_ = 0, TDM_ = 1, FSW_ = 0, WS_ = 0, HIZOFF_ = 0, SLOTL_ = 0, SLOTR_ = 1 LRCLK 16 CYCLES SDOUT 16 CYCLES 16 CYCLES HI-Z L L L L L L L L R R R R R R R R HI-Z L L L L L L L L 1 1 1 1 R R R R 16 CYCLES HI-Z BCLK SDIN Figure 17. TDM Mode Data Format Examples 75 MAX9888 Stereo Audio CODEC with FLEXSOUND Technology Clock Control The digital signal paths in the IC require a master clock (MCLK) between 10MHz and 60MHz to function. Internally, the MAX9888 requires a clock between 10MHz and 20MHz. A prescaler divides MCLK by 1, 2, or 4 to create the internal clock (PCLK). PCLK is used to clock all portions of the IC. The MAX9888 includes two digital audio signal paths, both capable of supporting any sample rate from 8kHz to 96kHz. Each path is independently configured to allow different sample rates. To accommodate a wide range of system architectures, three main clocking modes are supported: U PLL Mode: When operating in slave mode, enable the PLL to lock onto any LRCLK input. This mode requires the least configuration, but provides the lowest performance. Use this mode to simplify initial setup or when normal mode and exact integer mode cannot be used. U Normal Mode: This mode uses a 15-bit clock divider to set the sample rate relative to PCLK. This allows high flexibility in both the PCLK and LRCLK frequencies and can be used in either master or slave mode. U Exact Integer Mode (DAI1 only): In both master and slave modes, common MCLK frequencies (12MHz, 13MHz, 16MHz, and 19.2MHz) can be programmed to operate in exact integer mode for both 8kHz and 16kHz sample rates. In these modes, the MCLK and LRCLK rates are selected by using the FREQ1 bits instead of the NI, and PLL control bits. Table 11. Clock Control Registers REGISTER BIT NAME 5 0x10 PSCLK 4 DAI1/DAI2 Sample Rate Used by the ALC to correctly set the dual-band crossover frequency and the excursion limiter to set the predefined corner frequencies. 7 6 0x11/0x19 SR1/SR2 5 4 76 DESCRIPTION MCLK Prescaler Generates PCLK, which is used by all internal circuitry. 00 = PCLK disabled 01 = 10MHz P MCLK P 20MHz (PCLK = MCLK) 10 = 20MHz P MCLK P 40MHz (PCLK = MCLK/2) 11 = 40MHz P MCLK P 60MHz (PCLK = MCLK/4) VALUE SAMPLE RATE (kHz) VALUE SAMPLE RATE (kHz) 0x0 Reserved 0x8 48 0x1 8 0x9 88.2 0x2 11.025 0xA 96 0x3 16 0xB Reserved 0x4 22.05 0xC Reserved 0x5 24 0xD Reserved 0x6 32 0xE Reserved 0x7 44.1 0xF Reserved Stereo Audio CODEC with FLEXSOUND Technology REGISTER BIT NAME DESCRIPTION Exact Integer Mode Overrides PLL1 and NI1 and configures a specific PCLK to LRCLK ratio. 3 0x11 2 FREQ1 1 7 0x12/0x1A PLL1/PLL2 6 4 3 2 1 7 SAMPLE RATE VALUE 0x0 Disabled 0x8 0x1 Reserved 0x9 0x2 Reserved 0xA 0x3 Reserved 0xB 0x4 Reserved 0xC 0x5 Reserved 0xD 0x6 Reserved 0xE 0x7 Reserved 0xF SAMPLE RATE PCLK = 12MHz, LRCLK = 8kHz PCLK = 12MHz, LRCLK = 16kHz PCLK = 13MHz, LRCLK = 8kHz PCLK = 13MHz, LRCLK = 16kHz PCLK = 16MHz, LRCLK = 8kHz PCLK = 16MHz, LRCLK = 16kHz PCLK = 19.2MHz, LRCLK = 8kHz PCLK = 19.2MHz, LRCLK = 16kHz PLL Mode Enable (Slave Mode Only) PLL1/PLL2 enables a digital PLL that locks on to the externally supplied LRCLK frequency and automatically sets the LRCLK divider (NI1/NI2). 0 = Disabled 1 = Enabled Normal Mode LRCLK Divider When PLL1/PLL2 = 0, the frequency of LRCLK is determined by NI1/NI2. See Table 12 for common NI values. 5 0 VALUE NI1/ NI2 6 5 SAMPLE RATE DHF1/DHF2 NI1/NI2 FORMULA 8kHz P LRCLK P 48kHz 0 NI = 65536 x 96 x fLRCLK fPCLK 48kHz < LRCLK P 96kHz 1 NI = 65536 x 48 x fLRCLK fPCLK 4 3 0x13/0x1B fLRCLK = LRCLK frequency fPCLK = Prescaled MCLK frequency (PCLK) 2 1 0 NI1[0]/NI2[0] Rapid Lock Mode Program NI1/NI2 to the nearest valid ratio and set NI1[0]/NI2[0] when PLL1/PLL2 = 1 to enable rapid lock mode. Normally, the PLL automatically calculates and dynamically adjusts NI1/NI2. When rapid lock mode is properly configured, the PLL starting point is much closer to the correct value, thus speeding up lock time. Wait one LRCLK period after programming NI1/NI2 before setting PLL1/PLL2 = 1. 77 MAX9888 Table 11. Clock Control Registers (continued) MAX9888 Stereo Audio CODEC with FLEXSOUND Technology Table 12. Common NI1/NI2 Values LRCLK (kHz) PCLK (MHz) 10 DHF1/2 = 0 DHF1/2 = 1 8 11.025 12 16 22.05 24 32 44.1 48 64 88.2 96 13A9 1B18 1D7E 2752 3631 3AFB 4EA5 6C61 75F7 4EA5 6C61 75F7 11 11E0 18A2 1ACF 23BF 3144 359F 477E 6287 6B3E 477E 6287 6B3E 11.2896 116A 1800 1A1F 22D4 3000 343F 45A9 6000 687D 45A9 6000 687D 624E 12 1062 1694 1893 20C5 2D29 3127 4189 5A51 624E 4189 5A51 12.288 1000 160D 1800 2000 2C1A 3000 4000 5833 6000 4000 5833 6000 13 0F20 14D8 16AF 1E3F 29AF 2D5F 3C7F 535F 5ABE 3C7F 535F 5ABE 16 0C4A 10EF 126F 1893 21DE 24DD 3127 43BD 49BA 3127 43BD 49BA 16.9344 0B9C 1000 116A 1738 2000 22D4 2E71 4000 45A9 2E71 4000 45A9 18.432 0AAB 0EB3 1000 1555 1D66 2000 2AAB 3ACD 4000 2AAB 3ACD 4000 20 09D5 0D8C 0EBF 13A9 1B18 1D7E 2752 3631 3AFB 2752 3631 3AFB Note: Values in bold are exact integers that provide maximum full-scale performance. Passband Filtering Use music mode when processing high-fidelity audio content. The music FIR filters reduce power consumption and are linear phase to maintain stereo imaging. An optional DC-blocking filter is available to eliminate unwanted DC offset. Each digital signal path in the IC includes options for defining the path bandwidth (Figure 18). The playback and record paths connected to DAI1 support both voice and music filtering while the playback path connected to DAI2 supports music filtering only. In music mode, a second set of FIR filters are available to support sample rates greater than 50kHz. The filters can be independently selected for DAI1 and DAI2 and support both the playback and record audio paths. The voice IIR filters provide greater than 70dB stopband attenuation at frequencies above fS/2 to reduce aliasing. Three selectable highpass filters eliminate unwanted low-frequency signals. DV1G: 0/6/12/18dB DVST: 0dB TO -60dB SIDETONE + MIX DSTS MULTIBAND ALC NOISE GATE AUTOMATIC GAIN CONTROL AUDIO/ VOICE FILTERS MODE1 AVFLT ADLEN ADCL AVLG: 0/6/12/18dB AVL: 3dB TO -12dB DVEQ1: 0dB TO -15dB 5-BAND PARAMETRIC EQ DVEQ2: 0dB TO -15dB 5-BAND PARAMETRIC EQ EQ1EN DV2: 0dB TO -15dB ADCR ADREN AVRG: 0/6/12/18dB AVR: 3dB TO -2dB Figure 18. Digital Passband Filtering Block Diagram 78 MIXDAL EQ2EN EXCURSION LIMITER DV1: 0dB TO -15dB MIX DACL DALEN AUDIO/ FILTERS DCB2 AUDIO/ VOICE FILTERS MODE1 DVFLT MIXDAR MIX DACR DAREN Stereo Audio CODEC with FLEXSOUND Technology REGISTER BIT NAME 7 MODE1 6 5 AVFLT1 0x18 DHF1 2 1 DVFLT1 MODE1 AVFLT1 0 See Table 14 1 Select a nonzero value to enable the DC-blocking filter DAI1 High Sample Rate Mode Selects the sample rate range. 0 = 8kHz P LRCLK P 48kHz 1 = 48kHz P LRCLK < 96kHz MODE1 DVFLT1 0 See Table 14 1 Select a nonzero value to enable the DC-blocking filter DHF2 DAI2 High Sample Rate Mode Selects the sample rate range. 0 = 8kHz P LRCLK P 48kHz 1 = 48kHz < LRCLK P 96kHz DCB2 DAI2 DC Blocking Filter Enables a DC-blocking filter on the DAI2 playback audio path. 0 = Disabled 1 = Enabled 0x20 0 DAI1 Passband Filtering Mode 0 = Voice filters 1 = Music filters (recommended for fS > 24kHz) DAI1 DAC Highpass Filter Mode 0 3 DESCRIPTION DAI1 ADC Highpass Filter Mode 4 3 MAX9888 Table 13. Passband Filtering Registers 79 Table 14. Voice Highpass Filters AVFTL/DVFLT VALUE INTENDED SAMPLE RATE FILTER RESPONSE 000 N/A Disabled 0 001/011 16kHz/8kHz AMPLITUDE (dB) -10 -20 -30 -40 -50 -60 0 200 400 600 800 1000 800 1000 FREQUENCY (Hz) 0 010/100 16kHz/8kHz AMPLITUDE (dB) -10 -20 -30 -40 -50 -60 0 200 400 600 FREQUENCY (Hz) 0 -10 101 8kHz to 48kHz AMPLITUDE (dB) MAX9888 Stereo Audio CODEC with FLEXSOUND Technology -20 -30 -40 -50 LRCLK = 48kHz -60 0 200 400 600 FREQUENCY (Hz) 110/111 80 N/A Reserved 800 1000 Stereo Audio CODEC with FLEXSOUND Technology Automatic Level Control The automatic level control (ALC) circuit ensures maximum signal amplitude without producing audible clipping. This is accomplished by a variable gain stage that works on a sample by sample basis to increase the gain up to 12dB. A look-ahead circuit determines if the next sample exceeds full scale and reduces the gain so that the sample is exactly full scale. A programmable low signal threshold determines the minimum signal amplitude that is amplified. Select a threshold that prevents the amplification of background noise. When the signal level drops below the low signal threshold, the ALC reduces the gain to 0dB until the signal increases above the threshold. Figure 20 shows an example of ALC input vs. output curves. The ALC can optionally be configured in dual-band mode. In this mode, the input signal is filtered into two bands with a 5kHz center frequency. Each band is routed through independent ALCs and then summed together. In multiband mode, both bands use the same parameters. OUTPUT SIGNAL (dBFS) 0 LOW-LEVEL -12 0 THRESHOLD ALC WITH ALCTH 000 INPUT SIGNAL (dBFS) OUTPUT SIGNAL (dBFS) 0 DV1G: 0/6/12/18dB + 0 INPUT SIGNAL (dBFS) 0 INPUT SIGNAL (dBFS) MULTIBAND ALC DVEQ1: 0dB TO -15dB 5-BAND PARAMETRIC EQ LOW-LEVEL THRESHOLD DVEQ2: 0dB TO -15dB ALC WITH ALCTH = 000 OUTPUT SIGNAL (dBFS) 5-BAND PARAMETRIC EQ EQ1EN EQ2EN DV1: 0dB TO -15dB 0 MIXDAL EXCURSION LIMITER DV2: 0dB TO -15dB -12 MIX DACL DALEN AUDIO/ FILTERS DCB2 AUDIO/ VOICE FILTERS MODE1 DVFLT MIXDAR MIX DACR DAREN LOW-LEVEL THRESHOLD -12 ALC DISABLED Figure 19. Playback Path Signal Processing Block Diagram Figure 20. ALC Input vs. Output Examples 81 MAX9888 Playback Path Signal Processing The IC playback signal path includes automatic level control (ALC) and a 5-band parametric equalizer (EQ) (Figure 19). The DAI1 and DAI2 playback paths include separate ALCs controlled by a single set of registers. Two completely separate parametric EQs are included for the DAI1 and DAI2 playback paths. Table 15. Automatic Level Control Registers REGISTER BIT 7 NAME ALCEN ALC and Excursion Limiter Release Time Sets the release time for both the ALC and Excursion Limiter. See the Excursion Limiter section for Excursion Limiter release times. ALC release time is defined as the time required to adjust the gain from 12dB to 0dB. 6 5 0x41 ALCRLS 4 3 0 VALUE 000 001 010 011 100 101 110 111 ALC RELEASE TIME (s) 8 4 2 1 0.5 0.25 Reserved Reserved ALCMB Multiband Enable Enables dual-band processing with a 5kHz center frequency. SR1 and SR2 must be configured properly to achieve the correct center frequency for each playback path. 0 = Single-band ALC 1 = Dual-band ALC ALCTH Low Signal Threshold Selects the minimum signal level to be boosted by the ALC. 000 = -JdB (low-signal threshold disabled) 001 = -12dB 010 = -18dB 011 = -24dB 100 = -30dB 101 = -36dB 110 = -42dB 111 = -48dB 2 1 DESCRIPTION ALC Enable Enables ALC on both the DAI1 and DAI2 playback paths. 0 = Disabled 1 = Enabled Parametric Equalizer The parametric EQ contains five independent biquad filters with programmable gain, center frequency, and bandwidth. Each biquad filter has a gain range of Q12dB and a center frequency range from 20Hz to 20kHz. Use a filter Q less than that shown in Figure 21 to achieve ideal frequency responses. Setting a higher Q results in nonideal frequency response. The biquad filters are series connected, allowing a total gain of Q60dB. 1000 MAXIMUM RECOMMENDED FILTER Q MAX9888 Stereo Audio CODEC with FLEXSOUND Technology fs = 8kHz 100 fs = 48kHz 10 fs = 96kHz 1 0.1 100 1000 10,000 100,000 CENTER FREQUENCY (Hz) Figure 21. Maximum Recommended Filter Q vs. Frequency 82 Stereo Audio CODEC with FLEXSOUND Technology The MAX9888 EV kit software includes a graphic interface for generating the EQ coefficients. The coefficients are sample rate dependent and stored in registers 0x50 through 0xB3. Table 16. EQ Registers REGISTER BIT NAME 4 EQCLP1/ EQCLP2 2 DVEQ1/DVEQ2 1 0 0x47 DAI1/DAI2 EQ Clip Detection Automatically controls the EQ attenuator to prevent clipping in the EQ. 0 = Enabled 1 = Disabled DAI1/DAI2 EQ Attenuator Provides attenuation to prevent clipping in the EQ when full-scale signals are boosted. DVEQ1/DVEQ2 operates only when EQ1EN/EQ2EN = 1 and EQCLP1/EQCLP2 = 1. 3 0x2C/0x2E DESCRIPTION VALUE GAIN (dB) VALUE GAIN (dB) 0x0 0 0x8 -8 0x1 -1 0x9 -9 0x2 -2 0xA -10 0x3 -3 0xB -11 0x4 -4 0xC -12 0x5 -5 0xD -13 0x6 -6 0xE -14 0x7 -7 0xF -15 7 VS2EN 6 VSEN 5 ZDEN 1 EQ2EN DAI2 EQ Enable 0 = Disabled 1 = Enabled 0 EQ1EN DAI1 EQ Enable 0 = Disabled 1 = Enabled See the Click-and-Pop Reduction section. 83 MAX9888 Use the attenuator at the EQ's input to avoid clipping the signal. The attenuator can be programmed for fixed attenuation or dynamic attenuation based on signal level. If the dynamic EQ clip detection is enabled, the signal level from the EQ is fed back to the attenuator circuit to determine the amount of gain reduction necessary to avoid clipping. MAX9888 Stereo Audio CODEC with FLEXSOUND Technology Playback Level Control allows boost when MODE1 = 0 and attenuation in any mode. The DAI2 signal path allows attenuation only. The IC includes separate digital level control for the DAI1 and DAI2 playback audio paths. The DAI1 signal path DV1G: 0/6/12/18dB + MULTIBAND ALC DVEQ1: 0dB TO -15dB 5-BAND PARAMETRIC EQ EQ1EN DVEQ2: 0dB TO -15dB 5-BAND PARAMETRIC EQ EQ2EN MIXDAL EXCURSION LIMITER DACL MIX DV2: 0dB TO -15dB DV1: 0dB TO -15dB DALEN AUDIO/ FILTERS DCB2 AUDIO/ VOICE FILTERS MIXDAR MIX MODE1 DVFLT DACR DAREN Figure 22. Playback Level Control Block Diagram Table 17. DAC Playback Level Control Register REGISTER BIT 7 NAME DV1M/DV2M 5 DV1G 4 0x2B/0x2D VALUE 2 DV1/DV2 0 84 DAI1 Voice Mode Gain DV1G only applies when MODE1 = 0. 00 = 0dB 01 = 6dB 10 = 12dB 11 = 18dB DAI1/DAI2 Attenuation 3 1 DESCRIPTION DAI1/DAI2 Mute 0 = Disabled 1 = Enabled GAIN (dB) VALUE GAIN (dB) 0x0 0 0x8 -8 0x1 -1 0x9 -9 0x2 -2 0xA -10 0x3 -3 0xB -11 0x4 -4 0xC -12 0x5 -5 0xD -13 0x6 -6 0xE -14 0x7 -7 0xF -15 Stereo Audio CODEC with FLEXSOUND Technology DV1G: 0/6/12/18dB + MULTIBAND ALC DVEQ1: 0dB TO -15dB 5-BAND PARAMETRIC EQ DVEQ2: 0dB TO -15dB 5-BAND PARAMETRIC EQ EQ1EN EQ2EN MIXDAL EXCURSION LIMITER DV2: 0dB TO -15dB DV1: 0dB TO -15dB MIX DACL DALEN AUDIO/ FILTERS DCB2 AUDIO/ VOICE FILTERS MODE1 DVFLT MIXDAR MIX DACR DAREN Figure 23. DAC Input Mixer Block Diagram Table 18. DAC Input Mixer Register REGISTER BIT NAME 7 6 5 0x21 MIXDAL Left DAC Input Mixer 1xxx = DAI1 left channel x1xx = DAI1 right channel xx1x = DAI2 left channel xxx1 = DAI2 right channel MIXDAR Right DAC Input Mixer 1xxx = DAI1 left channel x1xx = DAI1 right channel xx1x = DAI2 left channel xxx1 = DAI2 right channel 4 3 2 1 0 DESCRIPTION 85 MAX9888 DAC Input Mixers The IC's stereo DAC accepts input from two digital audio paths. The DAC mixer routes any audio path to the left and right DACs (Figure 23). MAX9888 Stereo Audio CODEC with FLEXSOUND Technology Preoutput Signal Path The IC's preoutput mixer stage provides mixing and level adjustment for line input signals routed to the output amplifiers. Figure 24 shows a block diagram of the preoutput signal path. 9dB is added between the line input amplifiers and the output amplifiers to boost the 1VP-P maximum line input signal level to the 1VRMS maximum DAC signal level. RECP/ RXINP RECVOL: +8dB TO -62dB 0dB MIX MIXREC RECEN RECN/ RXINN RECBYP SPKBYP BATTERY ADC SPVOLL: +8dB TO -62dB SPKLVDD SPKLP +6dB MIX SPKLN MIXSPL SPLEN POWER/ DISTORTION LIMITER SPKLGND SPKRVDD SPKRP +6dB MIX MIXSPR SPVOLR: +8dB TO -62dB PGAINA: +20dB TO -6dB PGAOUT1: 0dB TO -23dB INADIFF + PGAINA: +20dB TO -6dB PREOUT1 MIX MIXOUT1 PGAINB: +20dB TO -6dB PREOUT2 MIXHPL SPKRPGND HPL HPLEN HPSNS HPVOLR: +3dB TO -67dB MIX +9dB HPR HPREN PGAOUT3: 0dB TO -23dB MIX + +9dB MIXHPR MIXOUT2 INBDIFF PGAINB: +20dB TO -6dB MIX PGAOUT2: 0dB TO -23dB MIX SPKRN SPREN HPVOLL: +3dB TO -67dB PREOUT3 +9dB MIXOUT3 Figure 24. Preoutput Signal Path Block Diagram Preoutput Mixer The IC's output amplifiers each accept input from one of the three preoutput mixers. Configure each preoutput mixer to mix any combination of the four line input signals. Table 19. Preoutput Mixer Registers REGISTER BIT NAME 3 0x24/0x25/ 0x26 2 1 0 86 MIXOUT1/ MIXOUT2/ MIXOUT3 DESCRIPTION Preoutput Mixer 1 1xxx = INA1 x1xx = INA2 (INADIFF = 0) or INA2 - INA1 (INADIFF = 1) xx1x = INB1 xxx1 = INB2 (INBDIFF = 0) or INB2 - INB1 (INBDIFF = 1) Stereo Audio CODEC with FLEXSOUND Technology Table 20. Preoutput PGA Registers REGISTER BIT NAME DESCRIPTION Preoutput PGA Level 3 2 0x35/0x36/ 0x37 1 PGAOUT1/ PGAOUT2/ PGAOUT3 0 VALUE GAIN (dB) VALUE GAIN (dB) 0x0 0 0x8 -15 0x1 -1 0x9 -17 0x2 -3 0xA -19 0x3 -5 0xB -21 0x4 -7 0xC -23 Mute 0x5 -9 0xD 0x6 -11 0xE Mute 0x7 -13 0xF Mute Receiver Amplifier The IC includes a single differential receiver amplifier. The receiver amplifier is designed to drive 32I receivers. In cases where a single transducer is used for the loudspeaker and receiver, use the SPKBYP switch to route the receiver amplifier output to the left speaker outputs. RECP/ RXINP RECVOL: +8dB TO -62dB MIX MIXREC DACL 0dB RECEN RECN/ RXINN RECBYP SPKBYP DALEN DACR DAREN PGAOUT1: 0dB TO -23dB PREOUT1 +9dB PGAOUT2: 0dB TO -23dB PREOUT2 +9dB Figure 25. Receiver Amplifier Block Diagram 87 MAX9888 Preoutput PGA The IC's preoutput PGAs allow line input signals to be attenuated to match DAC output signal levels. Use the 0dB setting for maximum performance. MAX9888 Stereo Audio CODEC with FLEXSOUND Technology Receiver Output Mixer The IC's receiver amplifier accepts input from the stereo DAC and the line inputs. Configure the mixer to mix any combination of the available sources. When more than one signal is selected, the mixed signal is attenuated by 6dB for 2 signals, 9.5dB for 3 signals, or 12dB for 4 signals. Table 21. Receiver Output Mixer Register REGISTER BIT NAME 3 0x28 2 1 MIXREC 0 DESCRIPTION Receiver Output Mixer 1xxx = Left DAC x1xx = Right DAC xx1x = Preoutput mixer 1 xxx1 = Preoutput mixer 2 Receiver Output Volume Table 22. Receiver Output Level Register REGISTER BIT 7 NAME RECM Receiver Output Volume Level 4 3 0x3A 2 RECVOL 1 0 88 DESCRIPTION Receiver Output Mute 0 = Disabled 1 = Enabled VALUE VOLUME (dB) VALUE VOLUME (dB) 0x00 -62 0x10 -10 0x01 -58 0x11 -8 0x02 -54 0x12 -6 0x03 -50 0x13 -4 0x04 -46 0x14 -2 0x05 -42 0x15 0 0x06 -38 0x16 +1 0x07 -35 0x17 +2 0x08 -32 0x18 +3 0x09 -29 0x19 +4 0x0A -26 0x1A +5 0x0B -23 0x1B +6 0x0C -20 0x1C +6.5 0x0D -17 0x1D +7 0x0E -14 0x1E +7.5 0x0F -12 0x1F +8 Stereo Audio CODEC with FLEXSOUND Technology Traditional Class D amplifiers require the use of external LC filters or shielding to meet EN55022B and FCC electromagnetic-interference (EMI) regulation standards. Maxim's patented active emissions limiting edge-rate control circuitry reduces EMI emissions (Figure 26). 40 40 30 30 AMPLITUDE (dBV/m) AMPLITUDE (dBV/m) The high efficiency of a Class D amplifier is due to the switching operation of the output stage transistors. In a Class D amplifier, the output transistors act as current steering switches and consume negligible additional power. Any power loss associated with the Class D output stage is mostly due to the I2R loss of the MOSFET on-resistance, and quiescent current overhead. 20 10 20 10 0 0 -10 -10 30 60 80 100 120 140 160 180 200 220 240 260 280 300 300 350 400 450 500 550 600 650 700 750 800 850 900 950 1000 FREQUENCY (MHz) FREQUENCY (MHz) Figure 26. EMI with 15cm of Speaker Cable BATTERY ADC SPVOLL: +8dB TO -62dB MIX MIXSPL DACL MIX DACR DAREN SPKLP +6dB SPKLN SPLEN POWER/DISTORTION LIMITER DALEN MIXSPR SPVOLR: +8dB TO -62dB SPKLVDD SPKLGND SPKRVDD SPKRP +6dB SPKRN SPREN SPKRPGND PGAOUT2: 0dB TO -23dB PREOUT2 +9dB PGAOUT3: 0dB TO -23dB PREOUT3 +9dB Figure 27. Speaker Amplifier Path Block Diagram 89 MAX9888 The theoretical best efficiency of a linear amplifier is 78%, however, that efficiency is only exhibited at peak output power. Under normal operating levels (typical music reproduction levels), efficiency falls below 30%, whereas the IC's Class D amplifier still exhibits 80% efficiency under the same conditions. Speaker Amplifiers The IC integrates a stereo filterless Class D amplifier that offers much higher efficiency than Class AB without the typical disadvantages. MAX9888 Stereo Audio CODEC with FLEXSOUND Technology Speaker Output Mixers The IC's speaker amplifiers accept input from the stereo DAC and the line inputs. Configure the mixer to mix any combination of the available sources. When more than one signal is selected, the mixed signal is attenuated by 6dB for 2 signals, 9.5dB for 3 signals, or 12dB for four signals. Table 23. Speaker Output Mixer Register REGISTER BIT NAME 7 6 5 0x29 MIXSPL Left Speaker Output Mixer 1xxx = Left DAC x1xx = Right DAC xx1x = Reserved xxx1 = Preoutput mixer 3 MIXSPR Right Speaker Output Mixer 1xxx = Left DAC x1xx = Right DAC xx1x = Reserved xxx1 = Preoutput mixer 2 4 3 2 1 DESCRIPTION 0 Speaker Output Volume Table 24. Speaker Output Mixer Register REGISTER BIT 7 NAME SPLM/SPRM DESCRIPTION Left/Right Speaker Output Mute 0 = Disabled 1 = Enabled Left/Right Speaker Output Volume Level 4 3 0x3B/0x3C 2 1 0 90 SPVOLL/SPVOLR VALUE VOLUME (dB) VALUE VOLUME (dB) 0x00 -64 0x10 -10 0x01 -59 0x11 -8 0x02 -55 0x12 -6 0x03 -50 0x13 -4 0x04 -46 0x14 -2 0x05 -42 0x15 0 0x06 -38 0x16 +1 0x07 -35 0x17 +2 0x08 -32 0x18 +3 0x09 -29 0x19 +4 0x0A -26 0x1A +5 0x0B -23 0x1B +6 0x0C -20 0x1C +6.5 0x0D -17 0x1D +7 0x0E -14 0x1E +7.5 0x0F -12 0x1F +8 Stereo Audio CODEC with FLEXSOUND Technology Excursion Limiter The excursion limiter is a dynamic highpass filter that monitors the speaker outputs and increases the highpass corner frequency when the speaker amplifier's output exceeds a predefined threshold. The filter smoothly transitions between the high and low corner frequency to prevent unwanted artifacts. The filter can operate in four different modes: U Fixed Frequency Preset Mode. The highpass corner frequency is fixed at the upper corner frequency and does not change with signal level. U Preset Dynamic Mode. The highpass filter automatically slides between a preset upper and lower corner frequency based on output signal level. U User Programmable Dynamic Mode. The highpass filter slides between a user-programmed biquad filter on the low side to a predefined corner frequency on the high side. The transfer function for the user-programmable biquad is: b + b1z -1 + b 2z -2 H(z) = 0 1 + a 1z -1 + a 2z -2 The coefficients b0, b1, b2, a1, and a2 are sample rate dependent and stored in registers 0xB4 through 0xC7. Store b0, b1, and b2 as positive numbers. Store a1 and a2 as negated two's complement numbers. Separate filters can be stored for the DAI1 and DAI2 playback paths. The MAX9888 EV kit software includes a graphic interface for generating the user-programmable biquad coefficients. Note: Only change the excursion limiter settings when the signal path is disabled to prevent undesired artifacts. U Fixed Frequency Programmable Mode. The highpass corner frequency is fixed to that specified by the programmable biquad filter. DV1G: 0/6/12/18dB + MULTIBAND ALC DVEQ1: 0dB TO -15dB 5-BAND PARAMETRIC EQ BATTERY ADC DVEQ2: 0dB TO -15dB SPVOLL: +8dB TO -62dB 5-BAND PARAMETRIC EQ EQ1EN MIX MIXSPL EQ2EN EXCURSION LIMITER DV2: 0dB TO -15dB DV1: 0dB TO -15dB MIX AUDIO/ FILTERS MIXDAL DACL SPKLP +6dB SPKLN SPLEN POWER/ DISTORTION LIMITER DALEN SPKLVDD SPKLGND SPKRVDD SPKRP DCB2 MIX AUDIO/ VOICE FILTERS MODE1 DVFLT MIX MIXDAR DACR MIXSPR SPVOLR: +8dB TO -62dB +6dB SPKRN SPREN SPKRPGND DAREN Figure 28. Speaker Amplifier Signal Processing Block Diagram 91 MAX9888 Speaker Amplifier Signal Processing The IC includes signal processing to improve the sound quality of the speaker output and protect transducers from damage. An excursion limiter dynamically adjusts the highpass corner frequency, while a power limiter and distortion limiter prevent the amplifier from outputting too much distortion or power. The excursion limiter is located in the DSP while the distortion limiter and power limiter control the analog volume control (Figure 28). All three limiters analyze the speaker amplifier's output signal to determine when to take action. MAX9888 Stereo Audio CODEC with FLEXSOUND Technology Table 25. Excursion Limiter Registers REGISTER BIT NAME Excursion Limiter Corner Frequency The excursion limiter has limited sliding range and minimum corner frequencies. Listed below are all the valid filter combinations. 6 5 DESCRIPTION DHPUCF LOWER CORNER FREQUENCY -- 000 00 400Hz -- 001 00 600Hz -- 010 00 800Hz -- 011 00 1kHz -- 100 00 Programmable using biquad 0x3F 1 DHPLCF 0 ALCRLS 4 3 2 0x40 DHPTH 1 0 92 100Hz 000 11 200Hz 400Hz -- 001 01 400Hz 600Hz -- 010 10 400Hz Programmable using biquad Programmable using biquad Programmable using biquad Programmable using biquad 800Hz -- 011 10 400Hz 200Hz 001 11 600Hz 300Hz 010 11 800Hz 400Hz 011 11 1kHz 500Hz 100 11 ALC and Excursion Limiter Release Time Sets the release time for both the ALC and Excursion Limiter. See the Automatic Level Control section for ALC release times. Excursion limiter release time is defined as the time required to slide from the high corner frequency to the low corner frequency. 6 5 MINIMUM BIQUAD DHPUCF DHPLCF CORNER FREQUENCY Excursion limiter disabled 4 0x41 UPPER CORNER FREQUENCY VALUE EXCURSION LIMITER RELEASE TIME (s) 000 4 001 2 010 1 011 0.5 100 0.25 101 0.25 110 Reserved 111 Reserved Excursion Limiter Threshold Measured at the Class D speaker amplifier outputs. Signals above the threshold use the upper corner frequency. Signals below the threshold use the lower corner frequency. VBAT must correctly reflect the voltage of SPKLVDD to achieve accurate thresholds. 000 = 0.34VP 001 = 0.71VP 010 = 1.30VP 011 = 1.77VP 100 = 2.33VP 101 = 3.25VP 110 = 4.25VP 111 = 4.95VP Stereo Audio CODEC with FLEXSOUND Technology Loudspeakers are typically damaged when the voice coil overheats due to extended operation above the rated power. During normal operation, heat generated in the voice coil is transferred to the speaker's magnet, which transfers heat to the surrounding air. For the voice coil to overheat, both the voice coil and the magnet must overheat. The result is that a loudspeaker can operate above its rated power for a significant time before it heats sufficiently to cause damage. The IC's power limiter includes user-programmable time constants and power thresholds to match a wide range of loudspeakers. Program the power limiter's threshold to match the loudspeaker's rated power handling. This can be determined through measurement or the loudspeaker's specification. Program time constant 1 to match the voice coil's thermal time constant. Program time constant 2 to match the magnet's thermal time constant. The time constants can be determined by plotting the voice coil's resistance vs. time as power is applied to the speaker. Table 26. Power Limiter Registers REGISTER BIT NAME DESCRIPTION Power Limiter Threshold If the RMS output power from the speaker amplifiers exceeds this threshold, the output is briefly muted to protect the speaker. The threshold is measured in watts assuming an 8I load. VBAT must correctly reflect the voltage of SPKLVDD/SPKRVDD to achieve accurate thresholds. 7 VALUE THRESHOLD (W) VALUE THRESHOLD (W) 0x0 Power limiter disabled 0x8 0.27 0x1 0.05 0x9 0.35 0x2 0.06 0xA 0.48 0x3 0.09 0xB 0.72 0x4 0.11 0xC 1.00 0x5 0.13 0xD 1.43 0x6 0.18 0xE 1.57 0x7 0.22 0xF 1.80 6 PWRTH 5 0x42 4 Power Limiter Weighting Factor Determines the balance between time constant 1 and 2 to match the dominance of each time constant in the loudspeaker. 2 1 PWRK 0 VALUE T1 (%) 000 50 50 001 62.5 37.5 010 75 25 011 87.5 12.5 100 100 0 101 12.5 87.5 110 25 75 37.5 62.5 111 REGISTER BIT NAME T2 (%) DESCRIPTION 93 MAX9888 Power Limiter The IC's power limiter tracks the RMS power delivered to the loudspeaker and briefly mutes the speaker amplifier output if the speaker is at risk of sustaining permanent damage. MAX9888 Stereo Audio CODEC with FLEXSOUND Technology Table 26. Power Limiter Registers (continued) Power Limiter Time Constant 2 Select a value that matches the thermal time constant of the loudspeaker's magnet. 7 6 PWRT2 5 4 0x43 2 PWRT1 0 TIME CONSTANT (min) VALUE TIME CONSTANT (min) 0x0 Disabled 0x8 3.75 0x1 0.50 0x9 5.00 0x2 0.67 0xA 6.66 0x3 0.89 0xB 8.88 0x4 1.19 0xC Reserved 0x5 1.58 0xD Reserved 0x6 2.11 0xE Reserved 0x7 2.81 0xF Reserved Power Limiter Time Constant 1 Select a value that matches the thermal time constant of the loudspeaker's voice coil. 3 1 VALUE VALUE TIME CONSTANT (s) VALUE TIME CONSTANT (s) 0x0 Disabled 0x8 3.75 0x1 0.50 0x9 5.00 0x2 0.67 0xA 6.66 0x3 0.89 0xB 8.88 0x4 1.19 0xC Reserved 0x5 1.58 0xD Reserved 0x6 2.11 0xE Reserved 0x7 2.81 0xF Reserved Distortion Limiter The IC's distortion limiter ensures that the speaker amplifier's output does not exceed the programmed THD+N limit. The distortion limiter analyzes the Class D output duty cycle to determine the percentage of the waveform that is clipped. If the distortion exceeds the programmed threshold, the output gain is reduced. 94 Stereo Audio CODEC with FLEXSOUND Technology REGISTER BIT NAME 7 6 5 THDCLP 4 0x44 2 1 0 DESCRIPTION Distortion Limit Measured in % THD+N. THDT1 VALUE THD+N LIMIT (%) VALUE THD+N LIMIT (%) 0x0 Limiter disabled 0x8 12 0x1 <1 0x9 14 0x2 1 0xA 16 0x3 2 0xB 18 0x4 4 0xC 20 0x5 6 0xD 21 0x6 8 0xE 22 0x7 10 0xF 24 Distortion Limiter Release Time Constant Duration of time required for the speaker amplifier's output gain to adjust back to the nominal level after a large signal has passed. 000 = 6.2s 001 = 3.1s 010 = 1.6s 011 = 815ms 100 = 419ms 101 = 223ms 110 = 116ms 111 = 76ms Headphone Amplifier The IC's headphone amplifier integrates Maxim's DirectDrive architecture to eliminate the need for large DC-blocking capacitors. Traditional single-supply headphone amplifiers have outputs biased at a nominal DC voltage (typically half the supply). Large coupling capacitors are needed to block this DC bias from the headphone. Without these capacitors, a significant amount of DC current flows to the headphone, resulting in unnecessary power dissipation and possible damage to both the headphone and headphone amplifier. The DirectDrive architecture uses a charge pump to create an internal negative supply voltage. This allows the IC's headphone outputs to be biased at GND while operating from a single supply (Figure 29). Without a DC component, there is no need for the large DC-blocking capacitors. Instead of two large (220FF, typ) capacitors, the IC charge pump requires two small ceramic capacitors, conserving board space, reducing cost, and improving the frequency response of the headphone amplifier. There is a low DC voltage on the amplifier outputs due to amplifier offset. However, the offset of the IC is typically Q0.2mV, which, when combined with a 32I load, results in less than 6FA of DC current flow to the headphones. In addition to the cost and size disadvantages of the DC-blocking capacitors required by conventional headphone amplifiers, these capacitors limit the amplifier's low-frequency response and can distort the audio signal. The DC-blocking capacitor not only blocks DC, but also low-frequency audio. Improving the low-frequency response of a conventional headphone amplifier requires increasing the capacitor size, further adding to the cost and size of the solution. Due to the voltage coefficient of the capacitors used for DC blocking, they introduce significant distortion near the corner frequency of the highpass filter they create. This distortion further degrades the low-frequency audio quality. 95 MAX9888 Table 27. Distortion Limiter Registers MAX9888 Stereo Audio CODEC with FLEXSOUND Technology Alternative approaches to eliminating the output-coupling capacitors involve biasing the headphone return (sleeve) to the DC bias voltage of the headphone amplifiers. This method raises some issues: U The sleeve is typically grounded to the chassis. Using the midrail biasing approach, the sleeve must be isolated from system ground, complicating product design. U During an ESD strike, the amplifier's ESD structures are the only path to system ground. Thus, the amplifier must be able to withstand the full energy from an ESD strike. U When using the headphone jack as a line out to other equipment, the bias voltage on the sleeve may conflict with the ground potential from other equipment, resulting in possible damage to the amplifiers. The IC features a low-noise charge pump to generate a negative supply for the headphone amplifier. The nominal switching frequency is well beyond the audio range, and thus does not interfere with audio signals. The switch drivers feature a controlled switching speed that minimizes noise generated by turn-on and turn-off transients. By limiting the switching speed of the charge pump, the di/dt noise caused by the parasitic trace inductance is minimized. The charge pump is active only in headphone modes. To reduce audible noise at the outputs, the IC's headphone amplifier includes headphone ground sensing. Connect the sense line (HPSNS) to the ground terminal of the device's headphone jack. Any noise present at the headphone ground is then added to the headphone output. The result is elimination of this noise from the audible output. If ground sensing is not required, connect HPSNS directly to ground. Figure 30 shows a block diagram of the headphone output section including the headphone sense function. Headphone Output Mixers The IC's headphone amplifier accepts input from the stereo DAC and the line inputs. The output of the left and right DAC cannot be mixed at the headphone mixer. Use MIXDAL/MIXDAR to mix the left and right audio channels before conversion. VDD VDD/2 DACL DALEN GND CONVENTIONAL AMPLIFIER BIASING SCHEME +VDD DACR HPVOLL: +3dB TO -67dB DAREN PGAOUT1: 0dB TO -23dB PREOUT1 HPL MIX HPLEN +9dB MIXHPL GND HPSNS MIX PREOUT2 DirectDrive AMPLIFIER BIASING SCHEME -VDD (VSS) Figure 29. Traditional Amplifier Output vs. DirectDrive Output 96 HPVOLR: +3dB TO -67dB HPR +9dB MIXHPR PGAOUT2: 0dB TO -23dB Figure 30. Headphone Amplifier Block Diagram HPREN Stereo Audio CODEC with FLEXSOUND Technology REGISTER BIT NAME 6 5 0x27 MIXHPL MIXHPR Right Headphone Output Mixer 10xx = Left DAC (requires DAREN = 0 for proper operation) 01xx = Right DAC 11xx = Right DAC xx1x = Reserved xxx1 = Preoutput mixer 2 4 3 2 1 DESCRIPTION Left Headphone Output Mixer 10xx = Left DAC 01xx = Right DAC (requires DALEN = 0 for proper operation) 11xx = Left DAC xx1x = Reserved xxx1 = Preoutput mixer 1 7 0 MAX9888 Table 28. Headphone Output Mixer Register Headphone Output Volume Table 29. Headphone Output Level Register REGISTER BIT 7 NAME HPLM/HPRM DESCRIPTION Headphone Output Mute 0 = Disabled 1 = Enabled Left/Right Headphone Output Volume Level 4 0x38/0x39 3 HPVOLL/HPVOLR 2 1 0 VALUE VOLUME (dB) VALUE VOLUME (dB) 0x00 -67 0x10 -15 0x01 -63 0x11 -13 0x02 -59 0x12 -11 0x03 -55 0x13 -9 0x04 -51 0x14 -7 0x05 -47 0x15 -5 0x06 -43 0x16 -4 0x07 -40 0x17 -3 0x08 -37 0x18 -2 -1 0x09 -34 0x19 0x0A -31 0x1A 0 0x0B -28 0x1B +1 0x0C -25 0x1C +1.5 0x0D -22 0x1D +2 0x0E -19 0x1E +2.5 0x0F -17 0x1F +3 97 MAX9888 Stereo Audio CODEC with FLEXSOUND Technology Output Bypass Switches an external receiver amplifier is used, route its output to the left speaker through RECP/RXINP and RECN/RXINN, bypassing the Class D amplifier. In systems where an external amplifier drives both the receiver and the IC's line input, one of the differential signals can be disconnected from the receiver when not needed by passing it through the analog switch that connects RECP/RXINP to RECN/RXINN. The IC includes two output bypass switches that solve common applications problems. When a single transducer is used for the loudspeaker and receiver, the need exists for two amplifiers to power the same transducer. Bypass switches connect the IC's receiver amplifier output to the speaker amplifier's output, allowing either amplifier to power the same transducer. In systems where RECP/RXINP 10I* 0dB RECN/RXINN RECEN 10I* EXTERNAL RECEIVER AMP RECP/RXINP EXTERNAL RECEIVER AMP RECN/RXINN 0dB RECN/RXINN RECEN RECBYP 0dB RECN/RXINN RECBYP RECEN SPKBYP +6dB SPKBYP SPKLVDD SPKLP SPKLN SPKLGND SPLEN RECBYP SPKBYP SPKLVDD SPKLP POWER/DISTORTION LIMITER +6dB SPKLN SPLEN SPKLGND POWER/DISTORTION LIMITER *OPTIONAL 10I RESISTORS IMPROVE DISTORTION THROUGH THE ANALOG SWITCH. SPEAKER AMPLIFIER BYPASS USING AN EXTERNAL RECEIVER AMPLIFIER SPEAKER AMPLIFIER BYPASS USING THE INTERNAL RECEIVER AMPLIFIER SPKLVDD SPKLP +6dB SPKLN SPLEN SPKLGND POWER/DISTORTION LIMITER CONTROLLING AN EXTERNAL RECEIVE AMPLIFIER AND SPEAKER Figure 31. Output Bypass Switch Block Diagrams Table 30. Output Bypass Switches Register REGISTER BIT NAME 7 INABYP 4 MIC2BYP 1 98 See the Microphone Inputs section. RECBYP RXINP to RXINN Bypass Switch Shorts RXINP to RXINN allowing a signal to pass through the MAX9888. Disable the receiver amplifier when RECBYP = 1. 0 = Disabled 1 = Enabled SPKBYP RXIN to SPKL Bypass Switch Shorts RXINP/RXINN to SPKLP/SPKLN allowing either the internal or an external receiver amplifier to power the left speaker. Disable the left speaker amplifier when SPKBYP = 1. 0 = Disabled 1 = Enabled 0x48 0 DESCRIPTION Stereo Audio CODEC with FLEXSOUND Technology Zero-crossing detection is implemented on all analog PGAs and volume controls to prevent large glitches when volume changes are made. Instead of making a volume change immediately, the change is made when the audio signal crosses the midpoint. If no zero-crossing occurs within the timeout window, the change is forced. Volume slewing breaks up large volume changes into the smallest available step size and the steps through each step between the initial and final volume setting. When enabled, volume slewing also occurs at device turn-on and turn-off. During turn-on the volume is set to mute before the output is enabled. Once the output is on, the volume ramps to the desired level. At turn-off the volume is ramped to mute before the outputs are disabled. When there is no audio signal zero-crossing detection can prevent volume slewing from occurring. Enable enhanced volume slewing to prevent the volume controller from requesting another volume level until the previous one has been set. Each step in the volume ramp then occurs after a zero crossing has occurred in the audio signal or the timeout window has expired. During turn-off, enhance volume slewing is always disabled. Table 31. Click-and-Pop Reduction Register REGISTER BIT 7 6 NAME VS2EN VSEN Volume Adjustment Smoothing Volume changes are smoothed by stepping through intermediate steps. Also ramps the volume from minimum to the programmed value at turn-on and back to minimum at turn-off. 0 = Enabled 1 = Disabled Applies to volume changes in HPVOLL, HPVOLR, RECVOL, SPVOLL, and SPVOLR. ZDEN Zero-Crossing Detection Holds volume changes until there is a zero crossing in the audio signal. This reduces click and pop during volume changes (zipper noise). If no zero crossing is detected within 100ms, the volume change is forced. 0 = Enabled 1 = Disabled Applies to volume changes in PGAM1, PGAM2, PGAOUTA, PGAOUTB, PGAOUTC, HPVOLL, HPVOLR, RECVOL, SPVOLL, and SPVOLR. 0x49 5 DESCRIPTION Enhanced Volume Smoothing During volume slewing, the controller waits for each step in the ramp to be applied before sending the next step. When zero-crossing detection is enabled this prevents large steps in the output volume when no zero crossings are detected. 0 = Enabled 1 = Disabled Applies to volume changes in HPVOLL, HPVOLR, RECVOL, SPVOLL, and SPVOLR. 1 EQ2EN 0 EQ1EN See the 5-Band Parametric EQ section. 99 MAX9888 Click-and-Pop Reduction The IC includes extensive click-and-pop reduction circuitry. The circuitry minimizes clicks and pops at turn-on, turn-off, and during volume changes. MAX9888 Stereo Audio CODEC with FLEXSOUND Technology Jack Detection The IC features jack detection that can detect the insertion and removal of a jack as well as the load type. When a jack is detected, an interrupt on IRQ can be triggered to alert the microcontroller of the event. Figure 32 shows the typical configuration for jack detection. Jack Insertion To detect a jack insertion, the IC must have a power supply and MICBIAS should be disabled. Set JDETEN to enable jack detection circuitry and apply a pullup current to JACKSNS. Set JDWK to minimize supply current. Clear JDWK to differentiate between headsets with a microphone and headphones without a microphone. The voltage on JACKSNS is equal to SPKLVDD as long as no load is applied to JACKSNS. Table 32 shows the change in JKSNS that occurs when a jack is inserted. Accessory Button Detection After jack insertion, the MAX9888 can detect button presses on accessories that include a microphone and a switch that shorts the microphone signal to ground. Set JDETEN to enable jack detection circuitry. A pullup current is automatically applied to JACKSNS if MICBIAS is disabled. Clear JDWK to allow differentiation between the microphone load and a short to ground. Button presses can be detected both when MICBIAS is enabled and disabled. Table 33 shows the change in JKSNS that occurs when the accessory button is pressed. HPL MICBIAS JACKSNS HPR MIC1P Figure 32. Typical Configuration for Jack Detection Table 32. Change in JKSNS Upon Jack Insertion JACK TYPE JDWK = 1 JDWK = 0 GND GND R L JKSNS: 11 e 00 JKSNS: 11 e 00 MIC GND R L JKSNS: 11 e 00 JKSNS: 11 e 01 Table 33. Change in JKSNS Upon Button Press JACK TYPE MIC 100 GND MICBIAS ENABLED OR DISABLED R L JKSNS: 01 e 00 Stereo Audio CODEC with FLEXSOUND Technology applied to JACKSNS if MICBIAS is disabled. Set JDWK to minimize supply current if button detection is not required. Table 34 shows the change in JKSNS that occurs when a jack is removed. Table 34. Change in JKSNS Upon Jack Removal JACK TYPE JDWK = 1 AND MICBIAS DISABLED JDWK = 0 OR MICBIAS ENABLED GND GND R L JKSNS: 00 e 11 JKSNS: 00 e 11 MIC GND R L JKSNS: 00 e 11 JKSNS: 01 e 11 Table 35. Jack Detection Registers REGISTER BIT NAME DESCRIPTION JACKSNS State Reports the status of JACKSNS when JDETEN = 1. VALUE 7 00 0x02 (Read Only) JKSNS 01 10 6 11 7 0x49 JDETEN 1 JDEB 0 7 6 SHDN VBATEN 0x4C 1 JDWK MODE MBEN = 1 DESCRIPTION VJACKSNS < 0.1 x VMICBIAS MBEN = 0 VJACKSNS < 0.1 x VSPKLVDD MBEN = 1 0.1 x VMICBIAS < VJACKSNS < 0.95 x VMICBIAS MBEN = 0 0.1 x VSPKLVDD < VJACKSNS < 0.95 x VSPKLVDD MBEN = 1 Reserved MBEN = 0 Reserved MBEN = 1 0.95 x VMICBIAS < VJACKSNS MBEN = 0 0.95 x VSPKLVDD < VJACKSNS Jack Detection Enable 0 = Disabled 1 = Enabled Jack Detection Debounce Configures the debounce time for setting JDET. 00 = 25ms 01 = 50ms 10 = 100ms 11 = 200ms See the Power Management section. See the Battery Measurement section. JACKSNS Pullup When JDWK = 1 JACKSNS is slow to increase in voltage. Set JDWK = 0 before setting JDETEN = 1 to prevent false detection. Valid when MBIAS = 0 or SHDN = 0. 0 = 2.4kI to SPKLVDD (allows microphone detection) 1 = 5FA to SPKLVDD (minimizes supply current) 101 MAX9888 Jack Removal The IC detects jack removal by monitoring JACKSNS for transitions to the 11 state. Set JDETEN to enable jack detection circuitry. A pullup current is automatically MAX9888 Stereo Audio CODEC with FLEXSOUND Technology Battery Measurement The IC measures the voltage applied to SPKLVDD (typically the battery voltage) and reports the value in register 0x03. This value is also used by the speaker limiter circuitry to set accurate thresholds. When the battery measurement function is disabled, the battery voltage is user programmable. Table 36. Battery Measurement Registers REGISTER BIT NAME 4 3 0x03 2 VBAT 1 0 0x4C 102 7 SHDN 6 VBATEN 1 JDWK DESCRIPTION Battery Voltage Read VBAT when VBATEN = 1 to determine VSPKLVDD. Program VBAT when VBATEN = 0 to allow proper speaker amplifier signal processing. Calculate the battery voltage using the following formula: VBATTERY = 2.55V + [VBAT/10] See the Power Management section. Battery Measurement Enable Enables an internal ADC to measure VSPKLVDD. 0 = Disabled (register 0x03 readable and writeable) 1 = Enabled (register 0x03 read only) See the Headset Detection section. Stereo Audio CODEC with FLEXSOUND Technology either by poling register 0x00 or configuring the IRQ to pull low when specific events occur. IRQ is an opendrain output that requires a pullup resistor for proper operation. Register 0x0F determines which bits in the status register trigger IRQ to pull low. Table 37. Status and Interrupt Registers REGISTER BIT NAME DESCRIPTION CLD Full Scale 0 = All digital signals are less than full scale. 1 = The DAC or ADC signal path has reached or exceeded full scale. This typically indicates clipping. 6 SLD Volume Slew Complete SLD reports that any of the programmable-gain arrays or volume controllers has completed slewing from a previous setting to a new programmed setting. If multiple gain arrays or volume controllers are changed at the same time, the SLD flag is set after the last volume slew completes. SLD also reports when the digital audio interface soft-start or soft-stop process has completed. MCLK is required for proper SLD operation. 0 = No volume slewing sequences have completed since the status register was last read. 1 = Volume slewing complete. 5 ULK Digital Audio Interface Unlocked 0 = Both digital audio interfaces are operating normally. 1 = Either digital audio interface is configured incorrectly or receiving invalid data. 1 JDET Jack Configuration Change JDET reports changes to any bit in the Jack Status register (0x02). Changes to the Jack Status bits are debounced before setting JDET. The debounce period is programmable using the JDEB bits. JDET is always set the first time JDETEN or SHDN is set the first time power is applied to the IC. Read the status register following such an event to clear JDET and allow for proper jack detection. 0 = No change in jack configuration. 1 = Jack configuration has changed. 7 ICLD 6 ISLD 5 IULK 1 IJDET 7 0x00 (Read Only) 0x0F Full-Scale Interrupt Enable 0 = Disabled 1 = Enabled Volume Slew Complete Interrupt Enable 0 = Disabled 1 = Enabled Digital Audio Interface Unlocked Interrupt Enable 0 = Disabled 1 = Enabled Jack Configuration Change Interrupt Enable 0 = Disabled 1 = Enabled 103 MAX9888 Device Status The IC uses register 0x00 and IRQ to report the status of various device functions. The status register bits are set when their respective events occur, and cleared upon reading the register. Device status can be determined MAX9888 Stereo Audio CODEC with FLEXSOUND Technology Device Revision Table 38. Device Revision Register REGISTER BIT NAME DESCRIPTION 7 6 5 0xFF (Read Only) 4 3 Device Revision Code REV is always set to 0x43. REV 2 1 0 I2C Serial Interface The IC features an I2C/SMBusK-compatible, 2-wire serial interface comprising a serial-data line (SDA) and a serial-clock line (SCL). SDA and SCL facilitate communication between the IC and the master at clock rates up to 400kHz. Figure 5 shows the 2-wire interface timing diagram. The master generates SCL and initiates data transfer on the bus. The master device writes data to the IC by transmitting the proper slave address followed by the register address and then the data word. Each transmit sequence is framed by a START (S) or REPEATED START (Sr) condition and a STOP (P) condition. Each word transmitted to the IC is 8 bits long and is followed by an acknowledge clock pulse. A master reading data from the IC transmits the proper slave address followed by a series of nine SCL pulses. The IC transmits data on SDA in sync with the master-generated SCL pulses. The master acknowledges receipt of each byte of data. Each read sequence is framed by a START or REPEATED START condition, a not acknowledge, and a STOP condition. SDA operates as both an input and an open-drain output. A pullup resistor, typically greater than 500I, is required on SDA. SCL operates only as an input. A pullup resistor, typically greater than 500I, is required on SCL if there are multiple masters on the bus, or if the single master has an open-drain SCL output. Series resistors in line with SDA and SCL are optional. Series S SCL SDA Figure 33. START, STOP, and REPEATED START Conditions SMBus is a trademark of Intel Corp. 104 resistors protect the digital inputs of the IC from high voltage spikes on the bus lines, and minimize crosstalk and undershoot of the bus signals. Bit Transfer One data bit is transferred during each SCL cycle. The data on SDA must remain stable during the high period of the SCL pulse. Changes in SDA while SCL is high are control signals (see the START and STOP Conditions section). START and STOP Conditions SDA and SCL idle high when the bus is not in use. A master initiates communication by issuing a START condition. A START condition is a high-to-low transition on SDA with SCL high. A STOP condition is a low-tohigh transition on SDA while SCL is high (Figure 33). A START condition from the master signals the beginning of a transmission to the IC. The master terminates transmission, and frees the bus, by issuing a STOP condition. The bus remains active if a REPEATED START condition is generated instead of a STOP condition. Early STOP Conditions The IC recognizes a STOP condition at any point during data transmission except if the STOP condition occurs in the same high pulse as a START condition. For proper operation, do not send a STOP condition during the same SCL high pulse as the START condition. Sr P Stereo Audio CODEC with FLEXSOUND Technology is busy or if a system fault has occurred. In the event of an unsuccessful data transfer, the bus master retries communication. The master pulls down SDA during the 9th clock cycle to acknowledge receipt of data when the IC is in read mode. An acknowledge is sent by the master after each read byte to allow data transfer to continue. A not acknowledge is sent when the master reads the final byte of data from the IC, followed by a STOP condition. Acknowledge The acknowledge bit (ACK) is a clocked 9th bit that the IC uses to handshake receipt each byte of data when in write mode (Figure 34). The IC pulls down SDA during the entire master-generated 9th clock pulse if the previous byte is successfully received. Monitoring ACK allows for detection of unsuccessful data transfers. An unsuccessful data transfer occurs if a receiving device Write Data Format A write to the IC includes transmission of a START condition, the slave address with the R/W bit set to 0, one byte of data to configure the internal register address pointer, one or more bytes of data, and a STOP condition. Figure 35 illustrates the proper frame format for writing one byte of data to the IC. Figure 35 illustrates the frame format for writing n-bytes of data to the IC. CLOCK PULSE FOR ACKNOWLEDGMENT START CONDITION SCL 2 1 8 9 NOT ACKNOWLEDGE SDA ACKNOWLEDGE Figure 34. Acknowledge ACKNOWLEDGE FROM MAX9888 B7 SLAVE ADDRESS S B6 B5 B4 B3 B2 B1 B0 ACKNOWLEDGE FROM MAX9888 ACKNOWLEDGE FROM MAX9888 A O A REGISTER ADDRESS DATA BYTE A P 1 BYTE R/W AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER Figure 35. Writing One Byte of Data to the IC ACKNOWLEDGE FROM MAX9888 ACKNOWLEDGE FROM MAX9888 ACKNOWLEDGE FROM MAX9888 S SLAVE ADDRESS O A REGISTER ADDRESS R/W ACKNOWLEDGE FROM MAX9888 B7 B6 B5 B4 B3 B2 B1 B0 A DATA BYTE 1 1 BYTE B7 B6 B5 B4 B3 B2 B1 B0 A DATA BYTE n A P 1 BYTE AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER Figure 36. Writing n-Bytes of Data to the IC 105 MAX9888 Slave Address The slave address is defined as the seven most significant bits (MSBs) followed by the read/write bit. For the IC, the seven most significant bits are 0010000. Setting the read/write bit to 1 (slave address = 0x21) configures the IC for read mode. Setting the read/write bit to 0 (slave address = 0x20) configures the IC for write mode. The address is the first byte of information sent to the IC after the START condition. MAX9888 Stereo Audio CODEC with FLEXSOUND Technology The slave address with the R/W bit set to 0 indicates that the master intends to write data to the IC. The IC acknowledges receipt of the address byte during the master-generated 9th SCL pulse. The first byte transmitted from the IC is the content of register 0x00. Transmitted data is valid on the rising edge of SCL. The address pointer autoincrements after each read data byte. This autoincrement feature allows all registers to be read sequentially within one continuous frame. A STOP condition can be issued after any number of read data bytes. If a STOP condition is issued followed by another read operation, the first data byte to be read is from register 0x00. The second byte transmitted from the master configures the IC's internal register address pointer. The pointer tells the IC where to write the next byte of data. An acknowledge pulse is sent by the IC upon receipt of the address pointer data. The address pointer can be preset to a specific register before a read command is issued. The master presets the address pointer by first sending the IC's slave address with the R/W bit set to 0 followed by the register address. A REPEATED START condition is then sent followed by the slave address with the R/W bit set to 1. The IC then transmits the contents of the specified register. The address pointer autoincrements after transmitting the first byte. The third byte sent to the IC contains the data that is written to the chosen register. An acknowledge pulse from the IC signals receipt of the data byte. The address pointer autoincrements to the next register address after each received data byte. This autoincrement feature allows a master to write to sequential registers within one continuous frame. The master signals the end of transmission by issuing a STOP condition. Register addresses greater than 0xC7 are reserved. Do not write to these addresses. The master acknowledges receipt of each read byte during the acknowledge clock pulse. The master must acknowledge all correctly received bytes except the last byte. The final byte must be followed by a not acknowledge from the master and then a STOP condition. Figure 37 illustrates the frame format for reading one byte from the IC. Figure 38 illustrates the frame format for reading multiple bytes from the IC. Read Data Format Send the slave address with the R/W bit set to 1 to initiate a read operation. The IC acknowledges receipt of its slave address by pulling SDA low during the 9th SCL clock pulse. A START command followed by a read command resets the address pointer to register 0x00. ACKNOWLEDGE FROM MAX9888 S O SLAVE ADDRESS ACKNOWLEDGE FROM MAX9888 A REGISTER ADDRESS ACKNOWLEDGE FROM MAX9888 A Sr A R/W REPEATED START R/W 1 SLAVE ADDRESS NOT ACKNOWLEDGE FROM MASTER DATA BYTE A P 1 BYTE AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER Figure 37. Reading One Byte of Data from the IC ACKNOWLEDGE FROM MAX9888 S SLAVE ADDRESS O ACKNOWLEDGE FROM MAX9888 A REGISTER ADDRESS R/W ACKNOWLEDGE FROM MAX9888 A REPEATED START Sr SLAVE ADDRESS 1 R/W A DATA BYTE A 1 BYTE AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER Figure 38. Reading n Bytes of Data from the IC 106 Stereo Audio CODEC with FLEXSOUND Technology required for the IC to operate. Additional components may be required by the application. Typical Operating Circuits Figures 39 and 40 provide example operating circuits for the IC. The external components shown are the minimum Analog Microphones and Bypass Switch 2.8V TO 5.5V 1.8V 10FF 1.8V TO 3.6V 1FF 1.8V TO 5.5V DVDDS1 DVDD 1FF 1FF HPVDD AVDD 1.8V TO 3.6V 1FF 1FF SPKLVDD 1FF SPKRVDD 1FF DVDDS2 10kI TO MICROCONTROLLER BCLKS2 IRQ BCLKS1 DIGITAL AUDIO PORT 1 I2C CONTROL PORT JACKSNS 1kI 2.2kI SDINS2 LRCLKS1 SDOUTS2 SDINS1 JACKSNS SDOUTS1 RECP/RXINP SDA RECN/RXINN SCL MICROPHONE OUTPUT TO BASEBAND MAX9888 MIC1N/DIGMICCLK 8I SPKRP 8I SPKRN MICBIAS 1FF HPR HPL MIC2N HPSNS 1FF INA1/EXTMICP REF 1FF INA2/EXTMICN PREG 1FF INB1 1kI LINE INPUT BYPASS SWITCH INPUT SPKLN 1FF HANDSET MICROPHONE JACKSNS SPKLP MIC1P/DIGMICDATA MIC2P HEADSET MICROPHONE DIGITAL AUDIO PORT 2 LRCLKS2 MCLK 10MHz TO 60MHz CLOCK INPUT REG 1FF INB2 1FF DGND 1FF AGND HPGND SPKRGND SPKLGND HPVSS C1N 1FF 2.2FF C1P 1FF 1FF Figure 39. Typical Application Circuit Using Analog Microphone Inputs and the Bypass Switch 107 MAX9888 Applications Information Stereo Audio CODEC with FLEXSOUND Technology MAX9888 Digital Microphones and Receiver Amplifier 2.8V TO 5.5V 1.8V 10FF 1.8V TO 3.6V 1FF 1.8V TO 5.5V DVDDS1 DVDD 1FF 1FF HPVDD 1.8V TO 3.6V 1FF AVDD 1FF SPKLVDD 1FF SPKRVDD 1FF DVDDS2 10kI TO MICROCONTROLLER BCLKS2 IRQ 10MHz TO 60MHz CLOCK INPUT LRCLKS2 MCLK BCLKS1 DIGITAL AUDIO PORT 1 I2C CONTROL DATA DIGITAL MIC 1 DIGITAL MIC 2 PORT SDINS2 LRCLKS1 SDOUTS2 SDINS1 JACKSNS SDOUTS1 RECP/RXINP SDA RECN/RXINN SCL DATA SPKRP 8I SPKRN MICBIAS 1FF HPR MIC2P HEADSET MICROPHONE 8I MAX9888 CLOCK 2.2kI 32I SPKLN MIC1N/ DIGMICCLK JACKSNS JACKSNS SPKLP MIC1P/DIGMICDATA CLOCK DIGITAL AUDIO PORT 2 HPL 1FF MIC2N HPSNS 1FF LINE INPUT INA1/EXTMICP REF INA2/EXTMICN PREG 1FF 1FF INB1 LINE INPUT REG 1FF 1FF INB2 1FF DGND AGND HPGND SPKRGND SPKLGND HPVSS C1N C1P 1FF 1FF Figure 40. Typical Application Circuit Using the Digital Microphone Input and Receiver Amplifier 108 1FF 2.2FF Stereo Audio CODEC with FLEXSOUND Technology The IC does not require an output filter. The device relies on the inherent inductance of the speaker coil and the natural filtering of both the speaker and the human ear to recover the audio component of the square-wave output. Eliminating the output filter results in a smaller, less costly, more efficient solution. Because the frequency of the IC output is well beyond the bandwidth of most speakers, voice coil movement due to the square-wave frequency is very small. Although this movement is small, a speaker not designed to handle the additional power can be damaged. For optimum results, use a speaker with a series inductance > 10FH. Typical 8I speakers exhibit series inductances in the 20FH to 100FH range. RF Susceptibility GSM radios transmit using time-division multiple access (TDMA) with 217Hz intervals. The result is an RF signal with strong amplitude modulation at 217Hz and its harmonics that is easily demodulated by audio amplifiers. The IC is designed specifically to reject RF signals; however, PCB layout has a large impact on the susceptibility of the end product. In RF applications, improvements to both layout and component selection decrease the IC's susceptibility to RF noise and prevent RF signals from being demodulated into audible noise. Trace lengths should be kept below 1/4 of the wavelength of the RF frequency of interest. Minimizing the trace lengths prevents them from functioning as antennas and coupling RF signals into the IC. The wavelength (l) in meters is given by: l = c/f where c = 3 x 108 m/s, and f = the RF frequency of interest. Route audio signals on middle layers of the PCB to allow ground planes above and below to shield them from RF interference. Ideally, the top and bottom layers of the PCB should primarily be ground planes to create effective shielding. Additional RF immunity can also be obtained by relying on the self-resonant frequency of capacitors as it exhibits a frequency response similar to a notch filter. Depending on the manufacturer, 10pF to 20pF capacitors typically exhibit self resonance at the RF frequencies of interest. These capacitors, when placed at the input pins, can effectively shunt the RF noise to ground. For these capacitors to be effective, they must have a lowimpedance, low-inductance path to the ground plane. Avoid using microvias to connect to the ground plane whenever possible as these vias do not conduct well at RF frequencies. Startup/Shutdown Sequencing To ensure proper device initialization and minimal clickand-pop, program the IC's SHDN = 1 after configuring all registers. Table 39 lists an example startup sequence for the device. To shut down the IC, simply set SHDN = 0. Table 39. Example Startup Sequence SEQUENCE 1 DESCRIPTION Ensure SHDN = 0 REGISTERS 0x4C 2 Configure clocks 0x10 to 0x13, 0x19 to 0x1B 3 Configure digital audio interface 0x14 to 0x17, 0x1C to 0x1F 4 Configure digital signal processing 0x18, 0x20, 0x3D to 0x44 5 Load coefficients 0x50 to 0xC7 6 Configure mixers 0x21 to 0x29 7 Configure gain and volume controls 0x2A to 0x3C 8 Configure miscellaneous functions 0x45 to 0x49 9 Enable desired functions 0x4A, 0x4B 10 Set SHDN = 1 0x4C 109 MAX9888 Filterless Class D Operation Traditional Class D amplifiers require an output filter to recover the audio signal from the amplifier's output. The filters add cost, increase the solution size of the amplifier, and can decrease efficiency and THD+N performance. The traditional PWM scheme uses large differential output swings (2 x VDD peak to peak) and causes large ripple currents. Any parasitic resistance in the filter components results in a loss of power, lowering the efficiency. MAX9888 Stereo Audio CODEC with FLEXSOUND Technology While many configuration options in the IC can be made while the device is operating, some registers should only be adjusted when the corresponding audio path is disabled. Table 40 lists the registers that are sensitive during operation. Either disable the corresponding audio path or set SHDN = 0 while changing these registers. Component Selection Optional Ferrite Bead Filter In applications where speaker leads exceed 20mm, additional EMI suppression can be achieved by using a filter constructed from a ferrite bead and a capacitor to ground (Figure 41). Use a ferrite bead with low DC resistance, high-frequency (> 600MHz) impedance between 100I and 600I, and rated for at least 1A. The capacitor value varies based on the ferrite bead chosen and the actual speaker lead length. Select a capacitor less than 1nF based on EMI performance. Input Capacitor An input capacitor, CIN, in conjunction with the input impedance of the IC line inputs forms a highpass filter that removes the DC bias from an incoming analog signal. The AC coupling capacitor allows the amplifier to automatically bias the signal to an optimum DC level. Assuming zero-source impedance, the -3dB point of the highpass filter is given by: 1 f-3dB = 2RINCIN Choose CIN so that f-3dB is well below the lowest frequency of interest. For best audio quality use capacitors whose dielectrics have low-voltage coefficients, such as tantalum or aluminum electrolytic. Capacitors with highvoltage coefficients, such as ceramics, may result in increased distortion at low frequencies. Charge-Pump Capacitor Selection Use capacitors with an ESR less than 100mI for optimum performance. Low-ESR ceramic capacitors minimize the output resistance of the charge pump. Most surfacemount ceramic capacitors satisfy the ESR requirement. For best performance over the extended temperature range, select capacitors with an X7R dielectric. Table 40. Registers That Are Sensitive to Changes During Operation REGISTER DESCRIPTION 0x10 to 0x13, 0x19 to 0x1B Clock Control Registers 0x14 to 0x17, 0x1C to 0x1F Digital Audio Interface Configuration 0x18, 0x20 Digital Passband Filters 0x24 to 0x29 Analog Mixers 0x50 to 0xC7 Digital Signal Processing Coefficients SPK_P MAX9888 Figure 41. Optional Class D Ferrite Bead Filter 110 SPK_N Stereo Audio CODEC with FLEXSOUND Technology Charge-Pump Holding Capacitor The holding capacitor (bypassing HPVSS) value and ESR directly affect the ripple at HPVSS. Increasing the capacitor's value reduces output ripple. Likewise, decreasing the ESR reduces both ripple and output resistance. Lower capacitance values can be used in systems with low maximum output power levels. See the Output Power vs. Load Resistance graph in the Typical Operating Characteristics section for more information Unused Pins Table 41 shows how to connect the IC's pins when unused. Table 41. Unused Pins NAME CONNECTION NAME CONNECTION SPKRP Unconnected INB1 Unconnected SPKRVDD Always connected INA2/MICEXTN Unconnected SPKLVDD Always connect LRCLKS2 Unconnected SPKLP Unconnected MCLK Always connect RECN/RXINN Unconnected SDINS2 AGND HPVDD Always connect Unconnected C1P Unconnected IRQ MIC1P/DIGMICDATA HPGND AGND INA1/MICEXTP Unconnected SPKRN Unconnected DGND Always connect SPKRGND Always connect BCLKS2 Unconnected SPKLGND Always connect SDA Always connect Unconnected SPKLN Unconnected SCL Always connect RECP/RXINP Unconnected REG Always connect C1N Unconnected REF Always connect HPL Unconnected MIC1N/DIGMICCLK Unconnected HPVSS Unconnected MIC2P Unconnected SDINS1 AGND SDOUTS2 Unconnected LRCLKS1 Unconnected DVDDS2 DVDD HPSNS AGND DVDD Always connect INB2 Unconnected AVDD Always connect HPR Unconnected PREG Always connect DVDDS1 DVDD AGND Always connect SDOUTS1 Unconnected MICBIAS Unconnected BCLKS1 Unconnected MIC2N Unconnected JACKSNS Unconnected 111 MAX9888 Charge-Pump Flying Capacitor The value of the flying capacitor (connected between C1N and C1P) affects the output resistance of the charge pump. A value that is too small degrades the device's ability to provide sufficient current drive, which leads to a loss of output voltage. Increasing the value of the flying capacitor reduces the charge-pump output resistance to an extent. Above 1FF, the on-resistance of the internal switches and the ESR of external chargepump capacitors dominate. MAX9888 Stereo Audio CODEC with FLEXSOUND Technology Recommended PCB Routing The IC uses a 63-bump WLP package. Figure 42 provides an example of how to connect to all active bumps using 3 layers of the PCB. To ensure uninterrupted ground returns, use layer 2 as a connecting layer between layer 1 and layer 2 and flood the remaining area with ground. Supply Bypassing, Layout, and Grounding Proper layout and grounding are essential for optimum performance. When designing a PCB for the IC, partition the circuitry so that the analog sections of the IC are separated from the digital sections. This ensures that the analog audio traces are not routed near digital traces. Use a large continuous ground plane on a dedicated layer of the PCB to minimize loop areas. Connect AGND, DGND, HPGND, SPKLGND, and SPKRGND directly to the ground plane using the shortest trace length possible. Proper grounding improves audio performance, minimizes crosstalk between channels, and prevents any digital noise from coupling into the analog audio signals. Ground the bypass capacitors on MICBIAS, REG, PREG, and REF directly to the ground plane with minimum trace length. Also be sure to minimize the path length to AGND. Bypass AVDD directly to AGND. LAYER 1 Connect all digital I/O termination to the ground plane with minimum path length to DGND. Bypass DVDD, DVDDS1, and DVDDS2 directly to DGND. Place the capacitor between C1P and C1N as close as possible to the IC to minimize trace length from C1P to C1N. Inductance and resistance added between C1P and C1N reduce the output power of the headphone amplifier. Bypass HPVSS with a capacitor located close to HPVSS with a short trace length to HPGND. Close decoupling of HPVSS minimizes supply ripple and maximizes output power from the headphone amplifier. LAYER 2 LAYER 3 Figure 42. Suggested Routing 112 HPSNS senses ground noise on the headphone jack and adds the same noise to the output audio signal, thereby making the output (headphone output minus ground) noise free. Connect HPSNS to the headphone jack shield to ensure accurate pickup of headphone ground noise. Bypass SPKLVDD and SPKRVDD to SPKLGND and SPKRGND, respectively, with as little trace length as possible. Connect SPKLP, SPKLN, SPKRP, and SPKRN to the stereo speakers using the shortest traces possible. Reducing trace length minimizes radiated EMI. Route SPKLP/SPKLN and SPKRP/SPKRN as differential pairs on the PCB to minimize loop area, thereby the inductance of the circuit. If filter components are used on the speaker outputs, be sure to locate them as close as possible to the IC to ensure maximum effectiveness. Minimize the trace length from any ground-connected passive components to SPKLGND and SPKRGND to further minimize radiated EMI. Stereo Audio CODEC with FLEXSOUND Technology MAX9888 Route microphone signals from the microphone to the IC as a differential pair, ensuring that the positive and negative signals follow the same path as closely as possible with equal trace length. When using single-ended microphones or other single-ended audio sources, ground the negative microphone input as close as possible to the audio source and then treat the positive and negative traces as differential pairs. 0.24mm An evaluation kit (EV kit) is available to provide an example layout for the IC. The EV kit allows quick setup of the IC and includes easy-to-use software allowing all internal registers to be controlled. WLP Applications Information For the latest application details on WLP construction, dimensions, tape carrier information, PCB techniques, bump-pad layout, and recommended reflow temperature profile, as well as the latest information on reliability testing results, refer to the Application Note 1891: WaferLevel Packaging (WLP) and Its Applications. Figure 43 shows the dimensions of the WLP balls used on the IC. 0.21mm Figure 43. WLP Ball Dimensions 113 MAX9888 Stereo Audio CODEC with FLEXSOUND Technology Package Information For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a "+", "#", or "-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. 114 PACKAGE TYPE PACKAGE CODE OUTLINE No. LAND PATTERN NO. 63 WLP W633A3+1 21-0462 -- Stereo Audio CODEC with FLEXSOUND Technology REVISION NUMBER REVISION DATE 0 6/10 DESCRIPTION Initial release PAGES CHANGED -- Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2010 Maxim Integrated Products 115 Maxim is a registered trademark of Maxim Integrated Products, Inc. MAX9888 Revision History