ANALOG Microprocessor-Compatible DEVICES 12-Bit D/A Converter AD667 1.1 Scope. This specification covers the detail requirements for a complete 12-bit digital-to-analog converter with microprocessor interface, buried Zener reference and output amplifier. 1.2 Part Number. The complete part number per Table 1 of this specification is as follows: Device Part Number! -1 AD667S(X)/883B NOTE See paragraph 1.2.3 for package identifier. 1.2.3 Case Outline. See Appendix ! of General Specification ADI-M-1000: package outline: (X) Package Description D D-28 28-Pin DIP E E-28A 28-Pin LCC 1.3 Absolute Maximum Ratings. (T, = + 25C unless otherwise noted) Vcc to Power Ground... 2 1. es Oto +18V Veg to Power Ground... 2. ee es Oto 18V Digital Inputs (Pins 11-15, 17-28) to Power Ground .............02058 1.0V to +7.0V Ref In to Reference Ground... 0 0. 2 ee +12V Bipolar Offset to Reference Ground... 2... 2 ee ee +12V 10V Span R to Reference Ground... 2... 2 2. ee ee +12V 20V Span R to Reference Ground... 0 2... ee ee +24V Ref Out, Vour (Pins 6,9) 2... 0. ee ee ee es Indefinite Short to Power Ground Momentary Short to Voc Power Dissipation... 6... ee ee 1000mW Storage Temperature Range... 2... ee et tes 65C to + 150C Lead Temperature (Soldering 10sec) 2... 0. ee ee ee + 300C 1.5 Thermal Characteristics. Thermal Resistance @;- = 25C/W for D-28 Oya = 60C/W for D-28 42C/W for E-28A 125C/W for E-28A 8jc Oya REV. C DIGITAL-TO-ANALOG CONVERTERS 8-45 DIGITAL-TO-ANALOG CONVERTERS aAD667 SPECIFICATIONS Table 1. Design Sub Sub Limit Group | Group Test Symbol | Device | @+25C | 1 2,3 Test Condition' Units Relative Accuracy RA -3 2 1/2 34 All Bits with Positive + LSB max Errors On. All Bits with Negative Errors On Differential Nonlinearity DNL -1 4 3/4 1 Major Carry Errors + LSB max Gain Error? Ag -1 0.20 0.20 All Bits On +% FSR max Gain Temperature TCA, | -1 30 30 All BitsOn + ppm/C max Coefficient Unipolar Offset Error Vos -1 2 2 Ail Bits Off + LSB max Temperature Coefficient TEVos | -1 3 3 All Bits Off + ppm/C max Unipolar Offset Bipolar Zero Error? Bry: -1 0.10 0.10 MSB On, All + % FSR max Other Bits Off Bipolar Mode B/P Zero Temperature TCBpy:| -1 10 10 MSBOn, All + ppm/C max Coefficient Other Bits Off Bipolar Mode Input Resistance Rin -1 15 kQmin 25 kQ) max Reference Output Voltage? Veet -1 99 9.9 9.9 Bipolar Mode, Vs= + 11.4 +Vmin 10.10 10.10 10.10 0.tmA External Load +V max Output Current lout -1 5 +mAmin Output Short-Circuit Current Ise ~1 40 +mA max Latch Functionality Ary -1 1 ! i See Notes 4 & 5 + LSB max Latch Functionality Voss ~1 1 1 | See Note 4 + LSB max Power Supply Rejection Ratio PSRR -1 10 10 All Bits On ppm of FSR/% +11.4VEVecs + 16.5V max 10 10 All Bits On -11.4V5Veirs - 16.5V Power Supply Current lec -1 12 12 Voc = + 16.5V, Viag= 16.5V +mA max Ioc: All Bits On Ter -1 5 25 Ign: AU Bits On ~ mA max Digital Input High Voltage Vin -1 2.0 2.0 2.0 +Vmin 5.5 +V max Digital Input Low Voltage Vin -1 0.8 0.8 0.7 +V max Digital Input High Current tu -1 10 10 Vin = 5.5V +A max Digital Input Low Current In. -1 5 5 Vu. =0.0V + pA max Data Setup Time toc -1 50 ns min Data Hold Time tox -1 0 ns min CS Pulse Width tcp -1 100 ns min Address Valid End of CS tac -t 100 ns min Output Voltage Settling Time tsi -t 4 Rep = 10k Ry, = 2k||S00pF ws max 3 Rep = 5k See Figure 1 NOTES Vee = + 15V, Ver = 15V, $0M resistor Pin 6 to Pin 7, Ay, Ai, Az, Ay, CS = LOGIC 0, Vipz = 2.0V, Viz, = 0.8V, Unipolar configuration unless otherwise specified. Unipolar Configuration Pins | and 2 to Pin 9, Pin 4 to PinS. Bipolar Configuration Pin 1 to Pin 9, $00 resistor Pin 4 to Pin 6. 2 Adjustable 100. "In subgroup 1, the reference output is loaded with 0.5mA nominal reference current, 1.0mA bipolar offset currentand 0. lmA additional current. In subgroups 2 and 3, only the 0.5mA reference input current is applied. The reference must be buffered to supply external loads at elevated temperatures. +All bits low, Ap, Ay, Az, As LOGIC 0; Ag, Aj, Ap, A; initialized to LOGIC 1, each 4-Bit register set to LOGIC 1, and Ao, Ai, A; set sequentially to LOGIC 0 and back to LOGIC 1 to latch data inta first rank. 5A, set to LOGIC 0 and back to LOGIC 1 to latch full-scale output into second rank. *See Figure ] and Table 2. 8-46 DIGITAL-TO-ANALOG CONVERTERS REV. CAD667 REV. C 3.2.1 Functional Block Diagram and Terminal Assignments. D811 - Dee 0B? --- 084 0B3 -= veo its Lg q) 12.81T PARALLEL LATCH eer CLEC itt 1 @) 12-81T HIGH SPEED DAC REF GND 5 Vary OUT 6 Veer IN 7 +Vcc 8 Vour 9 ~Vee 10 cs 3.2.4 Microcircuit Technology Group. E PACKAGE (LCC) oO r Zz 8a ts ge = Ss 4% 22, a > ao aae2k s Bs 4 3 2 1 2 27 2% T uJ AD667 TOP VIEW 1213 14 95 16 17 1B Be 2238 8 seo 7 Boe on 2 3 c z 9 This microcircuit is covered by technology group (56). 25 24 23 22 21 DIGITAL-TO-ANALOG CONVERTERS 8-47 Dee OB? De6 Des DB4 DB3 OB2 D PACKAGE (DIP) zov span(_]? * 20 [7] oats isa rov span (C] 2 27) aro sumuct.([] 3 OENTIFIER 28 [) 08s ew ore (] 4 2s [J ose acno(] 5 24 0) 087 Vner our [_] 23 7) ops Vee 6] 7 Anes? 22 {7} oes +Vvec Qe a1 [7] oes vou [J 20 [_] 583 a0 10 [_] bea sq 16 [-) 081 asx 17 [F) bso tse ar] 16 [7 Power GRouNnD at. 15 [a0 "NOTE DIP PACKAGE PIN NUMBERS AND LCC CONTACT NUMBERS SERVE THE SAME FUNCTION. DIGITAL-TO-ANALOG CONVERTERS aAD667 4.2.1 Life Test/Burn-In Circuit. Steady state life test is per MIL-STD-883 Method 1005. Burn-in is per MIL-STD-883 Method 1015 test condition (B). +15.00V 15.00 GND +5.00V tac _-| A2-A0 xX ix |- toc | DB11-DBO aa | MS OUTPUT | a| Figure 1. Table 2. AD667 Truth Table CS |A3 A2 Al AO | Operation 1 Xx X X X No Operation xX 1 1 tf 1 No Operation 0 1 1 1 #0 Enable 4 LSBs of First Rank 0 1 1 0 1 Enable 4 Middle Bits of First Rank 0 1 0 1 41 Enable 4 MSBs of First Rank 0 0 1 1 =1 Loads Second Rank from First Rank 0 0 0 0 0 All Latches Transparent X" - Don't Care 8-48 DIGITAL-TO-ANALOG CONVERTERS REV. C