sl al MxX29SL8000 FEATURES Extended single-supply voltage range 2.7V to 3.6V for read and write JEDEC-stapdard EEPROM commands Minimum 1,000 write/erase cycles Fast access time: 120ns Optimized block architecture - One 16 Kbyte protected block(16K-block) - Two & Kbyte parameter blocks - One 96 Kbyte main block - Seven 128 Kbyte main blocks Hardware and software data protection - Hardware Write Protection pin (WP) - Hardware Lockout bit for 16K-block - Software command data protection Software EEPROM emulation with parameter blocks Status register ~ For detection of program or erase cycle completion Auto Erase operation - Automatically erases any one of the sectors or the whole chip - Erase suspend capability - Fast erase time: 50ms typical for chip erase 1.06 GENERAL DESCRIPTION The MX29L8000 is a 8 Mbit, 3 V-only Flash memory organized as a 1 Mbytes of 8 bits each. For flexible erase and program capability, the 8 Mbits of data is divided into 11 sectors of one 16 Kbyte protected block, two 2 Kbyte parameter blocks, one 96 Kbyte main block, and seven 128 Kbyte main blocks. To allow for simple in-system operation, the device can be oprated with a sirigie 2:7 V to 3.6 V supply voltage. Since many designs read from the flash memory a large percentage of the time, significant power saving is achieved with the 2.7 V VCC operation. Manufactured with MXIC's advanced nonvolatile memory technology, the device offers access times of 120 ns, and a low iu A typical deep power-down current. The MX29L8000 command set is compatible with the JEDEC single-power-supply flash standard. Commands are written to the command register using standard microprocessor write timings. MxXIC's flash memory augments EPROM functionality with an internal state machine which controls the erase and program circuitry. The device Status Register provides a convenient way to monitor when a program or erase cycle is complete, and the success or failure of that cycle. 8M-BIT{[41M_x 8) | SINGLE VOLTAGE 3V ONLY FLASH EEPROM * Auto Page Program operation - Automatically programs and verifies data at specified addresses - internal address and data latches for 128 bytes per page Low power dissipation - 20mA active current - 20uA standby current ~ 1A deep power-down current * Hardware Reset pin (RP) - Reset internal state machin, and put the device into deep power-dawn mode * Built-in 128 Bytes Page Buffer - Work as SRAM for temporary data storage - Fast access to temporary data Low Vee write inhibit < 1.8V * industry standard surface mount packaging - 40-Lead TSOP Type 1 Programming the MX29L8000 is performed on a page basis; 128 bytes of data are loaded into the device and then programmed simultaneously. The typical Page Program time is 5ms.The device can also be reprogrammed in standard EPROM programmers. Reading data out of the device is similar t6 reading from an EPROM or other flash. Erase is accomplished by executing the Erase command sequence. This will invoke the Auto Erase aigarithm which is an internal algorithm that automatically times the erase pulse widths and verifies proper cell margin. This device features both chip erase and block erase. Each block can be erased and programmed without affecting other blocks. Using MX{C's advanced design technology, no preprogram is required (internally or externally). Asa result, the whole chip can be typically erased and verified in as fast as 50 ms. A combined feature of Write Protection pin (WP), Reset pin (RP), 16K-biock lockout bit, and software command sequences provides complete data protection. First, software data protection protects the device from PIN: PM0419 REV.1.0. JUL 12. 1996Mit inadvertent program. or erase. Two "unlock" write cycles must be presented to the devic before the program or erase command can be accepted by the device. For hardware data protection, the WP pin and RP pin provide protection against unwanted command writes due to invalid system bus condition that may occur during system reset and power-up/down sequence. Finally, with 16K-block lockout bit feature, the device provides complete core security for the kernel code required for system initialization. The device has 128 Bytes built-in page buffer, which can serve as SRAM. This feature provides a convenient way to store temporary data for fast read and write. MXIC's Flash technology reliably stores memory contents after 1,000 erase and program cycles. The MXIC's cell is designed to optimize the erase and program mechanism. In addition, the combination of advanced tunnel oxide processing and tow internal electric fields for erase and program operations produce reliable cycling. ~, The highest degree of latch-up protection is achieved _; With MXIC's proprietary non-epi process. Latch-up - protection is proved for stresses up to 100 mifliamps on address and data pin from -1V to VCC +1V. 1.2 PINOUTS 40TSOP (TPYE 1) 10 x 20mm AYR 1 40 ANS 2 C) 38 Ala 3 38 AWS 4 3 Alz 5 36 Alt 6 8 ag 7 Rod AB a 33 WE a 32 ap 10 MX29L8000 4 NG i 30 WP 12 2a ANB 13 2 a? te o AB 15 26 AS 16 25 Aa W 24 AR 18 23 AQ 12 22 Ay 1 at AV? GNO NC Ald Ald poy DOE os ine Nc Dad nae pas . OO Oe GND AG MX29t-8900 1.1 MX29L8000 SECTOR ARCHITECTURE FFFFFH | -Kbyt K eCOO0H 16-Kbyte BLOC FBFFFH FAQDOH 8-Kpyte PARAMETER BLOCK FOFFFH . PAR K EBODOM 8-Kbyte PARAMETER BLOC F7FFFH ' 96-Kbyte MAIN BLOCK i E0O00H i DFFFFH 128-Kbyte MAIN BLOCK COO00H BFFFFEH 128-Kbyte MAIN BLOCK AQOOOH QFFEFEH 128-Kbyie MAIN BLOCK 80000H 7FERFH 128-Kbyte MAIN BLOCK 60000H 5FFFFH 128-Kbyte MAIN BLOCK 40000H 3FFEFH 128-Kpyte MAIN BLOCK 20000H 1FFRFFH 128-Kbyte MAIN BLOCK ooo00H MX29L8000 Memory Map PIN CONFIGURATIONS SYMBOL PIN NAME AQ-A19 ~~ Address Input QO0 - Q7 Data input/Output CE Chip Enable input OE Output Enable Input WE ss WiiteEnable CS RP Reset/Deep Power-down We Write Protect VCC Power Supply Pin (2.7V - 3.6V) GND Ground PinMI Mx29L8000 Table 1 .PIN DESCRIPTIONS SYMBOL TYPE NAME AND FUNCTION AQ-A19 INPUT ADDRESS INPUTS: for memory addresses. Addresses are internally latched during a write cycle. Q0 - Q7 INPUT/OUTPUT INPUTS/OUTPUTS DATA BUS: Input data and commands during Command interface Register(CIR) write cycles. Outputs array,status ,identifier data, and page.buffer in the appropriate read mode. Float to tri-state when the chip is de- selected or the outputs are disabled. CE INPUT CHIP ENABLE INPUTS: Activate the device's control logic, input buffers, decoders and sense amplifiers. With CE high, the device is deselected and power consumption reduces to Standby fevel upon completion of any current program or erase operations. CE must be low to select the device. OE INPUT OUTPUT ENABLES: Gates the device's.data through the output buffers during aread cycle. OE is active low. WE INPUT( WRITE ENABLE: Controls writes to the Command interface Register(CIR). WE is active low. RP INPUT RESET/DEEP POWER-DOWN: When RFP is low, the device is in reset/deep power-down mode. When AP is high, the device is in standard operation. WP INPUT WRITE PROTECTION: Provides a method for locking the 16K-block, using three voltage levels (VIL, VIH, and VHH). When WP is low, the 16K-block is locked. When WP is high the 16K-block is unlocked, if the 16K-block lockout bit is disabled. When is WP is at VHH, the 16K-block is unlocked. This overrides the status of the lockout bit. See Section for details of data-protection vcc DEVICE POWER SUPPLY(2.7V - 3.6V) GND GROUND 1.3 BUS OPERATION Flash memory reads, erases and writes in-system viathe local CPU . Allbus cycles to or from the flash memory conform to standard microprocessor bus cycles. These bus. operations are summarized below. Tabie2 MX29L8000 Bus Operations Mode : Notes CE | oF | We | AP | ao | At | ag | Qo-a7 | Read 1 ve | ove | ov |v x | xX x | DOUT OutputDisable vi VIH VIH vVIH |x | x x Highz Standby VIN x xX VIH x | xX x | HighZ Deeppowerdown VIH : Xx x VIL | x : Xx Xx HighZ ! : Manufacturer!D T VIL VIL: VIH VIH VIL bo VIL VHH CoH DevicelD vit VL Tin Pye) VI Vil VHH | 83H + tH Write vit Vij vl IH XX | xX oN NOTES :1.X can be VIH or VIL for adcress or control pins. 2. VHH = 11.5V- 12.5V. 61-3MEIC 1.4 WRITE OPERATIONS The Command Interface Register (CIR) is the interface between the microprocessor and the internal chip controller. Device operations are selected by writing specific address and data sequence into the CIR, using standard microprocessor write timings. Writing incorrect data value or writing them in improper sequence will reset the device to the read mode. Table 3 defines the valid command sequences. Note that the Erase Suspend (BOH) and Erase Resume (30H) are valid only while an erase operation is in progress and will be ignored in other circumstance. There are four read modes: Read Array, Read Silicon ID, Read Status Register, and Read Page Buffer. For Program and Erase commands, the CIR will Mx29L_s8000 inform the internal state machine that a program or erase sequence has been requested. During the execution of program or erase operation, the state machine will control the program /erase sequence. After the state machine has completed its task, it will set bit 7 of the Status Register (SR. 7) to a "1", which indicates that the CIR can respond to the full command set. TABLE 3. COMMAND DEFINITIONS : Command Read/ Silicon {Page/Byte | Chip Blockr Erase Erase Sleep - Sequence Reset ID Read{ Program J Erase Erase | Suspend] Resume Mode Bus Write 1 4 4 6 6 1 4 3 Cycles Required First Bus Addr XXXXH | 5555H | 555SH 5555H SB55H_ | XXXXH | XXXXH 5555H Write Cycle Daia FOH AAH AAH AAH AAH Bou 30H AAH Second Bus Addr RA 2AAAH 2AAAH [T2AAAH [ 2AAAH 2AAAH Write Cycle Data RD 55H 55H 55H 55H 55H Third Bus Addr 5555H | 5555H 9 5555H 5555H 5555H Write Cycle Data 90H AOQH 80H 80H COH . Fourth Bus Addr Q00H/01H PA 5555H 5555H Read/Write Cycleaj Data C2H/83H PD AAH AAH Fifth Bus Addr 2AAAH | 2AAAH Write Cycle Data 55H 55H 4 Sixth Bus Addr 5555H SA a | Write Cycle Data 10H 30H - wat 61-4MxX29L8000 COMMAND DEFINITIONS(continue Table 3.) Command Lack Lock Status Read Write Sequence 16K-block Read Page Buffer | Page Buffer Bus Write 6 4 4 4 Cycles Required First Bus Addr 5555H 5555H 5555H 5555H Write Cycle Data AAH AAH AAH AAH Second Bus Addr 2AAAH 2AAAH 2AAAH 2AAAH Write Cycle Data 55H 55H 55H 55H Third Bus Addr 5555H 5555H 5555H 5555H Write Cycle Data 60H 90H 75H EOQH Fourth Bus Addr 5555H 02H PA PA Read/Write Cyc! Data AAH C2H/00H PD PD Fifth Bus Addr 2AAAH Write Cycle Data 55H fp ; Sixth Bus Addr XXXXH Write Cycle Data 20H Notes: 1. Address bit At5 -- Ai9 = X = Don't care for ali address commands except for Program Address(PA) and Sector Address(SA). 5555H and 2AAAH address command codes stand for Hex number starting from AQ to A14. Bus operations are defined in Table 2. RA = Address of the memory location to be read __ PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of the WE puise. SA = Address of the block to be erased. The combination of A14 -- A19 will uniquely select any block. RD = Data read from location RA during a read operation. 2. 3. - Aa PD = Data to be programmed at location PA. Datd is latched on the rising edge of WE . Erase can be suspended during sector erase with Addr = don't care. Data = BOH . Erase can be resumed after suspend with Addr = don't care. Data = 30H 61-5". rype MIC 2.0 DEVICE OPERATION 2.1 SILICON ID READ The Silicon ID Read mode allows the reading out of a binary code from the device and will identify its manufacturer and type. This mode is intended for use by programming equipment for the purpose of automatically matching the device to be programmed with its corresponding programming algorithm. This mode is functional over the entire temperature range of the device. To activate this mode, the programming equipment must force VHH (11.5V~12.5V) on address pin AQ. Two identifier bytes may then be sequenced from the device outputs by toggling address AO from VIL to VIH. All addresses are don't cares except AO and A1. The manufacturer and device codes may also be read via the command register. for instances when the MxX29L8000 MX29L8000 is erased or programmed ina system without access to high voltage on the A9 pin. The command sequence is illustrated in Table 3. Following the command write, a read cycle with AD = VIL retrieves the manufacturer code of C@H. Areadcycle with AO = VIH returns the device code of 83H. To terminate the operation, it is necessary to write the Read/Reset command squence into the CIR. Table 4. MX29L8000 Silion ID Codes and Verify Sector Protect Code A, ~A, A, |Code({HEX)| DQ, | DQ,) DQ,/DG,/DQ, | DQ, DQ,|/DA, Manufacturer Code x VIL} VIL} C2H" 1 1 o0;0;,0 G 1/0 MX29L8000 Device Code x VIL] VIH| = 83H* 1 9 0;0} 0 0 1 1 . | Verity 16K Block Protect** x VIHi VILE C2Ht 1 1 010 0 0 1; 0 * MX29L8000 Manufacturer Code = C2H, Device Code =83H ** Outputs C2H if 16K-block is protected (lockout bit is enabled), OOH otherwise. ***Only the 16K-Biock has protect-bit feature. 61-62.2 READ/RESET COMMAND The read or reset operation is initiated by writing the Read/Reset command sequence into the command register. Microprocessor read cycles retrieve array data from the memory. The device remains ready for reads until the CIR contents are altered by a valid command sequence. The device will automatically power-up in the read/reset State. in this case, a command sequence is not required to read data. Standard microprocessor read cycies will retrieve array data. This default value ensures that no spurious afteration of the memory content occurs during the power transition. Refer to the AC Read Characteristics and Waveforms for the specific timing parameters. The MX29L8000 is accessed like an EPROM. When CE and OE are jow and WE is high the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state whenever CE or OE is high. This dual fine control gives designers flexibility in preventing bus contention. Note that the Read/Reset command is not valid when program or erase is in progress. 2.3 PAGE PROGRAM To initiate Page program mode, a three-cycle command sequence is required. There are two " unlock write cycles. These are followed by writing the page program command AOH.Any attempt to write to the device without the three-cycle command sequence will not start the internal Write State Machine(WSM), no data will be written to the device. After three-cycle command sequence is given, a byte load is performed by applying a low pulse on the WE or CE input with CE or WE low (respectively) and OE high. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge ot CE or WE. Maximum of 128 bytes of data may be loaded into each page. 2.3.1 PROGRAM Any page to be programmed should have the page in the erased state first, i.e. performing sector erase is suggested before page programming can be performed. The device is programmed on a page basis. If a byte of data within a page is to be changed, data for the entire page can be loaded into the device. Any byte that is not loaded during the programming of its page will be still in the erased state (i.e. FFH). Once the bytes of a page are loaded into the device, they are simultaneously programrmned during the internal programming period. After the first data byte has been toaded into the device, successive bytes are entered in the same manner. Each new byte to be progranimed must have its high to low transition on WE (or CE) within 30ps of the tow to high transition of WE (or CE) of the preeding byte. A7 to A19 specify the pags address, i.e.; the device is page-aligned on 128 bytes boundary. The page address must be valid during each high to low transition of WE or CE. AO to A6 specify the byte address within the page The byte may be loaded in any order; sequential loading is not required. if a high to low transition of CE or WE is not detected whithin 100us of the last low to high transition, the load period will end and the internal programming period will start. The status of programcan be determined by checking the Status Register. While the program operation is in progress, bit 7 of the Status Register (SR. 7) is"0". When the Status Register indicates that program.is complete (when. SR. 7 = 1), the Program Status bit should be checked to. verify that the program operation was successful. If the program operation was unsuccessful, SR. 4 of the Status Register will be set to 1" to indicate a program failure. The Status Register should be cleared before attempting the next operation.a 2.4 CHIP ERASE Chip erase is a six-bus cycle operation. There are two untock" write cycles.. These are followed by writing the "set-up" command-80H. Two more "unlock" write cycles are then followed by the Chip Erase command 10H. Chip erase does not require the user to program the device prior to.erase. The 16K-Biock will not.be erased if it is protected (16K-Block Lockout bit enabled). The Auto. Chip Erase begins on the rising edge of the last WE pulse in the command sequence and terminates when the status on SR.7 is "1". While the erase sequence is in progress, SR,7 of the Status Register is "0". When erase is complete, the Erase Status bit should be checked. If the erase operation was unsuccessful, SR.5 of the Status Register is set to a."1" to indicate an erase failure. Clear the Status Register before attempting the next operation. 2.5 BLOCK ERASE Sector erase is a six-bus cycle operation. There are two "unlock" write cycles. These are followed by writing the set-up command 80H. Two more "unlock" write cycles are then followed by the sector erase command-30H. The sector address is latched on the falling edge of WE, while the command (data) is latched on the rising edge of WE. Only one sector can be erased at a time. Sector erase does not require the user to program the device prior to erase. The system is not required to provide any controls or timings during these operations. The AutomaticBlock Erase begins on the rising edge of the last WE pulse in the command sequence and terminates when the data on SR.7 is "1". When erasing a block, the remaining unselected blocks are unaffected.During the execution of the Block Erase command, only the Erase Suspend and Erase Resume commands are allowed. The Erase Suspend/Resume command may be issued as many time as required. Similar to the Chip Erase mode, the Status Register should be checked when erase is complete. MxX28t80o 2.6 ERASE SUSPEND AND RESUME The Erase Suspend command is provided to altow the user to interrupt an erase sequence and then read data from a block other than that which is being erased. This command is applicable only during the erase operation. During the erase operation, writing the Erase Suspend command to the CIR will cause the internal state machine to pause the erase sequence at.a predetermined point. The Status Register will indicate when the erase operation has been suspended. Once in erase suspend, a Read Array command can be written to the CIR in order to read data from biocks not being erase suspended. The only other valid commands during erase suspend are Erase Resume and Read Status Register commands. Read Page Buffer command, however, is not applicable during erase suspend. To resume the erase operation, the Erase Resume command 30H should be written to the CIR. Another Erase Suspend command can be written after the chip has resumed erasing. 61-8MxX29L8000 Table5. Status Register Bit Definition WSMS | ESS ES PS SLP 7 6 5 4 2 NOTE : SR.7 = WRITE STATE MACHINE STATUS(WSMS) State machine bit must first be checked to determine 1 = Ready Program or Erase completion, before the Program or 0 = Busy Erase Status bits are checked for success. SR.6 = ERASE-SUSPEND STATUS (ESS) When Erase Suspend is issued, state machine halts 1 = Erase Suspended execution and sets both WSMS and ESS bits to "1," ESS 0 = Erase in Progress/Compieted bit remains set to "1" until an Erase Resume command is issued. SR.5= ERASE STATUS When this bit set to "1," state machine has applied the 1 = Error in Erase maximum number of erase pulses to the device and is 0 = Successful Erasure still unable to successfully verify erasure. SR.4 = PROGRAM STATUS When this bit is set to "1," state machine has attempted 1 = Error. in Page/Byte Program but failed to program page data. 0 = Successful Page/Byte Program SR.2 = SLEEP STATUS When this bit is setto "1", the device isin sleep mode{deep 1 = Device in sleep mode 0 = Device not in sleep mode Others = Reserved for future enhancements power-down). Writing the Read Array command will Wake up the device, and the device will return to standby. 2.7 STATUS REGISTER The device contains a Status Register which may be read to determine when a Program or Erase operation is complete, and whether that operation completed suc- cessfully. The Status Register may be read at any time by writing the Read Status command to the command interface. After writing this command, all subsequent Read operations output data from the Status Register until another command is written to the command inter- face. A Read Array command must be written to the command interface to return to the read array mode. The Status Register bits are output on DQ{0:7]. The contents of the Status Register are latched on the falling edge of OE or CE, whichever occurs last in the read cycle. This prevents possible bus errors which might occur if the contents of the Status Register change while reading the Status Register. CE or must be toggled with each subsequent status read, or the com- pletion of a Program or Erase operation will not be evident from the Status Register. When the state machine is active, this register will indicate the status of the state machine, and will also hold the bits indicating whether or not the state machine was successful in performing the desired operation. 2.7.1 CLEARING THE STATUS REGISTER The state machine sets status bits 4 through 7 to "1", and clears bits 6 and 7 to"0", but cannot clear status bits 4 and 5 to "0". Bits 4 and 5 can only be cleared by the controlling CPU through the use of the Clear Status Register command. These bits can indicate various error conditions. By allowing the system software to control the resetting of these bits, several operations 61-9MI may be performed (such as cumulatively programming several bytes or erasing multiple blocks in sequence). The Status Register may then be read to determine if an error occurred during that programming or erasure series. This adds flexibility to the way the device may be programmed or erased. Once an error occurred, the command interface only responds to clear Status Reg- ister, Read Status Register and Read Array. To clear the Status Register, the Clear Status Register com- mand is written to the command. interface. Then, any other command may be issued to the command inter- face. Note, again, that before read cycle can be initi- ated, a Read Array command must be written to the command interface to specify whether the read data is to come from the Memory Array, Status Register, Page Buffer. or silicon ID. 2.8 SLEEP MODE The MX29L8000 features a sofware controlled low power modes: Sleep modes. Sleep made is allowed during any * Current operations except that once Suspend command is issued, Sleep command is ignored. To activate Sleep mode, a three-bus cycle operation is required. The COH command (Refer to Table 3) puts the device in the Sleep mode. Once in the Sleep mode and with CMOS input level applied, the power of the device is reduced to deep power- downcurrentlevels. The only power consumed is diffusion leakage, transistor subthreshold conduction, input leakage, and output leakage. The Steep command allows the device to compiete its current operations before going into Sleep mode. During Sleep mode, Silicon ID codes remain valid and can still be read. The Device Sleep Status bit SR.2 will indicate that the device in the'siep mode. Writing the Read Array command wakes up the device out of sleep mode. SR.2 is reset to "0" and device returns to standby current level 2.9 PAGE BUFFER READ AND WRITE The MX29L8000 has 128 Bytes of page buffers, which can work as SRAM tostore temporary data for fast access purpose. To write data into page buffers, the Write Page Buffer command is written to the CIR. There are two "unlock"write cycles, followed by the command OH. Loading data to page buffer is similar to that in Page MxX29Ls8000 Program. Sequential loading is not required. AO to AG must be valid to specify byte address within the page buffers during each high-to-iow transition of WE or CE. Each new byte to be stored must have its high-to-low transition of WE or CE within 30 us of the low- -to-high transition of WE or CE of the preceding byte. Otherwise, the Write Page Buffer mode is terminated automaticatly. To read data from the page buffer, the Read Page Buffer command is written to the CIR, There are two unlock" write cycles, which are followed by the command 75H. Each subsequent toggle of address (or OE, CE) will read data from the specified byte address of the page buffer {AD to AG). To terminate the operation, itis necessary to write the Read/Reset command sequence into the CIR. 3.0 DATA PROTECTION The MX29L8000 is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transitions. During power up the device automatically resets the internal state machine in the Read Array mode. Also, with its control register architecture. alteration of the memory contents only occurs after successful completion: of specific multi-bus cycle command sequences. The device also incorporates several features to prevent inadvertent write cycles resulting from VCC power-up 3.1 16K-BLOCK LOCKING The MX2918000 features hardware 16K-Block protection:. This feature will disable both program and erase operations in the 16K-Block. The block protection feature is enabled using system software by the user(Refer. to Table. 3). The device is shipped with 16K- Block unprotected. Alternatively, MXiC may: protect 16K-Block in the factory prior to shipping the device. 3.1.1 LOCK BLOCK To activate this mode, a six-bus cycle operation is required. There are two unlock write cycles. These are followed by writing the set-up command. Two more untock write cycles are then followed by the Lock Sector command 20H. The automatic Lock operation begins 61-19on the rising edge of the last WE pulse in the command sequence and terminates when the status on SR 7 is '1' at which time the device stays at the read mode. 3.1.2 LOCK STATUS READ To verify the Protect status of the 16K-Block, operation iS initiated by writing Silicon {D read command into the command register. Following the command write, a read cycle from address XXX2H retrieves the Manufacturer code of C2H if the 16K-Block is protected. If the 16K- Biock is unprotected, OOH will be read instead. To terminate the operation, itis necessary to write the Read/ Reset command sequence into the CIR. A few retries are required if Protect status can not be verified successfully after each operation. 3.2 HARDWARE PROTECTION Protection for parameter blocks and main blocks can be achieved using combinations of RP and WP pins. 3.2.1 AP = VIL FOR COMPLETE PROTECTION For complete data protection of all blocks, the RP can be held low. 3.2.2 WP = VIL FOR 16K-BLOCK LOCKING When WP = VIL, the 16K-block is locked, while ail other blocks remain unlocked in this condition and can be programmed or erased normally. 3.2.3 WP = VHH FOR 16K-BLOCK UNLOCKING if WP = VHH, the 16K-Biock is unlocked and can be programmed or erased. Note that this feature will override the 16K-Block Lock bit protection. 3.2.4 WP = VIH FOR REGULAR BLOCK UNLOCKING lf WP = VIH and RP = VIH, all the regular blocks (parameter blocks and main blocks) are unlocked and can be programmed or erased. !n this condition, whether the 16K-Block is locked is dependent on the 16K-Biock Lock bit, If the 16K-Block Lock bit is enabled, then the 16K-Block is still protected; otherwise, itis unlocked. The following truth table clearly defines the write protection methods. Table 5. WRITE PROTECTION TRUTH TABLE FOR MX29L8000 RP | WP /16K-Block | Write Protection Provided Lockout bit) 16K-Block |Regutar Block X VHH; xX untocked unlocked VIL x - xX locked locked Vin T Vit X locked | unlocked VIH VIH 1 locked unlocked vIH | viH | oO unlocked | unlocked t 1. 3.3 LOW VCC WRITE INHIBIT To avoid initiation of a write cycle during VCC power-up and power-down, a write cycle is locked out for VCC less than VLKO( typically 1.8V). If VCC <VLKO, the command register is disabled and all internal prograrm/erase circuits are disabled. Under this condition the device will reset to the read mode. Subsequent writes will be ignored until the VCC level is greater than VLKO. It is the user's responsibility to ensure that the control pins are logically correct to prevent unintentional write when VCC is above VLKO. 3.4 WRITE PULSE "GLITCH" PROTECTION Noise pulses of less than 5ns (typical) on CE or WE will not initiate a write cycle. 3.5 LOGICAL INHIBIT Writing is inhibited by holding any one of OE = VIL,CE = VIH or WE = VIH. To initiate a write cycle CE and WE must be a logical zero while OE is a logical one. 61-11Mic _ MX29L8000 Figure 1. AUTO PAGE PROGRAM FLOW CHART - oo { L \. START 1 Write Program Cmd Sequence 1 i i Whte Program Date/Address ao NO i <Q. toading End? > _ - oe | YES | _-. _- . { | Heac Status Register ' oN. a ~N ~ NO i 1 mt aa N oI SA.7=1 > aaa 2 oe aie 1 1 1 | | i i YES y | oo | a sre Ss YES eee | =1 Program Faii Cosmet - | : y | | | 4 | J Page Program Completed } 7 ne | if 61-12Figure 2. AUTO ERASE FLOW CHART Mx29E9000 _ f stant) SN 1 Write Erase Cmd Sequence Y Read Status Register NO mN, To Exacute ~~_ YES s~._Suspend Mode 7? a end fo a. | Erase Fail } Ne ( Erase Gompleted ae Erase Suspend Fiow (Figure 4) 61-13=I MxX28L8000 Figure 3. ERASE SUSPEND/ERASE RESUME FLOW CHART I ff S ( START \ . I Write BOH aa ___f [ Read Status Register t UA NO <a pe ' YES : co __ , ALG = 4 NO Erase Suspend \ > _/ NL a ' Write FFH J ia Read Array t Lon Non ! . Dane Reading > Ne aa [wate DOH I 61-14Figure 4. 16K-BLOCK PROTECTION FLOW CHART ( START / Y Write 16K-Block Protect Cmd Sequence ! Read Status Register J a oN oS ? a wail YES a. OT \ ( Secior Protect Completed I Figure 5. VERIFY 16K-BLOCK PROTECT FLOW CHART 0 ( START ee Y Write Verify-Protection and Sequence (te Protect Status } oe Note: 1. Protect Status: Data Outputs OOH otherwise 2. Sificon ID can be read via this Fiow Chart. Refer to Table 4. Data Outputs C2H if biock is protected(iockout bit is enabled). 61-15MxX298L8000 5.0 ELECTRICAL SPECIFICATIONS OPERATING RANGES RATING VALUE ABSOLUTE MAXIMUM RATINGS Ambient Temperature -20C to 70C VALUE Ambient Temperature -20C to 70C Vee Supply Voltage 2.7V TO 3.6V _ en NOTICE: Storage Temperature -65C to 125C Applied Input Voltage -0.5V to VCC + 4.5 Applied Output Voltage -0.5V to VCC + 0.6 VCC to Ground Potential -0.5V to 5.5V AQ, WP -0.5V to 13.0V CAPACITANCE TA = 25C, f = 1.0 MHz 1.This document contains information on product in the dsign phase of development. Revised information will be published when the product is available. 2.5pecifications contained within the following tables are subject to change. WARNING: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is stress rating only and functional operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended period may affect reliability. SYMBOL PARAMETER MIN. TYP. MAX. UNIT CONDITIONS CIN input Capacitance 14 pF VIN = OV COUT Output Capacitance 16 pF VOUT = OV = SWITCHING TEST CIRCUITS o | | | | DEVICE | ; 2.7KQ 3av ! en <n | TEST | | : | V7 4 ne yo | | Dog cL, |. DIODES = 1N3064 | | i 2 62KQ Vv OR EQUIVALENT i : : 7 | 4! Yo { . fl } | : CL = 100 pF including jig capacitance for 150/200ns | CL = 50 pF for 120ns t : SWITCHING TEST WAVEFORMS | | 2.4V . SOM SOO | Ne Hg 2 a, | x TEST POINTS x 15V . LN 2 o.8v fos | o4sy ON NN INPUT OUTPUT | | AC TESTING: Inputs are dnven at 2.4V for a lagic "1" and 0.45V for a logic "0". | Input pulse rise and fall times are Sns. | j 61-16MEIe. _ Mx29st80e0 5.1 DC CHARACTERISTICS Vcc = 2.7V to 3.6V SYMBOL PARAMETER NOTES MIN. TYP. MAX. UNITS TEST CONDITIONS HL Input Load 1 et BA VCC = VCC Max Current VIN = VCC or GND ILO Output Leakage 1 #10 BA VCC = VCC Max Current VIN = VCC or GND iSB1 VCC Standby 1 20 30 pA VCC = VCC Max 7 Current(CMOS) CE = VIH 1SB2 VCC Standby 1 2 mA VGC = VCC Max Current(TTL) CE = VIH {cC1 VCC Read 1 20 35 mA VCC = VCG Max Current f = 10MHz, [OUT = 0 mA Icc2 VGC Erase 1.2 5 mA CE =VIH Suspend Current Block Erase Suspended iCC3 VCC Program 1 15 30 mA Program in Progress oo Current oo - . Icc4 VCC Erase Current 1 15 30 mA Erase in Progress IPPD VCC Deep Power-down 1 13 HA VCC = VCC Max Current CE = ViH VIL Input Low Voltage 3 0.3 0.6 Vv VIH input High Voltage 4 2.0 VCC+0.3 V VOL Output Low Voltage 0.45 Vv IOL = 5.8mA, Vee = Vee Min VOH Output High Voltage 24 Vv {OH = -100nA, Vee = Vee Min NOTES: 1. Ail currents are in RMS unless otherwise noted. Typical values at VCC = 3.0V, T= 25C. These currents are valid for all product versions (package and speeds). 2. ICC2 is specitied with the device de-selected. If the device is read while in erase suspend mode, current draw is the sum of ICC2 and ICC. 3. VIL min. = -1.0V for pulse width < 50ns. VIL min. = -2.0V for pulse width < 20ns. 4. VIH max. = VCC + 1.5V for pulse width < 20ns. If VIH is over the specified maximum value, read operation cannot be guaranteed. 61-175.2 AC CHARACTERISTICS READ OPERATIONS MxX2eLsout 29L6000-12 29L8000-15 29L8000-20 SYMBOL DESCRIPTIONS MIN. MAX. MIN. MAX. MIN. MAX. UNIT CONDITIONS tacc Address to Output Delay 120 150 200 ns CTE=OE=VIL 1CE a CE to Output Delay : 420 150 200 ns OE=VIL_ (OE =s Eto OutputDelay i Otit~iSS 400 ons CSV DF CE Highto OutputDelay = 0. 5 0 55 0 55 ns GEsViL {OH AddresstoOutputhold =i i ttstiisisS ns CESOE=ViL TEST CONDITIONS: NOTE: * Input pulse levels: 0.45V/2.4V * Input rise and falf times: 5ns * Outputioad: 1TTL gate+ 1G0pF (including scape and jig} Reference levels for measuring timing: 1.5V 1. tDF is defined as the time at which the output achieves the open circuit condition and data is no longer driven. 61-8vc Figure 6. READ TIMING WAVEFORMS | ADDRESSES CE DATA OUT Vec Power-up Vit VIL VIK VIL ViH VIL VIR Vik VOH VOL Device and Standby address selection Outputs Enabled Standby Data valid . Vee Power-down ADDRESSES STABLE f _> / / . a i Nee ore | ene Y f / y ee, a < OF f \ f \ _ = #iWEF yy Ne ICE ~ - OH HIGH Z 7 if HIGH Z Data out vatic SAAA ? } ; _ - tACT | 61-19MIC | MxX29~-8000 5.3 AC CHARACTERISTICS WRITE/ERASE/PROGRAM OPERATIONS 29L8000-12 29L.8000-15 29.8000-20 SYMBOL DESCRIPTION MIN. MAX. MIN. MAX. MIN. MAX. UNIT twe Write Cycle Time 120 150 200 ns - tAS Address Setup Time 0 0 0 ns tAH Address Hold Time 60 60 60 ns tDS Data Setup Time 50 50 50 ns tOH Data Hold Time 10 10 1 ns tOES Qutput Enable Setup Time : 0 0 0 7 ns tCES CE Setup Time 0 0 9 i ns tGHWL Read Recover Time Before Write 0 0 9 tcs CE Setup Time Oo 0 _ oO 7 ns . tCH CE Hold Time 4g 0 0 ns awe Write Pulse Width 60 60 80 ns > tWPH Write Pulse Width High 40 40 7 40 ns tBALC Byte Address Load Cycle 0 2 30 0.2 30 0.2 30 LS TBAL Byte Address Load Time 100 100 100 ps tSRA Status Register Access Time 120 150 7. 200 ns - tCESR CE Setup before S.R. Read 100 _ 100 100 ns tPHWL AP High Recovery to WE Going Low 1 1 1 us tVCS VCC Setup Time 2 2 2 - us : 61-20Figure 7. COMMAND WRITE TIMING WAVEFORMS CE . (CH \ NK tOES _. re cs OE = ~ we - - WE tGHWL aN a tWPH ~\ we _ ~ ADDRESSES {DS 1DH > - HIGH Z as ~ 7X f DATA ----_---=*____/ f ae a ae 1 | f | Z | vcCc ~ wes - 61-21Mai Mx298L8000 Figure 8. AUTOMATIC PAGE PROGRAM/WRITE PAGE BUFFER TIMING WAVEFORMS 1.Please refer to SECTION 2.3 for detail page program operation. 1 : \/ Vf Byie offser | A0AG __ 55H K AAH x 55H XY Address A | I f \ | AT~At4 55H 2AH xX 58H xX Page Address 2" | _ | tAS tA et ed : : ' ' Page Address 2** | A1S~a1g age Te ~~ BALC BAL | =~ > _ > | ce fn oN TN mo fon fo LA NS NS NYS LL LY wP oo IWPH : - > | WE a \_/f YY \ __f \ VL _/ \ 7 | ICES | = i | - / \ _ : OE _ / i | : WS tor AA \ r - , - JS 1 DATA AAH \ ( 55H > (AOHIEO ) ~ we y+ \ { Last Wote \ ~< SRD \_ r LL ae ee Lai a. { / Dal B. Nee a ee ' \ :PHWL } _- | f 1 . ; | RP al | i | NOTE: i j **2.Page address is not required for Wnte Page Butfer 61-22Figure 5. AUTOMATIC BLOCK/CHIP ERASE TIMING WAVEFORMS AQ~A14 A13~A19 cE WE O DATA XX 5555H Xx 2AAAH \ S5SSH \X _ 5858H x 2AAAH x 1 S555H AS tAH -_ > ~ - __ ~ _ a SVS VS NS NS NT f tWP TWPH =-_ > ~<-, ay a ane -_ ICES " / __/ \ ws <> (DH ~~ SRA ~~ \/ / aria \ AAH Sad 55H r+ 80H >{ ABH sed 55H y430H/10H}~-{ SRD p} tPHWE ~_ _/ NOTES: 1. "X" means don't care in this diagram 2."SA" means Block Address"(required for Block Erase only) MxX29L8000 61-23MI MxX29L8000 5.4 AC CHARACTERISTICS. WRITE/ERASE/PROGRAM OPERATIONS (Alternate CE Controlled) 291.8000-12 29L.8000-15 291.8000-20 SYMBOL DESCRIPTION MIN. MAX. MIN. MAX. MIN. MAX. UNIT iwc Write Cycle Time 120 480. 200 ns tAS Address Setup Time oo 10 7 10 10 ns tAH Address Hold Time 100 100 100 ns 1DS Data Setup Time a {DH Data Hold Time 4g 10 i ~))0hums tOES Output Enable Setup Time 0 0 0 ns ICES CE Setup Time a ee ee ee tGHWL Read Recover TimeBefore Write 0 0 o (ws WE Setup Time 0 0 0 ns {WH WE Hold Time o 0 o ns tCP CE Pulse Width oo 50 50 50 ns tCPH CE Pulse Width High 50 50 50 ns CS vec Setup Time 3 2 2 us 7 61-24Figure 10. COMMAND. WRITE TIMING WAVEFORMS(Alternate CE Controlled) } | | WE - ow yo | 10ES. Na | -, - ~~ ws : OE = ~ | 7 we - - CE / tGHWL ~\ 4 tCPH ~, i NY ~ rN ~< tCP ~ tAH a ADDRESSES VALID | | 1S IDH ~~ - + - IGH Z fo {f DATA " DIN rnd Na tn ttt a f Vcc wes ~~ - | 61-25Figure 11. AUTOMATIC PAGE PROGRAM TIMING WAVEFORM(Alternate CE Controlled) f Byte offset \astBye AQ~A6 \ AAH ee N ss AAH 58H X itese X_N ess : FN \, 1 A7~A14 55H ( 2AH HK 55H x Page Address 1AS AR =. wa - P; | A15~A19 age Address | | we _ - tBALC WE oF mf laa 7 \ po Sf YY Vf a, VL _f f icp 1CPH IBAL semen <a > <P < * [\ SSNS NS NS / \ / ff ey, \ f . :CES f- \ _ _ poo _ [ \ f | OF ee! i | SoH tSRA co = _ \ / / Last write / DATA (mn) aa 55H Ware i { sap ) I {ace} pa fet Vee 81-26M=IiC MX29L8000 5.5 ERASE AND PROGRAMMING PERFORMANCE I i LIMITS PARAMETER MIN. TYP. MAX. UNITS | Chip/Sector Erase Time 50 ms | : ! 1 ' : ' Page Programming Time : 5 ms Chip Programming Time 40 | sec ! i i | | Byte Program Time(average}) 50 : Hs Erase/Program Cycles 1,000 | Cycles L | i | : 5.6 LATCHUP CHARACTERISTICS MIN. i MAX. Input Voltage with respect to GND on all pins except I/O pins -1.0V 13.5V Input Voltage with respect to GND on all /O pins -1.0V Vec + 1.0V Current -100mA +100mA i includes all pins except Vcc. Test conditions: Vcc = 3.0V, one pin at a time. 61-27