512MB, 1GB, 2GB Registered DIMM
Rev. 1.0 January 2004
SDRAM
SDRAM Registered Module
168pin Registered Module based on 512Mb B-die
with 72-bit ECC
Revision 1.0
January 2004
* Samsung Electronics reserves the right to change products or specification without notice.
512MB, 1GB, 2GB Registered DIMM
Rev. 1.0 January 2004
SDRAM
Revision History
Revision 1.0 (January, 2004)
- First release
512MB, 1GB, 2GB Registered DIMM
Rev. 1.0 January 2004
SDRAM
168Pin Registered DIMM based on 512Mb B-die (x4, x8)
Ordering Information
Operating Frequencies
Part Number Density Organization Component Composition Component
Package Height
M390S6553BT1-C7A 512MB 64Mx72 64Mx8(K4S510832B) * 9EA
54-TSOP(II)
1,500mil
M390S6553BTU-C7A 512MB 64Mx72 64Mx8(K4S510832B) * 9EA 1,200mil
M390S2950BT1-C7A 1GB 128Mx72 128Mx4(K4S510432B) * 18EA 1,700mil
M390S2950BTU-C7A 1GB 128Mx72 128Mx4(K4S510432B) * 18EA 1,200mil
M390S2953BT1-C7A 1GB 128Mx72 64Mx8(K4S510832B) * 18EA 1,700mil
M390S5658BT1-C7A 2GB 256Mx72 st.256Mx4(K4S1G0632B) * 18EA 1,700mil
M390S5658BTU-C7A 2GB 256Mx72 st.256Mx4(K4S1G0632B) * 18EA 1,200mil
7A
@CL3 @CL2
Maximum Clock Frequency 133MHz(7.5ns) 100MHz(10ns)
CL-tRCD-tRP(clock) 3 - 3 - 3 2 - 2 - 2
Feature
• Burst mode operation
• Auto & self refresh capability (8192 Cycles/64ms)
• LVTTL compatible inputs and outputs
• Single 3.3V ± 0.3V power supply
• MRS cycle with address key programs Latency (Access from column address)
Burst length (1, 2, 4, 8)
Data scramble (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the system clock
• Serial presence detect with EEPROM
512MB, 1GB, 2GB Registered DIMM
Rev. 1.0 January 2004
SDRAM
* SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
PIN CONFIGURATIONS (Front side/back side)
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Front
VSS
DQ0
DQ1
DQ2
DQ3
VDD
DQ4
DQ5
DQ6
DQ7
DQ8
VSS
DQ9
DQ10
DQ11
DQ12
DQ13
VDD
DQ14
DQ15
CB0
CB1
VSS
NC
NC
VDD
WE
DQM0
Pin
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
Front
DQM1
**CS0
DU
VSS
A0
A2
A4
A6
A8
A10/AP
BA1
VDD
VDD
**CLK0
VSS
DU
**CS2
DQM2
DQM3
DU
VDD
NC
NC
CB2
CB3
VSS
DQ16
DQ17
Pin
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
Front
DQ18
DQ19
VDD
DQ20
NC
*VREF
**CKE1
VSS
DQ21
DQ22
DQ23
VSS
DQ24
DQ25
DQ26
DQ27
VDD
DQ28
DQ29
DQ30
DQ31
VSS
**CLK2
NC
NC
SDA
SCL
VDD
Pin
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
Back
VSS
DQ32
DQ33
DQ34
DQ35
VDD
DQ36
DQ37
DQ38
DQ39
DQ40
VSS
DQ41
DQ42
DQ43
DQ44
DQ45
VDD
DQ46
DQ47
CB4
CB5
VSS
NC
NC
VDD
CAS
DQM4
Pin
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
Back
DQM5
**CS1
RAS
VSS
A1
A3
A5
A7
A9
BA0
A11
VDD
**CLK1
A12
VSS
**CKE0
**CS3
DQM6
DQM7
*A13
VDD
NC
NC
CB6
CB7
VSS
DQ48
DQ49
Pin
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
Back
DQ50
DQ51
VDD
DQ52
NC
*VREF
REGE
VSS
DQ53
DQ54
DQ55
VSS
DQ56
DQ57
DQ58
DQ59
VDD
DQ60
DQ61
DQ62
DQ63
VSS
**CLK3
NC
SA0
SA1
SA2
VDD
1. * These pins are not used in this module.
2. Pins 82,83,165,166,167 should be NC in the system which does not support SPD.
3. ** About these pins, Refer to the Block Diagram of each.
Note :
Pin Description
Pin Name Function Pin Name Function
A0 ~ A12 Address input (Multiplexed) DQM0 ~ 7 DQM
BA0 ~ BA1 Select bank VDD Power supply (3.3V)
DQ0 ~ DQ63 Data input/output VSS Ground
CB0 ~ CB7 Check bit (Data-in/data-out) *VREF Power supply for reference
CLK0 ~ 3 Clock input REGE Register enable
CKE0, CKE1 Clock enable input SDA Serial data I/O
CS0 ~ CS3 Chip select input SCL Serial clock
RAS Row address strobe SA0 ~ 2 Address in EEPROM
CAS Colume address strobe DU Don′t use
WE Write enable NC No connection
512MB, 1GB, 2GB Registered DIMM
Rev. 1.0 January 2004
SDRAM
PIN CONFIGURATION DESCRIPTION
Pin Name Input Function
CLK System clock Active on the positive going edge to sample all inputs.
CS Chip select Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM
CKE Clock enable
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
CKE should be enabled 1CLK+tss prior to valid command.
A0 ~ A12 Address Row/column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA12
Column address : (x4 : CA0 ~ CA9, CA11, CA12), (x8 : CA0 ~ CA9, CA11)
BA0 ~ BA1 Bank select address Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
RAS Row address strobe Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
CAS Column address strobe Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
WE Write enable Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
DQM0 ~ 7 Data input/output mask Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when DQM active. (Byte masking)
REGE Register enable
The device operates in the transparent mode when REGE is low. When REGE is high,
the device operates in the registered mode. In registered mode, the Address and con-
trol inputs are latched if CLK is held at a high or low logic level. the input s are stored in
the latch/flip-flop on the rising edge of CLK. REGE is tied to VDD through 10K ohm
Resistor on PCB. So if REGE of module is floating, this module will be operated as reg-
istered mode.
DQ0 ~ 63 Data input/output Data inputs/output s are multiplexed on the same pins.
CB0 ~ 7 Check bit Check bits for ECC.
VDD/VSS Power supply/ground Power and ground for the input buffers and the core logic.
512MB, 1GB, 2GB Registered DIMM
Rev. 1.0 January 2004
SDRAM
512MB, 64Mx72 ECC Module (M390S6553BT1) (Populated as 1 bank of x8 SDRAM Module)
FUNCTIONAL BLOCK DIAGRAM
A0~A9
RAS,CAS,WE
DQM0,1,4,5
CS0
REGE
PCLK2
B0A0~B0A9
BRAS,BCAS,BWE
BDQM0,1,4,5
BCS0
74ALVCF162835 B0A10,B0A11,B0A12,BBA0~1
BCS2
BCKE0
BDQM2,3,6,7
V
DD
10k
Ω
OE
LE
74ALVCF162835
OE
LE
CLK
CS
CKE
Add,CTL
DQM
DQ0~7
D0
CLK
CS
CKE
Add,CTL
DQM
DQ0~7
D1
CLK
CS
CKE
Add,CTL
DQM
DQ0~7
D2
CLK
CS
CKE
Add,CTL
DQM
DQ0~7
D3
CLK
CS
CKE
Add,CTL
DQM
DQ0~7
D5
CLK
CS
CKE
Add,CTL
DQM
DQ0~7
D4
CLK
CS
CKE
Add,CTL
DQM
DQ0~7
D6
CLK
CS
CKE
Add,CTL
DQM
DQ0~7
D8
CLK
CS
CKE
Add,CTL
DQM
DQ0~7
D7
10
Ω
10
Ω
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
CDCF2509
2G
AGND
1G
AVCL
1Y0
1Y1
1Y2
1Y3
1Y4
2Y0
2Y1
2Y2
2Y3
CLK
FIBIN
V
SS
10
Ω
V
DD
CLK0
FBOUT
12pF
10
Ω
10
Ω
10
Ω
10
Ω
10
Ω
10
Ω
10
Ω
10
Ω
CLK1,2,3 12pF
Note
1. The actual values of
Cb
will depend upon the PLL chosen.
Cb
*1
Serial PD
SDA
SCL A1 A2A0
SA1 SA2SA0
WP
47K
Ω
PCLK0
BCS0
BCKE0
B0A0~B0A12,BBA0~1,BRAS,BCAS,BWE
BDQM0
DQ0~7
DQ8~15
PCLK1
BDQM1
CB0~7
BCS2
BDQM2
DQ16~23
PCLK3
BDQM3
DQ24~31
BDQM4
DQ32~39
BDQM5
DQ40~47
BDQM6
DQ48~55
BDQM7
DQ56~63
PCLK0
PCLK1
PCLK2
PCLK3
A10,A11,A12,BA0~1
CS2
CKE0
DQM2,3,6,7
512MB, 1GB, 2GB Registered DIMM
Rev. 1.0 January 2004
SDRAM
512MB, 64Mx72 ECC Module (M390S6553BTU) (Populated as 1 bank of x8 SDRAM Module)
FUNCTIONAL BLOCK DIAGRAM
A0~A6
RAS,CAS,WE
DQM0,1,4,5
CS0
REGE
PCLK2
B0A0~B0A6
BRAS,BCAS,BWE
BDQM0,1,4,5
BCS0
74ALVCF162835
V
DD
10k
Ω
OE
LE
74ALVCF162835
OE
LE
CLK
CS
CKE
Add,CTL
DQM
DQ0~7
D0
CLK
CS
CKE
Add,CTL
DQM
DQ0~7
D1
CLK
CS
CKE
Add,CTL
DQM
DQ0~7
D2
CLK
CS
CKE
Add,CTL
DQM
DQ0~7
D3
CLK
CS
CKE
Add,CTL
DQM
DQ0~7
D5
CLK
CS
CKE
Add,CTL
DQM
DQ0~7
D4
CLK
CS
CKE
Add,CTL
DQM
DQ0~7
D6
CLK
CS
CKE
Add,CTL
DQM
DQ0~7
D8
CLK
CS
CKE
Add,CTL
DQM
DQ0~7
D7
10
Ω
10
Ω
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
CDCF2509
2G
AGND
1G
AVCL
1Y0
1Y1
1Y2
1Y3
1Y4
2Y0
2Y1
2Y2
2Y3
CLK
FIBIN
V
SS
10
Ω
V
DD
CLK0
FBOUT
12pF
10
Ω
10
Ω
10
Ω
10
Ω
10
Ω
10
Ω
10
Ω
10
Ω
CLK1,2,3 12pF
Note
1. The actual values of
Cb
will depend upon the PLL chosen.
Cb
*1
PCLK1
•
•
•
Serial PD
SDA
SCL A1 A2A0
SA1 SA2SA0
WP
47K
Ω
PCLK0
BCS0
BCKE0
B0A0~B0A12,BBA0~1,BRAS,BCAS,BWE
BDQM0
DQ0~7
DQ8~15
PCLK2
BDQM1
CB0~7
PCLK3
BCS2
BDQM2
DQ16~23
PCLK4
BDQM3
DQ24~31
BDQM4
DQ32~39
BDQM5
DQ40~47
BDQM6
DQ48~55
BDQM7
DQ56~63
PCLK4
PCLK5
PCLK0
PCLK1
PCLK2
PCLK3
A7~A12,BA0~1
CS2
CKE0
DQM2,3,6,7
B0A7~B0A12,BBA0~BBA1
BCS2
BCKE0
BDQM2,3,6,7
512MB, 1GB, 2GB Registered DIMM
Rev. 1.0 January 2004
SDRAM
FUNCTIONAL BLOCK DIAGRAM
1GB 128Mx72 ECC Module (M390S2950BT1) (Populated as 1 bank of x4 SDRAM Module)
10
Ω
10
Ω
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
D0
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
D1
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
D2
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
D3
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
D5
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
D4
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
D6
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
D8
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
D7
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
D9
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
D10
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
D11
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
D12
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
D14
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
D13
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
D15
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
D17
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
D16
CDCF2510
2G
AGND
1G
AVCL
IY0
IY1
IY2
IY3
IY4
2Y0
2Y1
CLK
FIBIN
V
SS
10
Ω
V
DD
CLK0
10
Ω
10
Ω
10
Ω
10
Ω
10
Ω
10
Ω
10
Ω
10
Ω
10
Ω
10
Ω
10
Ω
10
Ω
10
Ω
FBOUT
PCLK0
PCLK1
PCLK2
PCLK3
PCLK4
PCLK5
PCLK6
10
Ω
A3~A10,BA0
74ALVCF162835
A11,A12,BA1
CS2
CKE0
DQM2,3,6,7
B0A0,B0A1,B0A2
B1A0,B1A1,B1A2
B0RAS, B0CAS, B0WE
B1RAS, B1CAS, B1WE
BCS0
BDQM0,1,4,5
V
DD
10k
Ω
OE
LE
74ALVCF162835
OE
LE
PCLK6
REGE
74ALVCF162835
OE
LE
A0,A1,A2
RAS,CAS,WE
12pF
10
Ω
B0A11.B0A12.B0BA1
B1A11.B1A12.B1BA1
BCS2
B0CKE0
B1CKE0
BDQM2,3,6,7
B0A3~B0A10,B0BA0
B1A3~B1A10,B1BA0
CS0
DQM0,1,4,5
10
Ω
10
Ω
CLK1,2,3 12pF
Note
1. The actual values of
Cb
will depend upon the PLL chosen.
Cb
*1
Serial PD
SDA
SCL A1 A2A0
SA1 SA2SA0
WP
47K
Ω
PCLK0
BCS0
B0CKE0
B0A0~B0A12,B0BA0,B0BA1,B0RAS,B0CAS,B0WE
BDQM0
DQ0~3
DQ4~7
PCLK1
BDQM1
DQ8~11
PCLK2
DQ12~15
CB0~3
PCLK3
BCS2
DQ16~19
PCLK4
BDQM2
DQ20~23
DQ24~27
PCLK5
B1A0~B1A12,B1BA0,B1BA1,B1RAS,B1CAS,B1WE
BDQM3
DQ28~31
B1CKE0
BDQM4
DQ32~35
DQ36~39
BDQM5
DQ40~43
DQ44~47
CB4~7
DQ48~51
BDQM6
DQ52~55
DQ56~59
BDQM7
DQ60~63
512MB, 1GB, 2GB Registered DIMM
Rev. 1.0 January 2004
SDRAM
FUNCTIONAL BLOCK DIAGRAM
1GB 128Mx72 ECC Module (M390S2950BTU) (Populated as 1 bank of x4 SDRAM Module)
CDCF2510
2G
AGND
1G
AVCL
IY0
IY1
IY2
IY3
IY4
IY5
IY6
IY7
IY8
IY9
CLK
FIBIN
V
SS
10
Ω
V
DD
CLK0
FBOUT
12pF
10
Ω
CLK1,2,3 12pF
Note
1. The actual values of
Cb
will depend upon the PLL chosen.
Cb
*1
PCLK9
PCLK5
PCLK6
PCLK7
PCLK8
PCLK0
PCLK1
PCLK2
PCLK3
PCLK4
Serial PD
SDA
SCL A1 A2A0
SA1 SA2SA0
WP
47K
Ω
A0~A12,BA0~1, RAS, CAS
74ALVCF162835
B0WE
B1WE
V
DD
10k
Ω
OE
LE
74ALVCF162835
OE
LE
PCLK9
REGE
74ALVCF162835
OE
LE
CKE0 B0A0~B0A12,B0BA0~1, B0RAS, B0CAS
DQM0~7,CS0,CS2
B1A0~B1A12,B1BA0~1, B1RAS, B1CAS
B0CKE0
B1CKE0
WE
10
Ω
10
Ω
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
D0
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
D1
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
D2
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
D3
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
D5
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
D4
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
D6
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
D8
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
D7
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
10
Ω
10
Ω
10
Ω
10
Ω
10
Ω
10
Ω
10
Ω
10
Ω
10
Ω
10
Ω
10
Ω
10
Ω
10
Ω
10
Ω
10
Ω
10
Ω
D9
D10
D11
D12
D14
D13
D15
D17
D16
BCS0
B0CKE0
B0A0~B0A12,B0BA0~1, B0RAS, B0CAS, B0WE
BDQM0
DQ0~3
PCLK0
PCLK1
DQ4~7
PCLK2
BDQM1
DQ8~11
PCLK3
DQ12~15
PCLK4
CB0~3
PCLK5
BCS2
BDQM2
DQ16~19
PCLK6
DQ20~23
PCLK7
BDQM3
DQ24~27
PCLK8
BCS2
B1CKE0
B1A0~B1A12,B1BA0~1, B1RAS, B1CAS, B1WE
DQ28~31
BDQM0~7, BCS0,BCS2
BDQM4
DQ32~35
DQ36~39
BDQM5
DQ40~43
DQ44~47
CB4~7
BDQM6
DQ48~51
DQ52~55
BDQM7
DQ56~59
DQ60~63
512MB, 1GB, 2GB Registered DIMM
Rev. 1.0 January 2004
SDRAM
FUNCTIONAL BLOCK DIAGRAM
1GB, 128Mx72 ECC Module (M390S2953BT1) (Populated as 2 bank of x8 SDRAM Module)
10
Ω
10
Ω
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
D0
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
D1
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
D2
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
D3
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
D5
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
D4
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
D6
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
D8
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
D7
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
D9
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
D10
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
D11
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
D12
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
D14
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
D13
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
D15
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
D17
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
D16
CDCF2510
2G
AGND
1G
AVCL
IY0
IY1
IY2
IY3
IY4
2Y0
2Y1
CLK
FIBIN
V
SS
10
Ω
V
DD
CLK0
10
Ω
10
Ω
10
Ω
10
Ω
10
Ω
10
Ω
10
Ω
10
Ω
10
Ω
10
Ω
10
Ω
10
Ω
10
Ω
FBOUT
PCLK0
PCLK1
PCLK2
PCLK3
PCLK4
PCLK5
PCLK6
10
Ω
A3~A10,BA0
74ALVCF162835
A11,A12,BA1
CS2
CKE0
DQM2,3,6,7
B0A0,B0A1,B0A2
B1A0,B1A1,B1A2
B0RAS, B0CAS, B0WE
B1RAS, B1CAS, B1WE
BCS0
BDQM0,1,4,5
V
DD
10k
Ω
OE
LE
74ALVCF162835
OE
LE
PCLK6
REGE
74ALVCF162835
OE
LE
A0,A1,A2
RAS,CAS,WE
12pF
10
Ω
B0A11.B0A12.B0BA1
B1A11.B1A12.B1BA1
BCS2
B0CKE0
B1CKE0
BDQM2,3,6,7
B0A3~B0A10,B0BA0
B1A3~B1A10,B1BA0
CS0
DQM0,1,4,5
10
Ω
10
Ω
CLK1,2,3 12pF
Note
1. The actual values of
Cb
will depend upon the PLL chosen.
Cb
*1
Serial PD
SDA
SCL A1 A2A0
SA1 SA2SA0
WP
47K
Ω
PCLK0
BCS0
B0CKE0
B0A0~B0A12,B0BA0,B0BA1,B0RAS,B0CAS,B0WE
BDQM0
DQ0~3
DQ4~7
PCLK1
BDQM1
DQ8~11
PCLK2
DQ12~15
CB0~3
PCLK3
BCS2
DQ16~19
PCLK4
BDQM2
DQ20~23
DQ24~27
PCLK5
B1A0~B1A12,B1BA0,B1BA1,B1RAS,B1CAS,B1WE
BDQM3
DQ28~31
B1CKE0
BDQM4
DQ32~35
DQ36~39
BDQM5
DQ40~43
DQ44~47
CB4~7
DQ48~51
BDQM6
DQ52~55
DQ56~59
BDQM7
DQ60~63
512MB, 1GB, 2GB Registered DIMM
Rev. 1.0 January 2004
SDRAM
FUNCTIONAL BLOCK DIAGRAM
2GB, 256Mx72 ECC Module (M390S5658BT1) (Populated as 2 bank of x4 SDRAM Module)
10Ω
CB4~7
10Ω
CB0~3
10Ω
DQ12~15
10Ω
DQ8~11
CLK
CS1,CKE
CTL
Add
DQM
DQ0~3
D0L
10Ω
10Ω
10Ω
CLK
CS0,CKE
CTL
Add
DQM
DQ0~3
D0U
BCS1,B2CKE0
CLK
CS1,CKE
CTL
Add
DQM
DQ0~3
D1L CLK
CS0,CKE
CTL
Add
DQM
DQ0~3
D1U
DQ0~3
DQ4~7
CLK
CS0,CKE
CTL
Add
DQM
DQ0~3
D9L CLK
CS1,CKE
CTL
Add
DQM
DQ0~3
D9U
DQ32~35
10Ω
CLK
CS0,CKE
CTL
Add
DQM
DQ0~3
D10L CLK
CS1,CKE
CTL
Add
DQM
DQ0~3
D10U
DQ36~39
CLK
CS1,CKE
CTL
Add
DQM
DQ0~3
D2L CLK
CS0,CKE
CTL
Add
DQM
DQ0~3
D2U
CLK
CS1,CKE
CTL
Add
DQM
DQ0~3
D3L CLK
CS0,CKE
CTL
Add
DQM
DQ0~3
D3U
PCLK2
BDQM1
CLK
CS1,CKE
CTL
Add
DQM
DQ0~3
D4L CLK
CS0,CKE
CTL
Add
DQM
DQ0~3
D4U
10Ω
CLK
CS0,CKE
CTL
Add
DQM
DQ0~3
D11L CLK
CS1,CKE
CTL
Add
DQM
DQ0~3
D11U
DQ40~43
BDQM5
10Ω
CLK
CS0,CKE
CTL
Add
DQM
DQ0~3
D12L CLK
CS1,CKE
CTL
Add
DQM
DQ0~3
D12U
DQ44~47
CLK
CS0,CKE
CTL
Add
DQM
DQ0~3
D13L CLK
CS1,CKE
CTL
Add
DQM
DQ0~3
D13U
10Ω
DQ28~31
10Ω
DQ24~27
CLK
CS1,CKE
CTL
Add
DQM
DQ0~3
D5L
10Ω
10Ω
10Ω
CLK
CS0,CKE
CTL
Add
DQM
DQ0~3
D5U
CLK
CS1
CTL
Add
DQM
DQ0~3
D6L CLK
CS0,CKE
CTL
Add
DQM
DQ0~3
D6U
DQ16~19
DQ20~23
CLK
CS0,CKE
CTL
Add
DQM
DQ0~3
D14L CLK
CS1,CKE
CTL
Add
DQM
DQ0~3
D14U
DQ48~51
BDQM6
10Ω
CLK
CS0,CKE
CTL
Add
DQM
DQ0~3
D15L CLK
CS1,CKE
CTL
Add
DQM
DQ0~3
D15U
DQ52~55
CLK
CS1,CKE
CTL
Add
DQM
DQ0~3
D7L CLK
CS0,CKE
CTL
Add
DQM
DQ0~3
D7U
CLK
CS1,CKE
CTL
Add
DQM
DQ0~3
D8L CLK
CS0,CKE
CTL
Add
DQM
DQ0~3
D8U
PCLK7
BDQM3
10Ω
CLK
CS0,CKE
CTL
Add
DQM
DQ0~3
D16L CLK
CS1,CKE
CTL
Add
DQM
DQ0~3
D16U
DQ56~59
BDQM7
10Ω
CLK
CS0,CKE
CTL
Add
DQM
DQ0~3
D17L CLK
CS1,CKE
CTL
Add
DQM
DQ0~3
D17U
DQ60~63
BDQM4
A3~A10,BA0 B0A3~B0A10,B0BA0
74ALVCF162835
CS2,CS3
CKE0
DQM2,3,6,7
VDD
10kΩ
OE
LE
74ALVCF162835
OE
LE
PCLK9
REGE
BCS2,BCS3
B0CKE0,B1CKE0
B2CKE0,B3CKE0
BDQM2,3,6,7
74ALVCF162835
OE
LE
A0,A1,A2
RAS,CAS,WE
CS0,CS1
DQM0,1,4,5
CDCF2510
G
AGND
AVDD
IY0
IY1
IY2
IY3
IY4
IY5
IY6
IY7
IY8
CLK
FBIN
VSS
10Ω
VDD
CLK0 12pF FBOU
PCLK0
PCLK1
PCLK2
PCLK3
PCLK4
PCLK5
PCLK6
PCLK7
PCLK8
PCLK9
PCLK8
PCLK6
PCLK1
PCLK3
PCLK4
BCS0,B0CKE0
BCS2,B1CKE0
B1A0~B1A12
B0RAS,B0CAS,B0WE,B0BA0,B0BA1
B0A0~B0A12
PCLK0
BDQM0
BCS3,B3CKE0
B1A3~B1A10,B1BA0
A11,A12,BA1 B0A11,B0A12.B0BA1
B1A11,B1A12.B1BA1
CS2,CS3
CKE0
DQM2,3,6,7
B0A0,B0A1,B0A2
B1A0,B1A1,B1A2
B0RAS, B0CAS, B0WE
B1RAS, B1CAS, B1WE
BCS0,BCS1
BDQM0,1,4,5
B1RAS,B1CAS,B1WE,B1BA0,B1BA1
10Ω
CLK1,2,3 12pF
Note
1. The actual values of
Cb
will depend upon the PLL chosen.
Cb*1
Serial PD
SDA
SCL A1 A2A0
SA1 SA2SA0
WP
47KΩ
PCLK5
BDQM2
512MB, 1GB, 2GB Registered DIMM
Rev. 1.0 January 2004
SDRAM
FUNCTIONAL BLOCK DIAGRAM
2GB, 256Mx72 ECC Module (M390S5658BTU) (Populated as 2 bank of x4 SDRAM Module)
CDCF2510
2G
AGND
1G
AVCL
IY0
IY1
IY2
IY3
IY4
IY5
IY6
IY7
IY8
IY9
CLK
FIBIN
V
SS
10
Ω
V
DD
CLK0
FBOUT
12pF
10
Ω
CLK1,2,3 12pF
Note
1. The actual values of
Cb
will depend upon the PLL chosen.
Cb
*1
PCLK9
PCLK5
PCLK6
PCLK7
PCLK8
PCLK0
PCLK1
PCLK2
PCLK3
PCLK4
Serial PD
SDA
SCL A1 A2A0
SA1 SA2SA0
WP
47K
Ω
A0~A12,BA0~1, RAS, CAS
74ALVCF162835
B0WE,B0CKE1
B1WE,B1CKE1
V
DD
10k
Ω
OE
LE
74ALVCF162835
OE
LE
PCLK9
REGE
74ALVCF162835
OE
LE
CKE0 B0A0~B0A12,B0BA0~1, B0RAS, B0CAS
DQM0~7,CS0~3
B1A0~B1A12,B1BA0~1, B1RAS, B1CAS
B0CKE0
B1CKE0
WE
BDQM0~7, BCS0~3
10
Ω
10
Ω
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
D0L
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
D1L
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
D2L
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
D3L
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
D5L
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
D4L
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
D6L
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
D8L
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
D7L
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
10
Ω
10
Ω
10
Ω
10
Ω
10
Ω
10
Ω
10
Ω
10
Ω
10
Ω
10
Ω
10
Ω
10
Ω
10
Ω
10
Ω
10
Ω
D9L
D10L
D11L
D12L
D14L
D13L
D15L
D17L
D16L
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
D9
D10
D11
D12
D14
D13
D15
D17
D16
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
D0U
D1U
D2U
D3U
D5U
D4U
D6U
D8U
D7U
10
Ω
BCS3
BCS1
PCLK0
BCS0
B0CKE0
B0A0~B0A12,B0BA0~1, B0RAS, B0CAS, B0WE
BDQM0
DQ0~3
PCLK1
DQ4~7
PCLK2
BDQM1
DQ8~11
PCLK3
DQ12~15
PCLK4
CB0~3
PCLK5
BCS2
BDQM2
DQ16~19
PCLK6
DQ20~23
PCLK7
BDQM3
DQ24~27
PCLK8
BCS2
B1CKE0
B1A0~B1A12,B1BA0~1, B1RAS, B1CAS, B1WE
BDQM0
DQ28~31
BDQM4
DQ32~35
DQ36~39
BDQM5
DQ40~43
DQ44~47
CB4~7
BDQM6
DQ48~51
DQ52~55
BDQM7
DQ56~59
BDQM7
DQ60~63
512MB, 1GB, 2GB Registered DIMM
Rev. 1.0 January 2004
SDRAM
td, tr = Delay of register
Notes : 1. In case of module timing, command cycles delayed 1CLK with respect to external input timing at the address and input signal
because of the buffering in register. Therefore, Input/Output signals of read/write function should be
issued 1CLK earlier as compared to Unbuffered DIMMs.
2. DIN is to be issued 1clock after write command in external timing because DIN is issued directly to module.
: Don′t care
STANDARD TIMING DIAGRAM WITH PLL & REGISTER (CL=2, BL=4)
REG
Control Signal(RAS,CAS,WE)
*1
*2
*3 DOUT
*1. Register Input
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
CLK
RAS
CAS
WE
RAS
CAS
WE
tSAC
tRDL
ReadRow Active Command Row Active Write
Command Precharge
Command
1CLK
td tr td tr
*2. Register Output
*3. SDRAM
tRAC(refer to *1)
CAS latency(refer to *1)
=2CLK+1CLK
DQ Qa0 Qa1 Qa2 Qa3 Db0 Db1 Db2 Db3
Precharge
Command
CAS latency(refer to *2)
=2CLK
tRAC(refer to *2)
512MB, 1GB, 2GB Registered DIMM
Rev. 1.0 January 2004
SDRAM
ABSOLUTE MAXIMUM RATINGS
Parameter Symbol Value Unit
Voltage on any pin relative to Vss VIN, VOUT -1.0 ~ 4.6 V
Voltage on VDD supply relative to Vss VDD, VDDQ -1.0 ~ 4.6 V
Storage temperature TSTG -55 ~ +150 °C
Power dissipation PD1.0 * # of component W
Short circuit current IOS 50 mA
Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
Note :
DC OPERATING CONDITIONS AND CHARACTERISTICS
Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70°C)
Parameter Symbol Min Typ Max Unit Note
Supply voltage VDD 3.0 3.3 3.6 V
Input high voltage VIH 2.0 3.0 VDDQ+0.3 V 1
Input low voltage VIL -0.3 0 0.8 V 2
Output high voltage VOH 2.4 - - V IOH = -2mA
Output low voltage VOL --0.4VIOL = 2mA
Input leakage current ILI -10 - 10 uA 3
CAPACITANCE(Max.) (VDD = 3.3V, TA = 23°C, f = 1MHz , VREF = 1.4V ± 200 mV)
Parameter Symbol M390S6553BT1
M390S6553BTU M390S2950BT1
M390S2950BTU M390S2953BT1 M390S5658BT1
M390S5658BTU Unit
Input capacitance (A0 ~ A11)
Input capacitance (RAS, CAS, W E )
Input capacitance (CKE0)
Input capacitance (CLK0)
Input capacitance (CS0, CS2)
Input capacitance (DQM0 ~ DQM7)
Input capacitance (BA0 ~ BA1)
Data input/output capacitance(DQ0~DQ63)
Data input/ouput capacitance (CB0~CB7)
CIN1
CIN2
CIN3
CIN4
CIN5
CIN6
CIN7
COUT1
COUT2
15
15
15
23
15
15
15
16
16
15
15
15
20
15
15
15
16
16
19
19
33
12
12
12
12
19
19
15
15
15
20
15
15
15
22
22
pF
pF
pF
pF
pF
pF
pF
pF
pF
1. VIH (max) = 5.6V AC.The overshoot voltage duration is ≤ 3ns.
2. VIL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns.
3. Any input 0V ≤ VIN ≤ VDDQ.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
Notes :
512MB, 1GB, 2GB Registered DIMM
Rev. 1.0 January 2004
SDRAM
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, TA = 0 to 70°C)
Parameter Symbol Test Condition Version Unit Note
7A
Operating current
(One bank active) ICC1 Burst length = 1
tRC ≥ tRC(min)
IO = 0 mA 1,310 mA 1
Precharge standby current
in power-down mode ICC2P CKE ≤ VIL(max), tCC = 10ns 370 mA
ICC2PS CKE & CLK ≤ VIL(max), tCC =∞20
Precharge standby current
in non power-down mode
ICC2NCKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
Input signals are changed one time during 20ns 530 mA
ICC2NS CKE ≥ VIH(min), CLK ≤ VIL(max), tCC =∞
Input signals are stable 95
Active standby current in
power-down mode ICC3P CKE ≤ VIL(max), tCC = 10ns 405 mA
ICC3PS CKE & CLK ≤ VIL(max), tCC =∞60
Active standby current in
non power-down mode
(One bank active)
ICC3NCKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
Input signals are changed one time during 20ns 620 mA
ICC3NS CKE ≥ VIH(min), CLK ≤ VIL(max), tCC =∞
Input signals are stable 230 mA
Operating current
(Burst mode) ICC4
IO = 0 mA
Page burst
4Banks activated
tCCD = 2CLKs
1,400 mA 1
Refresh current ICC5 tRC ≥ tRC(min) 2,300 mA 2
Self refresh current ICC6 CKE ≤ 0.2V 405 mA
M390S6453BTU(1) (64M x 72, 512MB Module)
(Recommended operating condition unless otherwise noted, TA = 0 to 70°C)
Parameter Symbol Test Condition Version Unit Note
7A
Operating current
(One bank active) ICC1 Burst length = 1
tRC ≥ tRC(min)
IO = 0 mA 2,030 mA 1
Precharge standby current
in power-down mode ICC2P CKE ≤ VIL(max), tCC = 10ns 490 mA
ICC2PS CKE & CLK ≤ VIL(max), tCC =∞40
Precharge standby current
in non power-down mode
ICC2NCKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
Input signals are changed one time during 20ns 710 mA
ICC2NS CKE ≥ VIH(min), CLK ≤ VIL(max), tCC =∞
Input signals are stable 190
Active standby current in
power-down mode ICC3P CKE ≤ VIL(max), tCC = 10ns 460 mA
ICC3PS CKE & CLK ≤ VIL(max), tCC =∞110
Active standby current in
non power-down mode
(One bank active)
ICC3NCKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
Input signals are changed one time during 20ns 890 mA
ICC3NS CKE ≥ VIH(min), CLK ≤ VIL(max), tCC =∞
Input signals are stable 455 mA
Operating current
(Burst mode) ICC4
IO = 0 mA
Page burst
4Banks activated
tCCD = 2CLKs
2,120 mA 1
Refresh current ICC5 tRC ≥ tRC(min) 4,100 mA 2
Self refresh current ICC6 CKE ≤ 0.2V 460 mA
M390S2950BTU(1) (256M x 72, 2GB Module)
Notes : 1. Measured with outputs open.
2. Refresh period is 64ms.
512MB, 1GB, 2GB Registered DIMM
Rev. 1.0 January 2004
SDRAM
(Recommended operating condition unless otherwise noted, TA = 0 to 70°C)
Parameter Symbol Test Condition Version Unit Note
7A
Operating current
(One bank active) ICC1 Burst length = 1
tRC ≥ tRC(min)
IO = 0 mA 1,445 mA 1
Precharge standby current
in power-down mode ICC2P CKE ≤ VIL(max), tCC = 10ns 390 mA
ICC2PS CKE & CLK ≤ VIL(max), tCC =∞40
Precharge standby current
in non power-down mode
ICC2NCKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
Input signals are changed one time during 20ns 710 mA
ICC2NS CKE ≥ VIH(min), CLK ≤ VIL(max), tCC =∞
Input signals are stable 185
Active standby current in
power-down mode ICC3P CKE ≤ VIL(max), tCC = 10ns 460 mA
ICC3PS CKE & CLK ≤ VIL(max), tCC =∞110
Active standby current in
non power-down mode
(One bank active)
ICC3NCKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
Input signals are changed one time during 20ns 800 mA
ICC3NS CKE ≥ VIH(min), CLK ≤ VIL(max), tCC =∞
Input signals are stable 455 mA
Operating current
(Burst mode) ICC4
IO = 0 mA
Page burst
4Banks activated
tCCD = 2CLKs
1,625 mA 1
Refresh current ICC5 tRC ≥ tRC(min) 2,345 mA 2
Self refresh current ICC6 CKE ≤ 0.2V 405 mA
M390S2953BT1 (128M x 72, 1GB Module)
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, TA = 0 to 70°C)
Parameter Symbol Test Condition Version Unit Note
7A
Operating current
(One bank active) ICC1 Burst length = 1
tRC ≥ tRC(min)
IO = 0 mA 2,570 mA 1
Precharge standby current
in power-down mode ICC2P CKE ≤ VIL(max), tCC = 10ns 425 mA
ICC2PS CKE & CLK ≤ VIL(max), tCC =∞75
Precharge standby current
in non power-down mode
ICC2NCKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
Input signals are changed one time during 20ns 1,070 mA
ICC2NS CKE ≥ VIH(min), CLK ≤ VIL(max), tCC =∞
Input signals are stable 365
Active standby current in
power-down mode ICC3P CKE ≤ VIL(max), tCC = 10ns 570 mA
ICC3PS CKE & CLK ≤ VIL(max), tCC =∞220
Active standby current in
non power-down mode
(One bank active)
ICC3NCKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
Input signals are changed one time during 20ns 1,430 mA
ICC3NS CKE ≥ VIH(min), CLK ≤ VIL(max), tCC =∞
Input signals are stable 905 mA
Operating current
(Burst mode) ICC4
IO = 0 mA
Page burst
4Banks activated
tCCD = 2CLKs
2,660 mA 1
Refresh current ICC5 tRC ≥ tRC(min) 4,640 mA 2
Self refresh current ICC6 CKE ≤ 0.2V 570 mA
M390S5658BTU(1) (128M x 72, 1GB Module)
Notes : 1. Measured with outputs open.
2. Refresh period is 64ms.
512MB, 1GB, 2GB Registered DIMM
Rev. 1.0 January 2004
SDRAM
3.3V
1200Ω
870Ω
Output
50pF
VOH (DC) = 2.4V, IOH = -2mA
VOL (DC) = 0.4V, IOL = 2mA
Vtt = 1.4V
50Ω
Output
50pF
Z0 = 50Ω
(Fig. 2) AC output load circuit (Fig. 1) DC output load circuit
AC OPERATING TEST CONDITIONS (VDD = 3.3V ± 0.3V, TA = 0 to 70°C)
Parameter Value Unit
AC input levels (Vih/Vil) 2.4/0.4 V
Input timing measurement reference level 1.4 V
Input rise and fall time tr/tf = 1/1 ns
Output timing measurement reference level 1.4 V
Output load condition See Fig. 2
OPERATING AC PARAMETER
Notes :
(AC operating conditions unless otherwise noted)
Parameter Symbol Version Unit Note
7A
Row active to row active delay tRRD(min) 15 ns 1
RAS to CAS delay tRCD(min) 20 ns 1
Row precharge time tRP(min) 20 ns 1
Row active time tRAS(min) 45 ns 1
tRAS(max) 100 us
Row cycle time tRC(min) 65 ns 1
Last data in to row precharge tRDL(min) 2 CLK 2
Last data in to Active delay tDAL(min) 2 CLK + tRP -
Last data in to new col. address delay tCDL(min) 1 CLK 2
Last data in to burst stop tBDL(min) 1 CLK 2
Col. address to col. address delay tCCD(min) 1 CLK 3
Number of valid output data CAS latency=3 2 ea 4
CAS latency=2 1
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time
and then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
512MB, 1GB, 2GB Registered DIMM
Rev. 1.0 January 2004
SDRAM
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf) = 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
Notes :
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
Parameter Symbol 7A Unit Note
Min Max
CLK cycle
time CAS latency=3 tCC 7.5 1000 ns 1
CAS latency=2 10
CLK to valid
output delay CAS latency=3 tSAC 5.4 ns 1,2
CAS latency=2 6
Output data
hold time CAS latency=3 tOH 3ns 2
CAS latency=2 3
CLK high pulse width tCH 2.5 ns 3
CLK low pulse width tCL 2.5 ns 3
Input setup time tSS 1.5 ns 3
Input hold time tSH 0.8 ns 3
CLK to output in Low-Z tSLZ 1ns2
CLK to output
in Hi-Z CAS latency=3 tSHZ 5.4 ns
CAS latency=2 6
REFER TO THE INDIVIDUAL COMPONENET, NOT THE WHOLE MODULE.
512MB, 1GB, 2GB Registered DIMM
Rev. 1.0 January 2004
SDRAM
SIMPLIFIED TRUTH TABLE (V=Valid, X=Don′t care, H=Logic high, L=Logic low)
Command CKEn-1 CKEn CS RAS CAS WE DQM BA0,1 A10/AP A0 ~ A9,
A11, A12 Note
Register Mode register set H X L L L L X OP code 1,2
Refresh
Auto refresh HHLL LHX X 3
Self
refresh
Entry L 3
Exit L H LHHHXX3
HX XX 3
Bank active & row addr. H X L L H H X V Row address
Read &
column address Auto precharge disable HXLHLHXVLColumn
address 4
Auto precharge enable H 4,5
Write &
column address Auto precharge disable H XLHLLXV LColumn
address 4
Auto precharge enable H 4,5
Burst stop H X L H H L X X 6
Precharge Bank selection HXLLHLX
VL X
All banks XH
Clock suspend or
active power down Entry H L HX XXXX
LVVV
Exit L H X X X X X
Precharge power down mode
Entry H L HX XXX
X
LHHH
Exit L H HX XXX
LVVV
DQM H V X 7
No operation command H X HX XXXX
LHHH
1. OP Code : Operand code
A0 ~ A12 & BA0 ~ BA1 : Program keys. (@ MRS)
2. MRS can be issued only at all banks precharge state.
A new command can be issued after 2 clock cycles of MRS.
3. Auto refresh functions are as same as CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4. BA0 ~ BA1 : Bank select addresses.
If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.
If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected.
If BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.
If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected.
5. During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
6. Burst stop command is valid at every burst length.
7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0),
but makes Hi-Z state the data-out of 2 CLK cycles af ter. (Read DQM latency is 2)
Notes :
X
512MB, 1GB, 2GB Registered DIMM
Rev. 1.0 January 2004
SDRAM
PACKAGE DIMENSIONS : 64Mx72 (M390S6553BT1)
Units : Inches (Millimeters)
0.250
(6.350)
Detail A
0.123 ± 0.005
(3.125 ± 0.125)
0.250
(6.350)
Detail B
0.123 ± 0.005
(3.125 ± 0.125)
0.079 ± 0.004
(2.000 ± 0.100) 0.079 ± 0.004
(2.000 ± 0.100)
Tolerances : ± 0.005(.13) unless otherwise specified
The used device is 64Mx8 SDRAM, TSOPII
SDRAM Part No. : K4S510832B
This module is based on JEDEC PC133 Specification
5.250
5.014
R 0.079
(R 2.000 )
0.250
(6.350)
1.450
(36.830) 2.150
(54.61)
0.118
(3.000)
0.350
0.700
(17.780)
(8.890)
A C
0.250
(6.350)
.450
(11.430) 4.550
(115.57)
0.157 ± 0.004
(4.000 ± 0.100)
0.054
(1.372)
(127.350)
(133.350)
1.500
(38.1)
0.118
(3.000)
B
REG PLL REG
0.150 Max
0.050 ± 0.0039
(1.270 ± 0.10)
0.157 Min
(3.99 Min)
(3.81 Max)
0.050
0.008 ± 0.006
(0.200 ± 0.150)
(1.270)
Detail C
0.039 ± 0.002
(1.000 ± 0.050)
.118DIA +0.004/-0.000
(3.000DIA +0.100/-0.000)
0.0984 ±0.008
(2.500 ±0.2)
(2.500 ±0.2)
0.0984 ±0.008
512MB, 1GB, 2GB Registered DIMM
Rev. 1.0 January 2004
SDRAM
PACKAGE DIMENSIONS : 64Mx72 (M390S6553BTU)
Units : Inches (Millimeters)
0.250
(6.350)
Detail A
0.123 ± 0.005
(3.125 ± 0.125)
0.250
(6.350)
Detail B
0.123 ± 0.005
(3.125 ± 0.125)
0.079 ± 0.004
(2.000 ± 0.100) 0.079 ± 0.004
(2.000 ± 0.100)
Tolerances : ± 0.005(.13) unless otherwise specified
The used device is 64Mx8 SDRAM, TSOPII
SDRAM Part No. : K4S510832B
This module is based on JEDEC PC133 Specification
5.250
5.014 R 0.079
(R 2.000 )
0.250
(6.350)
1.450
(36.830) 2.150
(54.61)
0.118
(3.000)
0.350
0.0984 ±0.008
(2.500 ±0.2 )
0.700
(17.780)
.118DIA +0.004/-0.000
(3.000DIA +0.100/-0.000)
(8.890)
A C
0.250
(6.350)
.450
(11.430) 4.550
(115.57)
0.157 ± 0.004
(4.000 ± 0.100)
0.054
(1.372)
(127.350)
(133.350)
1.200
(38.1)
0.118
(3.000)
B
REG
PLL
0.150 Max
0.050 ± 0.0039
(1.270 ± 0.10)
0.157 Min
(3.99 Min)
(3.81 Max)
0.050
0.008 ± 0.006
(0.200 ± 0.150)
(1.270)
Detail C
0.039 ± 0.002
(1.000 ± 0.050)
REG
(2.500 ±0.2)
0.0984 ±0.008
512MB, 1GB, 2GB Registered DIMM
Rev. 1.0 January 2004
SDRAM
PACKAGE DIMENSIONS : 128Mx72 (M390S2950BT1)
0.250
(6.350)
Detail A
0.123 ± 0.005
(3.125 ± 0.125)
0.250
(6.350)
Detail B
0.123 ± 0.005
(3.125 ± 0.125)
0.079 ± 0.004
(2.000 ± 0.100) 0.079 ± 0.004
(2.000 ± 0.100)
Tolerances : ± 0.005(.13) unless otherwise specified
The used device is 128Mx4 SDRAM, TSOPII
SDRAM Part No. : K4S510432B
This module is based on JEDEC PC133 Specification
5.250
5.014
Units : Inches (Millimeters)
0.150 Max
0.050 ± 0.0039
(1.270 ± 0.10)
R 0.079
(R 2.000 )
0.250
(6.350)
1.450
(36.830) 2.150
(54.61)
0.118
(3.000)
0.350
0.700
(17.780)
(8.890)
A C
0.250
(6.350)
.450
(11.430) 4.550
(115.57)
0.157 ± 0.004
(4.000 ± 0.100)
0.054
(1.372)
(127.350)
(133.350)
1.700
(43.18)
0.118
(3.000)
0.165 Min
(4.19 Min)
(3.81 Max)
B
REG
REG PLLREG
0.050
0.008 ± 0.006
(0.200 ± 0.150)
(1.270)
Detail C
0.039 ± 0.002
(1.000 ± 0.050)
(2.500 ±0.2)
0.0984 ±0.008
0.0984 ±0.008
(2.500 ±0.2)
.118DIA +0.004/-0.000
(3.000DIA +0.100/-0.000)
512MB, 1GB, 2GB Registered DIMM
Rev. 1.0 January 2004
SDRAM
PACKAGE DIMENSIONS : 128Mx72 (M390S2950BTU)
0.250
(6.350)
Detail A
0.123 ± 0.005
(3.125 ± 0.125)
0.250
(6.350)
Detail B
0.123 ± 0.005
(3.125 ± 0.125)
0.079 ± 0.004
(2.000 ± 0.100) 0.079 ± 0.004
(2.000 ± 0.100)
Tolerances : ± 0.005(.13) unless otherwise specified
The used device is 128Mx4 SDRAM, TSOPII
SDRAM Part No. : K4S510432B
This module is based on JEDEC PC133 Specification
5.250
5.014
Units : Inches (Millimeters)
R 0.079
(R 2.000 )
0.250
(6.350)
1.450
(36.830) 2.150
(54.61)
0.118
(3.000)
0.350
0.700
(17.780)
(8.890)
A C
0.250
(6.350)
.450
(11.430) 4.550
(115.57)
0.157 ± 0.004
(4.000 ± 0.100)
0.054
(1.372)
(127.350)
(133.350)
1.200
(30.48)
0.118
(3.000)
B
PLL
0.050
0.008 ± 0.006
(0.200 ± 0.150)
(1.270)
Detail C
0.039 ± 0.002
(1.000 ± 0.050)
0.150 Max
0.050 ± 0.0039
(1.270 ± 0.10)
0.157 Min
(3.99 Min)
(3.81 Max)
REG
REG
REG
.118DIA +0.004/-0.000
(3.000DIA +0.100/-0.000)
0.0984 ±0.008
(2.500 ±0.2)
(2.500 ±0.2)
0.0984 ±0.008
512MB, 1GB, 2GB Registered DIMM
Rev. 1.0 January 2004
SDRAM
PACKAGE DIMENSIONS : 128Mx72 (M390S2953BT1)
0.250
(6.350)
Detail A
0.123 ± 0.005
(3.125 ± 0.125)
0.250
(6.350)
Detail B
0.123 ± 0.005
(3.125 ± 0.125)
0.079 ± 0.004
(2.000 ± 0.100) 0.079 ± 0.004
(2.000 ± 0.100)
Tolerances :± 0.005(.13) unless otherwise specified
The used device is 64Mx8 SDRAM, TSOPII
SDRAM Part No. : K4S510832B
This module is based on JEDEC PC133 Specification
0.050
0.039 ± 0.002
0.008 ±0.006
(0.200 ±0.150)
(1.000 ± 0.050)
(1.270)
Detail C
5.250
5.014
Units : Inches (Millimeters)
0.150 Max
0.050 ± 0.0039
R 0.079
(R 2.000 )
0.250
(6.350)
1.450
(36.830) 2.150
(54.61)
0.118
(3.000)
0.350
0.700
(17.780)
(8.890)
A C
0.250
(6.350)
.450
(11.430) 4.550
(115.57)
0.157 ± 0.004
(4.000 ± 0.100)
0.054
(1.372)
(127.350)
(133.350)
1.700
(43.18)
0.118
(3.000)
0.165 Min
(4.19 Min)
(3.81 Max)
REG
B
PLLREG
REG
(1.270 ± 0.10)
.118DIA +0.004/-0.000
(3.000DIA +0.100/-0.000)
0.0984 ±0.008
(2.500 ±0.2)
(2.500 ±0.2)
0.0984 ±0.008
512MB, 1GB, 2GB Registered DIMM
Rev. 1.0 January 2004
SDRAM
0.250
(6.350)
Detail A
0.123 ± 0.005
(3.125 ± 0.125)
0.250
(6.350)
Detail B
0.123 ± 0.005
(3.125 ± 0.125)
0.079 ± 0.004
(2.000 ± 0.100) 0.079 ± 0.004
(2.000 ± 0.100)
Tolerances : ± 0.005(.13) unless otherwise specified
SDRAM Part No. : K4S1G0632B
- The used device is stacked 256Mx4 SDRAM, TSOPII
- Staktek’s stacking technology is Samsung’s stacking technology of choice
This module is based on JEDEC PC133 Specification
5.250
5.014
Units : Inches (Millimeters)
0.254 Max
0.050 ± 0.0039
(1.270 ± 0.10)
R 0.079
(R 2.000 )
0.250
(6.350)
1.450
(36.830) 2.150
(54.61)
0.118
(3.000)
0.350
0.100 Min
(2.540 Min)
0.700
(17.780)
.118DIA ± 0.004
(3.000DIA ± 0.100)
(8.890)
A C
0.250
(6.350)
.450
(11.430) 4.550
(115.57)
0.157 ± 0.004
(4.000 ± 0.100)
0.054
(1.372)
(127.350)
(133.350)
1.700
(43.18)
0.118
(3.000)
0.157 Min
(3.99 Min)
(6.452 Max)
B
REG
REG PLLREG
0.050
0.008 ± 0.006
(0.200 ± 0.150)
(1.270)
0.100 Min
(2.540 Min)
Detail C
0.039 ± 0.002
(1.000 ± 0.050)
PACKAGE DIMENSIONS : 256Mx72 (M390S5658BT1)
512MB, 1GB, 2GB Registered DIMM
Rev. 1.0 January 2004
SDRAM
Tolerances : ± 0.005(.13) unless otherwise specified
SDRAM Part No. : K4S1G0632B
- The used device is stacked 256Mx4 SDRAM, TSOPII
- Staktek’s stacking technology is Samsung’s stacking technology of choice
This module is based on JEDEC PC133 Specification
0.250
(6.350)
Detail A
0.123 ± 0.005
(3.125 ± 0.125)
0.250
(6.350)
Detail B
0.123 ± 0.005
(3.125 ± 0.125)
0.079 ± 0.004
(2.000 ± 0.100) 0.079 ± 0.004
(2.000 ± 0.100)
5.250
5.014
Units : Inches (Millimeters)
R 0.079
(R 2.000 )
0.250
(6.350)
1.450
(36.830) 2.150
(54.61)
0.118
(3.000)
0.350
0.100 Min
(2.540 Min)
0.700
(17.780)
.118DIA ± 0.004
(3.000DIA ± 0.100)
(8.890)
A C
0.250
(6.350)
.450
(11.430) 4.550
(115.57)
0.157 ± 0.004
(4.000 ± 0.100)
0.054
(1.372)
(127.350)
(133.350)
1.200
(30.48)
0.118
(3.000)
B
PLL
0.050
0.008 ± 0.006
(0.200 ± 0.150)
(1.270)
0.100 Min
(2.540 Min)
Detail C
0.039 ± 0.002
(1.000 ± 0.050)
REG
REG
REG
0.254 Max
0.050 ± 0.0039
(1.270 ± 0.10)
0.157 Min
(3.99 Min)
(6.452 Max)
PACKAGE DIMENSIONS : 256Mx72 (M390S5658BTU)
