BMR4641002 - Ericsson, Inc.

Key Features

 Small package

30.85 x 20.0 x 8.2 mm (1.215 x 0.787 x 0.323 in)

SIP: 33.0 x 7.6 x 18.1 mm (1.30 x 0.30 x 0.713 in)

 0.6 V - 3.3 V output voltage range

 High efficiency, typ. 97.2% at 5Vin, 3.3Vout half load

 Configuration and Monitoring via PMBus

 Synchonization & phase spr eading

 Current sharing, Voltage Tracking & Volta ge margining

 MTBF 10.9 Mh

General Characteristics

 Fully regulated

 For narrow board pitch applications (15 mm/0.6 in)

 Non-Linear Response for reduction of decoupling cap.

 Input under voltage shutdown

 Over temperature protection

 Output short-circuit & Output over voltage protection

 Remote control & Power Good

 Voltage setting via pin-strap or PMBus

 Advanced Configurable via Graphical

User Interface

 ISO 9001/14001 certified supplier

 Highly automated manufacturi ng ensures quality

Safety Approvals Design for Environment

Pending ETL number Meets requirements in high-

temperature lead-free soldering

processes.

Ericsson Internal

TABLE OF CONTENTS 1 (1)

Prepared (also subject responsible if other) No.

EAB/FAC/P Johan Hörman 00152-EN/LZT 146 435 Uen

Approved Checked Date Rev Reference

2011-07-08 D D

Contents

Ordering Information .............................................................2

General Information .............................................................2

Safety Specification .............................................................3

Absolute Maximum Ratings .............................................................4

Electrical Specification

40A/ 0.6-3.3V Through hole and Surface mount version BMR4640002, BMR4641002................5

40A/ 0.6-3.3V Single in Line version (SIP) BMR4642002...................................... 13

EMC Specification ........................................................... 21

Operating Information ...........................................................21

Thermal Consideration ........................................................... 30

Connections ...........................................................31

Mechanical Information ...........................................................38

Soldering Information ...........................................................41

Delivery Information ...........................................................42

Product Qualification Specification ........................................................... 44

BMR 464 series POL Regulators

Input 4.5-14 V, Output up to 40 A / 132 W EN/LZT 146 435 R2A July 2011

Technical Speciﬁcation

BMR 464 series POL Regulators

Input 4.5-14 V, Output up to 40 A / 132 W EN/LZT 146 435 R2B August 2011

Technical Speciﬁcation

Ordering Information

Product program Output

BMR 464 0.6-3.3 V, 40 A/ 132 W

Product number and Packagin g

BMR 464 n1n2n3n4/n5n6n7n8

Options n1 n2 n3 n4 / n5 n6 n7 n8

Mounting  /

Mechanical  /

Digital interface

  /

Configuration file /

  

Packaging /



Options Description

n3 n4

n5 n6 n7

001

Through hole mount version (TH)

Surface mount version (SMD)

Single in line (SIP)

Open frame

PMBus and analog pin strap

Standard configuration

Antistatic tray of 100 products (SIP only)

Antistatic tape & reel of 130 products

(Sample delivery avalable in lower

quantities. Not for SIP)

Example: Product number BMR 464 0002/001C equals a through-hole

mounted, open frame, PMBus and analog pin strap, standard configuration

variant.

General Information

Reliability

The failure rate () and mean time between failures

(MTBF= 1/) is calculated at max output power and an

operating ambient temperature (TA) of +40°C. Ericsson

Power Modules uses Telcordia SR-332 Issue 2 Method 1

to calculate the mean steady-state failure rate and standard

deviation ().

Telcordia SR-332 Issue 2 also provides techniques to

estimate the upper confidence leve ls of failure rates based

on the mean and standard deviation.

Mean steady-state failure rate,  Std. deviation, 

92 nFailures/h 13.0 nFailures/h

MTBF (mean value) for the BMR 464 ser ies = 10.9 Mh.

MTBF at 90% confidenc e level = 9.2 Mh

Compatibility with RoHS requirements

The products are compatible wit h the rel evant clauses and

requirements of the RoHS directive 2002/95/EC and have a

maximum concentration value of 0.1% b y weight in

homogeneous materials for lead, mercury, hexavalent

chromium, PBB and PBDE and of 0.01% by weight in

homogeneous materials for cadmi um.

Exemptions in the RoHS directive utilized in Ericsson

Power Modules products are found in the Statement of

Compliance document.

Ericsson Power Modules fulfills and will continuously fulfill

all its obligations under regulation (EC) No 1907/2006

concerning the registration, evaluation, authorization and

restriction of chemicals (REACH) as they enter into force

and is through product materials dec larations preparing for

the obligations to communicate information on substances

in the products.

Quality Statement

The products are designed and manufactured in an

industrial environment where quality systems and methods

like ISO 9000, Six Sigma, and SPC are inten sively in use to

boost the continuous improvements strateg y. Infant

mortality or early failures in the prod ucts are screened out

and they are subjected to an ATE-based final test.

Conservative design rules, design reviews and product

qualifications, plus the high competence of an engaged

work force, contribute to the high quality of the products.

Warranty

Warranty period and conditions are defined in Ericsson

Power Modules General Terms and Conditi ons of Sale.

Limitation of Liability

Ericsson Power Modules does not make any other

warranties, expressed or impli ed including any warranty of

merchantability or fitness for a particular purp ose

(including, but not limited to, use in life support

applications, where malfunctions of product can cause

injury to a person’s healt h or li fe).

The information and specifications in this technical

specification is believed to be correct at the time of

publication. However, no liabil ity is accepted for

inaccuracies, printing errors or for any consequences

thereof. Ericsson AB reserves the right to change the

contents of this technical specification at any time without

prior notice.

BMR 464 series POL Regulators

Input 4.5-14 V, Output up to 40 A / 132 W EN/LZT 146 435 R2A July 2011

Technical Speciﬁcation

BMR 464 series POL Regulators

Input 4.5-14 V, Output up to 40 A / 132 W EN/LZT 146 435 R2B August 2011

Technical Speciﬁcation

Safety Specification

General information

Ericsson Power Modules DC/DC converters and DC/DC

regulators are designed in accordance with safety

standards IEC/EN/UL 60950-1 Safety of Information

Technology Equip m ent.

IEC/EN/UL 60950-1 contains requirements to prevent injury

or damage due to the following hazar ds:

 Electrical shock

 Energy hazards

 Fire

 Mechanical and heat hazards

 Radiation hazards

 Chemical hazards

On-board DC/DC converters and DC/DC regulators are

defined as component power supplies. As components

they cannot fully comply with the provisions of any safety

requirements without “Conditions of Acceptability”.

Clearance between conductors and between conductive

parts of the component power supply and conductors on

the board in the final product must meet the applicable

safety requirements. Certain conditions of acceptabilit y

apply for component po wer supplies with limited stand-off

(see Mechanical Information for further information). It is

the responsibility of the installer to ensure that the final

product housing these compo nents complies with the

requirements of all applicable safety standards and

regulations for the final product.

Component power supplies for general use should comply

with the requirements in IEC 60950-1, EN 60950-1 and

UL 60950-1 Safety of Information Technology Equipment.

There are other more product related standards, e.g.

IEEE 802.3 CSMA/CD (Ethernet) Access Method, and

ETS-300132-2 Power supply interface at the input to

telecommunications equi pment, operated by direct current

(dc), but all of these standards are based on

IEC/EN/UL 60950-1 with regards to safety.

Ericsson Power Modules DC/DC converters and DC/DC

regulators are UL 60950-1 recognized and certified in

accordance with EN 60950-1.

The flammability rating for all construction parts of the

products meet requirements for V-0 class material

according to IEC 60695-11-10, Fire hazard testing, test

flames – 50 W horizontal and vertical flame test methods.

The products should be installed in the end-use equipment,

in accordance with the requirements of the ultimate

application. Normally the output of the DC/DC converter is

considered as SELV (Safety Extra Low Voltage) and the

input source must be isolated by minimum Doub le or

Reinforced Insulation from the primar y circuit (AC mains) in

accordance with IEC/EN/UL 60950-1.

Isolated DC/DC converters

It is recommended that a slow blow fuse is to be used at

the input of each DC/DC converter. If an input filter is used

in the circuit the fuse should be placed in front of the input

filter.

In the rare event of a component problem that imposes a

short circuit on the input source, this fuse will provide the

following functions:

 Isolate the fault from the input power source so as

not to affect the operation of other parts of the

system.

 Protect the distribution wiring from excessive

current and power loss thus preventing hazardous

overheating.

The galvanic isolation is verifi ed in an electric strength test.

The test voltage (Viso) between input and output is

1500 Vdc or 2250 Vdc (refer to product specification).

24 V DC systems

The input voltage to the DC/DC converter is SELV (Safety

Extra Low Voltage) and the output remains SELV under

normal and abnormal operating conditions.

48 and 60 V DC systems

If the input voltage to the DC/DC converter i s 75 Vdc or

less, then the output remains SELV (Safety Extra Low

Voltage) under normal and a bnormal operating con ditions.

Single fault testing in the input power supply circuit should

be performed with the DC/DC converter connecte d to

demonstrate that the input voltage does not exceed

75 Vdc.

If the input power source circuit is a DC power system, the

source may be treated as a TNV-2 circuit and testing has

demonstrated compliance with SELV limits in accordance

with IEC/EN/UL60950-1.

Non-isolated DC/DC regulators

The input voltage to the DC/DC regulator is SELV (Safety

Extra Low Voltage) and the output remains SELV under

normal and abnormal operating conditions.

BMR 464 series POL Regulators

Input 4.5-14 V, Output up to 40 A / 132 W EN/LZT 146 435 R2A July 2011

Technical Speciﬁcation

BMR 464 series POL Regulators

Input 4.5-14 V, Output up to 40 A / 132 W EN/LZT 146 435 R2B August 2011

Technical Speciﬁcation

Absolute Maximum Ratings

Characteristics min typ max Unit

TP1 Operating temperature (see Thermal Consideration section) -40 120 °C

TS Storage temperature -40 125 °C

VI Input voltage (See Operating Information Section for input and output voltage relations) -0.3 16 V

Logic I/O voltage CTRL, SA0, SA1, SALERT, SCL, SDA, VSET, SYNC, GCB, PG -0.3 6.5 V

Ground voltage differential -S, PREF, GND -0.3 0.3 V

Analog pin voltage VO, +S, VTRK -0.3 6.5 V

Stress in excess of Absolute Maximum Ratings may cause permanent damage. Absolute Maximum Ratings, sometimes referred to as no destruction limits, are

normally tested with one parameter at a time exceeding the limits in the Electrical Specification. If exposed to stress above these limits, function and performance

may degrade in an unspecified manner.

Configuration File

This product is designed with a digital control circuit. The control circuit uses a configuration file which determines the functionality and performance of the product.

The Electrical Specification table shows parameter values of functionality and performance with the default configuration file, unless otherwise specified. The default

configuration file is designed to fit most application need with focus on high efficiency. If different characteristics are required it is possible to change the

configuration file to optimize certain performan ce characteristic s. In this Technical specification examples are included to show the possibilities with digital control.

See Operating Information section for information about trade offs when optimizing certain key performance characteristics.

Fundamental Circuit Diagram

Controller and digi tal interface

VIN VOUT

GND

Ci Co

VTRK

SA0

SCL

VSET

SALERT

SDA

SYNC

SA1

-S

GND

VOUT

PREF

GCB

CTRL

VIN

Ci=140 F Co =400 F

BMR 464 series POL Regulators

Input 4.5-14 V, Output up to 40 A / 132 W EN/LZT 146 435 R2A July 2011

Technical Speciﬁcation

BMR 464 series POL Regulators

Input 4.5-14 V, Output up to 40 A / 132 W EN/LZT 146 435 R2B August 2011

Technical Speciﬁcation

Electrical Specification BMR 464 0002, BMR 464 1002

TP1 = -30 to +95ºC, VI = 4.5 to 14 V, VI > VO + 1.0 V

Typical values given at: TP1 = +25°C, VI = 12.0 V, max IO, unless otherwise specified under Conditions.

Default configuration file, 190 10-CDA 102 0206/001.

External CIN = 470 µF/10 m, COUT = 470 µF/10 m. See Operating Information section for selection of capacitor types.

Sense pins are connected to the output pins.

Characteristics Conditions min typ max Unit

VI Input voltage rise time monotonic 2.4 V/ms

Output voltage without pin strap 1.2 V

Output voltage adjustment range 0.60 3.30 V

Output voltage adjustment including

margining 0.54 3.63 V

Output voltage set-point resolution ±0.025 % VO

Output voltage accuracy Includes, line, load, temp. -1 1 %

VO = 0.6 V 2

VO = 1.0 V 3

VO = 1.8 V 3

Line regulation

VO = 3.3 V 3

VO = 0.6 V 2

VO = 1.0 V 2

VO = 1.8 V 2

Load regulation; IO = 0 - 100%

VO = 3.3 V 2

VO = 0.6 V 15

VO = 1.0 V 20

VO = 1.8 V 25

VOac Output ripple & noise

CO=470 F (minimum external

capacitance). See Note 12 VO = 3.3 V 35

mVp-p

IO Output current 40 A

VO = 0.6 V 2.4

VO = 1.0 V 3.8

VO = 1.8 V 6.5

IS Static input current at max IO

VO = 3.3 V 12

Ilim Current limit threshold 41 54 A

VO = 0.6 V 10 A

VO = 1.0 V 9

VO = 1.8 V 9

Isc Short circuit

current RMS, hiccup mode,

See Note 3 VO = 3.3 V 7

VO = 0.6 V 84.6

VO = 1.0 V 89.7

VO = 1.8 V 93.3

50% of max IO

VO = 3.3 V 95.3

VO = 0.6 V 81.8

VO = 1.0 V 87.6

VO = 1.8 V 92.4

 Efficiency

max IO

VO = 3.3 V 95.0

VO = 0.6 V 5.4

VO = 1.0 V 5.7

VO = 1.8 V 6.3

Pd Power dissipation at max IO

VO = 3.3 V 7.5

VO = 0.6 V 1.1

VO = 1.0 V 1.1

VO = 1.8 V 1.4

Pli Input idling

power

(no load)

Default configuration:

Continues Conduction

Mode, CCM VO = 3.3 V 2.2

PCTRL Input standby

power Turned off with

CTRL-pin

Default configuration:

Monitoring enabled,

Precise timing enabled 180

BMR 464 series POL Regulators

Input 4.5-14 V, Output up to 40 A / 132 W EN/LZT 146 435 R2A July 2011

Technical Speciﬁcation

BMR 464 series POL Regulators

Input 4.5-14 V, Output up to 40 A / 132 W EN/LZT 146 435 R2B August 2011

Technical Speciﬁcation

Characteristics Conditions min typ max Unit

Ci Internal input capacitance 140 F

Co Internal output capacitance 400 F

Total external output capacitance See Note 10 470 30 000 F

COUT ESR range of capacitors

(per single capacitor) See Note 10 5 30 m

VO = 0.6 V 250

VO = 1.0 V 250

VO = 1.8 V 240

Vtr1

Load transient

peak voltage

deviation

Load step

25-75-25% of

max IO

Default configuration

di/dt = 2 A/s

CO=470 F (minimum

external capacitance)

see Note 13 VO = 3.3 V 220

VO = 0.6 V 150

VO = 1.0 V 100

VO = 1.8 V 100

ttr1

Load transient

recovery time,

Note 5

Load step

25-75-25% of

max IO

Default configuration

di/dt = 2 A/s

CO=470 F (minimum

external capacitance)

see Note 13 VO = 3.3 V 50

s

Switching frequency 320 kHz

Switching frequency range PMBus configurable 200-640 kHz

fs Switching frequency set-point accuracy -5 5 %

Control Circuit PWM Duty Cycle 5 95 %

Minimum Sync Pulse Width 150 ns

Synchronization Frequency Tolerance External clock source -13 13 %

UVLO threshold 3.85 V

UVLO threshold range PMBus configurable 3.85-14 V

Set point accuracy -150 150 mV

UVLO hysteresis 0.35 V

UVLO hysteresis range PMBus configurable 0-10.15 V

Delay 2.5 s

Input Under Voltage

Lockout,

UVLO

Fault response See Note 3 Automatic restart, 70ms

IOVP threshold 16 V

IOVP threshold range PMBus configurable 4.2-16 V

Set point accuracy -150 150 mV

IOVP hysteresis 1 V

IOVP hysteresis range PMBus configurable 0-11.8 V

Delay 2.5 s

Input Over Voltage

Protection,

IOVP

Fault response See Note 3 Automatic restart, 70ms

PG threshold 90 % VO

PG hysteresis 5 % VO

PG delay 10 ms

Power Good, PG,

See Note 2 PG delay range PMBus configurable 0-500 s

UVP threshold 85 % VO

UVP threshold range PMBus configurable 0-100 % VO

UVP hysteresis 5 % VO

OVP threshold 115 % VO

OVP threshold range PMBus configurable 100-115 % VO

UVP/OVP response time 25 s

UVP/OVP

response time range PMBus configurable 5-60 s

Output voltage

Over/Under Voltage

Protection,

OVP/UVP

Fault response See Note 3 Automatic restart, 70ms

OCP threshold 48 A

OCP threshold range PMBus configurable 0-50 A

Protection delay, See Note 4 5 Tsw

Protection delay range PMBus configurable 1-32 Tsw

Over Current

Protection,

OCP Fault response See Note 3 Automatic restart, 70ms

BMR 464 series POL Regulators

Input 4.5-14 V, Output up to 40 A / 132 W EN/LZT 146 435 R2A July 2011

Technical Speciﬁcation

BMR 464 series POL Regulators

Input 4.5-14 V, Output up to 40 A / 132 W EN/LZT 146 435 R2B August 2011

Technical Speciﬁcation

Ericsson Internal

PRODUCT SPECIFICATION 4 (18)

Prepared (also subject responsible if other) No.

EAB/FJB/GMF QLAANDR 2/1301-BMR 464 Uen

Approved Checked Date Rev Reference

EAB/FJB/GMF (Ksenia Harrisen) (EKAMAGN) 2011-07-07 A

Characteristics Conditions min typ max Unit

OTP threshold 120 C

OTP threshold range PMBus configurable -40…+120 C

OTP hysteresis 15 C

OTP hysteresis range PMBus configurable 0-160 C

Over Temperature

Protection,

OTP at P1

See Note 9 Fault response See Note 3 Automatic restart, 70ms

VIL Logic input low threshold 0.8 V

VIH Logic input high threshold SYNC, SA0, SA1, SCL, SDA,

GCB, CTRL, VSET 2 V

IIL Logic input low sink current CTRL 0.6 mA

VOL Logic output low signal level 0.4 V

VOH Logic output high signal level 2.25 V

IOL Logic output low sink current 4 mA

IOH Logic output high source current

SYNC, SCL, SDA, SALERT,

GCB, PG 2 mA

tset Setup time, SMBus See Note 1 300 ns

thold Hold time, SMBus See Note 1 250 ns

tfree Bus free time, SMBus See Note 1 2 ms

Cp Internal capacitance on logic pins 10 pF

Start-Up time See Note 11 30 ms

Delay duration 10

Delay duration range PMBus configurable 2-500000 ms

Default configuration:

CTRL controlled

Precise timing enabled ±0.25 ms

Output Voltage

Delay Time

See Note 6 Delay accuracy PMBus controlled

Precise timing disabled -0.25/+4 ms

Ramp duration 10

Ramp duration range PMBus configurable 0-200 ms

Output Voltage

Ramp Time Ramp time accuracy 100 µs

VTRK Input Bias Current VVTRK = 5.5 V 110 200 µA

VTRK Tracking Ramp Accuracy, Note 8 100% Tracking (VO - VVTRK) -100 100 mV

VTRK Regulation Accuracy 100% Tracking (VO - VVTRK) -1 1 %

Max current difference between products in a

sharing group 20

% of full

scale

Number of products in a current sharing group 7

READ_VIN vs VI 3 %

READ_VOUT vs VO 1 %

READ_IOUT vs IO IO =0-40 A, TP1 = 0 to +95°C

VI = 12 V ±2.5 A

Monitoring accuracy

READ_IOUT vs IO IO =0-40 A, TP1 = 0 to +95°C

VI = 4.5-14 V ±4 A

Note 1: See section I2C/SMBus Setup and Hold Times – Definitions.

Note 2: Monitorable over PMBus Interface.

Note 3: Continuous re-starts with 70 ms between each start. See Power Management section for additional fault response types.

Note 4: Tsw is the switching period.

Note 5: Within +/-3% of VO

Note 6: See section Soft-start Power Up.

Note 8: Tracking functionality is designed to follow a VTRK signal with slewrate < 2.4V/ms. For faster VTRK signals accuracy will depend on the regulator bandwidth.

Note 9: See section Over Temperature Protection (OTP).

Note 10: See section External Capacitors.

Note 11: See section Start-Up Procedure.

Note 12: See graph Output Ripple vs External Capacitance and Operating information section Output Ripple and Noise.

Note 13: See graph Load Transient vs. External Capacitance and Operating information section External Capacitors.

BMR 464 series POL Regulators

Input 4.5-14 V, Output up to 40 A / 132 W EN/LZT 146 435 R2A July 2011

Technical Speciﬁcation

BMR 464 series POL Regulators

Input 4.5-14 V, Output up to 40 A / 132 W EN/LZT 146 435 R2B August 2011

Technical Speciﬁcation

Typical Characteristics

Efficiency and Power Dissipation BMR 464 0002, BMR 464 1002

Efficiency vs. Output Current, VI=5 V Power Dissipation vs. Output Current, VI=5 V

100

0 8 16 24 32 40 [A]

[%]

0.6 V

1.0 V

1.8 V

3.3 V

0 8 16 24 32 40 [A]

[W]

0.6 V

1.0 V

1.8 V

3.3 V

Efficiency v s. load current and output voltage:

TP1 = +25°C. VI=5 V, fsw=320 kHz, CO=470 µF/10 m. Dissipated power vs. load current and output voltage:

TP1 = +25°C. VI=5 V, fsw=320 kHz, CO=470 µF/10 m.

Efficiency vs. Output Current, VI=12 V Power Dissipation vs. Output Current, VI=12 V

100

0 8 16 24 32 40 [A]

[%]

0,6 V

1,0 V

1,8 V

3,3 V

0 8 16 24 32 40 [A]

[W]

0,6 V

1,0 V

1,8 V

3,3 V

Efficiency v s. load current and output voltage at

TP1 = +25°C. VI=12 V, fsw=320 kHz, CO=470 µF/10 m. Dissipated power vs. load current and output voltage:

TP1 = +25°C. VI=12 V, fsw=320 kHz, CO=470 µF/10 m.

Efficiency vs. Output Current and

Switching Frequency Power Dissipation vs. Output Current and

Switching frequency

0 8 16 24 32 40 [A]

[%]

200

kHz

320

kHz

480

kHz

640

kHz

0 8 16 24 32 40 [A]

[W]

200

kHz

320

kHz

480

kHz

640

kHz

Efficiency vs. load current and switch frequency at

TP1 = +25°C. VI=12 V, VO=1.0 V, CO=470 µF/10 m

Default configuration except changed frequency

Dissipated power vs. load current and switch frequency at

TP1 = +25°C. VI=12 V, VO=1.0 V, CO=470 µF/10 m

Default configuration except changed frequency

BMR 464 series POL Regulators

Input 4.5-14 V, Output up to 40 A / 132 W EN/LZT 146 435 R2A July 2011

Technical Speciﬁcation

BMR 464 series POL Regulators

Input 4.5-14 V, Output up to 40 A / 132 W EN/LZT 146 435 R2B August 2011

Technical Speciﬁcation

Typical Characteristics

Load Transient BMR 464 0002, BMR 4 64 1002

Load Transient vs. External Capacitance, VO=1.0 V Load Transient vs. External Capacitance, VO=3.3 V

100

150

200

250

012345

[mF]

[mV]

Default

PID/NLR

Opt. PID, No

NLR

Default PI D,

Opt. NLR

Opt.

PID/NLR

100

150

200

250

012345

[mF]

[mV]

Default

PID/NLR

Opt. PID, No

NLR

Default PID,

Opt. NLR

Opt.

PID/NLR

Load transient peak voltage deviation vs. external capacitance.

Step-change (10-30-10 A). Parallel coupling of capacitors with 470 µF/10 m,

TP1 = +25°C. VI=12 V, VO=1.0 V, fsw=320 kHz, di/dt=2 A/µs

Load transient peak voltage deviation vs. external capacitance.

Step-change (10-30-10 A). Parallel coupling of capacitors with 470 µF/10 m,

TP1 = +25°C. VI=12 V, VO=3.3 V, fsw=320 kHz, di/dt=2 A/µs

Load transient vs. Switch Frequency Output Load Transient Response, Default PID/NLR

100

150

200

250

300

200 300 400 500 600 [kHz]

[mV]

Default

PID/NLR

Opt. PID,

No NLR

Default

PID, Opt.

NLR

Opt.

PID/NLR

Load transient peak voltage deviation vs. frequency.

Step-change (10-30-10 A).

TP1 = +25°C. VI=12 V, VO=1.0 V, CO=470 µF/10 m

Output voltage response to load current step-

change (10-30-10 A) at:

TP1 = +25°C, VI = 12 V, VO =1.0 V

di/dt=2 A/µs, fsw=320 kHz, CO=470 µF/10 m

Top trace: output voltage (200 mV/div.).

Bottom trace: load current (10 A/div.).

Time scale: (0.1 ms/div.).

BMR 464 series POL Regulators

Input 4.5-14 V, Output up to 40 A / 132 W EN/LZT 146 435 R2A July 2011

Technical Speciﬁcation

BMR 464 series POL Regulators

Input 4.5-14 V, Output up to 40 A / 132 W EN/LZT 146 435 R2B August 2011

Technical Speciﬁcation

Ericsson Internal

PRODUCT SPECIFICATION 7 (18)

Prepared (also subject responsible if other) No.

EAB/FJB/GMF QLAANDR 2/1301-BMR 464 Uen

Approved Checked Date Rev Reference

EAB/FJB/GMF (Ksenia Harrisen) (EKAMAGN) 2011-07-07 A

Typical Characteristics

Output Current Characteristic BMR 464 0002, BMR 464 1002

Output Current Derating, VO=0.6 V Output Current Derating, VO=1.0 V

40 60 80 100 120 [°C]

[A]

3.0 m/s

2.0 m/s

1.0 m/s

0.5 m/s

Nat. Conv.

40 60 80 100 120 [°C]

[A]

3.0 m/s

2.0 m/s

1.0 m/s

0.5 m/s

Nat. Conv.

vailable load current vs. ambient air temperature and airflow at

VO=0.6V, VI = 12 V. See Thermal Consideration section. Available load current vs. ambient air temperature and airflow at

VO=1.0V, VI = 12 V. See Thermal Consideration section.

Output Current Derating, VO=1.8 V Output Current Derating, VO=3.3 V

40 60 80 100 120 [°C]

[A]

3.0 m/s

2.0 m/s

1.0 m/s

0.5 m/s

Nat. Conv.

40 60 80 100 120 [°C]

[A]

3.0 m/s

2.0 m/s

1.0 m/s

0.5 m/s

Nat. Conv.

vailable load current vs. ambient air temperature and airflow at

VO=1.8V, VI = 12 V. See Thermal Consideration section.

vailable load current vs. ambient air temperature and airflow at

VO=3.3V, VI = 12 V. See Thermal Consideration section.

Current Limit Characteristics, VO=1.0 V Current Limit Characteristics, VO=3.3 V

0,0

0,3

0,6

0,9

1,2

40 42 44 46 48 50 [A]

[V]

4.5V

5 V

12 V

14 V

0,0

1,0

2,0

3,0

4,0

40 42 44 46 48 50 [A]

[V]

4.5V

5 V

12 V

14 V

Output voltage vs. load current at TP1 = +25°C. VO=1.0V. Output voltage vs. load current at TP1 = +25°C. VO=3.3V.

BMR 464 series POL Regulators

Input 4.5-14 V, Output up to 40 A / 132 W EN/LZT 146 435 R2A July 2011

Technical Speciﬁcation

BMR 464 series POL Regulators

Input 4.5-14 V, Output up to 40 A / 132 W EN/LZT 146 435 R2B August 2011

Technical Speciﬁcation

Typical Characteristics

Output Voltage BMR 464 0002, BMR 464 1002

Output Ripple & Noise, VO=1.0 V Output Ripple & Noise, VO=3.3 V

Output voltage ripple at:

TP1 = +25°C, VI = 12 V, CO=470 µF/10 m

IO = 40 A

Trace: output voltage (10 mV/div.).

Time scale: (2 µs/div.). Output voltage ripple at:

TP1 = +25°C, VI = 12 V, CO=470 µF/1 0 m

IO = 40 A

Trace: output voltage (10 mV/div.).

Time scale: (2 µs/div.).

Output Ripple vs. Input Voltage Output Ripple vs. Frequency

5791113

[V]

[mV

pk-pk

]

0.6 V

1.0 V

1.8 V

3.3 V

100

200 250 300 350 400 450 500 550 600 [kHz]

[mVpk-pk]

0.6 V

1.0 V

1.8 V

3.3 V

Output voltage ripple Vpk-pk at: T P1 = +25°C, CO=470 µF/10 m, IO = 40 A. Output voltage ripple Vpk-pk at: TP1 = +25°C, VI = 12 V, CO=470 µF/10 m,

IO = 40 A. Default configuration except changed frequency.

Output Ripple vs. External Capacitance Load regulation, VO=1.0V

012345

[mF]

[mV]

0.6V

1.0 V

1.8 V

3.3 V

0,990

0,995

1,0 0 0

1,0 0 5

1,0 10

0 8 16 24 32 40 [A]

[V]

4.5V

5 V

12 V

14 V

Output voltage ripple Vpk-pk at: T P1 = +25°C, VI = 12 V. IO = 40 A. Parallel coupling

of capacitors with 470 µF/10 m, Load regulation at Vo=1.0 V at: TP1 = +25°C, CO=470 µF/10 m

BMR 464 series POL Regulators

Input 4.5-14 V, Output up to 40 A / 132 W EN/LZT 146 435 R2A July 2011

Technical Speciﬁcation

BMR 464 series POL Regulators

Input 4.5-14 V, Output up to 40 A / 132 W EN/LZT 146 435 R2B August 2011

Technical Speciﬁcation

Typical Characteristics

Start-up and shut-down BMR 464 0002, BMR 464 1002

Start-up by input source Shut-down by input source

Start-up enabled by connecting VI at:

TP1 = +25°C, VI = 12 V, VO = 1.0 V

CO = 470 µF/10 m, IO = 40 A

Top trace: output voltage (0.5 V/div.).

Bottom trace: input voltage (5 V/div.).

Time scale: (20 ms/div.).

Shut-down enabled by disconnecting VI at:

TP1 = +25°C, VI = 12 V, VO = 1.0 V

CO = 470 µF/10 m, IO = 40 A

Top trace: output voltage (0.5 V/div).

Bottom trace: input voltage (5 V/div.).

Time scale: (2 ms/div.).

Start-up by CTRL signal Shut-down by CTRL signal

Start-up by enabling CTRL signal at:

TP1 = +25°C, VI = 12 V, VO = 1.0 V

CO = 470 µF/10 m, IO = 40 A

Top trace: output voltage (0.5 V/div.).

Bottom trace: CTRL signal (5 V/div.).

Time scale: (20 ms/div.).

Shut-down enabled by disconnecting VI at:

TP1 = +25°C, VI = 12 V, VO = 1.0 V

CO = 470 µF/10 m, IO = 40 A

Top trace: output voltage (0.5 V/div).

Bottom trace: CTRL signal (5 V/div.).

Time scale: (2 ms/div.).

BMR 464 series POL Regulators

Input 4.5-14 V, Output up to 40 A / 132 W EN/LZT 146 435 R2A July 2011

Technical Speciﬁcation

BMR 464 series POL Regulators

Input 4.5-14 V, Output up to 40 A / 132 W EN/LZT 146 435 R2B August 2011

Technical Speciﬁcation

Electrical Specification BMR 464 2002 (SIP)

TP1 = -30 to +95ºC, VI = 4.5 to 14 V, VI > VO + 1.0 V

Typical values given at: TP1 = +25°C, VI = 12.0 V, max IO, unless otherwise specified under Conditions.

Default configuration file, 190 10-CDA 102 0259/001.

External CIN = 470 µF/10 m, COUT = 470 µF/10 m. See Operating Information section for selection of capacitor types.

Sense pins are connected to the output pins.

Characteristics Conditions min typ max Unit

VI Input voltage rise time monotonic 2.4 V/ms

Output voltage without pin strap 1.2 V

Output voltage adjustment range 0.60 3.30 V

Output voltage adjustment including

margining 0.54 3.63 V

Output voltage set-point resolution ±0.025 % VO

Output voltage accuracy Includes, line, load, temp. -1 1 %

VO = 0.6 V 2

VO = 1.0 V 2

VO = 1.8 V 2

Line regulation

VO = 3.3 V 2

VO = 0.6 V 2

VO = 1.0 V 2

VO = 1.8 V 2

Load regulation; IO = 0 - 100%

VO = 3.3 V 2

VO = 0.6 V 20

VO = 1.0 V 25

VO = 1.8 V 30

VOac Output ripple & noise

CO=470 F (minimum external

capacitance). See Note 12 VO = 3.3 V 45

mVp-p

IO Output current 40 A

VO = 0.6 V 2.5

VO = 1.0 V 3.8

VO = 1.8 V 6.5

IS Static input current at max IO

VO = 3.3 V 11.6

Ilim Current limit threshold 41 54 A

VO = 0.6 V 9 A

VO = 1.0 V 8

VO = 1.8 V 8

Isc Short circuit

current RMS, hiccup mode,

See Note 3 VO = 3.3 V 6

VO = 0.6 V 85.8

VO = 1.0 V 90.5

VO = 1.8 V 93.7

50% of max IO

VO = 3.3 V 95.5

VO = 0.6 V 81.4

VO = 1.0 V 87.5

VO = 1.8 V 92.1

 Efficiency

max IO

VO = 3.3 V 94.7

VO = 0.6 V 5.5

VO = 1.0 V 5.7

VO = 1.8 V 6.2

Pd Power dissipation at max IO

VO = 3.3 V 7.3

VO = 0.6 V 0.9

VO = 1.0 V 0.9

VO = 1.8 V 1.1

Pli Input idling

power

(no load)

Default configuration:

Continues Conduction

Mode, CCM VO = 3.3 V 1.7

PCTRL Input standby

power Turned off with

CTRL-pin

Default configuration:

Monitoring enabled,

Precise timing enabled 170

BMR 464 series POL Regulators

Input 4.5-14 V, Output up to 40 A / 132 W EN/LZT 146 435 R2A July 2011

Technical Speciﬁcation

BMR 464 series POL Regulators

Input 4.5-14 V, Output up to 40 A / 132 W EN/LZT 146 435 R2B August 2011

Technical Speciﬁcation

Characteristics Conditions min typ max Unit

Ci Internal input capacitance 140 F

Co Internal output capacitance 400 F

Total external output capacitance See Note 10 470 30 000 F

COUT ESR range of capacitors

(per single capacitor) See Note 10 5 30 m

VO = 0.6 V 240

VO = 1.0 V 240

VO = 1.8 V 220

Vtr1

Load transient

peak voltage

deviation

Load step

25-75-25% of

max IO

Default configuration

di/dt = 2 A/s

CO=470 F (minimum

external capacitance)

see Note 13 VO = 3.3 V 200

VO = 0.6 V 120

VO = 1.0 V 100

VO = 1.8 V 80

ttr1

Load transient

recovery time,

Note 5

Load step

25-75-25% of

max IO

Default configuration

di/dt = 2 A/s

CO=470 F (minimum

external capacitance)

see Note 13 VO = 3.3 V 40

s

Switching frequency 320 kHz

Switching frequency range PMBus configurable 200-640 kHz

fs Switching frequency set-point accuracy -5 5 %

Control Circuit PWM Duty Cycle 5 95 %

Minimum Sync Pulse Width 150 ns

Synchronization Frequency Tolerance External clock source -13 13 %

UVLO threshold 3.85 V

UVLO threshold range PMBus configurable 3.85-14 V

Set point accuracy -150 150 mV

UVLO hysteresis 0.35 V

UVLO hysteresis range PMBus configurable 0-10.15 V

Delay 2.5 s

Input Under Voltage

Lockout,

UVLO

Fault response See Note 3 Automatic restart, 70ms

IOVP threshold 16 V

IOVP threshold range PMBus configurable 4.2-16 V

Set point accuracy -150 150 mV

IOVP hysteresis 1 V

IOVP hysteresis range PMBus configurable 0-11.8 V

Delay 2.5 s

Input Over Voltage

Protection,

IOVP

Fault response See Note 3 Automatic restart, 70ms

PG threshold 90 % VO

PG hysteresis 5 % VO

PG delay 10 ms

Power Good, PG,

See Note 2 PG delay range PMBus configurable 0-500 s

UVP threshold 85 % VO

UVP threshold range PMBus configurable 0-100 % VO

UVP hysteresis 5 % VO

OVP threshold 115 % VO

OVP threshold range PMBus configurable 100-115 % VO

UVP/OVP response time 25 s

UVP/OVP

response time range PMBus configurable 5-60 s

Output voltage

Over/Under Voltage

Protection,

OVP/UVP

Fault response See Note 3 Automatic restart, 70ms

OCP threshold 48 A

OCP threshold range PMBus configurable 0-50 A

Protection delay, See Note 4 5 Tsw

Protection delay range PMBus configurable 1-32 Tsw

Over Current

Protection,

OCP Fault response See Note 3 Automatic restart, 70ms

BMR 464 series POL Regulators

Input 4.5-14 V, Output up to 40 A / 132 W EN/LZT 146 435 R2A July 2011

Technical Speciﬁcation

BMR 464 series POL Regulators

Input 4.5-14 V, Output up to 40 A / 132 W EN/LZT 146 435 R2B August 2011

Technical Speciﬁcation

Characteristics Conditions min typ max Unit

OTP threshold 120 C

OTP threshold range PMBus configurable -40…+120 C

OTP hysteresis 15 C

OTP hysteresis range PMBus configurable 0-160 C

Over Temperature

Protection,

OTP at P1

See Note 9 Fault response See Note 3 Automatic restart, 70ms

VIL Logic input low threshold 0.8 V

VIH Logic input high threshold SYNC, SA0, SA1, SCL, SDA,

GCB, CTRL, VSET 2 V

IIL Logic input low sink current CTRL 0.6 mA

VOL Logic output low signal level 0.4 V

VOH Logic output high signal level 2.25 V

IOL Logic output low sink current 4 mA

IOH Logic output high source current

SYNC, SCL, SDA, SALERT,

GCB, PG 2 mA

tset Setup time, SMBus See Note 1 300 ns

thold Hold time, SMBus See Note 1 250 ns

tfree Bus free time, SMBus See Note 1 2 ms

Cp Internal capacitance on logic pins 10 pF

Start-Up time See Note 11 30 ms

Delay duration 10

Delay duration range PMBus configurable 2-500000 ms

Default configuration:

CTRL controlled

Precise timing enabled ±0.25 ms

Output Voltage

Delay Time

See Note 6 Delay accuracy PMBus controlled

Precise timing disabled -0.25/+4 ms

Ramp duration 10

Ramp duration range PMBus configurable 0-200 ms

Output Voltage

Ramp Time Ramp time accuracy 100 µs

VTRK Input Bias Current VVTRK = 5.5 V 110 200 µA

VTRK Tracking Ramp Accuracy, Note 8 100% Tracking (VO - VVTRK) -100 100 mV

VTRK Regulation Accuracy 100% Tracking (VO - VVTRK) -1 1 %

Max current difference between products in a

sharing group 20

% of full

scale

Number of products in a current sharing group 7

READ_VIN vs VI 3 %

READ_VOUT vs VO 1 %

READ_IOUT vs IO IO =0-40 A, TP1 = 0 to +95°C

VI = 12 V ±2.5 A

Monitoring accuracy

READ_IOUT vs IO IO =0-40 A, TP1 = 0 to +95°C

VI = 4.5-14 V ±4 A

Note 1: See section I2C/SMBus Setup and Hold Times – Definitions.

Note 2: Monitorable over PMBus Interface.

Note 3: Continuous re-starts with 70 ms between each start. See Power Management section for additional fault response types.

Note 4: Tsw is the switching period.

Note 5: Within +/-3% of VO

Note 6: See section Soft-start Power Up.

Note 8: Tracking functionality is designed to follow a VTRK signal with slewrate < 2.4V/ms. For faster VTRK signals accuracy will depend on the regulator bandwidth.

Note 9: See section Over Temperature Protection (OTP).

Note 10: See section External Capacitors.

Note 11: See section Start-Up Procedure.

Note 12: See graph Output Ripple vs External Capacitance and Operating information section Output Ripple and Noise.

Note 13: See graph Load Transient vs. External Capacitance and Operating information section External Capacitors.

BMR 464 series POL Regulators

Input 4.5-14 V, Output up to 40 A / 132 W EN/LZT 146 435 R2A July 2011

Technical Speciﬁcation

BMR 464 series POL Regulators

Input 4.5-14 V, Output up to 40 A / 132 W EN/LZT 146 435 R2B August 2011

Technical Speciﬁcation

Ericsson Internal

PRODUCT SPECIFICATION 13 (18)

Prepared (also subject responsible if other) No.

EAB/FJB/GMF QLAANDR 2/1301-BMR 464 Uen

Approved Checked Date Rev Reference

EAB/FJB/GMF (Ksenia Harrisen) (EKAMAGN) 2011-07-07 A

Typical Characteristics

Efficiency and Power Dissipation BMR 464 2002 (SIP)

Efficiency vs. Output Current, VI=5 V Power Dissipation vs. Output Current, VI=5 V

100

0 8 16 24 32 40 [A]

[%]

0.6 V

1.0 V

1.8 V

3.3 V

0 8 16 24 32 40 [A]

[W]

0.6 V

1.0 V

1.8 V

3.3 V

Efficiency v s. load current and output voltage:

TP1 = +25°C. VI=5 V, fsw=320 kHz, CO=470 µF/10 m. Dissipated power vs. load current and output voltage:

TP1 = +25°C. VI=5 V, fsw=320 kHz, CO=470 µF/10 m.

Efficiency vs. Output Current, VI=12 V Power Dissipation vs. Output Current, VI=12 V

100

0 8 16 24 32 40 [A]

[%]

0,6 V

1,0 V

1,8 V

3,3 V

0 8 16 24 32 40 [A]

[W]

0,6 V

1,0 V

1,8 V

3,3 V

Efficiency v s. load current and output voltage at

TP1 = +25°C. VI=12 V, fsw=320 kHz, CO=470 µF/10 m. Dissipated power vs. load current and output voltage:

TP1 = +25°C. VI=12 V, fsw=320 kHz, CO=470 µF/10 m.

Efficiency vs. Output Current and

Switching Frequency Power Dissipation vs. Output Current and

Switching frequency

0 8 16 24 32 40 [A]

[%]

200

kHz

320

kHz

480

kHz

640

kHz

0 8 16 24 32 40 [A]

[W]

200

kHz

320

kHz

480

kHz

640

kHz

Efficiency vs. load current and switch frequency at

TP1 = +25°C. VI=12 V, VO=1.0 V, CO=470 µF/10 m

Default configuration except changed frequency

Dissipated power vs. load current and switch frequency at

TP1 = +25°C. VI=12 V, VO=1.0 V, CO=470 µF/10 m

Default configuration except changed frequency

BMR 464 series POL Regulators

Input 4.5-14 V, Output up to 40 A / 132 W EN/LZT 146 435 R2A July 2011

Technical Speciﬁcation

BMR 464 series POL Regulators

Input 4.5-14 V, Output up to 40 A / 132 W EN/LZT 146 435 R2B August 2011

Technical Speciﬁcation

Typical Characteristics

Load Transient BMR 464 2002 (SIP)

Load Transient vs. External Capacitance, VO=1.0 V Load Transient vs. External Capacitance, VO=3.3 V

100

150

200

250

300

01234

[mF]

[mV]

Default

PID/NLR

Opt. PID,

No NLR

Default PI D,

Opt. NLR

Opt.

PID/NLR

10 0

15 0

200

250

300

01234

[mF]

[mV]

Default

PID/NLR

Opt. PI D,

No NL R

De fa u l t PID,

Opt. NLR

Opt.

PID/NLR

Load transient peak voltage deviation vs. external capacitance.

Step-change (10-30-10 A). Parallel coupling of capacitors with 470 µF/10 m,

TP1 = +25°C. VI=12 V, VO=1.0 V, fsw=320 kHz, di/dt=2 A/µs

Load transient peak voltage deviation vs. external capacitance.

Step-change (10-30-10 A). Parallel coupling of capacitors with 470 µF/10 m,

TP1 = +25°C. VI=12 V, VO=3.3 V, fsw=320 kHz, di/dt=2 A/µs

Load transient vs. Switch Frequency Output Load Transient Response, Default PID/NLR

100

150

200

250

300

350

400

200 300 400 500 600 [kHz]

[mV]

Default

PID/NLR

Opt. PID,

No NLR

Default

PID, Opt.

NLR

Opt.

PID/NLR

Load transient peak voltage deviation vs. frequency.

Step-change (10-30-10 A).

TP1 = +25°C. VI=12 V, VO=1.0 V, CO=470 µF/10 m

Output voltage response to load current step-

change (10-30-10 A) at:

TP1 = +25°C, VI = 12 V, VO =1.0 V

di/dt=2 A/µs, fsw=320 kHz, CO=470 µF/10 m

Top trace: output vo ltage (200 mV/div.).

Bottom trace: load current (10 A/div.).

Time scale: (0.1 ms/div.).

BMR 464 series POL Regulators

Input 4.5-14 V, Output up to 40 A / 132 W EN/LZT 146 435 R2A July 2011

Technical Speciﬁcation

BMR 464 series POL Regulators

Input 4.5-14 V, Output up to 40 A / 132 W EN/LZT 146 435 R2B August 2011

Technical Speciﬁcation

Ericsson Internal

PRODUCT SPECIFICATION 15 (18)

Prepared (also subject responsible if other) No.

EAB/FJB/GMF QLAANDR 2/1301-BMR 464 Uen

Approved Checked Date Rev Reference

EAB/FJB/GMF (Ksenia Harrisen) (EKAMAGN) 2011-07-07 A

Typical Characteristics

Output Current Characteristic BMR 464 2002 (SIP)

Output Current Derating, VO=0.6 V Output Current Derating, VO=1.0 V

40 60 80 100 120 [°C]

[A]

3.0 m/s

2.0 m/s

1.0 m/s

0.5 m/s

Nat. Conv.

40 60 80 100 120 [°C]

[A]

3.0 m/s

2.0 m/s

1.0 m/s

0.5 m/s

Nat. Conv.

vailable load current vs . ambient air temperature and airflow at

VO=0.6V, VI = 12 V. See Thermal Consideration section. Available load current vs. ambient air temperature and airflow at

VO=1.0V, VI = 12 V. See Thermal Consideration section.

Output Current Derating, VO=1.8 V Output Current Derating, VO=3.3 V

40 60 80 100 120 [°C]

[A]

3.0 m/s

2.0 m/s

1.0 m/s

0.5 m/s

Nat. Conv.

40 60 80 100 120 [°C]

[A]

3.0 m/s

2.0 m/s

1.0 m/s

0.5 m/s

Nat. Conv.

vailable load current vs . ambient air temperature and airflow at

VO=1.8V, VI = 12 V. See Thermal Consideration section.

vailable load current vs . ambient air temperature and airflow at

VO=3.3V, VI = 12 V. See Thermal Consideration section.

Current Limit Characteristics, VO=1.0 V Current Limit Characteristics, VO=3.3 V

0,0

0,3

0,6

0,9

1,2

40 42 44 46 48 50 [A]

[V]

4.5V

5 V

12 V

14 V

0,0

1,0

2,0

3,0

4,0

40 42 44 46 48 50 [A]

[V]

4.5V

5 V

12 V

14 V

Output voltage vs. load current at TP1 = +25°C. VO=1.0V. Output voltage vs. load current at TP1 = +25°C. VO=3.3V.

BMR 464 series POL Regulators

Input 4.5-14 V, Output up to 40 A / 132 W EN/LZT 146 435 R2A July 2011

Technical Speciﬁcation

BMR 464 series POL Regulators

Input 4.5-14 V, Output up to 40 A / 132 W EN/LZT 146 435 R2B August 2011

Technical Speciﬁcation

Typical Characteristics

Output Voltage BMR 464 2002 (SIP)

Output Ripple & Noise, VO=1.0 V Output Ripple & Noise, VO=3.3 V

Output voltage ripple at:

TP1 = +25°C, VI = 12 V, CO=470 µF/10 m

IO = 40 A

Trace: output voltage (10 mV/div.).

Time scale: (2 µs/div.). Output voltage ripple at:

TP1 = +25°C, VI = 12 V, CO=470 µF/1 0 m

IO = 40 A

Trace: output voltage (10 mV/div.).

Time scale: (2 µs/div.).

Output Ripple vs. Input Voltage Output Ripple vs. Frequency

5791113

[V]

[mV

pk-pk

]

0.6 V

1.0 V

1.8 V

3.3 V

100

200 250 300 350 400 450 500 550 600 [kHz]

[mV

pk-pk

]

0.6 V

1.0 V

1.8 V

3.3 V

Output voltage ripple Vpk-pk at: T P1 = +25°C, CO=470 µF/10 m, IO = 40 A. Output voltage ripple Vpk-pk at: TP1 = +25°C, VI = 12 V, CO=470 µF/10 m,

IO = 40 A. Default configuration except changed frequency.

Output Ripple vs. External Capacitance Load regulation, VO=1.0V

01234

[mF]

[mV]

0.6V

1.0 V

1.8 V

3.3 V

0,990

0,995

1,000

1,005

1,010

0 8 16 24 32 40 [A]

[V]

4.5V

5 V

12 V

14 V

Output voltage ripple Vpk-pk at: T P1 = +25°C, VI = 12 V. IO = 40 A. Parallel coupling

of capacitors with 470 µF/10 m, Load regulation at Vo=1.0 V at: TP1 = +25°C, CO=470 µF/10 m

BMR 464 series POL Regulators

Input 4.5-14 V, Output up to 40 A / 132 W EN/LZT 146 435 R2A July 2011

Technical Speciﬁcation

BMR 464 series POL Regulators

Input 4.5-14 V, Output up to 40 A / 132 W EN/LZT 146 435 R2B August 2011

Technical Speciﬁcation

Typical Characteristics

Start-up and shut-down BMR 464 2002 (SIP)

Start-up by input source Shut-down by input source

Start-up enabled by connecting VI at:

TP1 = +25°C, VI = 12 V, VO = 1.0 V

CO = 470 µF/10 m, IO = 40 A

Top trace: output voltage (0.5 V/div.).

Bottom trace: input voltage (5 V/div.).

Time scale: (20 ms/div.).

Shut-down enabled by disconnecting VI at:

TP1 = +25°C, VI = 12 V, VO = 1.0 V

CO = 470 µF/10 m, IO = 40 A

Top trace: output voltage (0.5 V/div).

Bottom trace: input voltage (5 V/div.).

Time scale: (2 ms/div.).

Start-up by CTRL signal Shut-down by CTRL signal

Start-up by enabling CTRL signal at:

TP1 = +25°C, VI = 12 V, VO = 1.0 V

CO = 470 µF/10 m, IO = 40 A

Top trace: output voltage (0.5 V/div.).

Bottom trace: CTRL signal (5 V/div.).

Time scale: (20 ms/div.).

Shut-down enabled by disconnecting VI at:

TP1 = +25°C, VI = 12 V, VO = 1.0 V

CO = 470 µF/10 m, IO = 40 A

Top trace: output voltage (0.5 V/div).

Bottom trace: CTRL signal (5 V/div.).

Time scale: (2 ms/div.).

BMR 464 series POL Regulators

Input 4.5-14 V, Output up to 40 A / 132 W EN/LZT 146 435 R2A July 2011

Technical Speciﬁcation

BMR 464 series POL Regulators

Input 4.5-14 V, Output up to 40 A / 132 W EN/LZT 146 435 R2B August 2011

Technical Speciﬁcation

EMC Specification

Conducted EMI measured according to test set-up an d

standard MIL std 0141 - 58000.

The fundamental switching frequency is 320 kHz for BMR464

at VI = 12.0 V, max IO.

Conducted EMI Input terminal value (typical for default

configuration)

EMI without filter

Test set-up

Layout Recommendations

The radiated EMI performanc e of the product will depend on

the PWB layout and ground l ayer design. It is also important to

consider the stand-off of the product. If a ground layer is us ed,

it should be connected to the output of the product and the

equipment ground or chassis.

A ground layer will increase the stray capacitance in the PWB

and improve the high frequency EMC performance.

Output Ripple and Noise

Output ripple and noise is measured accord ing to figure below.

A 50 mm conductor works as a small inductor forming together

with the two capacitances a damped filter.

Output ripple and noise test set-up.

Operating information

Power Management O verview

This product is equipped with a PMBus interface. The product

incorporates a wide rang e of readable and configurable power

management features that are simple to implement

with a minimum of external components. Additional ly, the

product includes protection features that continuously

safeguard the load from dama ge due to unexpected system

faults. A fault is also shown as an alert on the SALERT pin.

The following product parameters can continuously be

monitored by a host: Input voltage, output voltage/current,

and internal temperature. If the monitoring is not needed it can

be disabled and the prod uct enters a low power mode reducing

the power consumption. The protection features are not

affected.

The product is delivered with a default configuration suitable

for a wide range operation in terms of input v oltage, output

voltage, and load. The configuration is stored in an internal

Non-Volatile Memory (NVM). All po wer managem ent functions

can be reconfigured using the PMBus interface. Please contact

your local Ericsson Power Modules representative for design

support of custom configurations or appropriate SW tools for

design and down-load of your own configur ations.

Input Voltage

The input voltage range, 4.5 - 14 V, makes the product

easy to use in intermediate bus applications when powered

by a non-regulated bus conve r ter or a regulated bus converter.

See Ordering Information for input voltage range.

Input Under Voltage Lockout, UVLO

The product monitors the input voltage and will turn-on and

turn-off at configured levels. The default turn-on input voltage

level setting is 4.20 V, whereas the correspo nding turn-off input

voltage level is 3.85 V. Hence, the default hysteresis between

turn-on and turn-off input voltage is 0.35 V. Once an in put turn-

Vout Tantalum

Capacitor Ceramic

Capacitor

S

S 0.1 µF 10 µF

Load

50 mm conductor

50 mm conductor BNC-contact to

oscillosco

Output

Capacitor

470 µF//10 m

GND

BMR 464 series POL Regulators

Input 4.5-14 V, Output up to 40 A / 132 W EN/LZT 146 435 R2A July 2011

Technical Speciﬁcation

BMR 464 series POL Regulators

Input 4.5-14 V, Output up to 40 A / 132 W EN/LZT 146 435 R2B August 2011

Technical Speciﬁcation

off condition occurs, the device can respon d in a number of

ways as follows:

1. Continue operating without interruption. The unit will

continue to operate as long as the input voltage can be

supported. If the input voltage continues to fall, there will

come a point where the unit will cease to operate.

2. Continue operating for a given delay period, followed by

shutdown if the fault still exists. The device will remain in

shutdown until instructed to restart.

3. Initiate an immediate shutdown until the fault has been

cleared. The user can select a specific number of retry

attempts.

The default response from a turn-off is an immediate shutdown

of the device. The device will continuously check for the

presence of the fault condition. If the fault condition is no

longer present, the product will be re-enabled. The turn-on and

turn-off levels and response can be reconfigured using the

PMBus interface.

Remote Control

The product is equipped with a

remote control function, i.e., the

CTRL pin. The remote control

can be connected to either the

primary negative inp ut

connection (GND) or an external

voltage (Vext), which is a 3 - 5 V

positive supply voltage in

accordance to the SMBus

Specification version 2.0.

The CTRL function allows the product to be turned on/off by an

external device like a semiconductor or mechanical switch. By

default the product will turn on when the CTRL pin is left open

and turn off when the CTRL pin is applied to GND. The CTRL

pin has an internal pull-up resistor. When the CTRL pin is left

open, the voltage generated o n the CTRL pin is max 5.5 V.

If the device is to be synchronized to an external clock source,

the clock frequency must be stable prior to asserting the CTRL

pin.

The product can also be configure d usin g the PMBus interface

to be “Always on”, or turn on/off can be performed with PMBus

commands.

Input and Output Impedance

The impedance of both the input source and the load will

interact with the impedance of the product. It is important that

the input source has low characteristic imp edance. The

performance in some applications can be enhanced by

addition of external capacitance as described under External

Decoupling Capacitors. If the input voltage source contains

significant inductance, the additio n a cap acitor with low ESR at

the input of the product will ensure stable operation.

External Capacitors

Input capacitors:

The input ripple RMS current in a buck co nverter is equal to

Eq. 1.





DDII loadinputRMS  1,

where is the output load current and is the duty cycle.

The maximum load ripp le current becomes

load

I. The ripple

current is divided into three parts, i.e., currents in the input

source, external input capacitor, and inter na l input capacitor.

How the current is divided depends on the impedance of the

input source, ESR and capacitance values in the capacitors. A

minimum capacitance of 300 µF with low ESR is

recommended. The ripple current rating of the capacitors must

follow Eq. 1. For high-performance/transie nt applications or

wherever the input source performance is degraded, additional

low ESR ceramic type capacitors at the inp ut is recomme nded.

The additional input low ESR capacitance above the minimum

level insures an optimized performance.

Output capacitors:

When powering loads with significant d ynamic current

requirements, the voltage regulation at the point of load can be

improved by addition of decoupling ca pacitors at the load.

The most effective technique is to locate low ESR ceramic and

electrolytic capacitors as close to the load as possible, using

several capacitors in parallel to lower the effective ESR. The

ceramic capacitors will handle high-frequency dynamic load

changes while the electrolytic capacitors are used to handle

low frequency dynamic load changes. Ceramic capacitors will

also reduce high frequenc y noise at the load.

It is equally important to use low resistance and low inductance

PWB layouts and cabling.

External decoupling cap acitors are a part of the control loop of

the product and may affect the stability margins.

Stable operation is guaranteed for the following total

capacitance in the output decoupling capacitor bank where

Eq. 2.









30000 ,470, maxmin  CCCO µF.

The decoupling capac itor bank should consist of capacitors

which has a capacitance value larger than and has

an range of min

CC 

ESR

Eq. 3.



 

30 ,5 , maxmin 



ESRESRESR m

The control loop stabilit y margins are limited by the minimum

time constant of the capacitors. Hence, the time constant

of the capacitors should follow Eq. 4.

min



Eq. 4. s 35.2

minminmin



 ESRC

This relation can be used if yo ur preferred capacitors have

parameters outside the above stated ranges in Eq. 2 and Eq.3.

 If the capacitors capacitance value is min

CC  one must

use at least Ncapacitors where









C

Nmin and C

ESRESR min

min

.

 If the ESR value is max

ESR one must use at least N

capacitors of that type where

ESR 

CTRL

GND

Vext

BMR 464 series POL Regulators

Input 4.5-14 V, Output up to 40 A / 132 W EN/LZT 146 435 R2A July 2011

Technical Speciﬁcation

BMR 464 series POL Regulators

Input 4.5-14 V, Output up to 40 A / 132 W EN/LZT 146 435 R2B August 2011

Technical Speciﬁcation









ESR

ESR and





max

Cmin

.

 If the

ESR value is min

ESR the capacitance value

should be ESR 

ESR

CC min

min .

For a total capacitance outside the above stated range or

capacitors that do not follow the stated above requir ements

above a re-design of the control loop parameters will be

necessary for robust dynamic operation and stability.

Control Loop Compensation

The product is configured with a robust control loop

compensation which allows for a wide range operation of input

and output voltages and capa citive loads as defined in the

section External Decoupling Capacitors. For an application

with a specific input voltage, output voltage, and ca pacitive

load, the control loop can be optimized for a robust and stable

operation and with an improved load transient response. This

optimization will minimize the amount of required output

decoupling capacitors for a giv en load transient requirement

yielding an optimized cost an d minimized board space. T he

control loop parameters can be reconfi gured using the PMBus

interface.

Load Transient Respo nse Optimization

The product incorporates a Non-Linear transient Respo nse,

NLR, loop that decreases the response time and the output

voltage deviation during a load transient. The NLR results i n a

higher equivalent loop bandwidth than is possible using a

traditional linear control loop. The product is pre-configured

with appropriate NLR settin gs for robust and stable operation

for a wide range of input voltage and a cap acitive load range

as defined in the section External Decoupling Capacitors. For

an application with a specific input voltage, output voltage, and

capacitive load, the NLR confi guration can be optimized for a

robust and stable operation and with an improved load

transient response. This will also reduce the amount of output

decoupling capacitors and yield a reduced cost. However, the

NLR slightly reduces the efficiency. In order to obtain maximal

energy efficiency the load transient requirement has to be met

by the standard control loop compensation a nd the decoupling

capacitors. The NLR settings can be reconfigured using the

PMBus interface.

Remote Sense

The product has remote sense that can be u s ed to

compensate for voltage drops between the output and the

point of load. The sense traces should be located close to the

PWB ground layer to reduce noise susceptibilit y. Due to

derating of internal output capacitance the voltage drop should

be kept below . A large voltage

drop will impact the electrical performance of the regulator. If

the remote sense is not needed +S should be connected to

VOUT and S should be connected to GND.

2/)5.5( OUTDROPMAX VV 

Output Voltage Adjust using Pin-strap Resistor

Using an external Pin-strap

resistor, RSET, the output

voltage can be set in the

range 0.6 V to 3.3 V at 28

different levels shown in the

table below. The resistor

should be applied between

the VSET pin and the PREF

pin.

RSET also sets the maximum output voltage, see section

“Output Voltage Range Limitation”. T he resistor is sensed only

during product start-up. Changin g the resisto r value during

normal operation will not change the output voltage. The input

voltage must be at least 1 V larger than the output voltage i n

order to deliver the correct output voltage. See Ordering

Information for output voltage rang e.

The following table sho ws recommended resistor values for

RSET. Maximum 1% tolerance resistors are required.

VOUT [V] RSET[k] VOUT [V] RSET[k]

0.60 10 1.50 46.4

0.65 11 1.60 51.1

0.70 12.1 1.70 56.2

0.75 13.3 1.80 61.9

0.80 14.7 1.90 68.1

0.85 16.2 2.00 75

0.90 17.8 2.10 82.5

0.95 19.6 2.20 90.9

1.00 21.5 2.30 100

1.05 23.7 2.50 110

1.10 26.1 3.00 121

1.15 28.7 3.30 133

1.20 31.6

1.25 34.8

1.30 38.3

1.40 42.2

The output voltage and the maximum o utput voltage can be pin

strapped to three fixed values b y connecting the VSET pin

according to the table below.

VOUT [V] VSET

0.60 Shorted to PREF

1.2 Open “high impedance”

2.5 Logic High, GND as reference

VSET

RSET

PREF

BMR 464 series POL Regulators

Input 4.5-14 V, Output up to 40 A / 132 W EN/LZT 146 435 R2A July 2011

Technical Speciﬁcation

BMR 464 series POL Regulators

Input 4.5-14 V, Output up to 40 A / 132 W EN/LZT 146 435 R2B August 2011

Technical Speciﬁcation

Output Voltage Adjust using PMBus

The output voltage of the product can be configured using the

PMBus interface in the range 0.54 to 3.63. S ee Ordering

Information for output voltage rang e.

Output Voltage Range Limitation

The output voltage range configurable by the PMBus interface

is limited by the pin-strap resistor RSET. RSET sets the maximum

output voltage to approximate ly 110% of the nominal output

value, , where

calibration offset is max 70 mV. A PMBus command can not

set the output voltage higher than . This protects the

load from an over voltage due to an acci dental wrong PMBus

command.

offsetncalibratioVV OUTOUTMAX _1.1 

OUTMAX

Over Voltage Protection (OVP)

The product includes over volt age limiting circuitry for

protection of the load. The default OVP limit is 15% above the

nominal output voltage. If the output voltage exceeds the OVP

limit, the product can respond in different ways:

1. Initiate an immediate shutdown until the fault has been

cleared. The user can select a specific number of retry

attempts.

2. Turn off the high-side MOSFET and turn on t he low-side

MOSFET. The low-side MOSFET remains ON until the

device attempts a restart, i.e. the output voltage is pulled to

ground level (crowbar function).

The default response from an overvoltage fault is to

immediately shut do wn as in 2. The device will continuously

check for the presence of the fault condition, and when the

fault condition no longer exists the device will be re-enabled.

For continuous OVP when operating from an external clock for

synchronization, the only allowed respons e is an immediate

shutdown. The OVP limit and fault response can be

reconfigured using the PMBus interface.

Under Voltage Protection (UVP)

The product includes output under vo ltage limiting circuitry for

protection of the load. The default UVP limit is 15% be low the

nominal output voltage. T he UVP limit can be reconfigured

using the PMBus interface.

Power Good

The product provides a Power Good (PG) flag in the Status

Word register that indicates the output voltage is within a

specified tolerance of its target level an d no fault condition

exists. If specified in section Connections, the product also

provides a PG signal output. The PG pin is active high and by

default open-drain but may also be configured as push-pull via

the PMBus interface.

By default, the PG signal will be asserted if the output is within

-10%/+15% of the target voltage. These limits may be changed

via the PMBus interface. A PG delay period is defined as the

time from when all conditions within the product for asserting

PG are met to when the PG signal is actually asserted. By

default, the PG delay is set equal to the soft-start ramp time

setting. Therefore, if the soft-start ramp time is set to 10 ms,

the PG delay will be set to 10 ms. The PG delay may be set

independently of the soft-start ramp using the PMBus interface.

Switching Frequency

The fundamental switching frequency is 320 kHz, which yields

optimal power efficiency. The switching frequency can be set

to any value between 200 kHz and 640 kHz using the PMBus

interface. The switching frequency will change the

efficiency/power dissipation, load transient response and

output ripple. For optimal control loop performance the control

loop must be re-designed when changing the switching

frequency.

Synchronization

Synchronization is a feature that allows multiple products to be

synchronized to a common frequency. Synchronized products

powered from the same bus eliminate beat frequencies

reflected back to the input supply, and also reduces EMI

filtering requirements. Eliminating the slow beat frequencies

(usually <10 kHz) allows the EMI filter to be designed to

attenuate only the synchronization frequency. Synchronization

can also be utilized for phase spreading, described in section

Phase Spreading.

The products can be synchronized with an external oscillator or

one product can be configur ed with the SYNC pin as a SYNC

Output working as a master driving the synchronization. All

others on the same synchronization bus should be configured

with SYNC Input or SYNC Auto Detect (Default configuration)

for correct operation. When the SYNC pin is config ured in auto

detect mode the product will automatically ch eck for a clock

signal on the SYNC pin.

Phase Spreading

When multiple products share a common DC input supply,

spreading of the switching clock phase between the products

can be utilized. T his dramatically reduces input capacitance

requirements and efficiency losses, since the peak curre nt

drawn from the input supply is effectively spread out over the

whole switch period. This requires that the products are

synchronized. Up to 16 different phases can be used.

The phase spreading of the product can be configured using

the PMBus interface.

Parallel Operation (Current Sharing)

Paralleling multiple products can be used to increase the

output current capability of a single power rail. By connecting

the GCB pins of each device and configuring the devices as a

current sharing rail, the units will share the c urrent equally,

enabling up to 100% utiliz ation of the current capability for

each device in the current shar ing rail. The product uses a low-

bandwidth, first-order digital current sharing by aligning the

output voltage of the slave dev ices to del iver the same current

as the master device. Artificial droop resistance is added to the

output voltage path to control the slope of the loa d lin e curve,

calibrating out the phys ical parasitic mismatches due to power

train components and PWB layout. Up to 7 devices can be

configured in a given current shari ng group.

BMR 464 series POL Regulators

Input 4.5-14 V, Output up to 40 A / 132 W EN/LZT 146 435 R2A July 2011

Technical Speciﬁcation

BMR 464 series POL Regulators

Input 4.5-14 V, Output up to 40 A / 132 W EN/LZT 146 435 R2B August 2011

Technical Speciﬁcation

Phase Adding and Shedding fo r Parallel Operation

During periods of light load ing, it may be beneficial to disable

one or more phases (modules) in order to el iminate the current

drain and switching losses associated with those phases,

resulting in higher efficiency. The product offers the ability to

add and drop phases (modules) using a PMBus command in

response to an observed load current chan ge. All phases

(modules) in a current share rail ar e considered active prior to

the current sharing rail ramp to power-good. Phases can be

dropped after power-good is reached. An y member of the

current sharing rail can be dropped. If the reference module is

dropped, the remaining active module with the lowest member

position will become the ne w referenc e. Additionally, any

change to the number of members of a current sharing rail will

precipitate autonomous phase distribution within the rail where

all active phases realign their phase position based on their

order within the number of active members. If the members of

a current sharing rail are forced to shut down due to an

observed fault, all members of the rail will attempt to re-start

simultaneously after the fault has cleared.

Adaptive Diode Emulation

Most power converters use synchronous rectification to

optimize efficiency over a wide range of input and output

conditions. However, at light loads the synchronous MOSFET

will typically sink current and introduce additional energy

losses associated with higher peak inductor currents, resulting

in reduced efficiency. Adaptive diode emulation mode turns off

the low-side FET gate drive at low load currents to prevent the

inductor current from going negative, reduci ng the energy

losses and increasing overall efficiency. Diode emul ation is not

available for current sharing groups. Note: the overall

bandwidth of the product may be reduced when in diode

emulation mode. It is recommended that diode emulation is

disabled prior to applying significant load steps. The diode

emulation mode can be configured using the PMBus interface.

Adaptive Frequency and Pulse Skip Control

Since switching losses contribute to the efficiency of the power

converter, reducing the switching frequency will reduce the

switching losses and incr ease efficiency. The product includes

an Adaptive Frequency C ontrol mode, which effectively

reduces the observed s witchi ng frequency as the load

decreases. Adaptive frequency mode is only available while

the device is operating within Adaptive Diode Emulation Mode.

As the load current is decreased, diode emulation mode

decreases the Synch-FET on-time to prevent negative inductor

current from flowing. As the load is decreased further, the

Switch-FET pulse width will be gin to decrease while

maintaining the programmed frequ ency, fPROG (set by the

FREQ_SWITCH command). Once the Switch-FET pulse width

(D) reaches 50% of the nominal duty cycle, DNOM (determined

by VI and VO), the switching frequency will start to decrease

according to the following equation:

Eq. 5.



MIN

NOM

MINPROG

sw f

Dff

Df 













2.

Disabling a minimum Sync h-FET makes the product also pulse

skip which reduces the power loss further.

It should be noted that adaptive frequency mode is not

available for current sharing groups and is not allowed when

the device is placed in auto-detect mode and a clock source is

present on the SYNC pin, or if the device is outputting a clock

signal on its SYNC pin. The adaptive frequency an d pulse skip

modes can be configured usin g the PMBus interface.

Efficiency Optimized Dead Time Control

The product utilizes a closed l oop algorithm to optimize the

dead-time applied between the gate drive signals for the switch

and synch FETs. The algorithm constantly adjusts the

deadtime non-overlap to minimize the duty cycle, thus

maximizing efficiency. This algorithm will null out deadtime

differences due to component variation, temperature and

loading effects. The algorithm can be configured via the

PMBus interface.

Over Current Protection (OCP)

The product includes current limiting circuitry for protection at

continuous overload. The following OCP response options ar e

available:

1. Initiate a shutdown and attempt to restart an infinite number

of times with a preset delay period between attempts.

2. Initiate a shutdown and attempt to restart a preset number

of times with a preset delay period

3. Continue operating for a given delay period, followed by

shutdown if the fault still exists.

4. Continue operating thro ugh the fault (this could result in

permanent damage to the product).

5. Initiate an immediate shutdown.

The default response from an over current fault is an

immediate shutdo wn of the device. The device will

continuously check for the presence of the fault condition, and

if the fault condition no longer exists the device will be re-

enabled.The load distribution should be designed for the

maximum output short circuit current specified. The OCP limit

and response of the product can be reconfigured using the

PMBus interface.

Note for BMR464.

When the ratio VO/VI is below 0.07 (e.g. VI = 12 V and VO= 0.6

V), and the default configuration file is used, the OCP limit

threshold may be below specified minimum value. If the

specified maximum output current is reached under such ope-

rating conditions, it is recommended to incr ease the OCP limit.

Start-up Procedure

The product follows a specific internal start-up procedure after

power is applied to the VIN pin:

1. Status of the address and output voltage pin-strap pins are

checked and values associated with the pin settings are

loaded.

BMR 464 series POL Regulators

Input 4.5-14 V, Output up to 40 A / 132 W EN/LZT 146 435 R2A July 2011

Technical Speciﬁcation

BMR 464 series POL Regulators

Input 4.5-14 V, Output up to 40 A / 132 W EN/LZT 146 435 R2B August 2011

Technical Speciﬁcation

2. Values stored in the Ericsson default non-v olatile memory

are loaded. This overwrites any previously loaded values.

3. Values stored in the user non-volatil e memory are loaded.

This overwrites any previously loaded values.

Once this process is completed and the start-up time has

passed (see Electrical Specification), the product is ready to be

enabled using the CTRL pin. The product is also ready to

accept commands via the PMBus interface, which will

overwrite any values loaded during the start-up procedure.

Soft-start Power Up

The soft-start control introduces a time-delay before allowing

the output voltage to rise. Once the start-up time has passed

and the output has been enabled, the device requires

approximately 2 ms before its output volta ge ma y be allowed to

start its ramp-up process. If a soft-start delay period less than 2

ms has been configured the device will default to a 2 ms delay

period. If a delay period greater than 2 ms is configured, the

device will wait for the configured delay period prior to starting

to ramp its output. After the delay period has expired, the

output will begin to ramp towards its target voltage according to

the configured soft-start ramp time.

The default settings for the soft-start delay period and the soft-

start ramp time is 10 ms. Hence, power-up is completed within

20 ms in default configuration using remote control. Precise

timing reduces the delay time variations and is by default

activated. The soft-start power up of the product can be

reconfigured using the PMBus interface.

Output Voltage Sequencing

A group of products may be configured to power up in a

predetermined sequence. This feature is especial ly useful

when powering advanced processors, FPGAs, and ASICs that

require one supply to reac h its operating voltage prior to

another. Multi-product sequencin g can b e achieved by

configuring the start delay and rise time of each device through

the PMBus interface and by using the CTRL start signal.

VOUT

Illustration of Output Voltage Sequencing.

Voltage Tracking

The product integrates a lossless tracking scheme that allows

its output to track a voltage that is applied to the VTRK pin with

no external components required. During ramp-up, the output

voltage follows the VTRK voltage u ntil the preset output

voltage level is met. The product offers two modes of tracking

as follows:

1. Coincident. This mode configures the prod uct to ramp its

output voltage at the same rate as the voltage applied to

the VTRK pin.

VOUT

MASTER

SLAVE

Illustration of Coincident Voltage Tracking.

2. Ratiometric. This mode configures the pro du ct to ramp its

output voltage at a rate that is a percentage of the voltag e

applied to the VTRK pin. The default settin g is 50%, but a

different tracking ratio may be set by an external resistive

voltage divider or through the PMBus interface.

VOUT

MASTER

SLAVE

Illustration of Ratiometric Voltage Tracking

The master device in a tracking group is defined as the device

that has the highest target output voltage within the gr oup. This

master device will control the ramp rate of all tracking devices

and is not configured for tracking mode. All of the CTRL pins in

the tracking group must be connected and driven by a single

logic source. It should be noted that current sharing gro ups

that are also configured to track another voltage do not offer

pre-bias protection; a minimu m load should therefore be

enforced to avoid the output voltag e from being held up by an

outside force.

Voltage Margining Up/Down

The product can adjust its output higher or lower than its

nominal voltage setting in ord er to determin e whether the load

device is capable of operatin g over its specified supply voltage

range. This provides a conven ient metho d for dynamically

BMR 464 series POL Regulators

Input 4.5-14 V, Output up to 40 A / 132 W EN/LZT 146 435 R2A July 2011

Technical Speciﬁcation

BMR 464 series POL Regulators

Input 4.5-14 V, Output up to 40 A / 132 W EN/LZT 146 435 R2B August 2011

Technical Speciﬁcation

testing the operation of the load circuit over its supply margin

or range. It can also be used to verify the function of supply

voltage supervisors. Margin limits of the nominal output voltage

±5% are default, but the margin limits can be reconfigured

using the PMBus interface.

Pre-Bias Startup Capability

Pre-bias startup often occurs in complex digital systems when

current from another power source is fed back through a dual-

supply logic component, such as FPGAs or ASICs. The

BMR464 product family incorporates synchronous rectifi ers,

but will not sink current during startup, or turn off, or whenever

a fault shuts down the product in a pre-bias condition. Pre-bias

protection is not offered for current sharing groups that also

have voltage tracking enabled .

Group Communication Bus

The Group Communication Bus, GCB, is used to communicate

between products. T his dedi cated bus provides the

communication channel between devices for features such as

sequencing, fault spreading, and current sharing. The GCB

solves the PMBus data rate limitation. The GCB pin on all

devices in an applicatio n should be connected together. For

robust communication it is recommended that 27 ohm series

resistors are placed, close to the GCB pin, between each

device and the common GCB connection. A pull-up resistor is

required on the common GCB in order to gua rantee the rise

time as follows:

Eq. 6 sCR GCBGCB





1 ,

where is the pull up resistor value and is the bus

loading. The pull-up resistor s hould be tied to to an external 3.3

V or 5 V supply voltage, which should be pr esent prior to or

during power-up.

GCB

RGCB

Fault spreading

The product can be configur ed to broadcast a fault event over

the GCB to the other devices in the group. When a non-

destructive fault occurs and the device is configured to shut

down on a fault, the device will shut down and broadcast the

fault event over the GCB. The other devices on the GCB will

shut down together if configured to do so, and will attempt to

re-start in their prescribed order if configured to do so.

Over Temperature Protection (OTP)

The products are protected from thermal overload by an

internal over temperature shut down circuit. When TP1 as

defined in thermal consideration section exceeds 120°C the

product will shut down. The product will make contin uous

attempts to start up and resume normal operation

automatically when the temperature h as dropped >15°C below

the over temperature threshold. The specified OTP level and

hysteresis are valid for worst case operation regarding cooling

conditions, input voltage and output voltage. This means the

OTP level and hysteresis in many cases will be lower. The

OTP level, hysteresis, and fault response of the product can be

reconfigured using the PMBus interface. T he fault respons e

can be configured as follows:

1. Initiate a shutdown and attempt to restart an infinite number

of times with a preset delay period between attempts

(default configuration).

2. Initiate a shutdown and attempt to restart a preset number

of times with a preset delay period between attempts.

3. Continue operating for a given delay period, followed by

shutdown if the fault still exists.

4. Continue operating thro ugh the fault (this could result in

permanent damage to the power sup pl y).

5. Initiate an immediate shutdown.

Optimization examples

This product is designed with a digital control circuit. The

control circuit uses a configuration file which determines the

functionality and performa nce of the product. It is possible to

change the configuration file to optimiz e certain performance

characteristics. In the table below is a schematic view on how

to change different configuration par ameters in order to

achieve an optimization towards a wanted performance.

 Increase

 No change

 Decrease

Config.

parameters Switching

frequency

Control

loop

bandwidth NLR

threshold

Diode

emulation

(DCM) Min.

pulse

Optimized

performence

Maximize

efficiency    Enable Disable

Minimize

ripple ampl.    Enable

disable

Enable

disable

Improve

load

transient

response    Disable Disable

Minimize

idle power

loss    Enable Enable

VO = 0.6 V 1.1

VO = 1.0 V 1.1

VO = 1.8 V 1.4

Default

configuration:

Continues

Conduction

Mode, CCM VO = 3.3 V 2.2

VO = 0.6 V 0.21

VO = 1.0 V 0.21

VO = 1.8 V 0.21

Pli Input idling

power

(no load) DCM,

Discontinues

Conduction

Mode

(diode

emulation) VO = 3.3 V 0.21

BMR 464 series POL Regulators

Input 4.5-14 V, Output up to 40 A / 132 W EN/LZT 146 435 R2A July 2011

Technical Speciﬁcation

BMR 464 series POL Regulators

Input 4.5-14 V, Output up to 40 A / 132 W EN/LZT 146 435 R2B August 2011

Technical Speciﬁcation

VO = 0.6 V 0.42

VO = 1.0 V 0.42

VO = 1.8 V 0.55

DCM with

Adaptive

Frequency

and Minimum

Pulse

Enabled VO = 3.3 V 0.81

VO = 0.6 V 0.19

VO = 1.0 V 0.19

VO = 1.8 V 0.20

Pli Input idling

power

(no load)

DCM with

Adaptive

Frequency

and Minimum

Pulse

Disabled VO = 3.3 V 0.20

Default

configuration:

Monitoring

enabled,

Precise

timing

enabled

180 mW

Monitoring

enabled,

Precise

timing

disabled

120 mW

PCTRL Input

standby

power

Turned off

with

CTRL-pin

Low power

mode:

Monitoring

disabled,

Precise

timing

disabled

85 mW

VO = 0.6 V 250

VO = 1.0 V 250

VO = 1.8 V 240

Default

configuration

di/dt = 2 A/s

CO=470 F VO = 3.3 V 220

VO = 0.6 V 120

VO = 1.0 V 120

VO = 1.8 V 120

Vtr1

Load

transient

peak

voltage

deviation

Load step

25-75-25%

of max IO

Optimized

PID and NLR

configuration

di/dt = 2 A/s

CO=470 F VO = 3.3 V 110

VO = 0.6 V 150

VO = 1.0 V 100

VO = 1.8 V 100

Default

configuration

di/dt = 2 A/s

CO=470 F VO = 3.3 V 50

VO = 0.6 V 75

VO = 1.0 V 50

VO = 1.8 V 50

ttr1

Load

transient

recovery

time

Load step

25-75-25%

of max IO

Optimized

PID and NLR

configuration

di/dt = 2 A/s

CO=470 F VO = 3.3 V 25

Efficiency vs. Output Current and Switching frequency

0 8 16 24 32 40 [A]

[%]

200

kHz

320

kHz

480

kHz

640

kHz

Efficiency vs. load current and switching frequency at

TP1 = +25°C. VI=12 V, VO=1.0 V, CO=470 µF/10  m

Default configuration except changed frequency

Power Dissipation vs. Output Current and Switching frequency

0 8 16 24 32 40 [A]

[W]

200

kHz

320

kHz

480

kHz

640

kHz

Dissipated power vs. load current and switching frequency at

TP1 = +25°C. VI=12 V, VO=1.0 V, CO=470 µF/10 m

Default configuration except changed frequency

Output Ripple vs. Switching frequency

100

200 250 300 350 400 450 500 550 600 [kHz]

[mVpk-pk]

0.6 V

1.0 V

1.8 V

3.3 V

Output voltage ripple Vpk-pk at: T P1 = +25°C, VI = 12 V, CO=470 µF/10 m,

IO = 40 A resistive load. Default configuration except changed frequency.

BMR 464 series POL Regulators

Input 4.5-14 V, Output up to 40 A / 132 W EN/LZT 146 435 R2A July 2011

Technical Speciﬁcation

BMR 464 series POL Regulators

Input 4.5-14 V, Output up to 40 A / 132 W EN/LZT 146 435 R2B August 2011

Technical Speciﬁcation

Load transient vs. Switching frequency

100

150

200

250

300

200 300 400 500 600 [kHz]

[mV]

Default

PID/NLR

Opt. PID,

No NLR

Default

PID, Opt.

NLR

Opt.

PID/NLR

Load transient peak voltage deviation vs. frequency.

Step-change (10-30-10 A).

TP1 = +25°C. VI=12 V, VO=1.0 V, CO=470 µF/10 m

Load Transient vs. Decoupling Capacitance, VO=1.0 V

100

150

200

250

012345

[mF]

[mV]

Default

PID/NLR

Opt. PID, No

NLR

Default PI D,

Opt. NLR

Opt.

PID/NLR

Load transient peak voltage deviation vs. decoupling capacitance.

Step-change (10-30-10 A). Parallel coupling of capacitors with 470 µF/10 m,

TP1 = +25°C. VI=12 V, VO=1.0 V, fsw=320 kHz, di/dt=2 A/µs

Load Transient vs. Decoupling Capacitance, VO=3.3 V

100

150

200

250

012345

[mF]

[mV]

Default

PID/NLR

Opt. PID, No

NLR

Default PI D,

Opt. NLR

Opt.

PID/NLR

Load transient peak voltage deviation vs. decoupling capacitance.

Step-change (10-30-10 A). Parallel coupling of capacitors with 470 µF/10 m,

TP1 = +25°C. VI=12 V, VO=3.3 V, fsw=320 kHz, di/dt=2 A/µs

Output Load Transient Response, Default PID/NLR

Output voltage response to load current step-

change (10-30-10 A) at:

TP1 = +25°C, VI = 12 V, VO =1.0 V

di/dt=2 A/µs, fsw=320 kHz, CO=470 µF/10 m

Default PID Control Loop and NLR

Top trace: output voltage (200 mV/div.).

Bottom trace: load current (10 A/div.).

Time scale: (0.1 ms/div.).

Output Load Transient Response, Optimized PID, no NLR

Output voltage response to load current step-

change (10-30-10 A) at:

TP1 = +25°C, VI = 12 V, VO =1.0 V

di/dt=2 A/µs, fsw=320 kHz, CO=470 µF/10 m

Optimized PID Control Lo op and no NLR

Top trace: output voltage (200 mV/div.).

Bottom trace: load current (10 A/div.).

Time scale: (0.1 ms/div.).

Output Load Transient Response, Optimized NLR

Output voltage response to load current step-

change (10-30-10 A) at:

TP1 = +25°C, VI = 12 V, VO =1.0 V

di/dt=2 A/µs, fsw=320 kHz, CO=470 µF/10 m

Default PID Control Loop and optimized NLR

Top trace: output voltage (200 mV/div.).

Bottom trace: load current (10 A/div.).

Time scale: (0.1 ms/div.).

BMR 464 series POL Regulators

Input 4.5-14 V, Output up to 40 A / 132 W EN/LZT 146 435 R2A July 2011

Technical Speciﬁcation

BMR 464 series POL Regulators

Input 4.5-14 V, Output up to 40 A / 132 W EN/LZT 146 435 R2B August 2011

Technical Speciﬁcation

Thermal Consideration

General

The product is designed to operate in different thermal

environments and sufficient cooling must be provided to

ensure reliable operation.

Cooling is achieved mainl y by conduction, from the pins to the

host board, and convection, which is dependant on the airflow

across the product. Increased airflow enhances the cooling of

the product.

The Output Current Derating graph foun d in the Output section

for each model provides the available output current vs.

ambient air temperature and air vel ocity at specified VI.

The product is tested on a 254 x 254 mm, 35 µm (1 oz), test

board mounted vertically in a wind tunn el with a cross-section

of 608 x 203 mm. The test board has 8 layers.

Proper cooling of the product can be verified by measuring the

temperature at positions P1 and P2. The temperature at these

positions should not exceed the max values provided in the

table below.

Note that the max value is the absolute maximum rating

(non destruction) and that the electrical Output data is

guaranteed up to TP1 +85°C.

See Design Note 019 for further information.

Definition of product operating temperature

The product operating temper atures are used to monitor the

temperature of the product, and proper thermal conditions can

be verified by measuring the tem perature at positions P1 and

P2. The temperature at these positions (TP1, TP2) should not

exceed the maximum temper atures in the table below. The

number of measurement points may vary with different thermal

design and topology. Temperatures above maximum TP1,

measured at the reference point P1 are not allowed and may

cause permanent damage.

Position Description Max Temp.

P1 Reference point, L1,

inductor 120º C

P2 N1, control circuit 120º C

Temperature positions and air flow direction.

SIP version

Temperature positions and air flow direction.

Definition of reference temperature TP1

The reference temperature is used to monitor the temperature

limits of the product. Temperature above maximum TP1,

measured at the reference point P1 is not allowed and may

cause degradation or permanent damage to the product. TP1 is

also used to define the temperature range for normal operating

conditions. TP1 is defined by the design and us ed to guarantee

safety margins, proper oper ation and high reliability ot the

product.

AIR FLOW

Top view Bottom view

P1 P2

AIR FLOW

Bottom view

Top view

P1 P2

BMR 464 series POL Regulators

Input 4.5-14 V, Output up to 40 A / 132 W EN/LZT 146 435 R2A July 2011

Technical Speciﬁcation

BMR 464 series POL Regulators

Input 4.5-14 V, Output up to 40 A / 132 W EN/LZT 146 435 R2B August 2011

Technical Speciﬁcation

Ericsson Internal

PRODUCT SPECIFICATION 11 (14)

Prepared (also subject responsible if other) No.

EAB/FJB/GMF QLAANDR 30/1301-BM R 464 Uen

Approved Checked Date Rev Reference

EAB/FJB/GMF (Ksenia Harrisen) (EKAMAGN) 2011-08-17 B

Connections

Pin layout, top view (component placement for illustration only).

Pin Designation Function

1A, 1B VIN Input Voltage

2A, 2B GND Power Ground

3A, 3B VOUT Output Voltage

4A VTRK Voltage Tracking input

4B PREF Pin-strap reference

5A +S Positive sense

5B −S Negative sense

6A SA0 PMBus address pinstrap 0

6B GCB Group Communication Bus

7A SCL PMBus Clock

7B SDA PMBus Data

8A VSET Output voltage pinstrap

8B SYNC Synchronization I/O

9A SALERT PMBus Alert

9B CTRL Remote Control

10A PG Power Good

10B SA1 PMBus address pinstrap 1

PWB layout considerations

The pinstrap resistors, Rset, and RSA0//RSA1 should be placed

as close to the product as possible to minimize loops that may

pick up noise.

Avoid current carrying planes under the pinstrap resistors and

the PMBus signals.

The capacitor CI (or capacitors implementing it) should be

placed as close to the input pins as possible.

Capacitor CO (or capacitors implementing it) should be placed

close to the load.

Connections (SIP version)

Pin layout, side view (component placement for illustration only).

Pin Designation Function

1A, 1B VIN Input Voltage

2A, 2B GND Power Ground

3A, 3B VOUT Output Voltage

4A +S Positive sense

4B −S Negative sense

5A VSET Output voltage pinstrap

5B VTRK Voltage Tracking input

6A SALERT PMBus Alert

6B SDA PMBus Data

7A SCL PMBus Clock

7B SA1 PMBus address pinstrap 1

8A SA0 PMBus address pinstrap 0

8B SYNC Synchronization I/O

9A PG Power Good

9B CTRL Remote Control

10A GCB Group Communication Bus

10B PREF Pin-strap reference

Unused input pins

Unused SDA, SCL and GCB pins should still have pull-up

resistors as specified. Unused VTRK or SYNC pins should be

left unconnected or connected to the PREF pin. Unuse d CTRL

pin can be left open due to internal pull-up.

VSET and SA0/SA1 pins must have pinstrap resistors as

specified.

BMR 464 series POL Regulators

Input 4.5-14 V, Output up to 40 A / 132 W EN/LZT 146 435 R2B August 2011

Technical Speciﬁcation

Ericsson Internal

PRODUCT SPECIFICATION 12 (14)

Prepared (also subject responsible if other) No.

EAB/FJB/GMF QLAANDR 30/1301-BM R 464 Uen

Approved Checked Date Rev Reference

EAB/FJB/GMF (Ksenia Harrisen) (EKAMAGN) 2011-07-07 A

Typical Application Circuit

Standalone with PMBus communication

BMR 464 series POL Regulators

Input 4.5-14 V, Output up to 40 A / 132 W EN/LZT 146 435 R2A July 2011

Technical Speciﬁcation

BMR 464 series POL Regulators

Input 4.5-14 V, Output up to 40 A / 132 W EN/LZT 146 435 R2B August 2011

Technical Speciﬁcation

Typical Application Circuit (SIP version)

4A4B

10A10B

BMR 464

+VIN

Load

GND

CTRL

3.0

5.0 V

SDA

SCL

SALERT

DGND

RSET

RSA0

RSA1

RPU1

RPU2

RPU3

GND

Standalone with PMBus communication. Top side view of product footprint.

BMR 464 series POL Regulators

Input 4.5-14 V, Output up to 40 A / 132 W EN/LZT 146 435 R2A July 2011

Technical Speciﬁcation

BMR 464 series POL Regulators

Input 4.5-14 V, Output up to 40 A / 132 W EN/LZT 146 435 R2B August 2011

Technical Speciﬁcation

PMBus Interface

This product provides a PMBus digital interfa ce that enables

the user to configure many aspects of the device operation as

well as to monitor the input and output voltages, output current

and device temperature. The product can be used with any

standard two-wire I2C or SMBus host devic e. In addition, the

module is compatible with PMBus version 1.1 and includes an

SALERT line to help mitigate bandwidth limitations related to

continuous fault monitoring. The product supports 100 kHz

bus clock frequency onl y. The PMBus signals, SCL, SDA and

SALERT require passive pull-up resistors as stated in the

SMBus Specification. Pull-up resistors are required to

guarantee the rise time as follows:

Eq. 7 sCR pP





1

where Rp is the pull-up resistor value and Cp is the bus

loading, the maximum allowed bus load is 400 pF. The pull-up

resistor should be tied to an external supply voltage in range

from 2.7 to 5.5V, which should be present prior to or during

power-up. If the proper power supply is not available, voltage

dividers may be applied. Note that in this case, the resistance

in the equation above corresponds to parallel connection of

the resistors forming the voltage divider.

Monitoring via PMBus

It is possible to monitor a wide variety of different parameters

through the PMBus interface. Fault conditions can be

monitored using the SALERT pin, which will be asserted when

any number of pre-co nfigured fault or warning conditio ns

occur. It is also possible to continuously monitor one or more

of the power conversion parameters including but not limited

to the following:

 Input voltage

 Output voltage

 Output current

 Internal junction temperature

 Switching frequency

 Duty cycle

Snap Shot Parameter Capture

This product offers a special feature that enables the us er to

capture parametric data during normal operation or following a

fault. The following parameters are stored:

 Input voltage

 Output voltage

 Output current

 Internal junction temperature

 Switching frequency

 Duty cycle

 Status registers

The Snapshot feature enables the user to read the parameters

via the PMBus interface during normal opera t ion, although it

should be noted that reading the 22 bytes will occupy the bus

for some time. The Snapshot enables the user to store the

snapshot parameters to Flash memory in response to a

pending fault as well as to read the stored data from Flash

memory after a fault has occurred. Automatic store to Flash

memory following a fault is triggered when any fault threshold

level is exceeded, provided that the specific fault resp onse is

to shut down. Writing to Flash memory is not allowed if the

device is configured to restart following the specific fault

condition. It should also be noted that the device supply

voltage must be maintained during the time the device is

writing data to Flash memory; a process that requires between

700-1400 μs depe nding on whether the data is set up for a

block write. Undesirabl e results may be observed if the input

voltage of the modules drops below 3.0 V during this process

Software Tools for Design and Production

Ericsson provides soft ware for configuration and monitoring of

this product via the PMBus interface.

For more information please contact your local

Ericsson sales representative.

PMBus Addressing

The PMBus address should be config ured with resistors

connected between the SA0/SA1 pins and the PREF pin, as

shown in the figure below. Recommended resistor values for

hard-wiring PMBus addresses are shown in the table. 1%

tolerance resistors are required.

Schematic of connection of address resistor.

SA0

SA1

PREF

RSA1 RSA0

BMR 464 series POL Regulators

Input 4.5-14 V, Output up to 40 A / 132 W EN/LZT 146 435 R2A July 2011

Technical Speciﬁcation

BMR 464 series POL Regulators

Input 4.5-14 V, Output up to 40 A / 132 W EN/LZT 146 435 R2B August 2011

Technical Speciﬁcation

Index RSA [k] Index RSA [k]

0 10 13 34.8

1 11 14 38.3

2 12.1 15 42.2

3 13.3 16 46.4

4 14.7 17 51.1

5 16.2 18 56.2

6 17.8 19 61.9

7 19.6 20 68.1

8 21.5 21 75

9 23.7 22 82.5

10 26.1 23 90.9

11 28.7 24 100

12 31.6

The PMBus address follo ws the equation b elow:

Eq. 8 PMBus Address (decimal) = 25 x (SA1 index) +

(SA0 index)

The user can theoretically configure up to 625 unique PMBus

addresses, however the PMBus address ran ge is inherently

limited to 128. Therefore, the user should use index values 0 -

4 on the SA1 pin and the full range of ind ex values on the SA0

pin, which will provide 125 device address combinations. T he

user shall also be aware of further limitations of the address

space as stated in the SMBus Specification.

Note that address 0x4B is allocated for production needs and

can not be used.

Optional PMBus Addressing

Alternatively the PMBus addr ess can be defined by

connecting the SA0/SA1 pins according to the following table.

SA1 = open for products with no SA1 pin.

SA0

low open high

low 0x20 0x21 0x22

open 0x23 0x24 0x25

SA1

high 0x26 0x27 Reserved

Low = Shorted to PREF

Open = High impedance

High = Logic high, GND as reference

Logic High definitions see Electrical Specification

I2C/SMBus – Timing

SCL

SDA

set

hold

Setup and hold times timing diagram

The setup time, tset, is the time data, SDA, must be stable

before the rising edge of the clock signal, SCL. The hold time

thold, is the time data, SDA, must be stable after the rising edge

of the clock signal, SCL. If these times are violated incorrect

data may be captured or meta-stability may occur and the bus

communication may fail. When configuring the pro duct, all

standard SMBus protocols must be followed, including clock

stretching. Additionally, a bus-free time delay between every

SMBus transmission (between every stop & start condition)

must occur. Refer to the SMBus specification, for SMBus

electrical and timing requirements. Note that an additional

delay of 20 ms has to be inserted in case of storing the RAM

content into the internal non-volatile memory.

BMR 464 series POL Regulators

Input 4.5-14 V, Output up to 40 A / 132 W EN/LZT 146 435 R2A July 2011

Technical Speciﬁcation

BMR 464 series POL Regulators

Input 4.5-14 V, Output up to 40 A / 132 W EN/LZT 146 435 R2B August 2011

Technical Speciﬁcation

PMBus Commands

The product is PMBus compliant. The following table lists the

implemented PMBus commands. For more detailed

information see PMBus Power System Management Proto col

Specification; Part I – General Requir ements, Transport and

Electrical Interface and PMBus Power System Management

Protocol; Part II – Command Language.

Designation Cmd Impl

Standard PMBus Commands

Control Commands

PAGE 00h No

OPERATION 01h Yes

ON_OFF_CONFIG 02h Yes

WRITE_PROTECT 10h No

Output Commands

VOUT_MODE (Read Onl

) 20h Yes

VOUT_COMMAND 21h Yes

VOUT_TRIM 22h Yes

VOUT_CAL_OFFSET 23h Yes

VOUT_MAX 24h Yes

VOUT_MARGIN_HIGH 25h Yes

VOUT_MARGIN_LOW 26h Yes

VOUT_TRANSITION_RATE 27h Yes

VOUT_DROOP 28h Yes

MAX_DUTY 32h Yes

FREQUENCY_SWITCH 33h Yes

IOUT_CAL_GAIN 38h Yes

IOUT_CAL_OFFSET 39h Yes

VOUT_SCALE_LOOP 29h No

VOUT_SCALE_MONITOR 2Ah No

COEFFICIENTS 30h No

Fault Limit Commands

POWER_GOOD_ON 5Eh Yes

VOUT_OV_FAULT_LIMIT 40h Yes

VOUT_UV_FAULT_LIMIT 44h Yes

IOUT_OC_FAULT_LIMIT 46h Yes

IOUT_UC_FAULT_LIMIT 4Bh Yes

OT_FAULT_LIMIT 4Fh Yes

OT_WARN_LIMIT 51h Yes

UT_WARN_LIMIT 52h Yes

UT_FAULT_LIMIT 53h Yes

VIN_OV_FAULT_LIMIT 55h Yes

VIN_OV_WARN_LIMIT 57h Yes

Designation Cmd Impl

VIN_UV_WARN_LIMIT 58h Yes

VIN_UV_FAULT_LIMIT 59h Yes

VOUT_OV_WARN_LIMIT 42h No

VOUT_UV_WARN_LIMIT 43h No

IOUT_OC_WARN_LIMIT 4Ah No

Fault Response Commands

VOUT_OV_FAULT_RESPONSE 41h Yes

VOUT_UV_FAULT_RESPONSE 45h Yes

OT_FAULT_RESPONSE 50h Yes

UT_FAULT_RESPONSE 54h Yes

VIN_OV_FAULT_RESPONSE 56h Yes

VIN_UV_FAULT_RESPONSE 5Ah Yes

IOUT_OC_FAULT_RESPONSE 47h No

IOUT_UC_FAULT_RESPONSE 4Ch No

Time settin

Commands

TON_DELAY 60h Yes

TON_RISE 61h Yes

TOFF_DELAY 64h Yes

TOFF_FALL 65h Yes

TON_MAX_FAULT_LIMIT 62h No

Status Commands (Read Onl

)

CLEAR_FAULTS 03h Yes

STATUS_BYTE 78h Yes

STATUS_WORD 79h Yes

STATUS_VOUT 7Ah Yes

STATUS_IOUT 7Bh Yes

STATUS_INPUT 7Ch Yes

STATUS_TEMPERATURE 7Dh Yes

STATUS_CML 7Eh Yes

STATUS_MFR_SPECIFIC 80h Yes

Monitor Commands (Read Onl

)

READ_VIN 88h Yes

READ_VOUT 8Bh Yes

READ_IOUT 8Ch Yes

READ_TEMPERATURE_1 8Dh Yes

READ_TEMPERATURE_2 8Eh No

READ_FAN_SPEED_1 90h No

READ_DUTY_CYCLE 94h Yes

READ_FREQUENCY 95h Yes

BMR 464 series POL Regulators

Input 4.5-14 V, Output up to 40 A / 132 W EN/LZT 146 435 R2A July 2011

Technical Speciﬁcation

BMR 464 series POL Regulators

Input 4.5-14 V, Output up to 40 A / 132 W EN/LZT 146 435 R2B August 2011

Technical Speciﬁcation

Designation Cmd Impl

Identification Commands (Read Onl

)

PMBUS_REVISION 98h Yes

MFR_ID 99h Yes

MFR_MODEL 9Ah Yes

MFR_REVISION 9Bh Yes

MFR_LOCATION 9Ch Yes

MFR_DATE 9Dh Yes

MFR_SERIAL 9Eh Yes

Group Commands

INTERLEAVE 37h Yes

Supervisor

Commands

STORE_DEFAULT_ALL 11h Yes

RESTORE_DEFAULT_ALL 12h Yes

STORE_USER_ALL 15h Yes

RESTORE_USER_ALL 16h Yes

Product Specific Commands

Time Settin

Commands

POWER_GOOD_DELAY D4h Yes

Fault limit Commands

IOUT_AVG_OC_FAULT_LIMIT E7h Yes

IOUT_AVG_UC_FAULT_LIMIT E8h Yes

Fault Response Commands

MFR_IOUT_OC_FAULT_RESPONSE E5h Yes

MFR_IOUT_UC_FAULT_RESPONSE E6h Yes

OVUV_CONFIG D8h Yes

Confi

uration and Control Commands

MFR_CONFIG D0h Yes

USER_CONFIG D1h Yes

MISC_CONFIG E9h Yes

PID_TAPS D5h Yes

INDUCTOR D6h Yes

NLR_CONFIG D7h Yes

TEMPCO_CONFIG DCh Yes

DEADTIME DDh Yes

DEADTIME_CONFIG DEh Yes

DEADTIME_MAX BFh Yes

SNAPSHOT EAh Yes

SNAPSHOT_CONTROL F3h Yes

DEVICE_ID E4h Yes

USER_DATA_00 B0h Yes

Designation Cmd Impl

Group Commands

SEQUENCE E0h Yes

GCB_GROUP E2h Yes

ISHARE_CONFIG D2h Yes

PHASE_CONTROL F0h Yes

Supervisor

Commands

PRIVATE_PASSWORD FBh Yes

PUBLIC_PASSWORD FCh Yes

UNPROTECT FDh Yes

SECURITY_LEVEL FAh Yes

Notes:

Cmd is short for Command.

Impl is short for Implemented.

BMR 464 series POL Regulators

Input 4.5-14 V, Output up to 40 A / 132 W EN/LZT 146 435 R2A July 2011

Technical Speciﬁcation

BMR 464 series POL Regulators

Input 4.5-14 V, Output up to 40 A / 132 W EN/LZT 146 435 R2B August 2011

Technical Speciﬁcation

Ericsson Internal

PRODUCT SPEC. MECHANICAL 1 (3)

Prepared (also subject responsible if other) No.

EPETSCH 4/1301-BMR 464 0002 Uen

Approved Checked Date Rev Reference

EAB/FJB/GMF [Ksenia Harrisen] See §1 2011-08-17 B

Mechanical Information - Hole Mount, Open Frame Version

All component placements – whether shown as physical components or symbolical outline – are for reference only and are subject to change throughout the product’s life cycle,

unless explicitly described and dimensioned in this drawing.

BMR 464 series POL Regulators

Input 4.5-14 V, Output up to 40 A / 132 W EN/LZT 146 435 R2B August 2011

Technical Speciﬁcation

Ericsson Internal

PRODUCT SPEC. MECHANICAL 2 (3)

Prepared (also subject responsible if other) No.

EPETSCH 4/1301-BMR 464 0002 Uen

Approved Checked Date Rev Reference

EAB/FJB/GMF [Ksenia Harrisen] See §1 2011-08-17 B

Mechanical Information - Surface Mou nt Version

All component placements – whether shown as physical components or symbolical outline – are for reference only and are subject to change throughout the product’s life cycle,

unless explicitly described and dimensioned in this drawing.

BMR 464 series POL Regulators

Input 4.5-14 V, Output up to 40 A / 132 W EN/LZT 146 435 R2B August 2011

Technical Speciﬁcation

Ericsson Internal

PRODUCT SPEC. MECHANICAL 1 (2)

Prepared (also subject responsible if other) No.

EPETSCH 4/1301 - BMR 464 2002 Uen

Approved Checked Date Rev Reference

EAB/FJB/GMF [Ksenia Harrisen] See §1 2011-08-17 C Template Rev F

Mechanical Information

All component placements – whether shown as physical components or symbolical outline – are for reference only and are subject to change throughout the product’s life cycle,

unless explicitly described and dimensioned in this drawing.

BMR 464 series POL Regulators

Input 4.5-14 V, Output up to 40 A / 132 W EN/LZT 146 435 R2B August 2011

Technical Speciﬁcation

Soldering Information - Surface Mounting

The surface mount product is intend ed for forced convection or

vapor phase reflow soldering in SnPb or Pb-free processes.

The reflow profile should be optimised to avoid excessive

heating of the product. It is recommended to have a sufficiently

extended preh eat time to ensure an even temperature across

the host PCB and it is also recommended to minimize the time

in reflow.

A no-clean flux is recommended to avoid entrapment of

cleaning fluids in cavities insid e the prod uct or between the

product and the host board, since cleaning residues may affect

long time reliability and isolation voltage.

Minimum Pin Temperature Recommendations

Pin number 2B chosen as reference location for the minimum

pin temperature recommendation since this will likely be the

coolest solder joint during the reflow process.

SnPb solder processes

For SnPb solder processes, a pin temperat ure (TPIN) in excess

of the solder melting temperature, (TL, 183°C for Sn63Pb37) for

more than 30 seconds and a peak temperature of 210°C is

recommended to ensure a reliabl e solder joint.

For dry packed products only: dependin g on the type of solder

paste and flux system used on the host board, up to a

recommended maximum temperature of 245°C could be used,

if the products are kept in a controlled environment (dry pack

handling and storage) prior to assembly.

General reflow process

specifications SnPb

eutectic Pb-free

Average ramp-up

(TPRODUCT) 3°C/s max 3°C/s max

Typical solder melting

(liquidus) temperature TL 183°C 221°C

Minimum reflow time

above TL 30 s 30 s

Minimum pin

temperature TPIN 210°C 235°C

Peak product

temperature TPRODUCT 225°C 260°C

Average ramp-down

(TPRODUCT) 6°C/s max 6°C/s max

Maximum time 25°C to

peak 6 minutes 8 minutes

TPRODUCT maximum

TPIN minimum

Time

profile

Product

profile

Time in

reflow

Time in preheat

/ soak zo ne

Time 25°C to peak

Temperature

Lead-free (Pb-free) solder processes

For Pb-free solder processes, a pin temperature (TPIN) in

excess of the solder melting temperature (TL, 217 to 221°C for

SnAgCu solder alloys) for more than 30 seconds and a peak

temperature of 235°C on all solder joints is recommended to

ensure a reliable solder joint.

Maximum Product Temperature Requirements

Top of the product PCB near pin 10B is chosen as reference

location for the maximum (peak) allowed product temperature

(TPRODUCT) since this will likely be the warmest part of the

product during the reflow process.

SnPb solder processes

For SnPb solder processes, the product is qualified for MSL 1

according to IPC/JEDEC standard J-STD-020C.

During reflow TPRODUCT must not exceed 225 °C at any time.

Pb-free solder processes

For Pb-free solder processes, the product is qualified for MSL 3

according to IPC/JEDEC standard J-STD-020C.

During reflow TPRODUCT must not exceed 260 °C at any time.

Dry Pack Information

Surface mounted versions of the products are delivered in

standard moisture barrier ba gs according to IPC/JEDEC

standard J-STD-033 (Handli ng, packing, shipping and use of

moisture/reflow sensitivity surface mount devices).

Using products in high temperature Pb-free soldering

processes requires dry pack stor age and handling. In case the

products have been stored in an uncontrolled environment and

no longer can be considered dry, the modules must be baked

according to J-STD-033.

BMR 464 series POL Regulators

Input 4.5-14 V, Output up to 40 A / 132 W EN/LZT 146 435 R2A July 2011

Technical Speciﬁcation

BMR 464 series POL Regulators

Input 4.5-14 V, Output up to 40 A / 132 W EN/LZT 146 435 R2B August 2011

Technical Speciﬁcation

Ericsson Internal

PRODUCT SPECIFICATION

MECHANICAL. 2 (4)

Prepared (also subject responsible if other) No.

EPETSCH 5/1301-BMR 464 0002 Uen

Approved Checked Date Rev Reference

EAB/FJB/GMF [Ksenia Harrisen] See §1 2011-05-04 PB1

Thermocoupler Attachment

Soldering Information - Hole Mounting

The hole mounted product is intended for plated through hole

mounting by wave or manual sold ering. The pin temperature

is specified to maximum to 270°C for maximum 10 seconds.

A maximum preheat rate of 4°C/s and maximum preheat

temperature of 150°C is suggested. W hen soldering by hand,

care should be taken to avoid direct contact between the hot

soldering iron tip and the pins for more than a few seconds in

order to prevent overheating.

A no-clean flux is recommended to avoid entrapment of

cleaning fluids in cavities insid e the prod uct or between the

product and the host board. The cleaning residues may affect

long time reliability and isolation voltage.

Delivery Package Information

The products are delivered in antistatic carrier tape

(EIA 481 standard).

Carrier Tape Specifications

Material PS, antistatic

Surface resistance < 107 Ohm/square

Bakeability The tape is not bakable

Tape width, W 56 mm [2.20 inch]

Pocket pitch, P1 32 mm [1.26 inch]

Pocket depth, K0 13 mm [0.51 inch]

Reel diameter 381 mm [15 inch]

Reel capacity 130 products /reel

Reel weight 1783 g/full reel

Pin 10B for measurement of maximum

Product temperature TPRODUCT

Pin 2B for measurement of minimum Pin (solder

oint) tem

erature TPIN

BMR 464 series POL Regulators

Input 4.5-14 V, Output up to 40 A / 132 W EN/LZT 146 435 R2A July 2011

Technical Speciﬁcation

BMR 464 series POL Regulators

Input 4.5-14 V, Output up to 40 A / 132 W EN/LZT 146 435 R2B August 2011

Technical Speciﬁcation

Soldering Information - Hole Mounting (SIP version)

The product is intended for plated through hole mounting by

wave or manual soldering. The pi n temperature is specified to

maximum to 270°C for maximum 10 seconds.

A maximum preheat rate of 4°C/s and maximum preheat

temperature of 150°C is suggested. W hen soldering by hand,

care should be taken to avoid direct contact between the hot

soldering iron tip and the pins for more than a few seconds in

order to prevent overheating.

A no-clean flux is recommended to avoid entrapment of

cleaning fluids in cavities insid e the prod uct or between the

product and the host board. The cleaning residues may affect

long time reliability and isolation voltage.

Delivery Package Information (SIP version)

The products are delivered in antistatic trays

Tray Specifications

Material Antistatic Polyethylene foam

Surface resistance 105< Ohms/square <1012

Bakability The trays are not bakeable

Tray thickness 15 mm [ 0.709 inch]

Box capacity 100 products, 2 full trays/box)

Tray weight 35 g empty tray, 549 g full tray

BMR 464 series POL Regulators

Input 4.5-14 V, Output up to 40 A / 132 W EN/LZT 146 435 R2A July 2011

Technical Speciﬁcation

BMR 464 series POL Regulators

Input 4.5-14 V, Output up to 40 A / 132 W EN/LZT 146 435 R2B August 2011

Technical Speciﬁcation

Product Qualification Specification

Characteristics

External visual inspection IPC-A-610

Change of temperature

(Temperature cycling) IEC 60068-2-14 Na Temperature range

Number of cycles

Dwell/transfer time

-40 to 100°C

1000

15 min/0-1 min

Cold (in operation) IEC 60068-2-1 Ad Temperature TA

Duration -45°C

72 h

Damp heat IEC 60068-2-67 Cy Temperature

Humidity

Duration

85°C

85 % RH

1000 hours

Dry heat IEC 60068-2-2 Bd Temperature

Duration 125°C

1000 h

Electrostatic discharge

susceptibility IEC 61340-3-1, JESD 22-A114

IEC 61340-3-2, JESD 22-A115 Human body model (HBM)

Machine Model (MM) Class 2, 2000 V

Class 3, 200 V

Immersion in cleaning solvents IEC 60068-2-45 XA, method 2 Water

Glycol ether

55°C

35°C

Mechanical shock IEC 60068-2-27 Ea Peak acceleration

Duration 100 g

6 ms

Moisture reflow sensitivity 1 J-STD-020C Level 1 (SnPb-eutectic)

Level 3 (Pb Free) 225°C

260°C

Operational life test MIL-STD-202G, method 108A Duration 1000 h

Resistance to soldering heat 2 IEC 60068-2-20 Tb, method 1A Solder temperature

Duration 270°C

10-13 s

Robustness of terminations IEC 60068-2-21 Test Ua1

IEC 60068-2-21 Test Ue1 Through hole mo unt products

Surface mount products All leads

All leads

Solderability

IEC 60068-2-58 test Td 1

IEC 60068-2-20 test Ta 2

Preconditioning

Temperature, SnPb Eutectic

Temperature, Pb-free

Preconditioning

Temperature, SnPb Eutectic

Temperature, Pb-free

150°C dry bake 16 h

215°C

235°C

Steam ageing

235°C

245°C

Vibration, broad band random IEC 60068-2-64 Fh, method 1 Frequency

Spectral density

Duration

10 to 500 Hz

0.07 g2/Hz

10 min in each direction

Notes

1 Only for products intended for reflow soldering (surface mount products)

2 Only for products intended for wave soldering (plated through hole products)

BMR 464 series POL Regulators

Input 4.5-14 V, Output up to 40 A / 132 W EN/LZT 146 435 R2A July 2011

Technical Speciﬁcation

BMR 464 series POL Regulators

Input 4.5-14 V, Output up to 40 A / 132 W EN/LZT 146 435 R2B August 2011

Technical Speciﬁcation