IS65WV12816ALL
IS65WV12816BLL
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 1
Rev. C
03/6/13
Copyright © 2013 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specication and its products at any time without notice. ISSI assumes no
liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specication before relying on
any published information and before placing orders for products.
128K x 16 LOW VOLTAGE,
ULTRA LOW POWER CMOS STATIC RAM
FEATURES
• High-speed access time: 55ns, 70ns
• CMOS low power operation:
36 mW (typical) operating
9 µW (typical) CMOS standby
• TTL compatible interface levels
• Single power supply:
1.65V to 2.2V Vdd (65WV12816ALL)
2.5V to 3.6V Vdd (65WV12816BLL)
• Fully static operation: no clock or refresh
required
• Three state outputs
• Data control for upper and lower bytes
• 2CS Option Available
• Temperature Offerings:
Option A: 0 to 70oC
Option A1: –40 to +85oC
Option A2: –40 to +105oC
Option A3: –40 to +125oC
• Lead-free available
DESCRIPTION
The ISSI IS65WV12816ALL/ IS65WV12816BLL are
high-speed, 2M bit static RAMs organized as 128K words
by 16 bits. It is fabricated using ISSI's high-performance
CMOS technology. This highly reliable process coupled
with innovative circuit design techniques, yields high-
performance and low power consumption devices.
When CS1 is HIGH (deselected) or when CS2 is LOW
(deselected) or when CS1 is LOW, CS2 is HIGH and both
LB and UB are HIGH, the device assumes a standby mode
at which the power dissipation can be reduced down with
CMOS input levels.
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs. The active LOW Write Enable
(WE) controls both writing and reading of the memory. A
data byte allows Upper Byte (UB) and Lower Byte (LB)
access.
The IS65WV12816ALL and IS65WV12816BLL are
packged in the JEDEC standard 48-pin mini BGA (6mm
x 8mm) and 44-Pin TSOP (TYPE II).
FUNCTIONAL BLOCK DIAGRAM
MARCH 2013
A0-A16
CS1
OE
WE
128K x 16
MEMORY ARRAY
DECODER
COLUMN I/O
CONTROL
CIRCUIT
GND
V
DD
I/O
DATA
CIRCUIT
I/O0-I/O7
Lower Byte
I/O8-I/O15
Upper Byte
UB
LB
CS2
IS65WV12816ALL, IS65WV12816BLL
2 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
03/6/13
PIN CONFIGURATIONS
48-Pin mini BGA (6mm x 8mm)
(Package Code B)
PIN DESCRIPTIONS
A0-A16 Address Inputs
I/O0-I/O15 Data Inputs/Outputs
CS1, CS2 Chip Enable Input
OE Output Enable Input
WE Write Enable Input
LB Lower-byte Control (I/O0-I/O7)
UB Upper-byte Control (I/O8-I/O15)
NC No Connection
Vdd Power
GND Ground
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A4
A3
A2
A1
A0
CS1
I/O0
I/O1
I/O2
I/O3
V
DD
GND
I/O4
I/O5
I/O6
I/O7
WE
A16
A15
A14
A13
A12
A5
A6
A7
OE
UB
LB
I/O15
I/O14
I/O13
I/O12
GND
V
DD
I/O11
I/O10
I/O9
I/O8
NC
A8
A9
A10
A11
NC
1 2 3 4 5 6
A
B
C
D
E
F
G
H
LB OE A0 A1 A2 N/C
I/O8UB A3 A4 CSI I/O0
I/O9I/O10 A5 A6 I/O1I/O2
GND I/O11 NC A7 I/O3VDD
VDD I/O12 NC A16 I/O4GND
I/O14 I/O13 A14 A15 I/O5I/O6
I/O15 NC A12 A13 WE I/O7
NC A8 A9 A10 A11 NC
48-Pin mini BGA (6mm x 8mm)
2 CS Option (Package Code B2)
44-Pin mini TSOP (Type II)
(Package Code T)
1 2 3 4 5 6
A
B
C
D
E
F
G
H
LB OE A0 A1 A2 CS2
I/O
8
UB A3 A4 CS1 I/O
0
I/O
9
I/O
10
A5 A6 I/O
1
I/O
2
GND I/O
11
NC A7 I/O
3
V
DD
V
DD
I/O
12
NC A16 I/O
4
GND
I/O
14
I/O
13
A14 A15 I/O
5
I/O
6
I/O
15
NC A12 A13 WE I/O
7
NC A8 A9 A10 A11 NC
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 3
Rev. C
03/6/13
IS65WV12816ALL, IS65WV12816BLL
TRUTH TABLE
I/O PIN
Mode WE CS1 CS2 OE LB UB I/O0-I/O7 I/O8-I/O15 Vdd Current
Not Selected X H X X X X High-Z High-Z Isb1, Isb2
X X L X X X High-Z High-Z Isb1, Isb2
X X X X H H High-Z High-Z Isb1, Isb2
Output Disabled H L H H L X High-Z High-Z Icc
H L H H X L High-Z High-Z Icc
Read H L H L L H dout High-Z Icc
H L H L H L High-Z dout
H L H L L L dout dout
Write L L H X L H dIn High-Z Icc
L L H X H L High-Z dIn
L L H X L L dIn dIn
OPERATING RANGE (Vdd)
Option Ambient Temperature IS65WV12816ALL IS65WV12816BLL
A 0°C to +70°C 1.65V - 2.2V 2.5V - 3.6V
A1 –40°C to +85°C 1.65V - 2.2V 2.5V - 3.6V
A2 –40°C to +105°C 1.65V - 2.2V 2.5V - 3.6V
A3 –40°C to +125°C 1.65V - 2.2V 2.5V - 3.6V
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameter Value Unit
Vterm Terminal Voltage with Respect to GND –0.2 to Vdd+0.3 V
tstg Storage Temperature –65 to +150 °C
Pt Power Dissipation 1.0 W
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reli-
ability.
IS65WV12816ALL, IS65WV12816BLL
4 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
03/6/13
CAPACITANCE(1)
Symbol Parameter Conditions Max. Unit
cIn Input Capacitance VIn = 0V 8 pF
cout Input/Output Capacitance Vout = 0V 10 pF
Note:
1. Tested initially and after any design or process changes that may affect these parameters.
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol Parameter Test Conditions Vdd Min. Max. Unit
VoH Output HIGH Voltage IoH = -0.1 mA 1.65-2.2V 1.4 — V
IoH = -1 mA 2.5-3.6V 2.2 — V
VoL Output LOW Voltage IoL = 0.1 mA 1.65-2.2V — 0.2 V
IoL = 2.1 mA 2.5-3.6V — 0.4 V
VIH Input HIGH Voltage 1.65-2.2V 1.4 Vdd + 0.2 V
2.5-3.6V 2.2 Vdd + 0.3 V
VIL(1) Input LOW Voltage 1.65-2.2V –0.2 0.4 V
2.5-3.6V –0.2 0.8 V
ILI Input Leakage GND ≤ VIn ≤ Vdd –1 1 µA
ILo Output Leakage GND ≤ Vout ≤ Vdd, Outputs Disabled –1 1 µA
Notes:
1. VIL (min.) = –1.0V for pulse width less than 10 ns.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 5
Rev. C
03/6/13
IS65WV12816ALL, IS65WV12816BLL
IS65WV12816ALL, POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
Symbol Parameter Test Conditions Options Max. Unit
-70 ns
Icc Vdd Dynamic Operating Vdd = Max., A, A1 15 mA
Supply Current Iout = 0 mA, f = fmaX A2, A3 20
Icc1 Operating Supply Vdd = Max., A, A1 7 mA
Current Iout = 0 mA, f = 0 A2, A3 7
Isb1 TTL Standby Current Vdd = Max., A, A1 0.6 mA
(TTL Inputs) VIn = VIH or VIL A2, A3 0.6
CS1 = VIH , CS2 = VIL,
f = 1 MHz
OR
ULB Control
Vdd = Max., VIn = VIH or VIL
CS1 = VIL, f = 0, UB = VIH, LB = VIH
Isb2 CMOS Standby Vdd = Max., A, A1 15 µA
Current (CMOS Inputs) CS1
≥
Vdd – 0.2V, A2 20
CS2
≤ 0.2V, A3 50
VIn
≥
Vdd – 0.2V, or
VIn
≤
0.2V, f = 0
OR
ULB Control Vdd = Max., CS1 = VIL, cs2=VIH
VIn ≤ 0.2V, f = 0; UB / LB = Vdd – 0.2V
IS65WV12816BLL, POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
Symbol Parameter Test Conditions Options Max. Max. Unit
-55 ns -70 ns
Icc Vdd Dynamic Operating Vdd = Max., A, A1 25 20 mA
Supply Current Iout = 0 mA, f = fmaX A2, A3 30 25
Icc1 Operating Supply Vdd = Max., A, A1 7 7 mA
Current Iout = 0 mA, f = 0 A2, A3 7 7
Isb1 TTL Standby Current Vdd = Max., A, A1 0.6 0.6 mA
(TTL Inputs) VIn = VIH or VIL A2, A3 0.6 0.6
CS1 = VIH , CS2 = VIL,
f = 1 MHz
OR
ULB Control
Vdd = Max., VIn = VIH or VIL
CS1 = VIL, f = 0, UB = VIH, LB = VIH
Isb2 CMOS Standby Vdd = Max., A, A1 15 15 µA
Current (CMOS Inputs) CS1
≥
Vdd – 0.2V, A2 25 25
CS2
≤ 0.2V, A3 65 65
VIn
≥
Vdd – 0.2V, or
VIn
≤
0.2V, f = 0
OR
ULB Control Vdd = Max., CS1 = VIL, cs2=VIH
VIn ≤ 0.2V, f = 0; UB / LB = Vdd – 0.2V
Note:
1. At f = fmaX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
IS65WV12816ALL, IS65WV12816BLL
6 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
03/6/13
AC TEST CONDITIONS
Parameter 65WV12816ALL 65WV12816BLL
(Unit) (Unit)
Input Pulse Level 0.4V to Vdd-0.2V 0.4V to Vdd-0.3V
Input Rise and Fall Times 5 ns 5ns
Input and Output Timing Vref Vref
and Reference Level
Output Load See Figures 1 and 2 See Figures 1 and 2
AC TEST LOADS
Figure 1 Figure 2
65WV12816ALL 65WV12816BLL
(1.65V-2.2V) (2.5V - 3.6V)
R1(Ω) 3070 3070
R2(Ω) 3150
3150
VRef 0.9V
1.5V
Vtm 1.8V 2.8V
R1
5 pF
Including
jig and
scope
R2
OUTPUT
VTM
R1
30 pF
Including
jig and
scope
R2
OUTPUT
VTM
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 7
Rev. C
03/6/13
IS65WV12816ALL, IS65WV12816BLL
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
-55 ns
-70 ns
Symbol Parameter Min. Max. Min. Max. Unit
trc Read Cycle Time 55 — 70 — ns
taa Address Access Time — 55 — 70 ns
toHa Output Hold Time 10 — 10 — ns
tacs1/tacs2 CS1/CS2 Access Time — 55 — 70 ns
tdoe OE Access Time — 25 — 35 ns
tHzoe(2) OE to High-Z Output — 20 — 25 ns
tLzoe(2) OE to Low-Z Output 5 — 5 — ns
tHzcs1/tHzcs2(2) CS1/CS2 to High-Z Output 0 20 0 25 ns
tLzcs1/tLzcs2(2) CS1/CS2 to Low-Z Output 10 — 10 — ns
tba LB, UB Access Time — 55 — 70 ns
tHzb LB, UB to High-Z Output 0 20 0 25 ns
tLzb LB, UB to Low-Z Output 0 — 0 — ns
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V, input pulse levels of 0.4 to 1.4V
and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
IS65WV12816ALL, IS65WV12816BLL
8 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
03/6/13
DATA VALID
PREVIOUS DATA VALID
t
AA
t
OHA
t
OHA
t
RC
DOUT
ADDRESS
AC WAVEFORMS
READ CYCLE NO. 1(1,2) (Address Controlled) (CS1 = OE = VIL, CS2 = WE = VIH, UB or LB = VIL)
t
RC
t
OHA
t
AA
t
DOE
t
LZOE
t
ACE1/
t
ACE2
t
LZCE1/
t
LZCE2
t
HZOE
HIGH-Z DATA VALID
t
HZCS1/
t
HZCS2
ADDRESS
OE
CS1
CS2
DOUT
LB, UB
t
HZB
t
BA
t
LZB
AC WAVEFORMS
READ CYCLE NO. 2(1,3) (CS1, CS2, OE, AND UB/LB Controlled)
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CS1, UB, or LB = VIL. cs2=WE=VIH.
3. Address is valid prior to or coincident with CS1 LOW transition.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 9
Rev. C
03/6/13
IS65WV12816ALL, IS65WV12816BLL
WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range)
-55 ns
-70 ns
Symbol Parameter Min. Max. Min. Max. Unit
twc Write Cycle Time 55 — 70 — ns
tscs1/tscs2 CS1/CS2 to Write End 45 — 60 — ns
taw Address Setup Time to Write End 45 — 60 — ns
tHa Address Hold from Write End 0 — 0 — ns
tsa Address Setup Time 0 — 0 — ns
tPwb LB, UB Valid to End of Write 45 — 60 — ns
tPwe WE Pulse Width 40 — 50 — ns
tsd Data Setup to Write End 25 — 30 — ns
tHd Data Hold from Write End 0 — 0 — ns
tHzwe(3) WE LOW to High-Z Output — 20 — 20 ns
tLzwe(3) WE HIGH to Low-Z Output 5 — 5 — ns
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V, input pulse levels of 0.4V to 1.4V
and output loading specified in Figure 1.
2.
The internal write time is defined by the overlap of CS1 LOW, CS2 HIGH and UB or LB, and WE LOW. All signals must be in valid states to initiate a Write, but
any one can go inactive to
terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the
write.
3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
IS65WV12816ALL, IS65WV12816BLL
10 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
03/6/13
AC WAVEFORMS
WRITE CYCLE NO. 1(1,2) (CS1 Controlled, OE = HIGH or LOW)
Notes:
1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the CS1 , CS2 and WE inputs and at
least one of the LB and UB inputs being in the LOW state.
2. WRITE = (CS1) [ (LB) = (UB) ] (WE).
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 11
Rev. C
03/6/13
IS65WV12816ALL, IS65WV12816BLL
AC WAVEFORMS
WRITE CYCLE NO. 2 (WE Controlled: OE is HIGH During Write Cycle)
DATA-IN VALID
DATA UNDEFINED
tWC
tSCS1
tSCS2
tAW
tHA
tPWE
tHZWE
HIGH-Z
tLZWE
tSA
tSD tHD
ADDRESS
OE
CS1
CS2
WE
LB, UB
DOUT
DIN
IS65WV12816ALL, IS65WV12816BLL
12 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
03/6/13
AC WAVEFORMS
WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle)
DATA-IN VALID
DATA UNDEFINED
t
WC
t
SCS1
t
SCS2
t
AW
t
HA
t
PWE
t
HZWE
HIGH-Z
t
LZWE
t
SA
t
SD
t
HD
ADDRESS
OE
CS1
CS2
WE
LB, UB
DOUT
DIN
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 13
Rev. C
03/6/13
IS65WV12816ALL, IS65WV12816BLL
AC WAVEFORMS
WRITE CYCLE NO. 4 (UB/LB Controlled)
DATA UNDEFINED
t
WC
ADDRESS 1 ADDRESS 2
t
WC
HIGH-Z
t
PBW
WORD 1
LOW
WORD 2
t
HD
t
SA
t
HZWE
DATA
IN
VALID
t
LZWE
t
SD
t
PBW
DATA
IN
VALID
t
SD
t
HD
t
SA
t
HA t
HA
UB_CSWR4.eps
HIGH
ADDRESS
OE
CS1
CS2
WE
LB, UB
DOUT
DIN
IS65WV12816ALL, IS65WV12816BLL
14 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
03/6/13
DATA RETENTION WAVEFORM (CS1 Controlled)
DATA RETENTION SWITCHING CHARACTERISTICS (LL)
Symbol Parameter Test Condition Options Min. Typ.(1) Max. Unit
Vdr Vdd for Data Retention See Data Retention Waveform 1.2 — 3.6 V
Idr Data Retention Current Vdd = 1.2V, CS1 ≥ Vdd – 0.2V A, A1 — 5 15 µA
A2 — — 25
A3 — — 65
tsdr Data Retention Setup Time See Data Retention Waveform 0 — — ns
trdr Recovery Time See Data Retention Waveform trc — — ns
Note 1: Typical values are measured at Vdd = 3.0V, Ta = 25
o
c and not 100% tested.
DATA RETENTION WAVEFORM (CS2 Controlled)
V
DD
CS1 ≥ VDD
- 0.2V
tSDR tRDR
VDR
CS1
GND
1.65V
1.4V
Data Retention Mode
CS2 ≤ 0.2V
t
SDR
t
RDR
VDR
0.4V
CE2
GND
3.0
2.2V
Data Retention Mode
VDD
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 15
Rev. C
03/6/13
IS65WV12816ALL, IS65WV12816BLL
ORDERING INFORMATION
IS65WV12816ALL (1.65V - 2.2V)
Temperature Range (A): 0°C to +70°C
Speed (ns) Order Part No. Package
70 IS65WV12816ALL-70TA TSOP
IS65WV12816ALL-70BA mini BGA (6mm x 8mm)
IS65WV12816ALL-70B2A mini BGA (6mm x 8mm), 2 CS Option
Temperature Range (A1): –40°C to +85°C
Speed (ns) Order Part No. Package
70 IS65WV12816ALL-70TA1 TSOP
IS65WV12816ALL-70BA1 mini BGA (6mm x 8mm)
IS65WV12816ALL-70B2A1 mini BGA (6mm x 8mm), 2 CS Option
Temperature Range (A2): –40°C to +105°C
Speed (ns) Order Part No. Package
70 IS65WV12816ALL-70TA2 TSOP
IS65WV12816ALL-70BA2 mini BGA (6mm x 8mm)
IS65WV12816ALL-70B2A2 mini BGA (6mm x 8mm), 2 CS Option
Temperature Range (A3): –40°C to +125°C
Speed (ns) Order Part No. Package
70 IS65WV12816ALL-70TA3 TSOP
IS65WV12816ALL-70BA3 mini BGA (6mm x 8mm)
IS65WV12816ALL-70B2A3 mini BGA (6mm x 8mm), 2 CS Option
IS65WV12816ALL, IS65WV12816BLL
16 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
03/6/13
ORDERING INFORMATION
IS65WV12816BLL (2.5V - 3.6V)
Temperature Range (A): 0°C to +70°C
Speed (ns) Order Part No. Package
55 IS65WV12816BLL-55TA TSOP
IS65WV12816BLL-55BA mini BGA (6mm x 8mm)
IS65WV12816BLL-55B2A mini BGA (6mm x 8mm), 2 CS Option
70 IS65WV12816BLL-70TA TSOP
IS65WV12816BLL-70BA mini BGA (6mm x 8mm)
IS65WV12816BLL-70B2A mini BGA (6mm x 8mm), 2 CS Option
Temperature Range (A1): –40°C to +85°C
Speed (ns) Order Part No. Package
55 IS65WV12816BLL-55TA1 TSOP
IS65WV12816BLL-55BA1 mini BGA (6mm x 8mm)
IS65WV12816BLL-55B2A1 mini BGA (6mm x 8mm), 2 CS Option
70 IS65WV12816BLL-70TA1 TSOP
IS65WV12816BLL-70BA1 mini BGA (6mm x 8mm)
IS65WV12816BLL-70B2A1 mini BGA (6mm x 8mm), 2 CS Option
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 17
Rev. C
03/6/13
IS65WV12816ALL, IS65WV12816BLL
ORDERING INFORMATION (continual)
IS65WV12816BLL (2.5V - 3.6V)
TEMPERATURE RANGE (A2): –40°C TO +105°C
Speed (ns) Order Part No. Package
55 IS65WV12816BLL-55TA2 TSOP
IS65WV12816BLL-55BA2 mini BGA (6mm x 8mm)
IS65WV12816BLL-55B2A2 mini BGA (6mm x 8mm), 2 CS Option
70 IS65WV12816BLL-70TA2 TSOP
IS65WV12816BLL-70BA2 mini BGA (6mm x 8mm)
IS65WV12816BLL-70B2A2 mini BGA (6mm x 8mm), 2 CS Option
Temperature Range (A3): –40°C to +125°C
Speed (ns) Order Part No. Package
55 IS65WV12816BLL-55TA3 TSOP
IS65WV12816BLL-55TLA3 TSOP, Lead-free
IS65WV12816BLL-55BA3 mini BGA (6mm x 8mm)
IS65WV12816BLL-55BLA3 mini BGA (6mm x 8mm), Lead-free
IS65WV12816BLL-55B2A3 mini BGA (6mm x 8mm), 2 CS Option
70 IS65WV12816BLL-70TA3 TSOP
IS65WV12816BLL-70BA3 mini BGA (6mm x 8mm)
IS65WV12816BLL-70B2A3 mini BGA (6mm x 8mm), 2 CS Option