September 1983
Revised February 1999
MM74HC373 3-STATE Octal D-Type Latch
© 1999 Fairchild Semicond uctor Corpor ation DS005335.prf www.f airchildsemi.com
MM74HC373
3-STATE Octal D-Type Latch
General Descript ion
The MM74HC373 high speed octal D-type latches utilize
advanced silicon-gate CMOS technology. They possess
the high noise immunity and low power consumption of
standard CMOS integrated circuits, as well as the ability to
drive 15 LS-T TL load s. Due to th e large output d rive capa-
bility and the 3-STATE feature, these devices are ideally
suited for interfacing with bus lines in a bus organized sys-
tem.
When the LATCH ENABLE input is HIGH, the Q outputs
will follow the D inputs. When the LATCH ENABLE goes
LOW, data at the D inputs will be retained at the outputs
until LATCH ENABLE returns HIGH again. When a high
logic level is applied to the OUTPUT CONTROL input, all
outputs go to a high impedance state, regardless of what
signals ar e present at th e other inputs an d the state of the
storage elements.
The 74HC logic family is spe ed , fu nctio n, and pin-ou t co m-
patible with the standard 74LS logic family. All inputs are
protected from damage due to static discharge by internal
diode clamps to VCC and ground.
Features
■Typical propagation delay: 18 ns
■Wide operating voltage range: 2 to 6 volts
■Low input current: 1 µA maximum
■Low quiescent current: 80 µA maximum (74 Series)
■Output drive capability: 15 LS-TTL loads
Ordering Code:
Devices also available in Tape and Reel. Specify by appen ding the suffix lett er “X” to the orde ring code.
Connection Diagram
Pin Assignmen ts for DIP, SOIC, SOP and TSSOP
Top View
Truth Table
H = HIGH Level
L = LOW Level
Q0 = Level of output before st eady-state input conditions w ere established.
Z = High Impedance
Order Number Package Number Package Description
MM74HC373WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
MM74HC373SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HC373MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HC373N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Output Latch Data 373
Control Enable Output
LHHH
LHLL
LLXQ
0
HXXZ
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MM74HC373
Absolute Maximum Ratings(Note 1)
(Note 2) Recommended Operating
Conditions
Note 1: Absolute Maximum Ratings are those va lues beyond which dam-
age to the device may occur.
Note 2: Unless ot herwise specif ied all voltages are refere nc ed to ground.
Note 3: Power Dissipati on temperat ure derat ing — plas tic “N” p ackage: −
12 mW/°C from 65°C to 85°C.
DC Electrical Characteristics
Note 4: For a power supply of 5V ±10% t he worst case ou tput voltages (V OH, an d VOL) occur for HC at 4.5V. Th us the 4 .5V valu es shou ld be used wh en
designing with this supply. Worst case VIH and VIL occur at VCC = 5.5V and 4.5V re s pectively. (Th e V IH value at 5.5V is 3.85V.) T he worst case leakage c ur-
rent (IIN, ICC, and IOZ) occur for CMO S at the highe r voltage and so the 6.0 V valu es s hould be used.
Supply Voltage (VCC)−0.5 to +7.0V
DC Input Voltage (VIN)−1.5 to VCC +1.5V
DC Output Voltage (VOUT)−0.5 to VCC +0.5V
Clamp Diode Current (IIK, IOK)±20 mA
DC Output Current, per pin (IOUT)±35 mA
DC VCC or GND Current, per pin (ICC)±70 mA
Storage Temperature Range (TSTG)−65°C to +150°C
Power Dissipation (PD)
(Note 3) 600 mW
S.O. Package only 500 mW
Lead Temperature (TL)
(Soldering 10 seco nds) 260°C
Min Max Units
Supply Voltage (VCC)26V
DC Input or Output Voltage
(VIN,VOUT)0V
CC V
Operating Temperature Range (TA)−40 +85 °C
Input Rise or Fall Times
(tr, tf) V
CC = 2.0V 1000 ns
VCC = 4.5V 500 ns
VCC = 6.0V 400 ns
Symbol Parameter Conditions VCC TA = 25°CT
A = −40 to 85°CT
A = −55 to 125°CUnits
Typ Guaranteed Limits
VIH Minimum HIGH Level 2.0V 1.5 1.5 1.5 V
Input Voltage 4.5V 3.15 3.15 3.15 V
6.0V 4.2 4.2 4.2 V
VIL Maximum LOW Level 2.0V 0.5 0.5 0.5 V
Input Voltage 4.5V 1.35 1.35 1.35 V
6.0V 1.8 1.8 1.8 V
VOH Minimum HIGH Level VIN = VIH or VIL
Output Voltage |IOUT| ≤ 20 µA 2.0V 2.0 1.9 1.9 1.9 V
4.5V 4.5 4.4 4.4 4.4 V
6.0V 6.0 5.9 5.9 5.9 V
VIN = VIH or VIL
|IOUT| ≤ 6.0 mA 4.5V 4.2 3.98 3.84 3.7 V
|IOUT| ≤ 7.8 mA 6.0V 5.7 5.48 5.34 5.2 V
VOL Maximum LOW Level VIN = VIH or VIL
Output Voltage |IOUT| ≤ 20 µA 2.0V 0 0.1 0.1 0.1 V
4.5V 0 0.1 0.1 0.1 V
6.0V 0 0.1 0.1 0.1 V
VIN = VIH or VIL
|IOUT| ≤ 6.0 mA 4.5V 0.2 0.26 0.33 0.4 V
|IOUT| ≤ 7.8 mA 6.0V 0.2 0.26 0.33 0.4 V
IIN Maximum Input VIN = VCC or GND 6.0V ±0.1 ±1.0 ±1.0 µA
Current
IOZ Maximum 3-STATE VIN = VIH or VIL, OC = VIH 6.0V ±0.5 ±5±10 µA
Output Leakage VOUT = VCC or GND
Current
ICC Maximum Quiescent VIN = VCC or GND 6.0V 8.0 80 160 µA
Supply Current IOUT = 0 µA
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MM74HC373
AC Electrical Characteri stics
VCC = 5V, TA = 25°C, tr = tf = 6 ns
AC Electrical Characteri stics
VCC = 2.0−6.0V, CL = 50 pF, tr = tf = 6 ns (unless otherwise specified)
Symbol Parameter Conditions Typ Guaranteed Units
Limit
tPHL, tPLH Maximum Propagation Delay, Data to Q CL = 45 pF 18 25 ns
tPHL, tPLH Maximum Propa gation Dela y, LE to Q CL = 45 pF 21 30 ns
tPZH, tPZL Maximum Output Enable Time RL = 1 kΩ20 28 ns
CL = 45 pF
tPHZ, tPLZ Maximum Output Disable Time RL = 1 kΩ18 25 ns
CL = 5 pF
tSMinimum Set U p Time 5ns
tHMinimum Hold Time 10 ns
tWMinimum Pulse Width 9 16 ns
Symbol Parameter Conditions VCC TA = 25°CT
A = −40 to 85°CT
A = −55 to 125°CUnits
Typ Guaranteed Limits
tPHL, tPLH Maximum Propagation CL = 50 pF 2.0V 50 150 188 225 ns
Delay, Data to Q CL = 150 pF 2.0V 80 200 250 300 ns
CL = 50 pF 4.5V 22 30 37 45 ns
CL = 150 pF 4.5V 30 40 50 60 ns
CL = 50 pF 6.0V 19 26 31 39 ns
CL = 150 pF 6.0V 26 35 44 53 ns
tPHL, tPLH Maximum Propagation CL = 50 pF 2.0V 63 175 220 263 ns
Delay, LE to Q CL = 150 pF 2.0V 110 225 280 338 ns
CL = 50 pF 4.5V 25 35 44 52 ns
CL = 150 pF 4.5V 35 45 56 68 ns
CL = 50 pF 6.0V 21 30 37 45 ns
CL = 150 pF 6.0V 28 39 49 59 ns
tPZH, tPZL Maximum Output RL = 1 kΩ
Enable Time CL = 50 pF 2.0V 50 150 188 225 ns
CL = 150 pF 2.0V 80 200 250 300 ns
CL = 50 pF 4.5V 21 30 37 45 ns
CL = 150 pF 4.5V 30 40 50 60 ns
CL = 50 pF 6.0V 19 26 31 39 ns
CL = 150 pF 6.0V 26 35 44 53 ns
tPHZ, tPLZ Maximum Output Disable RL = 1 kΩ2.0V 50 150 188 225 ns
Disable Time CL = 50 pF 4.5V 21 30 37 45 ns
6.0V 19 26 31 39 ns
tSMinimum Set Up Time 2.0V 50 60 75 ns
4.5V 9 13 15 ns
6.0V 9 11 13 ns
tHMinimum Hold Time 2.0V 5 5 5 ns
4.5V 5 5 5 ns
6.0V 5 5 5 ns
tWMinimum Pulse Width 2.0V 30 80 100 120 ns
4.5V 10 16 20 24 ns
6.0V 9 14 18 20 ns
tTHL, tTLH Maximum Output Rise CL = 50 pF 2.0V 25 60 75 90 ns
and Fall Time 4.5V 7 12 15 18 ns
6.0V 6 10 13 15 ns
CPD Power Dissipation (per latch)
Capacitance (Note 5) OC = VCC 30 pF
OC = GND 50 pF
CIN Maximum Input Capacitance 5 10 10 10 pF
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MM74HC373
AC El ectrical Charac teristics (Continued)
Note 5: CPD determines the no lo ad dynamic power c onsumption, PD = CPD VCC2 f + ICC VCC, and th e no load dynam ic c urrent consumption,
IS = CPD VCC f + ICC.
Symbol Parameter Conditions VCC TA = 25°CT
A = −40 to 85°CT
A = −55 to 125°CUnits
Typ Guaranteed Limits
COUT Maximum Output 15 20 20 20 pF
Capacitance
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MM74HC373
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
Package Number M20B
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D
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MM74HC373
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC20
F airchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and F airchild reserves the right at any tim e without notice to change said circuitry and specifications.
MM74HC373 3-STATE Octal D-Type Latch
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or system s a re devices or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A cr itical c ompon ent in any com ponent of a li fe support
device or system whose failure to perform can be rea-
sonably expected to cause th e failure of the li fe suppor t
device or system, or to affect its safety or effectiveness.
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Package Number N20A
