TPS72501 TPS72515, TPS72516 TPS72518, TPS72525 www.ti.com SLVS341D - MAY 2002 - REVISED MARCH 2004 LOW INPUT VOLTAGE, 1-A LOW-DROPOUT LINEAR REGULATORS WITH SUPERVISOR FEATURES * * * * * * * * * * * * DESCRIPTION 1-A Output Current Available in 1.5-V, 1.6-V, 1.8-V, 2.5-V Fixed-Output and Adjustable Versions (1.2-V to 5.5-V) Input Voltage Down to 1.8 V Low 170-mV Dropout Voltage at 1 A (TPS72525) Stable With Any Type/Value Output Capacitor Integrated Supervisor (SVS) With 50-ms RESET Delay Time Low 210-A Ground Current at Full Load (TPS72525) Less than 1-A Standby Current 2% Output Voltage Tolerance Over Line, Load, and Temperature (-40C to 125C) Integrated UVLO Thermal and Overcurrent Protection 5-Lead SOT223-5 or DDPAK and 8-Pin SOP (TPS72501 only) Surface Mount Package APPLICATIONS * * * * * PCI Cards Modem Banks Telecom Boards DSP, FPGA, and Microprocessor Power Supplies Portable, Battery-Powered Applications DCQ PACKAGE SOT223-5 (TOP VIEW) ENABLE 1 IN GND OUT RESET/FB 2 These regulators are ideal for higher current applications. The family operates over a wide range of input voltages (1.8 V to 6 V) and has very low dropout (170 mV at 1-A). Ground current is typically 210 A at full load and drops to less than 80 A at no load. Standby current is less than 1 A. Each regulator option is available in either a SOT223-5, D (TPS72501 only), or DDPAK package. With a low input voltage and properly heatsinked package, the regulator dissipates more power and achieves higher efficiencies than similar regulators requiring 2.5 V or more minimum input voltage and higher quiescent currents. These features make it a viable power supply solution for portable, battery-powered equipment. KTT PACKAGE DDPAK (TOP VIEW) 3 4 The TPS725xx family of 1-A low-dropout (LDO) linear regulators has fixed voltage options available that are commonly used to power the latest DSPs, FPGAs, and microcontrollers. An adjustable option ranging from 1.22 V to 5.5 V is also available. The integrated supervisory circuitry provides an active low RESET signal when the output falls out of regulation. The no capacitor/any capacitor feature allows the customer to tailor output transient performance as needed. Therefore, compared to other regulators capable of providing the same output current, this family of regulators can provide a stand-alone power supply solution or a post regulator for a switch mode power supply. 1 2 3 4 5 ENABLE IN GND OUT RESET/FB 5 D PACKAGE (TOP VIEW) OUT FB GND NC 1 8 2 7 3 6 4 5 IN GND GND ENABLE NC - No internal connection NOTE: TPS72501 replaces RESET with FB. Tab is GND for the DCK and KTT packages. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2002-2004, Texas Instruments Incorporated TPS72501 TPS72515, TPS72516 TPS72518, TPS72525 www.ti.com SLVS341D - MAY 2002 - REVISED MARCH 2004 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. DESCRIPTION (CONTINUED) Although an output capacitor is not required for stability, transient response and output noise are improved with a 10-F output capacitor. Unlike some regulators that have a minimum current requirement, the TPS725 family is stable with no output load current. The low noise capability of this family, coupled with its high current operation and ease of power dissipation, make it ideal for telecom boards, modem banks, and other noise-sensitive applications. ORDERING INFORMATION VOLTAGE (1) SOT223-5 (2) SYMBOL DDPAK (3) D (4) SYMBOL Adjustable (1.2 V to 5 V) TPS72501DCQ PS72501 TPS72501KTT TPS72501D TPS72501 1.5 V TPS72515DCQ PS72515 TPS72515KTT -- TPS72515 1.6 V TPS72516DCQ PS72516 TPS72516KTT -- TPS72516 1.8 V TPS72518DCQ PS72518 TPS72518KTT -- TPS72518 2.5 V TPS72525DCQ PS72525 TPS72525KTT -- TPS72525 TJ -40C to 125C (1) (2) (3) (4) Other voltage options are available upon request from the manufacturer. To order a taped and reeled part, add the suffix R to the part number (e.g., TPS72501DCQR). To order a 50-piece reel, add the suffix T (e.g., TPS72501KTTT); to order a 500-piece reel, add the suffix R (e.g., TPS72501KTTR). To order a taped and reeled part, add the suffix R or T (2500 or 500) to the part number (e.g. TPS72501DR) ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted (1) UNIT Input voltage, VI (2) -0.3 to 7 V Voltage range at EN, FB -0.3 to VI + 0.3 V Voltage on OUT, RESET 6 V ESD rating, HBM 2 kV Continuous total power dissipation Operating junction temperature range, TJ Maximum junction temperature range, TJ Storage temperature, Tstg (1) (2) See Dissipation Ratings Table -50 to 150 C 150 C -65 to 150 C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to network ground terminal. RECOMMENDED OPERATING CONDITIONS MIN NOM MAX UNIT Input voltage, VI (1) Continuous output current, IO Operating junction temperature, TJ (1) 2 Minimum VI = VO (nom) + VDO. 1.8 6 V 0 1 A -40 125 C TPS72501 TPS72515, TPS72516 TPS72518, TPS72525 www.ti.com SLVS341D - MAY 2002 - REVISED MARCH 2004 PACKAGE DISSIPATION RATINGS PACKAGE BOARD RJC RJA DDPAK High K (1) 2 C/W 23 C/W SOT223 Low K (2) 15 C/W 53 C/W 39.4 C/W 55 C/W D-8 (1) (2) High K (1) The JEDEC high-K (2s2p) board design used to derive this data was a 3-inch x 3-inch (7.5-cm x 7.5-cm), multilayer board with 1 ounce internal power and ground planes and 2 ounce copper traces on top and bottom of the board. The JEDEC low-K (1s) board design used to derive this data was a 3-inch x 3-inch (7.5-cm x 7.5-cm), two-layer board with 2 ounce copper traces on top of the board. ELECTRICAL CHARACTERISTICS over recommended operating free-air temperature range VI = VO(typ) + 1 V, IO= 1 mA, EN = IN, Co = 1 F, Ci = 1 F (unless otherwise noted) PARAMETER TEST CONDITIONS Bandgap voltage reference TPS72501 Adjustable TPS72515 VO Output voltage TPS72516 TPS72518 TPS72525 I Ground current Standby current 0 A < IO < 1 A (1) 1.22 V VO 5.5 V 0 A< IO < 1 A UNIT V 0.965 VO 2.6 V VI 5.5 V 1.568 TJ = 25C 0 A < IO < 1 A 1.632 2.8 V VI 5.5 V 1.764 1.836 2.5 3.5 V VI 5.5 V 2.45 2.55 IO = 0 A 75 120 IO = 1 A 210 300 EN < 0.4 V V 1.8 TJ = 25C 0 A < IO < 1 A 1.53 1.6 TJ = 25C 0 A < IO < 1 A 1.035 VO 1.5 1.47 TJ = 25C 0.2 EN < 0.4 V 1 BW = 200 Hz to 100 kHz, TJ = 25C Co = 10 F, IO = 1 mA PSRR Ripple rejection f = 1 kHz, Co = 10 F TJ = 25C limit (2) Output voltage load regulation MAX 1.263 1.8 V VI 5.5 V Output noise voltage Output voltage line regulation (VO/VO) (3) TYP 1.220 TJ = 25C Vn Current MIN 1.177 A A 150 V 60 dB 1.1 1.6 2.3 A VO + 1 V < VI 5.5 V -0.15 0.02 0.15 %/V 0 A < IO < 1 A -0.25 0.05 0.25 %/A input (2) VIH EN high level VIL EN low level input (2) II EN input current EN = 0 V or VI I(FB) Feedback current TPS72501 UVLO threshold VCC rising UVLO hysteresis TJ = 25C, VCC rising 50 mV UVLO deglitch TJ = 25C, VCC rising 10 s UVLO delay TJ = 25C, VCC rising 100 s (1) (2) (3) 1.3 -0.2 V(FB) = 1.22 0.4 0.01 100 nA 100 nA 1.57 1.70 -100 1.45 V V Minimum IN operating voltage used for testing is VO(typ) + 1 V. Test condition includes output voltage VO = VO - 15% and pulse duration = 10 ms. VImin = (VO + 1) or 1.8 V whichever is greater. V 5.5 V V O Imin Line regulation (mV) %V 1000 100 3 TPS72501 TPS72515, TPS72516 TPS72518, TPS72525 www.ti.com SLVS341D - MAY 2002 - REVISED MARCH 2004 ELECTRICAL CHARACTERISTICS (continued) over recommended operating free-air temperature range VI = VO(typ) + 1 V, IO= 1 mA, EN = IN, Co = 1 F, Ci = 1 F (unless otherwise noted) PARAMETER VDO TEST CONDITIONS TPS72525 (4) TPS72518 (4) IO = 1 A MIN TJ = 25C IO = 1 A 280 TJ = 25C 210 IO = 1 A 1.3 Trip threshold voltage 90 Hysteresis voltage Leakage current (4) 4 mV V 93 96 10 25 Rising edge deglitch Output low voltage (at 700 A) UNIT 320 Minimum input voltage for valid RESET t(RESET) delay time MAX 170 IO = 1 A Dropout voltage RESET TYP 50 mV 75 10 -0.3 %VO ms s 0.4 V 100 nA Dropout voltage is defined as the differential voltage between VO and VI when VO drops 100 mV below the value measured with VI = VO + 1 V. TPS72501 TPS72515, TPS72516 TPS72518, TPS72525 www.ti.com SLVS341D - MAY 2002 - REVISED MARCH 2004 FUNCTIONAL BLOCK DIAGRAM--ADJUSTABLE VERSION TPS72501 IN OUT EN Current Limit/Thermal Protection 1.220 Vref FB GND FUNCTIONAL BLOCK DIAGRAM--FIXED VERSION TPS72515/16/18/25 IN OUT EN Current Limit/Thermal Protection 1.220 Vref GND Deglitch and Delay RESET 0.93 x Vref TERMINAL FUNCTIONS TERMINAL NAME NO. D NO.D CQ & KTT I/O ENABLE 5 1 I FB 2 GND 3, 6, 7 3 IN 8 2 I RESET/FB -- 5 O/I NC 4 -- OUT 1 4 DESCRIPTION Enable input Feedback Ground Input supply voltage This terminal is the feedback point for the adjustable option TPS72501. For all other options, this terminal is the RESET output terminal. When used with a pullup resistor, this open-drain output provides the active low RESET signal when the regulator output voltage drops more than 5% below its nominal output voltage. The RESET delay time is typically 50 ms. No connection O Regulated output voltage 5 TPS72501 TPS72515, TPS72516 TPS72518, TPS72525 www.ti.com SLVS341D - MAY 2002 - REVISED MARCH 2004 RESET TIMING DIAGRAM IN VRES (see Note A) VRES t OUT VIT+(see Note B) VIT+(see Note B) Threshold Voltage VIT- (see Note B) VIT- (see Note B) t RESET Output Output Undefined 50 ms Delay 50 ms Delay Output Undefined t NOTES:A. VRES is the minimum input voltage for a valid RESET. The symbol VRES is not currently listed within EIA or JEDEC standards for semiconductor symbology. B. VIT -Trip voltage is typically 7% lower than the output voltage (93%VO) VIT- to VIT+ is the hysteresis voltage. 6 TPS72501 TPS72515, TPS72516 TPS72518, TPS72525 www.ti.com SLVS341D - MAY 2002 - REVISED MARCH 2004 TYPICAL CHARACTERISTICS TPS72518 OUTPUT VOLTAGE vs OUTPUT CURRENT TPS72518 OUTPUT VOLTAGE vs JUNCTION TEMPERATURE 1.805 1.8015 250 1.8 1.7995 Ground Current - A V O - Output Voltage - V 1.8005 1.800 IO = 0 mA 1.795 IO = 1 A 1.790 200 IO = 0 mA 100 50 1.7985 0 0.2 0.4 0.8 0.6 1 IO - Output Current - A 1.785 -40-25 -10 5 20 35 50 65 80 95 110 125 TJ - Junction Temperature - C 0 -40 -25 -10 5 Figure 2. Figure 3. TPS72518 GROUND CURRENT vs OUTPUT CURRENT TPS72525 DC DROPOUT VOLTAGE vs OUTPUT CURRENT TPS72518 DROPOUT VOLTAGE vs JUNCTION TEMPERATURE 300 300 VO = 1.7 V Co = 1 F VO = 2.5 V (nom) 175 125 100 75 50 25 V DO - Dropout Voltage - mV V DO - Dropout Voltage - mV 250 150 TJ = 125C 200 TJ = 25C 150 100 TJ = -40C 50 250 150 100 0 0.1 1 10 100 0 1000 IO - Output Current - mA 0.2 0.4 0.6 0.8 IO - Output Current - A IO = 1 A 200 50 IO = 10 mA 0 -40 -25 -10 5 1 20 35 50 65 80 95 110 125 TJ - Junction Temperature - C Figure 4. Figure 5. Figure 6. MINIMUM REQUIRED INPUT VOLTAGE vs OUTPUT VOLTAGE TPS72518 LINE TRANSIENT RESPONSE TPS72518 LOAD TRANSIENT RESPONSE 4 VI - Input Voltage - V 4.5 TJ = 125C 3.5 TJ = 25C IO = 1 A Co = 10 F 3.8 2.8 VO - Change in Output Voltage - mV 0 0.01 20 35 50 65 80 95 110 125 TJ - Junction Temperature - C Figure 1. 200 VO = 2.8 V Co = 10 F Ci = 1 F 100 0 -100 2.5 TJ = -40C 2 1.5 1.5 2 2.5 3 3.5 VO - Output Voltage - V Figure 7. 4 4.5 VO - Output Voltage - mV 3 100 0 -100 0 50 100 150 200 250 300 350 400 450 500 t - Time - s Figure 8. I O - Output Current - A Ground Current - A IO = 1 A 150 1.799 V I - Minimum Required Input Voltage - V VI = 2.8 V Co = 1 F TJ = 25 C VI = 2.8 V Co = 1 F VI = 2.8 V Co = 1 F TJ = 25 C 1.801 V O - Output Voltage - V TPS72518 GROUND CURRENT vs JUNCTION TEMPERATURE 1 0.5 0 0 5 10 15 20 25 30 35 40 45 50 t - Time - s Figure 9. 7 TPS72501 TPS72515, TPS72516 TPS72518, TPS72525 www.ti.com SLVS341D - MAY 2002 - REVISED MARCH 2004 TYPICAL CHARACTERISTICS (continued) TPS72518 OUTPUT VOLTAGE, ENABLE VOLTAGE vs TIME (START-UP) 1 0.5 0 0 5 10 15 20 25 30 35 40 t - Time - s 45 50 1 0 2 1.5 1 0.5 0 0 80 100 120 140 160 180 200 t - Time - s 20 40 60 RL = 1.8 Co = 1 F Ci = 1 F 5 4 3 VI 2 1 0 VO 0 100 200 300 400 500 600 700 800 900 1000 t - Time - s Figure 11. Figure 12. TPS72518 OUTPUT SPECTRAL NOISE DENSITY vs FREQUENCY OUTPUT IMPEDANCE vs FREQUENCY TPS72518 RIPPLE REJECTION vs FREQUENCY 10 2 IO = 1 A 1.5 1 0.5 100 0 10 100 1k 10 k f - Frequency - Hz 0.1 VI = 2.8 V Co = 10 F TJ = 25 C 0.01 80 70 60 10 F / 1mA 50 40 30 10 F / 1 A 20 10 0 0 10 100 k IO = 1 mA 1 IO = 1 mA VI= 2.8 V, VO = 1.8 V, CO = 10 F 90 IO = 1 A Ripple Rejection - dB VI = 2.8 V Co = 10 F Z o - Output Impedance - V/ 2.5 VI = 2.8 V IO = 1 A Co = 10 F 2 Figure 10. 3.5 3 3 VI - Input Voltage - V VI = 2.8 V Co = 1 F CI = 1 F TPS72518 POWER UP/POWER DOWN VO - Output Voltage - V -100 Output Spectral Noise Density - Hz Enable Voltage - V 0 V - Output Voltage - V O 100 IO - Output Current - A VO - Change in Output Voltage - mV TPS72518 LOAD TRASIENT RESPONSE 100 1k 10 k 100 k 1M 10 100 f - Frequency - Hz 10 k 100 k Figure 13. Figure 14. Figure 15. CURRENT LIMIT vs INPUT VOLTAGE TPS72515 GROUND CURRENT vs INPUT VOLTAGE DROPOUT VOLTAGE vs INPUT VOLTAGE 2000 600 300 500 250 Ground Current - A TJ = 125C 1800 1700 1600 1500 TJ = 25C 1400 TJ = -40C 1300 V DO - Dropout Voltage - mV 1900 Current Limit - A 1k 400 300 I=1A 200 I=0A 1200 1M f - Frequency - Hz 100 TJ = 125C TJ = 25C 200 150 100 TJ = -40C 50 1100 1000 1.5 2.5 3 3.5 4 4.5 VI - Input voltage - V Figure 16. 8 0 0 2 5 5.5 0 1 2 3 4 VI - Input Voltage - V Figure 17. 5 6 1.5 2 2.5 3 3.5 4 4.5 VI - Input Voltage - V Figure 18. 5 5.5 TPS72501 TPS72515, TPS72516 TPS72518, TPS72525 www.ti.com SLVS341D - MAY 2002 - REVISED MARCH 2004 APPLICATION INFORMATION The TPS725xx family of low-dropout (LDO) regulators has numerous features that make it applicable to a wide range of applications. The family operates with very low input voltage (1.8 V) and low dropout voltage (typically 200 mV at full load), making it an efficient stand-alone power supply or post regulator for battery or switch mode power supplies. Both the active low RESET and 1-A output current make the TPS725xx family ideal for powering processor and FPGA supplies. The TPS725xx family also has low output noise (typically 150 VRMS with 10-F output capacitor), making it ideal for use in telecom equipment. External Capacitor Requirements A 1-F or larger ceramic input bypass capacitor, connected between IN and GND and located close to the TPS725xx, is required for stability. To improve transient response, noise rejection, and ripple rejection, an additional 10-F or larger, low ESR capacitor is recommended. A higher-value, low ESR input capacitor may be necessary if large, fast-rise-time load transients are anticipated and the device is located several inches from the power source, especially if the minimum input voltage of 1.8 V is used. Although an output capacitor is not required for stability, transient response and output noise are improved with a 10-F output capacitor. Programming the TPS72501 Adjustable LDO Regulator The output voltage of the TPS72501 adjustable regulator is programmed using an external resistor divider as shown in Figure 19. The output voltage is calculated using: V O V ref 1 R1 R2 (1) Where: * VFB = VREF = 1.22 V typical (see the electrical characteristics for VREF range) Resistors R1 and R2 should be chosen for approximately 10-A divider current. Lower value resistors offer no inherent advantage and waste more power. Higher values should be avoided as leakage currents at FB increase the output voltage error. The recommended design procedure is to choose R2 = 120 k to set the divider current at 10 A and then calculate R1 using: R1 V V O 1 ref R2 (2) TPS72501 VI 1 F 1.3 V OUTPUT VOLTAGE PROGRAMMING GUIDE (Standard 1% Resistor Values) IN PROGRAM VOLTAGE EN OUT VO R1 0.4 V FB GND 1.22 V R2 Co ACTUAL R1 (K) R2 (k) VOLTAGE 1.8 V 56.2 118 1.801 2.5 V 127 121 2.500 3.3 V 196 115 3.299 3.6 V 205 105 3.602 Figure 19. TPS72501 Adjustable LDO Regulator Programming 9 TPS72501 TPS72515, TPS72516 TPS72518, TPS72525 www.ti.com SLVS341D - MAY 2002 - REVISED MARCH 2004 APPLICATION INFORMATION (continued) Regulator Protection The TPS725xx pass element has a built-in back diode that safely conducts reverse current when the input voltage drops below the output voltage (e.g., during power down). Current is conducted from the output to the input and is not internally limited. If extended reverse voltage is anticipated, external limiting might be appropriate. The TPS725xx also features internal current limiting and thermal protection. During normal operation, the TPS725xx limits output current to approximately 1.6 A. When current limiting engages, the output voltage scales back linearly until the overcurrent condition ends. While current limiting is designed to prevent gross device failure, care should be taken not to exceed the power dissipation ratings of the package. If the temperature of the device exceeds 165C, thermal-protection circuitry shuts it down. Once the device has cooled down to below 145C, regulator operation resumes. THERMAL INFORMATION The amount of heat that an LDO linear regulator generates is directly proportional to the amount of power it dissipates during operation. All integrated circuits have a maximum allowable junction temperature (TJmax) above which normal operation is not assured. A system designer must design the operating environment so that the operating junction temperature (TJ) does not exceed the maximum junction temperature (TJmax). The two main environmental variables that a designer can use to improve thermal performance are air flow and external heatsinks. The purpose of this information is to aid the designer in determining the proper operating environment for a linear regulator that is operating at a specific power level. In general, the maximum expected power (PD(max)) consumed by a linear regulator is computed as: P max V V I V xI D I(avg) O(avg) O(avg) I(avg) (Q) (3) Where: * VI(avg) is the average input voltage. * VO(avg) is the average output voltage. * IO(avg) is the average output current. * I(Q) is the quiescent current. For most TI LDO regulators, the quiescent current is insignificant compared to the average output current; therefore, the term VI(avg) x I(Q) can be neglected. The operating junction temperature is computed by adding the ambient temperature (TA) and the increase in temperature due to the regulator's power dissipation. The temperature rise is computed by multiplying the maximum expected power dissipation by the sum of the thermal resistances between the junction and the case (RJC), the case to heatsink (RCS), and the heatsink to ambient (RSA). Thermal resistances are measures of how effectively an object dissipates heat. Typically, the larger the device, the more surface area available for power dissipation and the lower the object's thermal resistance. Figure 20 illustrates these thermal resistances for (a) a SOT223 package mounted in a JEDEC low-K board, and (b) a DDPAK package mounted on a JEDEC high-K board. 10 TPS72501 TPS72515, TPS72516 TPS72518, TPS72525 www.ti.com SLVS341D - MAY 2002 - REVISED MARCH 2004 THERMAL INFORMATION (continued) A TJ RJC CIRCUIT BOARD COPPER AREA C B B A B TC RCS A C RSA SOT223 Package (a) TA DDPAK Package (b) C Figure 20. Thermal Resistances Equation 4 summarizes the computation: T J T PDmax x R R R A JC CS SA (4) The RJC is specific to each regulator as determined by its package, lead frame, and die size provided in the regulator's data sheet. The RSA is a function of the type and size of heatsink. For example, black body radiator type heatsinks can have RCS values ranging from 5C/W for very large heatsinks to 50C/W for very small heatsinks. The RCS is a function of how the package is attached to the heatsink. For example, if a thermal compound is used to attach a heatsink to a SOT223 package, RCSof 1C/W is reasonable. Even if no external black body radiator type heatsink is attached to the package, the board on which the regulator is mounted provides some heatsinking through the pin solder connections. Some packages, like the DDPAK and SOT223 packages, use a copper plane underneath the package or the circuit board's ground plane for additional heatsinking to improve their thermal performance. Computer-aided thermal modeling can be used to compute very accurate approximations of an integrated circuit's thermal performance in different operating environments (e.g., different types of circuit boards, different types and sizes of heatsinks, different air flows, etc.). Using these models, the three thermal resistances can be combined into one thermal resistance between junction and ambient (RJA). This RJAis valid only for the specific operating environment used in the computer model. Equation 4 simplifies into Equation 5: T T PDmax x R J A JA Rearranging Equation 5 gives Equation 6: T -T R J A JA P max D (5) (6) Using Equation 5 and the computer model generated curves shown in Figure 21 and Figure 24, a designer can quickly compute the required heatsink thermal resistance/board area for a given ambient temperature, power dissipation, and operating environment. DDPAK Power Dissipation The DDPAK package provides an effective means of managing power dissipation in surface mount applications. The DDPAK package dimensions are provided in the Mechanical Data section at the end of the data sheet. The addition of a copper plane directly underneath the DDPAK package enhances the thermal performance of the package. 11 TPS72501 TPS72515, TPS72516 TPS72518, TPS72525 www.ti.com SLVS341D - MAY 2002 - REVISED MARCH 2004 THERMAL INFORMATION (continued) To illustrate, the TPS72525 in a DDPAK package was chosen. For this example, the average input voltage is 5 V, the output voltage is 2.5 V, the average output current is 1 A, the ambient temperature 55C, the air flow is 150 LFM, and the operating environment is the same as documented below. Neglecting the quiescent current, the maximum average power is: P Dmax (5 2.5) V x 1 A 2.5 W (7) Substituting TJmax for TJ into Equation 6 gives Equation 8: R max (125 55)C2.5 W 28CW JA (8) 2 From Figure 21, DDPAK Thermal Resistance vs Copper Heatsink Area, the ground plane needs to be 1 cm for the part to dissipate 2.5 W. The operating environment used in the computer model to construct Figure 21 consisted of a standard JEDEC High-K board (2S2P) with a 1 oz. internal copper plane and ground plane. The package is soldered to a 2 oz. copper pad. The pad is tied through thermal vias to the 1 oz. ground plane. Figure 22 shows the side view of the operating environment used in the computer model. 40 R JA - Thermal Resistance - C/W No Air Flow 35 150 LFM 30 250 LFM 25 20 15 0.1 1 10 Copper Heatsink Area - cm2 100 Figure 21. DDPAK Thermal Resistance vs Copper Heatsink Area 2 oz. Copper Solder Pad with 25 Thermal Vias 1 oz. Copper Power Plane 1 oz. Copper Ground Plane Thermal Vias, 0.3 mm Diameter, 1,5 mm Pitch Figure 22. DDPAK Thermal Resistance 12 TPS72501 TPS72515, TPS72516 TPS72518, TPS72525 www.ti.com SLVS341D - MAY 2002 - REVISED MARCH 2004 THERMAL INFORMATION (continued) From the data in Figure 23 and rearranging Equation 6, the maximum power dissipation for a different ground plane area and a specific ambient temperature can be computed. TJM - Maximum Junction Temperature - 125 C 5 PD - Maximum Power Dissipation - W TA = 55C 4 250 LFM 150 LFM 3 No Air Flow 2 1 0.1 1 10 Copper Heatsink Area - cm2 100 Figure 23. Maximum Power Dissipation vs Copper Heatsink Area SOT223 Power Dissipation The SOT223 package provides an effective means of managing power dissipation in surface mount applications. The SOT223 package dimensions are provided in the Mechanical Data section at the end of the data sheet. The addition of a copper plane directly underneath the SOT223 package enhances the thermal performance of the package. To illustrate, the TPS72525 in a SOT223 package was chosen. For this example, the average input voltage is 3.3 V, the output voltage is 2.5 V, the average output current is 1 A, the ambient temperature 55C, no air flow is present, and the operating environment is the same as documented below. Neglecting the quiescent current, the maximum average power is: P Dmax (3.3 2.5) V x 1 A 800 mW (9) Substituting TJmax for TJ into Equation 6 gives Equation 10: R max (125 55)C800 mW 87.5CW JA (10) 2 From Figure 24, RJA vs PCB Copper Area, the ground plane needs to be 0.55 in for the part to dissipate 800 mW. The operating environment used to construct Figure 24 consisted of a board with 1 oz. copper planes. The package is soldered to a 1 oz. copper pad on the top of the board. The pad is tied through thermal vias to the 1 oz. ground plane. 13 TPS72501 TPS72515, TPS72516 TPS72518, TPS72525 www.ti.com SLVS341D - MAY 2002 - REVISED MARCH 2004 THERMAL INFORMATION (continued) R JA - Thermal Resistance - C/W 180 No Air Flow 160 140 120 100 80 60 40 20 0 0.1 1 PCB Copper Area - in2 10 Figure 24. SOT223 Thermal Resistance vs PCB AREA From the data in Figure 24 and rearranging Equation 6, the maximum power dissipation for a different ground plane area and a specific ambient temperature can be computed (as shown in Figure 25). 6 PD - Maximum Power Dissipation - W TA = 25C 5 4 4 in2 PCB Area 3 0.5 in2 PCB Area 2 1 0 0 25 50 75 100 125 TA - Ambient Temperature - C Figure 25. SOT223 Power Dissipation 14 150 PACKAGE OPTION ADDENDUM www.ti.com 16-Mar-2007 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TPS72501DCQ ACTIVE SOT-223 DCQ 6 78 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS72501DCQG4 ACTIVE SOT-223 DCQ 6 78 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS72501DCQR ACTIVE SOT-223 DCQ 6 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS72501DCQRG4 ACTIVE SOT-223 DCQ 6 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS72501DR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS72501DRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS72501DT ACTIVE SOIC D 8 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS72501DTG4 ACTIVE SOIC D 8 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS72501KTT OBSOLETE DDPAK/ TO-263 KTT 5 TBD Call TI Call TI TPS72501KTTR ACTIVE DDPAK/ TO-263 KTT 5 500 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR TPS72501KTTRG3 ACTIVE DDPAK/ TO-263 KTT 5 500 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR TPS72501KTTT ACTIVE DDPAK/ TO-263 KTT 5 50 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR TPS72501KTTTG3 ACTIVE DDPAK/ TO-263 KTT 5 50 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR TPS72515DCQ ACTIVE SOT-223 DCQ 6 78 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS72515DCQG4 ACTIVE SOT-223 DCQ 6 78 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS72515DCQR ACTIVE SOT-223 DCQ 6 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS72515DCQRG4 ACTIVE SOT-223 DCQ 6 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS72515KTT OBSOLETE DDPAK/ TO-263 KTT 5 TPS72515KTTR ACTIVE DDPAK/ TO-263 KTT 5 TPS72515KTTRG3 ACTIVE DDPAK/ TO-263 KTT TPS72515KTTT ACTIVE DDPAK/ TO-263 TPS72515KTTTG3 ACTIVE TPS72516DCQ Lead/Ball Finish MSL Peak Temp (3) TBD Call TI Call TI 500 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR 5 500 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR KTT 5 50 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR DDPAK/ TO-263 KTT 5 50 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR ACTIVE SOT-223 DCQ 6 78 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS72516DCQG4 ACTIVE SOT-223 DCQ 6 78 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS72516DCQR ACTIVE SOT-223 DCQ 6 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 16-Mar-2007 Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TPS72516DCQRG4 ACTIVE SOT-223 DCQ 6 TPS72516KTT OBSOLETE DDPAK/ TO-263 KTT 5 TPS72516KTTR ACTIVE DDPAK/ TO-263 KTT 5 TPS72516KTTRG3 ACTIVE DDPAK/ TO-263 KTT TPS72516KTTT ACTIVE DDPAK/ TO-263 TPS72516KTTTG3 ACTIVE TPS72518DCQ 2500 Green (RoHS & no Sb/Br) Lead/Ball Finish CU NIPDAU MSL Peak Temp (3) Level-2-260C-1 YEAR TBD Call TI Call TI 500 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR 5 500 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR KTT 5 50 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR DDPAK/ TO-263 KTT 5 50 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR ACTIVE SOT-223 DCQ 6 78 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS72518DCQG4 ACTIVE SOT-223 DCQ 6 78 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS72518DCQR ACTIVE SOT-223 DCQ 6 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS72518DCQRG4 ACTIVE SOT-223 DCQ 6 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS72518KTT OBSOLETE DDPAK/ TO-263 KTT 5 TPS72518KTTR ACTIVE DDPAK/ TO-263 KTT 5 TPS72518KTTRG3 ACTIVE DDPAK/ TO-263 KTT TPS72518KTTT ACTIVE DDPAK/ TO-263 TPS72518KTTTG3 ACTIVE TPS72525DCQ TBD Call TI Call TI 500 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR 5 500 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR KTT 5 50 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR DDPAK/ TO-263 KTT 5 50 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR ACTIVE SOT-223 DCQ 6 78 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS72525DCQG4 ACTIVE SOT-223 DCQ 6 78 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS72525DCQR ACTIVE SOT-223 DCQ 6 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS72525DCQRG4 ACTIVE SOT-223 DCQ 6 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS72525KTT OBSOLETE DDPAK/ TO-263 KTT 5 TPS72525KTTR ACTIVE DDPAK/ TO-263 KTT 5 TPS72525KTTRG3 ACTIVE DDPAK/ TO-263 KTT TPS72525KTTT ACTIVE DDPAK/ TO-263 TPS72525KTTTG3 ACTIVE DDPAK/ TO-263 TBD Call TI Call TI 500 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR 5 500 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR KTT 5 50 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR KTT 5 50 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. Addendum-Page 2 PACKAGE OPTION ADDENDUM www.ti.com 16-Mar-2007 NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. 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