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FEATURES DESCRIPTION
APPLICATIONS
1
2
3
4
5
DCQ PACKAGE
RESET/FB
OUT
GND
IN
ENABLE
SOT223-5
(TOP VIEW)
1
2
3
4
8
7
6
5
OUT
FB
GND
NC
IN
GND
GND
ENABLE
D PACKAGE
(TOP VIEW)
NC − No internal connection
1
KTT PACKAGE
(TOP VIEW)
2 3 4 5
ENABLE
IN
GND
OUT
DDPAK
RESET/FB
TPS72501TPS72515, TPS72516TPS72518, TPS72525
SLVS341D – MAY 2002 – REVISED MARCH 2004
LOW INPUT VOLTAGE, 1-A LOW-DROPOUT LINEAR REGULATORS WITH SUPERVISOR
•1-A Output Current
The TPS725xx family of 1-A low-dropout (LDO) linearregulators has fixed voltage options available that are•Available in 1.5-V, 1.6-V, 1.8-V, 2.5-V
commonly used to power the latest DSPs, FPGAs,Fixed-Output and Adjustable Versions
and microcontrollers. An adjustable option ranging(1.2-V to 5.5-V)
from 1.22 V to 5.5 V is also available. The integrated•Input Voltage Down to 1.8 V
supervisory circuitry provides an active low RESET•Low 170-mV Dropout Voltage at 1 A
signal when the output falls out of regulation. The no(TPS72525)
capacitor/any capacitor feature allows the customerto tailor output transient performance as needed.•Stable With Any Type/Value Output Capacitor
Therefore, compared to other regulators capable of•Integrated Supervisor (SVS) With 50-ms
providing the same output current, this family ofRESET Delay Time
regulators can provide a stand-alone power supply•Low 210-µA Ground Current at Full Load
solution or a post regulator for a switch mode powersupply.(TPS72525)
•Less than 1-µA Standby Current
These regulators are ideal for higher current appli-cations. The family operates over a wide range of• ±2% Output Voltage Tolerance Over Line,
input voltages (1.8 V to 6 V) and has very lowLoad, and Temperature (-40°C to 125°C)
dropout (170 mV at 1-A).•Integrated UVLO
Ground current is typically 210 µA at full load and•Thermal and Overcurrent Protection
drops to less than 80 µA at no load. Standby current•5-Lead SOT223-5 or DDPAK and 8-Pin SOP
is less than 1 µA.(TPS72501 only) Surface Mount Package
Each regulator option is available in either aSOT223-5, D (TPS72501 only), or DDPAK package.With a low input voltage and properly heatsinked•PCI Cards
package, the regulator dissipates more power and•Modem Banks
achieves higher efficiencies than similar regulators•Telecom Boards requiring 2.5 V or more minimum input voltage andhigher quiescent currents. These features make it a•DSP, FPGA, and Microprocessor Power
viable power supply solution for portable, bat-Supplies
tery-powered equipment.•Portable, Battery-Powered Applications
NOTE: TPS72501 replaces RESET with FB. Tab is GND for the DCK and KTT packages.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2002–2004, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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DESCRIPTION (CONTINUED)
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED OPERATING CONDITIONS
TPS72501
TPS72515, TPS72516TPS72518, TPS72525
SLVS341D – MAY 2002 – REVISED MARCH 2004
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.
Although an output capacitor is not required for stability, transient response and output noise are improved with a10-µF output capacitor.
Unlike some regulators that have a minimum current requirement, the TPS725 family is stable with no outputload current. The low noise capability of this family, coupled with its high current operation and ease of powerdissipation, make it ideal for telecom boards, modem banks, and other noise-sensitive applications.
ORDERING INFORMATION
T
J
VOLTAGE
(1)
SOT223-5
(2)
SYMBOL DDPAK
(3)
D
(4)
SYMBOL
Adjustable (1.2 V to 5 V) TPS72501DCQ PS72501 TPS72501KTT TPS72501D TPS725011.5 V TPS72515DCQ PS72515 TPS72515KTT — TPS72515-40°C to
1.6 V TPS72516DCQ PS72516 TPS72516KTT — TPS72516125°C
1.8 V TPS72518DCQ PS72518 TPS72518KTT — TPS725182.5 V TPS72525DCQ PS72525 TPS72525KTT — TPS72525
(1) Other voltage options are available upon request from the manufacturer.(2) To order a taped and reeled part, add the suffix Rto the part number (e.g., TPS72501DCQR).(3) To order a 50-piece reel, add the suffix T(e.g., TPS72501KTTT); to order a 500-piece reel, add the suffix R(e.g., TPS72501KTTR).(4) To order a taped and reeled part, add the suffix Ror T(2500 or 500) to the part number (e.g. TPS72501DR)
over operating free-air temperature range unless otherwise noted
(1)
UNIT
Input voltage, V
I
(2)
-0.3 to 7 VVoltage range at EN, FB -0.3 to V
I
+ 0.3 VVoltage on OUT, RESET 6 VESD rating, HBM 2 kVContinuous total power dissipation See Dissipation Ratings TableOperating junction temperature range, T
J
-50 to 150 °CMaximum junction temperature range, T
J
150 °CStorage temperature, T
stg
-65 to 150 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under recommended operatingconditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) All voltage values are with respect to network ground terminal.
MIN NOM MAX UNIT
Input voltage, V
I
(1)
1.8 6 VContinuous output current, I
O
0 1 AOperating junction temperature, T
J
-40 125 °C
(1) Minimum V
I
= V
O
(nom) + V
DO
.
2
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Line regulation (mV) %VVO5.5 V VImin
100 1000
PACKAGE DISSIPATION RATINGS
ELECTRICAL CHARACTERISTICS
TPS72501TPS72515, TPS72516TPS72518, TPS72525
SLVS341D – MAY 2002 – REVISED MARCH 2004
PACKAGE BOARD R
θJC
R
θJA
DDPAK High K
(1)
2°C/W 23 °C/WSOT223 Low K
(2)
15 °C/W 53 °C/WD-8 High K
(1)
39.4 °C/W 55 °C/W
(1) The JEDEC high-K (2s2p) board design used to derive this data was a 3-inch x 3-inch (7.5-cm x 7.5-cm), multilayer board with 1 ounceinternal power and ground planes and 2 ounce copper traces on top and bottom of the board.(2) The JEDEC low-K (1s) board design used to derive this data was a 3-inch x 3-inch (7.5-cm x 7.5-cm), two-layer board with 2 ouncecopper traces on top of the board.
over recommended operating free-air temperature range V
I
= V
O(typ)
+ 1 V, I
O
= 1 mA, EN = IN, C
o
= 1 µF, C
i
= 1 µF (unlessotherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Bandgap voltage reference 1.177 1.220 1.263 VTPS72501
0 µA < I
O
< 1 A
(1)
1.22 V ≤V
O
≤5.5 V 0.965 V
O
1.035 V
OAdjustable
T
J
= 25°C 1.5TPS72515
0 µA< I
O
< 1 A 1.8 V ≤V
I
≤5.5 V 1.47 1.53T
J
= 25°C 1.6TPS72516V
O
Output voltage V0 µA < I
O
< 1 A 2.6 V ≤V
I
≤5.5 V 1.568 1.632T
J
= 25°C 1.8TPS72518
0 µA < I
O
< 1 A 2.8 V ≤V
I
≤5.5 V 1.764 1.836T
J
= 25°C 2.5TPS72525
0 µA < I
O
< 1 A 3.5 V ≤V
I
≤5.5 V 2.45 2.55I
O
= 0 µA 75 120I Ground current µAI
O
= 1 A 210 300EN < 0.4 V T
J
= 25°C 0.2Standby current µAEN < 0.4 V 1BW = 200 Hz to 100 kHz, C
o
= 10 µF, I
O
= 1V
n
Output noise voltage 150 µVT
J
= 25°C mAPSRR Ripple rejection f = 1 kHz, C
o
= 10 µF T
J
= 25°C 60 dBCurrent limit
(2)
1.1 1.6 2.3 AOutput voltage line regulation
V
O
+ 1 V < V
I
≤5.5 V -0.15 0.02 0.15 %/V(∆V
O
/V
O
)
(3)
Output voltage load regulation 0 µA < I
O
< 1 A -0.25 0.05 0.25 %/AV
IH
EN high level input
(2)
1.3
VV
IL
EN low level input
(2)
-0.2 0.4I
I
EN input current EN = 0 V or V
I
0.01 100 nAI
(FB)
Feedback current TPS72501 V
(FB)
= 1.22 -100 100 nAUVLO threshold V
CC
rising 1.45 1.57 1.70 VUVLO hysteresis T
J
= 25°C, V
CC
rising 50 mVUVLO deglitch T
J
= 25°C, V
CC
rising 10 µsUVLO delay T
J
= 25°C, V
CC
rising 100 µs
(1) Minimum IN operating voltage used for testing is V
O(typ)
+ 1 V.(2) Test condition includes output voltage V
O
= V
O
- 15% and pulse duration = 10 ms.(3) V
Imin
= (V
O
+ 1) or 1.8 V whichever is greater.
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TPS72501
TPS72515, TPS72516TPS72518, TPS72525
SLVS341D – MAY 2002 – REVISED MARCH 2004
ELECTRICAL CHARACTERISTICS (continued)over recommended operating free-air temperature range V
I
= V
O(typ)
+ 1 V, I
O
= 1 mA, EN = IN, C
o
= 1 µF, C
i
= 1 µF (unlessotherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
I
O
= 1 A T
J
= 25°C 170TPS72525
(4)
I
O
= 1 A 280V
DO
Dropout voltage mVI
O
= 1 A T
J
= 25°C 210TPS72518
(4)
I
O
= 1 A 320Minimum input voltage for valid
1.3 VRESET
Trip threshold voltage 90 93 96 %V
O
Hysteresis voltage 10 mVRESET
t
(RESET)
delay time 25 50 75 msRising edge deglitch 10 µsOutput low voltage (at 700 µA) -0.3 0.4 VLeakage current 100 nA
(4) Dropout voltage is defined as the differential voltage between V
O
and V
I
when V
O
drops 100 mV below the value measured withV
I
= V
O
+ 1 V.
4
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TPS72501
OUT
IN
FB
GND
EN
Vref
Current
Limit/Thermal
Protection
1.220
TPS72515/16/18/25
OUT
IN
GND
EN
Vref
Current
Limit/Thermal
Protection
0.93 × Vref
Deglitch
and
Delay
RESET
1.220
TPS72501TPS72515, TPS72516TPS72518, TPS72525
SLVS341D – MAY 2002 – REVISED MARCH 2004
FUNCTIONAL BLOCK DIAGRAM—ADJUSTABLE VERSION
FUNCTIONAL BLOCK DIAGRAM—FIXED VERSION
TERMINAL FUNCTIONS
TERMINAL
NO.D
I/O DESCRIPTIONNO.NAME CQ &D
KTT
ENABLE 5 1 I Enable inputFB 2 FeedbackGND 3, 6, 7 3 GroundIN 8 2 I Input supply voltageRESET/FB — 5 O/I This terminal is the feedback point for the adjustable option TPS72501. For all other options, thisterminal is the RESET output terminal. When used with a pullup resistor, this open-drain outputprovides the active low RESET signal when the regulator output voltage drops more than 5% belowits nominal output voltage. The RESET delay time is typically 50 ms.NC 4 — No connectionOUT 1 4 O Regulated output voltage
5
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NOTES:A. VRES is the minimum input voltage for a valid RESET. The symbol VRES is not currently listed within EIA or JEDEC standards for
semiconductor symbology .
IN
VRES
(see Note A) VRES
t
t
t
OUT
Threshold
Voltage
RESET
Output 50 ms
Delay 50 ms
Delay
Output
Undefined
Output
Undefined
VIT+(see Note B)
VIT–
(see Note B)
VIT+(see Note B)
B. VIT –T rip voltage is typically 7% lower than the output voltage (93%VO) VIT– to VIT+ is the hysteresis voltage.
VIT–
(see Note B)
TPS72501
TPS72515, TPS72516TPS72518, TPS72525
SLVS341D – MAY 2002 – REVISED MARCH 2004
RESET TIMING DIAGRAM
6
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TYPICAL CHARACTERISTICS
1.785
1.795
1.805
−40−25−10 5 20 35 50 65 80 95 110 125
1.790
1.800
VI = 2.8 V
Co = 1 µF
TJ − Junction Temperature − °C
− Output Voltage − V
VO
IO = 1 A
IO = 0 mA
0 0.2 0.4 0.8
IO − Output Current − A
− Output Voltage − V
VO
10.6
VI = 2.8 V
Co = 1 µF
TJ = 25° C
1.7985
1.799
1.7995
1.8
1.8005
1.801
1.8015
0
50
100
150
200
250
−40−25−10 5 20 35 50 65 80 95 110 125
TJ − Junction Temperature − °C
Ground Current − Aµ
IO = 0 mA
VI = 2.8 V
Co = 1 µF
TJ = 25° CIO = 1 A
0
50
100
150
200
250
300
0 0.2 0.4 0.6 0.8 1
TJ = 125°C
TJ = 25°C
TJ = −40°C
− Dropout Voltage − mV
IO − Output Current − A
VDO
VO = 2.5 V (nom)
−40−25−10 5 20 35 50 65 80 95 110 125
IO = 1 A
IO = 10 mA
VO = 1.7 V
Co = 1 µF
TJ − Junction Temperature − °C
− Dropout Voltage − mV
VDO
0
50
100
150
200
250
300
0
25
50
75
100
125
150
175
200
0.01 0.1 1 10 100 1000
IO − Output Current − mA
Ground Current − Aµ
VO = 2.8 V
Co = 10 µF
Ci = 1 µF
− Output Current − A Output V oltage − mV
VO
∆
IO
− Change in
t − Time − µs
0 5 10 15 20 25 30 35 40 45 50
0
0.5
1
−100
0
100
t − Time − µs
100
−100
0 50 100 150 200 250 300
2.8
350 400 450 500
3.8
0
IO = 1 A
Co = 10 µF
− Input Voltage − V− Output Voltage − mVVOVI
1.5
2
2.5
3
3.5
4
4.5
1.5 2 2.5 3 3.5 4 4.5
TJ = 25°C
TJ = 125°C
TJ = −40°C
− Minimum Required Input Voltage − V
VO − Output Voltage − V
VI
TPS72501TPS72515, TPS72516TPS72518, TPS72525
SLVS341D – MAY 2002 – REVISED MARCH 2004
TPS72518 TPS72518 TPS72518OUTPUT VOLTAGE OUTPUT VOLTAGE GROUND CURRENTvs vs vsOUTPUT CURRENT JUNCTION TEMPERATURE JUNCTION TEMPERATURE
Figure 1. Figure 2. Figure 3.
TPS72518 TPS72525 TPS72518GROUND CURRENT DC DROPOUT VOLTAGE DROPOUT VOLTAGEvs vs vsOUTPUT CURRENT OUTPUT CURRENT JUNCTION TEMPERATURE
Figure 4. Figure 5. Figure 6.
MINIMUM REQUIRED
INPUT VOLTAGE
vs TPS72518 TPS72518OUTPUT VOLTAGE LINE TRANSIENT RESPONSE LOAD TRANSIENT RESPONSE
Figure 7. Figure 8. Figure 9.
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IO
t − Time − µs
015105 20 25 3530 40 45 50
− Output Current − A
VI = 2.8 V
Co = 1 µF
CI = 1 µF
1
0.5
0
−100
100
0
Output Voltage − mV
VO
∆− Change in
160
2
VO
t − Time − µs
0604020 80 100 140120 180 200
− Output Voltage − V
VI = 2.8 V
IO = 1 A
Co = 10 µF
Enable Voltage − V
1
1
0
0
1.5
2
3
0.5
t − Time − µs
1
0100 200 300 400 500 600
− Input Voltage − V
3
700 800 900 1000
5
0
− Output Voltage − VVOVI
4
2
VO
VI
RL = 1.8 Ω
Co = 1 µF
Ci = 1 µF
0
0.5
1
1.5
2
2.5
3
3.5
10 100 1 k 10 k 100 k
f − Frequency − Hz
IO = 1 mA
VI = 2.8 V
Co = 10 µF
IO = 1 A
V/ HzOutput Spectral Noise Density − µ
0.1
10 100 1 k 10 k
1
10
100 k 1 M
0.01
0
f − Frequency − Hz
− Output Impedance −ZoΩ
IO = 1 mA
IO = 1 A
VI = 2.8 V
Co = 10 µF
TJ = 25° C
50
30
20
010 100 1 k 10 k
Ripple Rejection − dB
70
90
f − Frequency − Hz
100
100 k 1 M
80
60
40
10
10 µF / 1mA
10 µF / 1 A
VI= 2.8 V,
VO = 1.8 V,
CO = 10 µF
0
50
100
150
200
250
300
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VI − Input Voltage − V
− Dropout Voltage − mV
VDO
TJ = 25°C
TJ = −40°C
TJ = 125°C
1000
1100
1200
1300
1400
1500
1600
1700
1800
1900
2000
1.5 2 2.5 3 3.5 4 4.5 5 5.5
TJ = 25°C
VI − Input voltage − V
Current Limit − A
TJ = −40°C
TJ = 125°C
0
100
200
300
400
500
600
0123456
I = 0 A
VI − Input Voltage − V
Ground Current − Aµ
I = 1 A
TPS72501
TPS72515, TPS72516TPS72518, TPS72525
SLVS341D – MAY 2002 – REVISED MARCH 2004
TYPICAL CHARACTERISTICS (continued)
TPS72518 OUTPUT VOLTAGE,ENABLE VOLTAGETPS72518 vs TPS72518LOAD TRASIENT RESPONSE TIME (START-UP) POWER UP/POWER DOWN
Figure 10. Figure 11. Figure 12.
TPS72518 OUTPUT SPECTRAL TPS72518NOISE DENSITY OUTPUT IMPEDANCE RIPPLE REJECTIONvs vs vsFREQUENCY FREQUENCY FREQUENCY
Figure 13. Figure 14. Figure 15.
CURRENT LIMIT TPS72515 GROUND CURRENT DROPOUT VOLTAGEvs vs vsINPUT VOLTAGE INPUT VOLTAGE INPUT VOLTAGE
Figure 16. Figure 17. Figure 18.
8
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APPLICATION INFORMATION
External Capacitor Requirements
Programming the TPS72501 Adjustable LDO Regulator
VOVref 1R1
R2
(1)
R1 VO
Vref 1R2
(2)
VO
VI
OUT
FB
R1
R2
GND
EN
IN
TPS72501
1 µF
Co
OUTPUT VOLTAGE
PROGRAMMING GUIDE
(Standard 1% Resistor Values)
PROGRAM
VOLTAGE R1 (KΩ)R2 (kΩ)
1.8 V
2.5 V
3.3 V
3.6 V
ACTUAL
VOLTAGE
56.2
127
196
205
118
121
115
105
1.801
2.500
3.299
3.602
1.22 V
≤ 0.4 V
≥ 1.3 V
TPS72501TPS72515, TPS72516TPS72518, TPS72525
SLVS341D – MAY 2002 – REVISED MARCH 2004
The TPS725xx family of low-dropout (LDO) regulators has numerous features that make it applicable to a widerange of applications. The family operates with very low input voltage (≥1.8 V) and low dropout voltage (typically200 mV at full load), making it an efficient stand-alone power supply or post regulator for battery or switch modepower supplies. Both the active low RESET and 1-A output current make the TPS725xx family ideal for poweringprocessor and FPGA supplies. The TPS725xx family also has low output noise (typically 150 µV
RMS
with 10-µFoutput capacitor), making it ideal for use in telecom equipment.
A 1-µF or larger ceramic input bypass capacitor, connected between IN and GND and located close to theTPS725xx, is required for stability. To improve transient response, noise rejection, and ripple rejection, anadditional 10-µF or larger, low ESR capacitor is recommended. A higher-value, low ESR input capacitor may benecessary if large, fast-rise-time load transients are anticipated and the device is located several inches from thepower source, especially if the minimum input voltage of 1.8 V is used.
Although an output capacitor is not required for stability, transient response and output noise are improved with a10-µF output capacitor.
The output voltage of the TPS72501 adjustable regulator is programmed using an external resistor divider asshown in Figure 19 . The output voltage is calculated using:
Where:
•V
FB
= V
REF
= 1.22 V typical (see the electrical characteristics for V
REF
range)
Resistors R1 and R2 should be chosen for approximately 10-µA divider current. Lower value resistors offer noinherent advantage and waste more power. Higher values should be avoided as leakage currents at FB increasethe output voltage error. The recommended design procedure is to choose R2 = 120 kΩto set the divider currentat 10 µA and then calculate R1 using:
Figure 19. TPS72501 Adjustable LDO Regulator Programming
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Regulator Protection
THERMAL INFORMATION
PDmax VI(avg) VO(avg)IO(avg) VI(avg)x I(Q)
(3)
TPS72501
TPS72515, TPS72516TPS72518, TPS72525
SLVS341D – MAY 2002 – REVISED MARCH 2004
APPLICATION INFORMATION (continued)
The TPS725xx pass element has a built-in back diode that safely conducts reverse current when the inputvoltage drops below the output voltage (e.g., during power down). Current is conducted from the output to theinput and is not internally limited. If extended reverse voltage is anticipated, external limiting might beappropriate.
The TPS725xx also features internal current limiting and thermal protection. During normal operation, theTPS725xx limits output current to approximately 1.6 A. When current limiting engages, the output voltage scalesback linearly until the overcurrent condition ends. While current limiting is designed to prevent gross devicefailure, care should be taken not to exceed the power dissipation ratings of the package. If the temperature of thedevice exceeds 165°C, thermal-protection circuitry shuts it down. Once the device has cooled down to below145°C, regulator operation resumes.
The amount of heat that an LDO linear regulator generates is directly proportional to the amount of power itdissipates during operation. All integrated circuits have a maximum allowable junction temperature (T
J
max)above which normal operation is not assured. A system designer must design the operating environment so thatthe operating junction temperature (T
J
) does not exceed the maximum junction temperature (T
J
max). The twomain environmental variables that a designer can use to improve thermal performance are air flow and externalheatsinks. The purpose of this information is to aid the designer in determining the proper operating environmentfor a linear regulator that is operating at a specific power level.
In general, the maximum expected power (P
D(max)
) consumed by a linear regulator is computed as:
Where:
•V
I(avg)
is the average input voltage.•V
O(avg)
is the average output voltage.•I
O(avg)
is the average output current.•I
(Q)
is the quiescent current.
For most TI LDO regulators, the quiescent current is insignificant compared to the average output current;therefore, the term V
I(avg)
x I
(Q)
can be neglected. The operating junction temperature is computed by adding theambient temperature (T
A
) and the increase in temperature due to the regulator's power dissipation. Thetemperature rise is computed by multiplying the maximum expected power dissipation by the sum of the thermalresistances between the junction and the case (R
θJC
), the case to heatsink (R
θCS
), and the heatsink to ambient(R
θSA
). Thermal resistances are measures of how effectively an object dissipates heat. Typically, the larger thedevice, the more surface area available for power dissipation and the lower the object's thermal resistance.
Figure 20 illustrates these thermal resistances for (a) a SOT223 package mounted in a JEDEC low-K board, and(b) a DDPAK package mounted on a JEDEC high-K board.
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A
B
C
TJ
A
RθJC
TC
B
RθCS
TA
C
RθSA
(a) (b)
DDPAK Package
SOT223 Package
CIRCUIT BOARD COPPER AREA
B
A
C
TJTAPDmax x RθJC RθCS RθSA
(4)
TJTAPDmax x RθJA
(5)
RθJA
TJ–TA
PDmax
(6)
DDPAK Power Dissipation
TPS72501TPS72515, TPS72516TPS72518, TPS72525
SLVS341D – MAY 2002 – REVISED MARCH 2004
THERMAL INFORMATION (continued)
Figure 20. Thermal Resistances
Equation 4 summarizes the computation:
The R
θJC
is specific to each regulator as determined by its package, lead frame, and die size provided in theregulator's data sheet. The R
θSA
is a function of the type and size of heatsink. For example, black body radiatortype heatsinks can have R
θCS
values ranging from 5°C/W for very large heatsinks to 50°C/W for very smallheatsinks. The R
θCS
is a function of how the package is attached to the heatsink. For example, if a thermalcompound is used to attach a heatsink to a SOT223 package, R
θCS
of 1°C/W is reasonable.
Even if no external black body radiator type heatsink is attached to the package, the board on which theregulator is mounted provides some heatsinking through the pin solder connections. Some packages, like theDDPAK and SOT223 packages, use a copper plane underneath the package or the circuit board's ground planefor additional heatsinking to improve their thermal performance. Computer-aided thermal modeling can be usedto compute very accurate approximations of an integrated circuit's thermal performance in different operatingenvironments (e.g., different types of circuit boards, different types and sizes of heatsinks, different air flows,etc.). Using these models, the three thermal resistances can be combined into one thermal resistance betweenjunction and ambient (R
θJA
). This R
θJA
is valid only for the specific operating environment used in the computermodel.
Equation 4 simplifies into Equation 5 :
Rearranging Equation 5 gives Equation 6 :
Using Equation 5 and the computer model generated curves shown in Figure 21 and Figure 24 , a designer canquickly compute the required heatsink thermal resistance/board area for a given ambient temperature, powerdissipation, and operating environment.
The DDPAK package provides an effective means of managing power dissipation in surface mount applications.The DDPAK package dimensions are provided in the Mechanical Data section at the end of the data sheet. Theaddition of a copper plane directly underneath the DDPAK package enhances the thermal performance of thepackage.
11
www.ti.com
PDmax (52.5)V x 1 A 2.5 W
(7)
RθJAmax (125 55)°C2.5 W 28°CW
(8)
15
20
25
30
35
40
0.1 1 10 100
Copper Heatsink Area − cm2
− Thermal Resistance −
θJA
R C/W
°
No Air Flow
150 LFM
250 LFM
1 oz. Copper
Power Plane
1 oz. Copper
Ground Plane
2 oz. Copper Solder Pad
with 25 Thermal Vias
Thermal Vias, 0.3 mm
Diameter, 1,5 mm Pitch
TPS72501
TPS72515, TPS72516TPS72518, TPS72525
SLVS341D – MAY 2002 – REVISED MARCH 2004
THERMAL INFORMATION (continued)To illustrate, the TPS72525 in a DDPAK package was chosen. For this example, the average input voltage is 5V, the output voltage is 2.5 V, the average output current is 1 A, the ambient temperature 55°C, the air flow is150 LFM, and the operating environment is the same as documented below. Neglecting the quiescent current,the maximum average power is:
Substituting T
J
max for T
J
into Equation 6 gives Equation 8 :
From Figure 21 , DDPAK Thermal Resistance vs Copper Heatsink Area, the ground plane needs to be 1 cm
2
forthe part to dissipate 2.5 W. The operating environment used in the computer model to construct Figure 21consisted of a standard JEDEC High-K board (2S2P) with a 1 oz. internal copper plane and ground plane. Thepackage is soldered to a 2 oz. copper pad. The pad is tied through thermal vias to the 1 oz. ground plane.Figure 22 shows the side view of the operating environment used in the computer model.
Figure 21. DDPAK Thermal Resistance vs Copper Heatsink Area
Figure 22. DDPAK Thermal Resistance
12
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− Maximum Junction Temperature − 125
TJM C
°
1
2
3
4
5
0.1 1 10 100
− Maximum Power Dissipation − W
PD
Copper Heatsink Area − cm2
TA = 55°C
No Air Flow
150 LFM
250 LFM
SOT223 Power Dissipation
PDmax (3.3 2.5)V x 1 A 800 mW
(9)
RθJAmax (125 55)°C800 mW 87.5°CW
(10)
TPS72501TPS72515, TPS72516TPS72518, TPS72525
SLVS341D – MAY 2002 – REVISED MARCH 2004
THERMAL INFORMATION (continued)From the data in Figure 23 and rearranging Equation 6 , the maximum power dissipation for a different groundplane area and a specific ambient temperature can be computed.
Figure 23. Maximum Power Dissipation vs Copper Heatsink Area
The SOT223 package provides an effective means of managing power dissipation in surface mount applications.The SOT223 package dimensions are provided in the Mechanical Data section at the end of the data sheet. Theaddition of a copper plane directly underneath the SOT223 package enhances the thermal performance of thepackage.
To illustrate, the TPS72525 in a SOT223 package was chosen. For this example, the average input voltage is3.3 V, the output voltage is 2.5 V, the average output current is 1 A, the ambient temperature 55°C, no air flow ispresent, and the operating environment is the same as documented below. Neglecting the quiescent current, themaximum average power is:
Substituting T
J
max for T
J
into Equation 6 gives Equation 10 :
From Figure 24 , R
ΘJA
vs PCB Copper Area, the ground plane needs to be 0.55 in
2
for the part to dissipate 800mW. The operating environment used to construct Figure 24 consisted of a board with 1 oz. copper planes. Thepackage is soldered to a 1 oz. copper pad on the top of the board. The pad is tied through thermal vias to the 1oz. ground plane.
13
www.ti.com
0
100
120
140
160
180
PCB Copper Area − in2
− Thermal Resistance −
θJA
R C/W
°
No Air Flow
80
60
40
20
0.1 1 10
0
1
2
3
6
0 25 50 75 100 150
− Maximum Power Dissipation − W
PD
125
TA = 25°C
TA − Ambient Temperature − °C
4
5
4 in2 PCB Area
0.5 in2 PCB Area
TPS72501
TPS72515, TPS72516TPS72518, TPS72525
SLVS341D – MAY 2002 – REVISED MARCH 2004
THERMAL INFORMATION (continued)
Figure 24. SOT223 Thermal Resistance vs PCB AREA
From the data in Figure 24 and rearranging Equation 6 , the maximum power dissipation for a different groundplane area and a specific ambient temperature can be computed (as shown in Figure 25 ).
Figure 25. SOT223 Power Dissipation
14
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
TPS72501DCQ ACTIVE SOT-223 DCQ 6 78 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS72501DCQG4 ACTIVE SOT-223 DCQ 6 78 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS72501DCQR ACTIVE SOT-223 DCQ 6 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS72501DCQRG4 ACTIVE SOT-223 DCQ 6 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS72501DR ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS72501DRG4 ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS72501DT ACTIVE SOIC D 8 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS72501DTG4 ACTIVE SOIC D 8 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS72501KTT OBSOLETE DDPAK/
TO-263 KTT 5 TBD Call TI Call TI
TPS72501KTTR ACTIVE DDPAK/
TO-263 KTT 5 500 Green (RoHS &
no Sb/Br) CU SN Level-2-260C-1 YEAR
TPS72501KTTRG3 ACTIVE DDPAK/
TO-263 KTT 5 500 Green (RoHS &
no Sb/Br) CU SN Level-2-260C-1 YEAR
TPS72501KTTT ACTIVE DDPAK/
TO-263 KTT 5 50 Green (RoHS &
no Sb/Br) CU SN Level-2-260C-1 YEAR
TPS72501KTTTG3 ACTIVE DDPAK/
TO-263 KTT 5 50 Green (RoHS &
no Sb/Br) CU SN Level-2-260C-1 YEAR
TPS72515DCQ ACTIVE SOT-223 DCQ 6 78 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS72515DCQG4 ACTIVE SOT-223 DCQ 6 78 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS72515DCQR ACTIVE SOT-223 DCQ 6 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS72515DCQRG4 ACTIVE SOT-223 DCQ 6 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS72515KTT OBSOLETE DDPAK/
TO-263 KTT 5 TBD Call TI Call TI
TPS72515KTTR ACTIVE DDPAK/
TO-263 KTT 5 500 Green (RoHS &
no Sb/Br) CU SN Level-2-260C-1 YEAR
TPS72515KTTRG3 ACTIVE DDPAK/
TO-263 KTT 5 500 Green (RoHS &
no Sb/Br) CU SN Level-2-260C-1 YEAR
TPS72515KTTT ACTIVE DDPAK/
TO-263 KTT 5 50 Green (RoHS &
no Sb/Br) CU SN Level-2-260C-1 YEAR
TPS72515KTTTG3 ACTIVE DDPAK/
TO-263 KTT 5 50 Green (RoHS &
no Sb/Br) CU SN Level-2-260C-1 YEAR
TPS72516DCQ ACTIVE SOT-223 DCQ 6 78 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS72516DCQG4 ACTIVE SOT-223 DCQ 6 78 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS72516DCQR ACTIVE SOT-223 DCQ 6 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
PACKAGE OPTION ADDENDUM
www.ti.com 16-Mar-2007
Addendum-Page 1
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
TPS72516DCQRG4 ACTIVE SOT-223 DCQ 6 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS72516KTT OBSOLETE DDPAK/
TO-263 KTT 5 TBD Call TI Call TI
TPS72516KTTR ACTIVE DDPAK/
TO-263 KTT 5 500 Green (RoHS &
no Sb/Br) CU SN Level-2-260C-1 YEAR
TPS72516KTTRG3 ACTIVE DDPAK/
TO-263 KTT 5 500 Green (RoHS &
no Sb/Br) CU SN Level-2-260C-1 YEAR
TPS72516KTTT ACTIVE DDPAK/
TO-263 KTT 5 50 Green (RoHS &
no Sb/Br) CU SN Level-2-260C-1 YEAR
TPS72516KTTTG3 ACTIVE DDPAK/
TO-263 KTT 5 50 Green (RoHS &
no Sb/Br) CU SN Level-2-260C-1 YEAR
TPS72518DCQ ACTIVE SOT-223 DCQ 6 78 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS72518DCQG4 ACTIVE SOT-223 DCQ 6 78 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS72518DCQR ACTIVE SOT-223 DCQ 6 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS72518DCQRG4 ACTIVE SOT-223 DCQ 6 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS72518KTT OBSOLETE DDPAK/
TO-263 KTT 5 TBD Call TI Call TI
TPS72518KTTR ACTIVE DDPAK/
TO-263 KTT 5 500 Green (RoHS &
no Sb/Br) CU SN Level-2-260C-1 YEAR
TPS72518KTTRG3 ACTIVE DDPAK/
TO-263 KTT 5 500 Green (RoHS &
no Sb/Br) CU SN Level-2-260C-1 YEAR
TPS72518KTTT ACTIVE DDPAK/
TO-263 KTT 5 50 Green (RoHS &
no Sb/Br) CU SN Level-2-260C-1 YEAR
TPS72518KTTTG3 ACTIVE DDPAK/
TO-263 KTT 5 50 Green (RoHS &
no Sb/Br) CU SN Level-2-260C-1 YEAR
TPS72525DCQ ACTIVE SOT-223 DCQ 6 78 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS72525DCQG4 ACTIVE SOT-223 DCQ 6 78 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS72525DCQR ACTIVE SOT-223 DCQ 6 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS72525DCQRG4 ACTIVE SOT-223 DCQ 6 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS72525KTT OBSOLETE DDPAK/
TO-263 KTT 5 TBD Call TI Call TI
TPS72525KTTR ACTIVE DDPAK/
TO-263 KTT 5 500 Green (RoHS &
no Sb/Br) CU SN Level-2-260C-1 YEAR
TPS72525KTTRG3 ACTIVE DDPAK/
TO-263 KTT 5 500 Green (RoHS &
no Sb/Br) CU SN Level-2-260C-1 YEAR
TPS72525KTTT ACTIVE DDPAK/
TO-263 KTT 5 50 Green (RoHS &
no Sb/Br) CU SN Level-2-260C-1 YEAR
TPS72525KTTTG3 ACTIVE DDPAK/
TO-263 KTT 5 50 Green (RoHS &
no Sb/Br) CU SN Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
PACKAGE OPTION ADDENDUM
www.ti.com 16-Mar-2007
Addendum-Page 2
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 16-Mar-2007
Addendum-Page 3
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