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ADC08831 /ADC08832 8-Bit Serial I/O CMOS A/D Converters with Multiplexer and
Sample/Hold Function
Check for Samples: ADC08831,ADC08832
1FEATURES DESCRIPTION
The ADC08831/ADC08832 are 8-bit successive
2• 3-Wire Serial Digital Data Link Requires Few approximation Analog to Digital converters with 3-wire
I/O Pins serial interfaces and a configurable input multiplexer
• Analog Input Track/Hold Function for 2 channels. The serial I/O will interface to
• 2-Channel Input Multiplexer Option with COPSfamily of micro-controllers, PLD's,
microprocessors, DSP's, or shift registers. The serial
Address Logic I/O is configured to comply with the MICROWIRE
• Analog Input Voltage Range from GND to VCC serial data exchange standard.
• No Zero or Full Scale Adjustment Required To minimize total power consumption, the
• TTL/CMOS Input/Output Compatible ADC08831/ADC08832 automatically go into low
• Superior Pin Compatible Replacement for power mode whenever they are not performing
ADC0831/2 conversions.
A track/hold function allows the analog voltage at the
APPLICATIONS positive input to vary during the actual A/D
• Digitizing Sensors and Waveforms conversion.
• Process Control Monitoring The analog inputs can be configured to operate in
various combinations of single-ended, differential, or
• Remote Sensing in Noisy Environments pseudo-differential modes. The voltage reference
• Instrumentation input can be adjusted to allow encoding of small
• Embedded Systems analog voltage spans to the full 8-bits of resolution.
KEY SPECIFICATIONS
• Resolution: 8 Bits
• Conversion Time (fC= 2 MHz): 4μs (Max)
• Power Dissipation: 8.5mW (Typ)
• Low Power Mode: 3.0mW (Typ)
• Single Supply: 5VDC
• Total Unadjusted Error: ±1LSB
• No Missing Codes over Temperature
Typical Application
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 1999–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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Connection Diagram xxx
Figure 1. ADC08831 Figure 2. ADC08832
8-Lead SOIC or VSSOP 8-Lead SOIC or VSSOP
See D or DGK Packages See D or DGK Packages
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings(1)(2)(3)
Supply Voltage (VCC) 6.5V
Voltage at Inputs and Outputs −0.3V to VCC + 0.3V
Input Current at Any Pin(4) ±5 mA
Package Input Current(4) ±20 mA
Human Body Model 2000V
ESD Susceptibility(5) Machine Model 200V
Junction Temperature(6) 150°C
Storage Temperature Range −65° C to 150°C
Mounting Temperature Lead Temp. (soldering, 10 sec) 260°C
Infrared (10 sec) 215°C
(1) All voltages are measured with respect to GND = 0 VDC, unless otherwise specified.
(2) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.
(3) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(4) When the input voltage VIN at any pin exceeds the power supplies (VIN < (GND) or VIN > VCC,) the current at that pin should be limited
to 5 mA. The 20 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an
input current of 5 mA to four pins.
(5) Human body model, 100 pF capacitor discharged through a 1.5 kΩresistor. The machine mode is a 200pF capacitor discharged directly
into each pin.
(6) The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX,θJA and the ambient temperature,
TA. The maximum allowable power dissipation at any temperature is PD= (TJMAX −TA)/θJA or the number given in the Absolute
Maximum Ratings, whichever is lower.
Operating Ratings(1)(2)
Temperature Range −40°C ≤TJ≤+85°C
Supply Voltage 4.5 V to 6.0 V
VSSOP, 8-pin Surface Mount 122°C/W
Thermal Resistance (θjA)SOIC Package, 8-pin Surface Mount 235°C/W
Clock Frequency 10kHz ≤fCLK ≤2MHz
(1) Operating Ratings indicate conditions for which the device is functional. These ratings do not specify specific performance limits. For
specifications and test conditions, see the Electrical Characteristics. The specifications apply only for the test conditions listed. Some
performance characteristics may degrade when the device is not operated under the listed test conditions.
(2) All voltages are measured with respect to GND = 0 VDC, unless otherwise specified.
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Electrical Characteristics
The following specifications apply for VCC = VREF = +5VDC, and fCLK = 2 MHz unless otherwise specified. Boldface limits
apply for TA= TJ= TMIN to TMAX;all other limits TA= TJ= 25°C.
Symbol Parameter Conditions Typical(1) Limits(2) Units (Limits)
CONVERTER AND MULTIPLEXER CHARACTERISTICS
TUE Total Unadjusted Error See(3) ±0.3 ±1 LSB
(max)
Offset Error ±0.2 LSB
DNL Differential NonLinearity ±0.2 LSB
INL Integral NonLinearity ±0.2 LSB
FS Full Scale Error ±0.3 LSB
RREF Reference Input Resistance See(4) 3.5 2.8 kΩ(min)
5.9 kΩ(max)
VIN Analog Input Voltage See(5) (VCC + 0.05) V (max)
(GND −0.05) V (min)
DC Common-Mode Error ±¼ LSB (max)
Power Supply Sensitivity VCC = 5V ±10%, ±¼ LSB (max)
VCC = 5V ±5% ±¼ LSB (max)
On Channel Leakage Current(6) On Channel = 5V, 0.2 μA (max)
Off Channel = 0V 1
On Channel = 0V −0.2 μA (min)
Off Channel = 5V −1
Off Channel Leakage Current(7) On Channel = 5V, Off −0.2 μA (min)
Channel = 0V −1
On Channel = 0V, 0.2 μA (max)
Off Channel = 5V 1
DC CHARACTERISTICS
VIN(1) Logical “1” Input Voltage 2.0 V (min)
VIN(0) Logical “0” Input Voltage 0.8 V (max)
IIN(1) Logical “1” Input Current VIN = 5.0V 0.05 +1 μA (max)
IIN(0) Logical “0” Input Current VIN = 0V 0.05 −1μA (max)
VOUT(1) Logical “1” Output Voltage VCC = 4.75V:
IOUT =−360 μA2.4 V (min)
IOUT =−10 μA4.5 V (min)
VOUT(0) Logical “0” Output Voltage VCC = 4.75V 0.4 V (max)
IOUT = 1.6 mA
(1) Typicals are at TJ= 25°C and represent the most likely parametric norm.
(2) Specified to TI's AOQL (Average Outgoing Quality Level).
(3) Total Unadjusted Error (TUE) includes offset, full-scale, linearity, multiplexer errors.
(4) It is not tested for the ADC08832.
(5) For VIN(−)≥VIN(+) the digital code will be 0000 0000. Two on-chip diodes are tied to each analog input (see ADC08832 Functional Block
Diagram) which will forward-conduct for analog input voltages one diode drop below ground or one diode drop greater than VCC supply.
During testing at low VCC levels (e.g., 4.5V), high level analog inputs (e.g., 5V) can cause an input diode to conduct, especially at
elevated temperatures, which will cause errors for analog inputs near full-scale. The spec allows 50 mV forward bias of either diode; this
means that as long as the analog VIN does not exceed the supply voltage by more than 50 mV, the output code will be correct.
Exceeding this range on an unselected channel will corrupt the reading of a selected channel. Achievement of an absolute 0 VDC to 5
VDC input voltage range will therefore require a minimum supply voltage of 4.950 VDC over temperature variations, initial tolerance and
loading.
(6) Channel leakage current is measured after a single-ended channel is selected and the clock is turned off. For off channel leakage
current the following two cases are considered: one, with the selected channel tied high (5 VDC) and the remaining off channel tied low
(0 VDC), total current flow through the off channel is measured; two, with the selected channel tied low and the off channels tied high,
total current flow through the off channel is again measured. The two cases considered for determining on channel leakage current are
the same except total current flow through the selected channel is measured.
(7) Channel leakage current is measured after a single-ended channel is selected and the clock is turned off. For off channel leakage
current the following two cases are considered: one, with the selected channel tied high (5 VDC) and the remaining off channel tied low
(0 VDC), total current flow through the off channel is measured; two, with the selected channel tied low and the off channels tied high,
total current flow through the off channel is again measured. The two cases considered for determining on channel leakage current are
the same except total current flow through the selected channel is measured.
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Electrical Characteristics (continued)
The following specifications apply for VCC = VREF = +5VDC, and fCLK = 2 MHz unless otherwise specified. Boldface limits
apply for TA= TJ= TMIN to TMAX;all other limits TA= TJ= 25°C.
Symbol Parameter Conditions Typical(1) Limits(2) Units (Limits)
IOUT TRI-STATE Output Current VOUT = 0V −3.0 μA (max)
VOUT = 5V 3.0 μA (max)
ISOURCE Output Source Current VOUT = 0V −6.5 mA (max)
ISINK Output Sink Current VOUT = VCC 8.0 mA (min)
ICC Supply Current ADC08831 CLK = VCC CS = VCC 0.6 1.0 mA (max)
CS = LOW 1.7 2.4 mA (max)
ICC Supply Current ADC08832 CLK = CS = VCC 1.3 1.8 mA (max)
VCC(8) CS = LOW 2.4 3.5 mA (max)
(8) For the ADC08832 Vref is internally tied to VCC, therefore, for the ADC08832 reference current is included in the supply current.
Electrical Characteristics
The following specifications apply for VCC = VREF = +5 VDC, and tr= tf= 20 ns unless otherwise specified. Boldface limits
apply for TA= TJ= TMIN to TMAX;all other limits TA= TJ= 25°C.
Symbol Parameter Conditions Typical(1) Limits(2) Units (Limits)
fCLK Clock Frequency 2MHz (max)
Clock Duty Cycle(3) 40 % (min)
60 % (max)
TCConversion Time (Not Including MUX fCLK = 2MHz 81/fCLK (max)
Addressing Time) 4μs (max)
tCA Acquisition Time ½1/fCLK (max)
tSET-UP CS Falling Edge or Data Input 25 ns (min)
Valid to CLK Rising Edge
tHOLD Data Input Valid after CLK 20 ns (min)
Rising Edge
tpd1, tpd0 CLK Falling Edge to Output Data Valid(4) CL= 100 pF:
Data MSB First 250 ns (max)
Data LSB First 200 ns (max)
t1H, t0H TRI-STATE Delay from Rising Edge CL= 10 pF, RL= 10 kΩ50 ns
of CS to Data Output and SARS Hi-Z (see TRI-STATE Test Circuits and
Waveforms)
CL= 100 pF, RL= 2 kΩ180 ns (max)
CIN Capacitance of Analog Input(5) 13 pF
CIN Capacitance of Logic Inputs 5 pF
COUT Capacitance of Logic Outputs 5 pF
(1) Typicals are at TJ= 25°C and represent the most likely parametric norm.
(2) Specified to TI's AOQL (Average Outgoing Quality Level).
(3) A 40% to 60% duty cycle range insures proper operation at all clock frequencies. In the case that an available clock has a duty cycle
outside of these limits the minimum time the clock is high or low must be at least 250 ns. The maximum time the clock can be high or
low is 60 μs.
(4) Since data, MSB first, is the output of the comparator used in the successive approximation loop, an additional delay is built in to allow
for comparator response time.
(5) Analog inputs are typically 300 ohms input resistance to a 13pF sample and hold capacitor.
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Dynamic Characteristics
The following specifications apply for VCC = 5V, fCLK = 2MHz, TA= 25°C, RSOURCE = 50Ω, fIN = 45kHz, VIN = 5VP, VREF = 5V,
non-coherent 2048 samples with windowing.
Symbol Parameter Conditions Typical(1) Limits(2) Units (Limits)
fSSampling Rate ADC08831 fCLK/11 181 ksps
ADC08832 fCLK/13(3) 153 ksps
SNR Signal-to -Noise Ratio(4) 48.5 dB
THD Total Harmonic Distortion(5) −59.5 dB
SINAD Signal-to -Noise and Distortion 48.0 dB
ENOB Effective Number Of Bits(6) 7.7 Bits
SFDR Spurious Free Dynamic Range 62.5 dB
(1) Typicals are at TJ= 25°C and represent the most likely parametric norm.
(2) Specified to TI's AOQL (Average Outgoing Quality Level).
(3) The maximum sampling rate is slightly less than fCLK/11 if CS is reset in less than one clock period.
(4) The signal-to-noise ratio is the ratio of the signal amplitude to the background noise level. Harmonics of the input signal are not included
in it's calculation.
(5) The contributions from the first 6 harmonics are used in the calculation of the THD.
(6) Effective Number Of Bits (ENOB) is calculated from the measured signal-to-noise plus distortion ratio (SINAD) using the equation ENOB
= (SINAD-1.76)/6.02.
Block Diagram
*For ADC08831 VREF pin is available, for ADC08832 DI pin is available, and VREF is tied to VCC
Pin names in parentheses refer to ADC08832
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Typical Performance Characteristics
The following specifications apply for TA= 25°C, VCC = VREF = 5V, unless otherwise specified.
Linearity Error (TUE) vs Linearity Error (TUE) vs
Reference Voltage Temperature
Figure 3. Figure 4.
Linearity Error (TUE) vs Power Supply Current vs
Clock Frequency Temperature (ADC08831)
Figure 5. Figure 6.
Power Supply Current vs Power Supply Current
Temperature (ADC08832) vs Clock Frequency, CS = Low, ADC08831
Figure 7. Figure 8.
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Typical Performance Characteristics (continued)
The following specifications apply for TA= 25°C, VCC = VREF = 5V, unless otherwise specified.
Output Current
vs
Temperature Spectral Response with 10KHz Sine Wave Input
Figure 9. Figure 10.
Spectral Response with 55 KHz Sine Wave Input Spectral Response with 90 KHz Sine Wave Input
Figure 11. Figure 12.
Total Unadjuster Error Plot
Figure 13.
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Timing Diagrams
Figure 17. Data Input Timing
Figure 18. Data Output Timing
Figure 19. ADC08831 Start Conversion Timing
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FUNCTIONAL DESCRIPTION
MULTIPLEXER ADDRESSING
The design of these converters utilizes a comparator structure with built-in sample-and-hold which provides for a
differential analog input to be converted by a successive approximation routine.
The actual voltage converted is always the difference between an assigned “+” input terminal and a “−” input
terminal. The polarity of each input terminal of the pair indicates which line the converter expects to be the most
positive. If the assigned “+” input voltage is less than the “−” input voltage the converter responds with an all
zeros output code.
A unique input multiplexing scheme has been utilized to provide multiple analog channels with software-
configurable single-ended, or differential operation. The analog signal conditioning required in transducer-based
data acquisition systems is significantly simplified with this type of input flexibility. One converter package can
now handle ground referenced inputs, differential inputs, as well as signals with some arbitrary reference voltage.
A particular input configuration is assigned during the MUX addressing sequence, prior to the start of a
conversion. The MUX address selects which of the analog inputs are to be enabled and whether this input is
single-ended or differential. In addition to selecting differential mode the polarity may also be selected. Channel 0
may be selected as the positive input and channel 1 as the negative input or vice versa. This programmability is
illustrated by the MUX addressing codes for the ADC08832.
The MUX address is shifted into the converter via the DI line. Because the ADC08831 contains only one
differential input channel with a fixed polarity assignment, it does not require addressing.
Table 1. Multiplexer/Package Options
Part Number Number of Analog Channels Number of Package Pins
Single-Ended Differential
ADC08831 1 1 8 or 14
ADC08832 2 1 8 or 14
Table 2. MUX Addressing: ADC08832
Single-Ended MUX Mode
MUX Address Channel #
Start Bit SGL/DIF ODD/SIGN 0 1
1 1 0 +
1 1 1 +
Differential MUX Mode
MUX Address Channel #
Start Bit SGL/DIF ODD/SIGN 0 1
1 0 0 + −
1 0 1 −+
Since the input configuration is under software control, it can be modified as required before each conversion. A
channel can be treated as a single-ended, ground referenced input for one conversion; then it can be
reconfigured as part of a differential channel for another conversion.
The analog input voltages for each channel can range from 50mV below ground to 50mV above VCC (typically
5V) without degrading conversion accuracy.
THE DIGITAL INTERFACE
A most important characteristic of these converters is their serial data link with the controlling processor. Using a
serial communication format offers two very significant system improvements. It allows many functions to be
included in a small package and it can eliminate the transmission of low level analog signals by locating the
converter right at the analog sensor; transmitting highly noise immune digital data back to the host processor.
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To understand the operation of these converters it is best to refer to Timing Diagrams and ADC08832 Functional
Block Diagram and to follow a complete conversion sequence. For clarity, a separate timing diagram is shown for
each device.
1. A conversion is initiated by pulling the CS (chip select) line low. This line must be held low for the entire
conversion. The converter is now waiting for a start bit and its MUX assignment word, if applicable.
2. On each rising edge of the clock the status of the data in (DI) line is clocked into the MUX address shift
register. The start bit is the first logic “1” that appears on this line (all leading zeros are ignored). Following
the start bit the converter expects the next 2 bits to be the MUX assignment word.
3. When the start bit has been shifted into the start location of the MUX register, and the input channel has
been assigned, a conversion is about to begin. An interval of ½ clock period (where nothing happens) is
automatically inserted to allow the selected MUX channel to settle to a final analog input value. The DI line is
disabled at this time. It no longer accepts data.
4. The data out (DO) line now comes out of TRI-STATE and provides a leading zero for this one clock period of
MUX settling time.
5. During the conversion the output of the SAR comparator indicates whether the analog input is greater than
(high) or less than (low) a series of successive voltages generated internally from a ratioed capacitor array
(first 5 bits) and a resistor ladder (last 3 bits). After each comparison the comparator's output is shipped to
the DO line on the falling edge of CLK. This data is the result of the conversion being shifted out (with the
MSB first) and can be read by the processor immediately.
6. After 8 clock periods the conversion is completed.
7. The stored data in the successive approximation register is loaded into an internal shift register. The data,
LSB first, is automatically shifted out the DO line after the MSB first data stream. The DO line then goes low
and stays low until CS is returned high. The ADC08831 is an exception in that its data is only output in MSB
first format.
8. The DI and DO lines can be tied together and controlled through a bidirectional processor I/O bit with one
wire. This is possible because the DI input is only “looked-at” during the MUX addressing interval while the
DO line is still in a high impedance state.
Reducing Power Consumption
The ADC08831 operate up to a 2MHz clock frequency, or about 181 ksps. At 5V supply, it consumes about 1.7
mA or 8.5 mW when CS is logic low. The ADC08831 has a low power mode to minimize total power
consumption.
When the chip select is asserted with a logic high, some analog circuitry and digital logic are pulled to a static,
low power condition. Also, DOUT, the output driver is taken into TRI-STATE mode.
To optimize static power consumption, special attention is needed to the digital input logic signals: CLK, CS, DI.
Each digital input has a large CMOS buffer between VCC and GND. A traditional TTL level high (2.4V) will be
sufficient for each input to read a logical “1”. However, there could be a large VIH to VCC voltage difference at
each input. Such a voltage difference would cause static power dissipation, even when chip select pin is high
and the part is in low power mode.
Therefore, to minimize static power dissipation, it is recommended that all digital input logic levels should equal
the converter's supply. Various CMOS logic is particularly well suited for this application.
The reference pin on the ADC08831 is not affected by the power-down mode. To reduce static reference current
during non-conversion time, there are a couple options. First, a low voltage external reference (ie, 2.5V could be
used). A shunt reference, such as the LM385-2.5, could be powered by a logic gate that is the inverse of the
signal on CS. When CS is high, the reference is off. As a second option, an external, low on-resistance switch
could be used.
The ADC08832 is similar to the ADC08831, except its reference is derived from VCC. The ADC08832 does enter
a low-power mode when CS is logic high, as the analog and digital logic enter static current modes. However
power dissipation from the reference ladder occurs, regardless of the signal on CS
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REFERENCE CONSIDERATIONS
The voltage applied to the reference input on these converters, VREF, defines the voltage span of the analog
input (the difference between VIN(MAX) and VIN(MIN) over which the 256 possible output codes apply. The devices
can be used either in ratiometric applications or in systems requiring absolute accuracy. The reference pin must
be connected to a voltage source capable of driving the reference input resistance which can be as low as
2.8kΩ. This pin is the top of a resistor divider string and capacitor array used for the successive approximation
conversion.
In a ratiometric system the analog input voltage is proportional to the voltage used for the A/D reference. This
voltage is typically the system power supply, so the VREF pin can be tied to VCC (done internally on the
ADC08832). This technique relaxes the stability requirements of the system reference as the analog input and
A/D reference move together maintaining the same output code for a given input condition.
For absolute accuracy, where the analog input varies between very specific voltage limits, the reference pin can
be biased with a time and temperature stable voltage source. The LM385, LM336 and LM4040 reference diodes
are good low current devices to use with these converters.
The maximum value of the reference is limited to the VCC supply voltage. The minimum value, however, can be
quite small (see Typical Performance Characteristics) to allow direct conversions of transducer outputs providing
less than a 5V output span. Particular care must be taken with regard to noise pickup, circuit layout and system
error voltage sources when operating with a reduced span due to the increased sensitivity of the converter (1
LSB equals VREF/256).
Left) Ratiometric
Right) Absolute with a Reduced Span
Figure 22. Reference Examples
THE ANALOG INPUTS
The most important feature of these converters is that they can be located right at the analog signal source and
through just a few wires can communicate with a controlling processor with a highly noise immune serial bit
stream. This in itself greatly minimizes circuitry to maintain analog signal accuracy which otherwise is most
susceptible to noise pickup. However, a few words are in order with regard to the analog inputs should the input
be noisy to begin with or possibly riding on a large common-mode voltage.
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The differential input of these converters actually reduces the effects of common-mode input noise, a signal
common to both selected “+” and “−” inputs for a conversion (60 Hz is most typical). The time interval between
sampling the “+” input and then the “−” input is ½ of a clock period. The change in the common-mode voltage
during this short time interval can cause conversion errors. For a sinusoidal common-mode signal this error is:
where
• where fCM is the frequency of the common-mode signal
• VPEAK is its peak voltage value
• fCLK is the A/D clock frequency (1)
For a 60Hz common-mode signal to generate a ¼ LSB error (≊5mV) with the converter running at 250kHz, its
peak value would have to be 6.63V which would be larger than allowed as it exceeds the maximum analog input
limits.
Source resistance limitation is important with regard to the DC leakage currents of the input multiplexer. Bypass
capacitors should not be used if the source resistance is greater than 1kΩ. The worst-case leakage current of
±1μA over temperature will create a 1mV input error with a 1kΩsource resistance. An op amp RC active low
pass filter can provide both impedance buffering and noise filtering should a high impedance signal source be
required.
Sample and Hold
The ADC08831/2 provide a built-in sample-and-hold to acquire the input signal. The sample and hold can sample
input signals in either single-ended or pseudo differential mode.
Input Op Amps
When driving the analog inputs with an op amp it is important that the op amp settle within the allowed time. To
achieve the full sampling rate, the analog input should be driven with a low impedance source (100Ω) or a high-
speed op amp such as the LM6142. Higher impedance sources or slower op amps can easily be accommodated
by allowing more time for the analog input to settle.
Source Resistance
The analog inputs of the ADC08831/2 look like a 13pF capacitor (CIN) in series with 300Ωresistor (Ron). CIN gets
switched between the selected “+” and “−” inputs during each conversion cycle. Large external source resistors
will slow the settling of the inputs. It is important that the overall RC time constants be short enough to allow the
analog input to completely settle.
Board Layout Consideration, Grounding and Bypassing:
The ADC08831/2 are easy to use with some board layout consideration. They should be used with an analog
ground plane and single-point grounding techniques. The GND pin should be tied directly to the ground plane.
The supply pin should be bypassed to the ground plane with a surface mount or ceramic capacitor with leads as
short as possible. All analog inputs should be referenced directly to the single-point ground. Digital inputs and
outputs should be shielded from and routed away from the reference and analog circuitry.
OPTIONAL ADJUSTMENTS
Zero Error
The offset of the A/D does not require adjustment. If the minimum analog input voltage value, VIN(MIN), is not
ground a zero offset can be done. The converter can be made to output 0000 0000 digital code for this minimum
input voltage by biasing any VIN (−) input at this VIN(MIN) value. This utilizes the differential mode operation of the
A/D.
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The zero error of the A/D converter relates to the location of the first riser of the transfer function and can be
measured by grounding the VIN (−) input and applying a small magnitude positive voltage to the VIN (+) input.
Zero error is the difference between the actual DC input voltage which is necessary to just cause an output
digital code transition from 0000 0000 to 0000 0001 and the ideal ½ LSB value (½ LSB = 9.8mV for VREF =
5.000VDC).
Full Scale
The full-scale adjustment can be made by applying a differential input voltage which is 1½ LSB down from the
desired analog full-scale voltage range and then adjusting the magnitude of the VREF input (or VCC for the
ADC08832) for a digital output code which is just changing from 1111 1110 to 1111 1111.
Adjusting for an Arbitrary Analog Input
Voltage Range
If the analog zero voltage of the A/D is shifted away from ground (for example, to accommodate an analog input
signal which does not go to ground), this new zero reference should be properly adjusted first. A VIN (+) voltage
which equals this desired zero reference plus ½ LSB (where the LSB is calculated for the desired analog span,
using 1 LSB = analog span/256) is applied to selected “+” input and the zero reference voltage at the
corresponding “−” input should then be adjusted to just obtain the 00HEX to 01HEX code transition.
The full-scale adjustment should be made [with the proper VIN (−) voltage applied] by forcing a voltage to the VIN
(+) input which is given by:
where
• VMAX = the high end of the analog input range
• VMIN = the low end (the offset zero) of the analog range
• (Both are ground referenced.) (2)
The VREFIN (or VCC) voltage is then adjusted to provide a code change from FEHEX to FFHEX. This completes the
adjustment procedure.
DYNAMIC PERFORMANCE
Dynamic performance specifications are often useful in applications requiring waveform sampling and digitization.
Typically, a memory buffer is used to capture a stream of consecutive digital outputs for post processing.
Capturing a number of samples that is a power of 2 (ie, 1024, 2048, 4096) allows the Fast Fourier Transform
(FFT) to be used to digitally analyze the frequency components of the signal. Depending on the application,
further digital filtering, windowing, or processing can be applied.
Sampling Rate
The Sampling Rate, sometimes referred to as the Throughput Rate, is the time between repetitive samples by an
Analog-to-Digital Converter. The sampling rate includes the conversion time, as well as other factors such a MUX
setup time, acquisition time, and interfacing time delays. Typically, the sampling rate is specified in the number of
samples taken per second, at the maximum Analog-to-Digital Converter clock frequency.
Signals with frequencies exceeding the Nyquist frequency (1/2 the sampling rate), will be aliased into frequencies
below the Nyquist frequency. To prevent signal degradation, sample at twice (or more) than the input signal
and/or use of a low pass (anti-aliasing) filter on the front-end. Sampling at a much higher rate than the input
signal will reduce the requirements of the anti-aliasing filter.
Some applications require under-sampling the input signal. In this case, one expects the fundamental to be
aliased into the frequency range below the Nyquist frequency. In order to be assured the frequency response
accurately represents a harmonic of the fundamental, a band-pass filter should be used over the input range of
interest.
16 Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated
Product Folder Links: ADC08831 ADC08832
ADC08831, ADC08832
www.ti.com
SNAS015C –SEPTEMBER 1999–REVISED MARCH 2013
Signal-to-Noise Ratio
Signal-to-Noise Ratio (SNR) is the ratio of RMS magnitude of the fundamental to the RMS sum of all the non-
fundamental signal, excluding the harmonics, up to 1/2 of the sampling frequency (Nyquist).
Total Harmonic Distortion
Total Harmonic distortion is the ratio of the RMS sum of the amplitude of the harmonics to the fundamental input
frequency.
THD = 20 log [(V22+ V32+ V42+ V52+ V62)1/2/V1]
where
• V1is the RMS amplitude of the fundamental
• V2,V3, V4, V5, V6are the RMS amplitudes of the individual harmonics. (3)
In theory, all harmonics are included in THD calculations, but in practice only about the first 6 make significant
contributions and require measurement.
For under-sampling applications, the input signal should be band pass filtered (BPF) to prevent out of band
signals, or their harmonics, to appear in the spectral response.
The DC Linearity transfer function of an Analog-to-Digital Converter tends to influence the dominant harmonics.
A parabolic Linearity curve would tend to create 2nd (and even) order harmonics, while an S-curve would tend to
create 3rd (or odd) order harmonics. The magnitude of an DC linearity error correlates to the magnitude of the
harmonics.
Signal-to-Noise and Distortion
Signal-to-Noise And Distortion ratio (SINAD) is the ratio of RMS magnitude of the fundamental to the RMS sum
of all the non-fundamental signals, including the noise and harmonics, up to 1/2 of the sampling frequency
(Nyquist), excluding DC.
SINAD is also dependent on the number of quantization levels in the A/D Converter used in the waveform
sampling process. The more quantization levels, the smaller the quantization noise and theoretical noise
performance. The theoretical SINAD for a N-Bit Analog-to-Digital Converter is given by:
SINAD = (6.02 N + 1.76) dB
Thus, for an 8-bit converter, the ideal SINAD = 49.92 dB
Effective Number of Bits
Effective Number Of Bits (ENOB) is another specification to quantify dynamic performance. The equation for
ENOB is given by:
ENOB = [(SINAD - 1.76)] / 6.02]
The Effective Number Of Bits portrays the cumulative effect of several errors, including quantization, non-
linearities, noise, and distortion.
Spurious Free Dynamic Range
Spurious Free Dynamic Range (SFDR) is the ratio of the signal amplitude to the amplitude of the highest
harmonic or spurious noise component. If the amplitude is at full scale, the specification is simply the reciprocal
of the peak harmonic or spurious noise.
Copyright © 1999–2013, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Links: ADC08831 ADC08832
ADC08831, ADC08832
SNAS015C –SEPTEMBER 1999–REVISED MARCH 2013
www.ti.com
Applications
Figure 23. Low-Cost Remote Temperature Sensor
*VIN(−) = 0.15 VCC
15% of VCC ≤VXDR ≤85% of VCC
Figure 24. Operating with Ratiometric Transducers
18 Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated
Product Folder Links: ADC08831 ADC08832
ADC08831, ADC08832
SNAS015C –SEPTEMBER 1999–REVISED MARCH 2013
www.ti.com
Diodes are 1N914
Figure 26. Protecting the Input
Uses one more wire than load cell itself
Two mini-DIPs could be mounted inside load cell for digital output transducer
Electronic offset and gain trims relax mechanical specs for gauge factor and offset
Low level cell output is converted immediately for high noise immunity
Figure 27. Digital Load Cell
20 Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated
Product Folder Links: ADC08831 ADC08832
ADC08831, ADC08832
SNAS015C –SEPTEMBER 1999–REVISED MARCH 2013
www.ti.com
REVISION HISTORY
Changes from Revision B (March 2013) to Revision C Page
• Changed layout of National Data Sheet to TI format .......................................................................................................... 22
24 Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated
Product Folder Links: ADC08831 ADC08832
PACKAGE OPTION ADDENDUM
www.ti.com 11-Jan-2021
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
ADC08831IM NRND SOIC D 8 95 Non-RoHS
& Green Call TI Call TI -40 to 85 08831
IM
ADC08831IM/NOPB ACTIVE SOIC D 8 95 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 08831
IM
ADC08831IMX/NOPB ACTIVE SOIC D 8 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 08831
IM
ADC08832IM/NOPB ACTIVE SOIC D 8 95 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 08832
IM
ADC08832IMM/NOPB ACTIVE VSSOP DGK 8 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 8832
ADC08832IMX/NOPB ACTIVE SOIC D 8 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 08832
IM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
PACKAGE OPTION ADDENDUM
www.ti.com 11-Jan-2021
Addendum-Page 2
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
ADC08831IMX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
ADC08832IMM/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
ADC08832IMX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 10-Aug-2016
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
ADC08831IMX/NOPB SOIC D 8 2500 367.0 367.0 35.0
ADC08832IMM/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0
ADC08832IMX/NOPB SOIC D 8 2500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 10-Aug-2016
Pack Materials-Page 2
www.ti.com
PACKAGE OUTLINE
C
.228-.244 TYP
[5.80-6.19]
.069 MAX
[1.75]
6X .050
[1.27]
8X .012-.020
[0.31-0.51]
2X
.150
[3.81]
.005-.010 TYP
[0.13-0.25]
0 - 8 .004-.010
[0.11-0.25]
.010
[0.25]
.016-.050
[0.41-1.27]
4X (0 -15 )
A
.189-.197
[4.81-5.00]
NOTE 3
B .150-.157
[3.81-3.98]
NOTE 4
4X (0 -15 )
(.041)
[1.04]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
18
.010 [0.25] C A B
5
4
PIN 1 ID AREA
SEATING PLANE
.004 [0.1] C
SEE DETAIL A
DETAIL A
TYPICAL
SCALE 2.800
www.ti.com
EXAMPLE BOARD LAYOUT
.0028 MAX
[0.07]
ALL AROUND
.0028 MIN
[0.07]
ALL AROUND
(.213)
[5.4]
6X (.050 )
[1.27]
8X (.061 )
[1.55]
8X (.024)
[0.6]
(R.002 ) TYP
[0.05]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
METAL SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
EXPOSED
METAL
OPENING
SOLDER MASK METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED
METAL
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SYMM
1
45
8
SEE
DETAILS
SYMM
www.ti.com
EXAMPLE STENCIL DESIGN
8X (.061 )
[1.55]
8X (.024)
[0.6]
6X (.050 )
[1.27] (.213)
[5.4]
(R.002 ) TYP
[0.05]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
SYMM
SYMM
1
45
8
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