ADMV8818-EVALZ Evaluation Board User Guide UG-1921 One Technology Way * P.O. Box 9106 * Norwood, MA 02062-9106, U.S.A. * Tel: 781.329.4700 * Fax: 781.461.3113 * www.analog.com Evaluating the ADMV8818 2 GHz to 18 GHz, Digitally Tunable, High-Pass and Low-Pass Filter FEATURES EVALUATION BOARD PHOTOGRAPH Fully featured evaluation board for the ADMV8818 On-board SDP-S connector for the SPI Evaluation using on-board LDO regulators powered by the USB ACE software interface for SPI control EQUIPMENT NEEDED Network analyzer Windows(R) PC USB cable EVAL-SDP-CS1Z (SDP-S) controller board DOCUMENTS NEEDED ADMV8818 data sheet SOFTWARE NEEDED ACE software GENERAL DESCRIPTION The ADMV8818 is a fully monolithic microwave integrated circuit (MMIC) that features a digitally selectable frequency of operation. The chip features four independently controlled high-pass and low-pass filters that span from 2 GHz to 18 GHz. The chip can be programmed using a 4-wire serial port interface (SPI). The SDP-S controller allows the user to interface with the ADMV8818 SPI through the Analog Devices, Inc., Analysis | Control | Evaluation (ACE) software. For full details on the ADMV8818, see the ADMV8818 data sheet, which must be consulted in conjunction with this user guide when using the ADMV8818-EVALZ. PLEASE SEE THE LAST PAGE FOR AN IMPORTANT WARNING AND LEGAL TERMS AND CONDITIONS. Rev. 0 | Page 1 of 18 25839-001 The ADMV8818-EVALZ is available for evaluating the ADMV8818 digitally tunable, high-pass and low-pass filter. The ADMV8818-EVALZ incorporates the ADMV8818 chip, as well as a negative voltage generator, low dropout (LDO) regulators, and an interface to the EVAL-SDP-CS1Z (SDP-S) system demonstration platform (SDP) to allow simple and efficient evaluation. The negative voltage generator and LDO regulators allow the ADMV8818 to be powered by either the 5 V USB supply voltage from the PC via the SDP-S or by using two external power supplies. Figure 1. UG-1921 ADMV8818-EVALZ Evaluation Board User Guide TABLE OF CONTENTS Features .............................................................................................. 1 Performing the Evaluation ...............................................................9 Equipment Needed........................................................................... 1 ADMV8818-EVALZ Quick Start ...............................................9 Documents Needed .......................................................................... 1 Network Analyzer Settings ..........................................................9 Software Needed ............................................................................... 1 CSV Files ........................................................................................9 General Description ......................................................................... 1 Automatic Chip Reset ............................................................... 10 Evaluation Board Photograph ........................................................ 1 Loss of Board Communication ................................................ 10 Revision History ............................................................................... 2 Regulator Bypass ........................................................................ 10 Evaluation Board Hardware ........................................................... 3 Plugin SPI Register Controller ................................................. 10 Evaluation Board Software .............................................................. 4 Evaluation Board Schematics and Artwork................................ 11 Installing the ACE Software, ADMV8818 Plugins, and Drivers ........................................................................................... 4 Ordering Information.................................................................... 17 Bill of Materials .......................................................................... 17 Plugin Overview ........................................................................... 5 Plugin Details ................................................................................ 6 REVISION HISTORY 12/2020--Revision 0: Initial Version Rev. 0 | Page 2 of 18 ADMV8818-EVALZ Evaluation Board User Guide EVALUATION BOARD HARDWARE The ADMV8818-EVALZ has the ADMV8818 chip on board. The ADMV8818-EVALZ also includes a negative voltage generator and three LDO regulators to provide the necessary supply voltages for the chip. The regulators can be entirely powered by the 5 V USB supply voltage from the PC via the SDP-S. UG-1921 Figure 2 shows an example lab bench setup for the ADMV8818-EVALZ. To observe the filter response from the ADMV8818-EVALZ, connect the RF input (RFIN) and RF output (RFOUT) ports to a network analyzer (or a similar instrument). Typically, RFIN and RFOUT are connected to Port 1 and Port 2 on the network analyzer, as shown in Figure 2. To power the ADMV8818-EVALZ using the 5 V USB supply, slide the S2 switch downward (as shown in Figure 2) to power the on-board negative voltage generator and LDO regulators. Alternatively, the ADMV8818-EVALZ can be powered externally by sliding the S2 switch upward and then connecting power supplies to the VPOS and VNEG Subminiature Version A (SMA) ports or test points. The applicable voltage range for the positive input VPOS is between 3.5 V and 5.5 V, and the applicable voltage range for the negative input VNEG is between -5.5 V and -2.7 V. NETWORK ANALYZER PORT 1 PORT 2 25839-002 S2 Figure 2. Lab Bench Setup Rev. 0 | Page 3 of 18 UG-1921 ADMV8818-EVALZ Evaluation Board User Guide EVALUATION BOARD SOFTWARE INSTALLING THE ACE SOFTWARE, ADMV8818 PLUGINS, AND DRIVERS The ADMV8818-EVALZ uses the Analog Devices ACE software. For instructions on how to install and use the ACE software, go to the ACE software page. Once the installation finishes, the ADMV8818 Board plugin appears in the Attached Hardware section of the Start tab when the ACE software is running. (see Figure 4). If the ACE software is already installed on the PC, ensure that the installed software is the latest version, as shown on the ACE software page. If the installed software is not the latest version, take the following steps to install the updated ACE software: 25839-004 3. Uninstall the current version of the ACE software on the PC. Delete the ACE folder found in C:\ProgramData\Analog Devices and C:\Program Files (x86)\Analog Devices. Install the latest version of the ACE software. During the installation, ensure that the .NET 40 Client, SDP Drivers, and LRF Drivers components are selected (see Figure 3). Figure 4. ADMV8818 Board Plugin Window after Opening the ACE Software 25839-003 1. 2. Figure 3. Required Driver Installations with the ACE Software Rev. 0 | Page 4 of 18 ADMV8818-EVALZ Evaluation Board User Guide UG-1921 PLUGIN OVERVIEW When the ADMV8818-EVALZ is connected to the PC, the ADMV8818 Board appears in the Attached Hardware section of the Start tab. Double click the ADMV8818 Board plugin to open two tabs, the board level plugin and the chip level plugin, which are the ADMV8818 Board plugin view (see Figure 5) and the ADMV8818 chip plugin (see Figure 6), respectively. The ADMV8818 chip plugin includes the following feature sections (see Table 1 for additional information on these sections): The CONFIGURATION section (load from CSV) The Logic Pins section The SFL Settings section The chip Status section The Display controls section The Filter Settings section Figure 5. ADMV8818 Board Plugin View 25839-006 The ACE software provides a simple tutorial for testing the ADMV8818. For a more customized and detailed implementation, refer to ADMV8818 data sheet for a full description of the functionality, registers, and corresponding settings. 25839-005 * * * * * * Figure 6. ADMV8818 Chip Plugin Rev. 0 | Page 5 of 18 UG-1921 ADMV8818-EVALZ Evaluation Board User Guide PLUGIN DETAILS The full screen ADMV8818 chip plugin with labels is shown in Figure 7. The labels correspond to items listed in Table 1, which describes the functionality of each section. For additional detailed programming, refer to the ADMV8818 data sheet. J1 J2 J3 J4 J5 J6 B C F G A H H E 25839-007 D Figure 7. ADMV8818 Chip Plugin with Labels Table 1. ADMV8818 Chip Plugin Label Functions (See Figure 7) Label A Function Use the CONFIGURATION section to initialize the ADMV8818-EVALZ. Load Settings from CSV: click the ... button to select which CSV file to load into the CONFIGURATION section. Check to Load Settings: once a file has been selected, select this check box to load the CSV file contents into the CONFIGURATION section. Note that a check mark does not appear when the check box is selected. WR Mode HPF Settings: select the input switch and high-pass filter (HPF) settings for SPI write mode. WR Mode LPF Settings: select the output switch and low-pass filter (LPF) settings for SPI write mode. SFL Settings: select the SPI fast latch (SFL) settings that are used when the chip is placed into the SPI fast latch mode. Note that this function is not shown in Figure 7. Scroll down in the CONFIGURATION section to view this function. Lookup Table 0 to 15: define the configuration for lookup table (LUT)0 to LUT15. Note that these functions are not shown in Figure 7. Scroll down in the CONFIGURATION section to view these functions. Lookup Table 16 to 31: define the configuration for LUT16 to LUT31. Lookup Table 32 to 47: define the configuration for LUT32 to LUT47. Lookup Table 48 to 63: define the configuration for LUT48 to LUT63. Lookup Table 64 to 79: define the configuration for LUT64 to LUT79. Lookup Table 80 to 95: define the configuration for LUT80 to LUT95. Lookup Table 96 to 111: define the configuration for LUT96 to LUT111. Lookup Table 112 to 127: define the configuration for LUT112 to LUT 127. Summary: click this button to review the settings for the initial setup. Apply: click this button to apply the settings to the chip. Note that clicking Apply Changes (J1) does not update the changes in this section. Also, at startup, the main diagram user controls cannot be updated until the Apply button is clicked at least once. Restore Software Defaults: click this button to zero out the CONFIGURATION section prior to loading a different CSV file. Rev. 0 | Page 6 of 18 ADMV8818-EVALZ Evaluation Board User Guide Label B C D E F G UG-1921 Function Use the Logic Pins section to toggle the SDP-S logic pins, which are connected to the logic pins on the ADMV8818 chip. This section includes the following: RSTB: clear the check box to bring the ADMV8818 RST pin low, which holds the chip in reset. Select the check box again to bring the chip out of reset. SFL: select the check box to bring the ADMV8818 SFL pin high, which places the chip in SFL mode. This action also toggles the on board ADG749BKSZ switch connected to the ADMV8818 CS pin (see Figure 10). While in SFL mode, the ADMV8818 CS pin is connected to the SDP-S logic pin, CSB_AUX, and normal SPI transactions are disallowed. CSB_AUX: this pin is only available in SFL mode. Selecting the check box brings the SDP-S logic pin, CSB_AUX, high, which advances the internal state machine pointer to the next lookup table. If an external waveform generator is connected to the CSB_EXT port on the ADMV8818-EVALZ, the CSB_AUX pin has no effect and the CSB_EXT port takes precedence. Use the SFL Settings section to configure the SPI fast latch settings on the chip when in the SFL mode. Refer to the ADMV8818 data sheet for more information regarding the internal state machine and SFL mode functionality. This section includes the following: FAST_LATCH_STATE: this value is the next state of the internal state machine pointer (read only). FAST_LATCH_LOAD: set this bit to load the pointer into the internal state machine. FAST_LATCH_POINTER: use this value to adjust the pointer location of the internal state machine. FAST_LATCH_START: this bit determines the start location within the internal state machine. FAST_LATCH_STOP: this bit determines the stop location within the internal state machine. FAST_LATCH_DIRECTION: this bit determines the direction that the internal state machine advances for each rising edge of the CS pin when in SFL mode. The displayed block diagram section shows the actively selected WR or LUT number. This section includes the following: Displaying States in...: the title updates to show the actively selected WR or LUT number. Displayed States (or Bypass): depending on which filter band number is selected, the filter state value or Bypass populates into the appropriate block. Input Switch: this section displays the configuration of the input switch. When displaying a WR number, the input switch position updates based on the SW_IN_SET_WRx bit fields, where x is a number from 0 to 4. If multiple bit fields are set, the priority is WR0 to WR4. If no bit fields are set, the Input Switch position shows WR ?. When displaying an LUT number, the Input Switch position reflects the SW_IN_SET_y bit fields, where y is a number from 0 to 127, depending on the LUT number selected. Output Switch: this section displays the configuration of the output switch. When displaying a WR number, the output switch position updates based on the SW_OUT_SET_WRx bit fields, where x is a number from 0 to 4. If multiple bit fields are set, the priority is WR0 to WR4. If no bit fields are set, the Output Switch position shows WR ?. When displaying an LUT number, the Output Switch position reflects the SW_OUT_SET_y bit fields, where y is a number from 0 to 127, depending on the LUT number selected. The Status section includes the following: Mode: when the SFL pin is low, the mode is SPI Write. When the SFL pin is high, the mode is SPI Fast Latch and the chip uses the LUT. CSB_AUX Count: when in SFL mode, this field displays the number of times the CSB_AUX pin has been toggled. Message: upon entering SFL mode, the Message field displays Waiting for CSB. Once the CSB_AUX pin has been toggled, the Message field displays the current LUT number followed by the next LUT number. The Display section determines the actively selected WR or LUT number. This section includes the following: Mode: use the dropdown menu to select either WR or LUT display mode. WR: when the Mode is set to WR, scroll up and down to set the WR number (0 to 4) that is currently being configured and displayed on the diagram. Changing the WR number automatically changes the Mode to WR. LUT: when the Mode is set to LUT, scroll up and down to set the LUT number (0 to 127) that is currently being configured and displayed on the diagram. Changing to the LUT number automatically changes the Mode to LUT. The Filter Settings section shows the filter states, filter band selection, and switch set for the actively selected WR or LUT number. This section includes the following: State: scroll up and down to set the desired filter state value (0 to 15). Changing the HPF state updates the HPF_WRx or HPF_y bit fields, and changing the LPF state updates the LPF_WRx or LPF_y bit fields, where x is the selected WR number, and y is the selected LUT number. Filter: scroll up and down to set the desired filter band value (0 to 4). A value of 0 corresponds to the bypass configuration, and all other values correspond to the filter band number. Changing the HPF band updates the SW_IN_WRx or SW_IN_y bit fields. Changing the LPF band updates the SW_OUT_WRx or SW_OUT_y bit fields. Switch Set: these check boxes determine if the input and output switches change. Toggling the Switch Set for HPF sets the SW_IN_SET_WRx or SW_IN_SET_y bit fields. Toggling the Switch Set for LPF sets the SW_OUT_SET_WRx or SW_OUT_SET_y bit fields. Rev. 0 | Page 7 of 18 UG-1921 J2 J3 J4 J5 J6 Function Click Proceed to Memory Map to open the ADMV8818 Memory Map (see Figure 8). All changes, except within the CONFIGURATION section, do not take effect until clicking Apply Changes. If Auto Apply is highlighted in the ADMV8818 Board tab (see Figure 5), the Apply Changes feature continuously runs every few seconds, and Apply Changes does not need clicking to apply or read back the block diagram settings. To read back all of the SPI registers of the chip, click Read All. Click Reset Chip to reset the chip. Click Diff to show registers that are different on the chip. Click Software Defaults to restore the software defaults to the chip, and then click Apply Changes. The software defaults for the ADMV8818 is for all registers to be zero, except for Register 0x011, which is set to 0x7F. Click Memory Map Side-By-Side to enable the side by side memory map view. 25839-008 Label H J1 ADMV8818-EVALZ Evaluation Board User Guide Figure 8. ADMV8818 Memory Map in the ACE Software Rev. 0 | Page 8 of 18 ADMV8818-EVALZ Evaluation Board User Guide UG-1921 PERFORMING THE EVALUATION ADMV8818-EVALZ QUICK START To set up the ADMV8818-EVALZ, take the following steps: 2. 3. 4. 5. 6. 7. Connect the RFIN and RFOUT ports to a network analyzer (or a similar instrument). Typically, RFIN and RFOUT are connected to Port 1 and Port 2 on the network analyzer, as shown in Figure 2. Connect the SDP-S to the 120-pin connector on the ADMV8818-EVALZ. Do not connect the SDP-S to the PC until after completing Step 3 or Step 4. On the ADMV8818-EVALZ, slide the S2 switch downward (as shown in Figure 2) to power the ADMV8818-EVALZ from the 5 V USB supply voltage from the PC via the SDP-S. Alternatively (to Step 3), slide the S2 switch upward and connect power supplies to the VPOS and VNEG ports. The applicable voltage range for VPOS is between 3.5 V and 5.5 V, and the applicable voltage range for VNEG is between -5.5 V and -2.7 V. The external supply current limits must be set to 20 mA. Expected supply current draw for VPOS is 12 mA to 14 mA and for VNEG is 2 mA to 3 mA. The ADMV8818 chip current drawn per supply pin is typically 10s of microamps or less. Most of the current drawn from the ADMV8818-EVALZ comes from the LDO regulators and the status indicator light emitting diodes (LEDs), DS1 to DS3. Connect a USB cable between the PC and the SDP-S. Open the ACE software. The ADMV8818 Board appears in the Attached Hardware section of the Start tab. Double click the ADMV8818 Board plugin to open two tabs, one for the ADMV8818 Board plugin view and one for the ADMV8818 chip plugin. Use the CONFIGURATION section (see Figure 9) in the ACE software to initialize the chip. By default, the ADMV8818_Register_Load_1.csv file is loaded into this section. Click Apply to send the default settings to the chip and to allow the main diagram user controls to become editable. 25839-009 1. Figure 9. ADMV8818 CONFIGURATION Section NETWORK ANALYZER SETTINGS CSV FILES When evaluating the ADMV8818-EVALZ, a good starting point for configuring the network analyzer is as follows: By default, the ADMV8818_Register_Load_1.csv file is loaded into the CONFIGURATION section. To load a different CSV file in the CONFIGURATION section, take the following steps: * * * * * * * * Start frequency = 0.1 GHz Stop frequency = 40 GHz Number of points = 400 Step size = 100 MHz Power level = -10 dBm Measure types = S-parameters (S21, S11, and S22) Format = log magnitude Calibration = full 2-port 1. 2. 3. 4. 5. Rev. 0 | Page 9 of 18 If the Modify button is visible, click to allow changes. Click Restore Software Defaults to zero out the CONFIGURATION section. Click the ... button next to Load Settings from CSV to select which CSV file to load (see Figure 9). Select the Check to Load Settings check box to load the CSV file contents into the CONFIGURATION section. Note that a check mark does not appear when the check box is selected. Click Apply to send out the settings to the hardware. UG-1921 ADMV8818-EVALZ Evaluation Board User Guide AUTOMATIC CHIP RESET If a reset of the ADMV8818 chip is required on the ADMV8818-EVALZ, click Reset Chip (see Figure 7 and Label J3 in Table 1 for additional information). This automated sequence performs the following actions: * * * * * Toggles all SDP-S general-purpose input/output (GPIO) logic pins to a low state, which brings the RST pin low to initiate a hard reset of the ADMV8818. Toggles the RST pin high to bring the ADMV8818 chip back to the normal operating state. Programs Register 0x000 to 0x81, which also resets the ADMV8818. This step covers legacy boards that did not have the RST pin connected. Programs Register 0x000 to 0x3C to enable the SDO pin on the ADMV8818 and to allow SPI streaming with Endian register ascending order. Reads back the register settings of the ADMV8818. Remove the R2, R3, and R90 resistors to disable these status indicators. See Figure 10 for more details. PLUGIN SPI REGISTER CONTROLLER The ADMV8818 plugin utilizes an SPI register controller to communicate with the ADMV8818. When using the ADMV8818 in a system, it is recommended to follow a similar methodology for implementing SPI communication. The following is a summary of the SPI register controller: 1. 2. 3. 4. LOSS OF BOARD COMMUNICATION When the ADMV8818 is turned off and then on, or if the USB cable is disconnected and connected while the ACE software is running, communication with the ADMV8818 may be lost. To regain communication, take the following steps: 1. 2. 3. Click the System tab. Click the USB symbol in the SDP-S Controller subsystem. Click Acquire. If this action does not work, restart the ACE software to reinitiate communication with the ADMV8818-EVALZ. 5. 6. 7. REGULATOR BYPASS The ADMV8818-EVALZ has a negative voltage generator and three LDO regulators on board that allow the user to operate using the 5 V USB supply voltage from the PC via the SDP-S. These on board LDO regulators provide the three necessary supply voltages, -2.5 V, 2.5 V, and 3.3 V. If desired, these LDO regulators can be bypassed by removing the 0 resistors (R23, R26, and R32) from the ADMV8818-EVALZ, and then applying each voltage independently by using the corresponding test points. Bypassing the on board regulators is useful for measuring the ADMV8818 supply current, but it must be noted that each supply pin is also connected to status indicator LEDs, DS1 to DS3, and each LED draws approximately 2 mA of current. Determine if Register 0x000 is not set to a value of 0x3C. If Step 1 is true, set Register 0x000 to a value of 0x3C to enable the SDO pin on the ADMV8818 and allow SPI streaming with Endian register ascending order. Determine if the values have changed for any of the WR registers (Register 0x020 to Register 0x029). If Step 3 is true, write Register 0x020 to Register 0x029 by pointing to Register 0x020 and streaming out 10 bytes of data. The transaction is 96 bits in total (R/W bit + 15 address bits + 80 data bits). Streaming out the data in this order ensures that the switch position priority is WR0 to WR4. If Step 4 has occurred, write dummy data to Address 0x0A. Note that Address 0x0A does not exist in the ADMV8818, and the written dummy data is ignored. This step is microcontroller architecture dependent and can be ignored in most cases. It is necessary for the SDP-S to clear the SPI bus and reconfigure for a standard 24-bit SPI transaction. Determine if the values have changed for any of the LUT registers (Register 0x100 to Register 0x1FF). If Step 6 is true, write Register 0x100 to Register 0x1FF by performing the following: * * * * 8. 9. Rev. 0 | Page 10 of 18 Pointing to Register 0x100 and streaming out 64 bytes of data. Pointing to Register 0x140 and streaming out 64 bytes of data. Pointing to Register 0x180 and streaming out 64 bytes of data. Pointing to Register 0x1C0 and streaming out 64 bytes of data. If Step 7 has occurred, repeat Step 5. Write out any remaining registers that may have changed. ADMV8818-EVALZ Evaluation Board User Guide UG-1921 EVALUATION BOARD SCHEMATICS AND ARTWORK HK-LR-SR2(12) HK-LR-SR2(12) 1 THRU1 DNI THRU2 DNI THRUCAL 50 OHM TRACE 3 1 3 2 2 LINE LENGTH SHALL BE SAME AS 43 44 45 46 47 48 49 50 51 52 53 54 55 TO DUT AS POSSIBLE GND GND GND GND GND GND GND GND GND GND GND GND GND PAD 56 PLACE SMALLER CAP AS CLOSE GND PAD4 LAUNCHES TO/FROM RFIN & RFOUT. N2P5V 1 2 3 4 5 6 RFIN 7 RFIN 8 50 OHM TRACE 9 HK-LR-SR2(12) 10 11 12 13 S1 VDD2(+3.3V) GND GND U1 RFIN GND GND RFOUT ADMV8818SCCZ-EP GND GND GND GND GND GND GND GND GND VDD1(+2.5V) RST GND PAD GND C1 42 100PF C11 0.1UF 41 40 39 3P3V 38 37 36 35 3 34 32 31 2P5V 30 29 PAD GND PLACE SMALLER CAP AS CLOSE TO DUT AS POSSIBLE PAD2 GND 28 GND 27 26 GND 25 SFL 24 SDI GND 23 GND 22 21 SDO 20 GND C13 0.1UF CS 2 HK-LR-SR2(12) 33 100PF 19 100PF 1 C3 GND C12 0.1UF 50 OHM TRACE C14 3P3V R11 SCLK C2 RFOUT RFOUT 0.1UF 18 2P5V N2P5V 33 CSB_U1 R90 R2 R3 750 330 330 33 DS1 A SDO A R12 DS2 C DS3 R13 LTST-C190GKT LTST-C190GKT A LTST-C190GKT C SDI C 33 R14 SFL 33 R1 CSB_AUX 330 FOR 10MILTHK CORE LAYER USE U7 R15 SFL 3P3VUSB C15 33 1 2 3 IN S2 VDD D GND S1 R80 6 5 R21 4 0 R16 1 142-0701-851 CSB_EXT 49.9 C80 R40 0402 DNI 0.1UF ADG749BKSZ CSB_U1 4 3 2 10PF DNI CSB 25839-010 DNI B3S-1000 PAD1 GND GND 17 2 GND SCLK 4 14 RSTB VSS1(-2.5V) GND 3 GND GND 15 1 GND 16 1 32 PAD GND PAD3 33 Figure 10. ADMV8818-EVALZ Schematic, Page 1 Rev. 0 | Page 11 of 18 Figure 11. ADMV8818-EVALZ Schematic, Page 2 Rev. 0 | Page 12 of 18 0 1 BLK GND1 142-0701-851 234 VNEG 1 C25 10UF USB_VBUS 1UF BLU 0 4 5 VIN VIN NFB SW 3 NFB TBD0402 TBD0402 R47 R46 S2 CL-SB-22A-11T 1 REG_POS_IN 2 3 4 REG_NEG_IN 5 6 TBD0402 TBD0402 R45 R44 2 GND SHDN_N VIN 1 R42 1 2 1UF C0402 C37 4 3 C A NFB 0 R70 24.9K R60 29.4K 10UF C24 R26 C22 10UF 0 R23 10UF C0603 C27 REG_NEG_IN BAT54H,115 D1 1UF 0 C36 R27 0 C33 1UF R24 L1 22UH COILCRAFT LPD5030-223MRC DNI TBD0402 7 REF 6 REF_SENSE PAD PAD EN BYP 8 VREG 4 5 DNI 1 VOUT 2 VOUT 3 VOUT_SENSE U3 ADP7156ACPZ-2.5 9 VIN 10 VIN 6 7 R41 TBD0402 REF_SENSE PAD REF 1 VOUT 2 VOUT 3 VOUT_SENSE PAD 5 EN 4 BYP 8 VREG 10 9 U4 LT1617ES5-1#PBF 1UF 0 C32 1UF VIN_POS USB_VBUS VIN_NEG N2P7V RED TP_VNEG FOR 10MILTHK CORE LAYER USE 142-0701-851 234 VPOS R25 R22 C34C35 1UF C31 TP_VPOS R28 10UF C23 10UF C21 FOR 10MILTHK CORE LAYER USE REG_POS_IN REG_POS_IN U2 ADP7156ACPZ-3.3-R7 0 R31 C0603 0 R29 RED C26 10UF 2P5V RED 3P3V 0 R30 10NF C38 1UF C40 TBD0402 R49 DNI DNI 7 5 4 2 3 8 1UF C39 PAD R50 TBD0402 DNI DNI C97 TBD0402 R53 100K R51 SCL_SDP EP P2 6 10 7 8 9 4 5 6 2 3 1 GND VOUT M20-9980546 VREG EN VAFB VIN SENSE VA 1 A0 A1 A2 SCL WP 0 R32 330 330 R9 R10 R8 330 330 330 330 330 3P3VUSB RSTB SCLK CSB CSB_AUX SDO SFL SDI GND2 BLK N2P5V BLU N2P5V TWI_A0 TBD0402 C91 SFL 0 C92 SCLK TBD0402 R33 CSB_AUX RSTB USB_VBUS 3P3VUSB C16 0.1UF SDA_SDP 24LC32A-I/MS 5 U6 SDA C28 10UF 4 VSS 8 VCC R7 R6 R5 R4 N2P7V 1 2 3 6 7 R48 TBD0402 DNI TBD0402 U5 ADP7183ACPZN2.5-R7 100K R54 TWI_A0 C96 TBD0402 2P5V TBD0402 R43 3P3V R52 TBD0402 DNI 2 1 4 3 6 5 7 9 8 11 10 12 17 16 15 14 13 20 19 18 23 22 21 26 25 24 28 27 30 29 32 31 33 34 36 35 38 37 40 39 43 42 41 44 46 45 47 49 48 51 50 53 52 54 56 55 58 57 59 60 P1 NC NC GND NC CLKOUT BMODE1 UART_TX GND SLEEP_N WAKE_N NC 71 70 68 69 67 66 63 64 65 62 61 TBD0402 C94C95 TBD0402 SDI FX8-120S-SV(21) C93 SDO GPIO6 GND TMR_C TMR_A TBD0402 CSB 72 TMR_D 73 TMR_B 74 GPIO7 75 GND 76 GPIO5 GPIO4 77 GPIO2 GPIO3 78 GPIO0 GPIO1 79 SCL_1 SCL_0 80 SDA_0 SDA_1 81 GND GND 82 SPI_SEL1/SPI_SS_N SPI_CLK 83 SPI_MISO SPI_SEL_C_N 84 SPI_SEL_B_N SPI_MOSI 85 SPI_SEL_A_N GND 86 GND SERIAL_INT 87 SPI_D3 SPORT_TSCLK 88 SPI_D2 SPORT_DT0 89 SPORT_DT1 SPORT_TFS 90 SPORT_DR1 SPORT_RFS 91 SPORT_TDV1 SPORT_DR0 92 SPORT_TDV0 SPORT_RSCLK 93 GND GND 94 PAR_CLK PAR_FS1 95 PAR_FS2 PAR_FS3 96 PAR_A0 PAR_A1 97 PAR_A2 PAR_A3 98 GND GND 99 PAR_INT PAR_CS_N 100 PAR_WR_N PAR_RD_N 101 PAR_D0 PAR_D1 102 PAR_D2 PAR_D3 103 PAR_D4 PAR_D5 104 GND GND 105 PAR_D6 PAR_D7 106 PAR_D8 PAR_D9 107 PAR_D10 PAR_D11 108 PAR_D12 PAR_D13 109 GND PAR_D14 110 PAR_D15 GND 111 PAR_D16 PAR_D17 112 PAR_D18 PAR_D19 113 PAR_D20 PAR_D21 114 PAR_D22 PAR_D23 115 GND GND 116 VIO USB_VBUS 117 GND GND 118 GND GND 119 NC NC 120 NC VIN NC NC GND NC NC RESET_IN_N UART_RX GND RESET_OUT_N EEPROM_A0 NC 0 R34 CSB SDO SDI SCLK SDA_SDP SCL_SDP SFL 3P3VUSB 25839-011 UG-1921 ADMV8818-EVALZ Evaluation Board User Guide UG-1921 25839-012 ADMV8818-EVALZ Evaluation Board User Guide Figure 12. ADMV8818-EVALZ Layer 1 Rev. 0 | Page 13 of 18 ADMV8818-EVALZ Evaluation Board User Guide 25839-013 UG-1921 Figure 13. ADMV8818-EVALZ Layer 2 Rev. 0 | Page 14 of 18 UG-1921 25839-014 ADMV8818-EVALZ Evaluation Board User Guide Figure 14. ADMV8818-EVALZ Layer 3 Rev. 0 | Page 15 of 18 ADMV8818-EVALZ Evaluation Board User Guide 25839-015 UG-1921 Figure 15. ADMV8818-EVALZ Layer 4 Rev. 0 | Page 16 of 18 ADMV8818-EVALZ Evaluation Board User Guide UG-1921 ORDERING INFORMATION BILL OF MATERIALS Table 2. ADMV8818-EVALZ Quantity 3 2 2 3 2 3 6 8 9 1 1 3 1 1 Reference Designator 2P5V, 3P3V, TP_VPOS GND1, GND2 N2P5V, TP_VNEG CSB_EXT, VNEG, VPOS RFIN, RFOUT C1 to C3 C11 to C16 C21 to C28 C31 to C39 C40 D1 DS1 to DS3 L1 P1 1 10 6 14 2 1 1 1 1 1 1 P2 R1 to R10 R11 to R16 R21 to R34 R53, R54 R60 R70 R80 R90 S2 U1 1 1 1 1 1 U2 U3 U4 U5 U6 1 1 U7 C80 7 13 1 2 C91 to C97 R40 to R52 S1 THRU1, THRU2 Description Test points, red Test points, black Test points, blue Connectors, edge launch, SMA Connector, 2.92 mm, 40 GHz Capacitors, 100 pF, 50 V, 5%, 0402 Capacitors, 0.1 F, 16 V, 5%, 0402 Capacitors, 10 F, 16 V, 10%, 0603 Capacitors, 1 F, 16 V, 20%, 0402 Capacitor, 10 nF, 25 V, 10%, 0402 Diode, BAT54H, 30 V, SOD123F LEDs, LTST-C190GKT, green, 0603 Coupled inductor, 22 H, 20% Connector, vertical, surface-mount technology (SMT), 120-pin Connector, vertical, header, 10-pin Resistors, 330 , 1/16 W, 5%, 0402 Resistors, 33 , 1/10 W, 5%, 0402 Resistors, 0 , 1/16 W, 0402 Resistors, 100 k, 1/16 W, 5%, 0402 Resistor, 29.4 k, 1/10 W, 1%, 0402 Resistor, 24.9 k, 1/16 W, 1%, 0402 Resistor, 49.9 , 1/16 W, 1%, 0402 Resistor, 750 , 1/16 W, 5%, 0402 Switch, mechanical, slide, DPDT, 0.2 A ADMV8818, 2 GHz to 18 GHz, digitally tunable, high-pass and low-pass filter IC, LDO regulator, 3.3 V IC, LDO regulator, 2.5 V IC, inverting dc-to-dc converter IC, LDO regulator, -2.5 V IC, 24LC32A, electronically erasable programmable read-only memory (EEPROM), I2C IC, CMOS, SPDT switch Capacitor, 10 pF, 50 V, 5%, 0402, do not install (DNI) Capacitors, 0402, DNI Resistors, 0402, DNI Switch, mechanical, push button, DNI Connector, 2.92 mm, 40 GHz Rev. 0 | Page 17 of 18 Manufacturer Components Corporation Components Corporation Components Corporation Cinch Connectivity Hirose Electric Co. Johanson Dielectrics Kemet Murata Murata Samsung NXP Semiconductor Lite-On Technology Coilcraft Hirose Electric Co. Part Number TP-104-01-02 TP-104-01-00 TP-104-01-06 142-0701-851 HK-LR-SR2(12) 500R07N101JV4T C0402C104J4RACTU GRM188R61C106KAALD GRM155R61C105MA12D CL05B103KA5NNNC BAT54H,115 LTST-C190GKT LPD5030-223MRC FX8-120S-SV(21) Harwin Inc. Panasonic Panasonic Stackpole Yageo Panasonic Panasonic Panasonic Panasonic Nidec Copal Electronics Analog Devices M20-9980546 ERJ-2GEJ331X ERJ-2GEJ330X RMCF0402ZT0R00 RC0402JR-07100KL ERJ-2RKF2942X ERJ-2RKF2492X ERJ-2RKF49R9X ERJ-2GEJ751X CL-SB-22A-11T ADMV8818SCCZ-EP Analog Devices Analog Devices Analog Devices Analog Devices Microchip Technology ADP7156ACPZ-3.3-R7 ADP7156ACPZ-2.5-R7 LT1617ES5-1#TRPBF ADP7183ACPZN2.5-R7 24LC32A-I/MS Analog Devices Yageo ADG749BKSZ CC0402JRNPO9BN100 Not applicable Not applicable Omron Electronics Inc. Hirose Electric Co. Not applicable Not applicable B3S1000 HK-LR-SR2(12) UG-1921 ADMV8818-EVALZ Evaluation Board User Guide NOTES I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ESD Caution ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality. Legal Terms and Conditions By using the evaluation board discussed herein (together with any tools, components documentation or support materials, the "Evaluation Board"), you are agreeing to be bound by the terms and conditions set forth below ("Agreement") unless you have purchased the Evaluation Board, in which case the Analog Devices Standard Terms and Conditions of Sale shall govern. Do not use the Evaluation Board until you have read and agreed to the Agreement. Your use of the Evaluation Board shall signify your acceptance of the Agreement. This Agreement is made by and between you ("Customer") and Analog Devices, Inc. ("ADI"), with its principal place of business at One Technology Way, Norwood, MA 02062, USA. Subject to the terms and conditions of the Agreement, ADI hereby grants to Customer a free, limited, personal, temporary, non-exclusive, non-sublicensable, non-transferable license to use the Evaluation Board FOR EVALUATION PURPOSES ONLY. Customer understands and agrees that the Evaluation Board is provided for the sole and exclusive purpose referenced above, and agrees not to use the Evaluation Board for any other purpose. Furthermore, the license granted is expressly made subject to the following additional limitations: Customer shall not (i) rent, lease, display, sell, transfer, assign, sublicense, or distribute the Evaluation Board; and (ii) permit any Third Party to access the Evaluation Board. As used herein, the term "Third Party" includes any entity other than ADI, Customer, their employees, affiliates and in-house consultants. The Evaluation Board is NOT sold to Customer; all rights not expressly granted herein, including ownership of the Evaluation Board, are reserved by ADI. CONFIDENTIALITY. This Agreement and the Evaluation Board shall all be considered the confidential and proprietary information of ADI. Customer may not disclose or transfer any portion of the Evaluation Board to any other party for any reason. Upon discontinuation of use of the Evaluation Board or termination of this Agreement, Customer agrees to promptly return the Evaluation Board to ADI. ADDITIONAL RESTRICTIONS. Customer may not disassemble, decompile or reverse engineer chips on the Evaluation Board. Customer shall inform ADI of any occurred damages or any modifications or alterations it makes to the Evaluation Board, including but not limited to soldering or any other activity that affects the material content of the Evaluation Board. Modifications to the Evaluation Board must comply with applicable law, including but not limited to the RoHS Directive. TERMINATION. ADI may terminate this Agreement at any time upon giving written notice to Customer. Customer agrees to return to ADI the Evaluation Board at that time. LIMITATION OF LIABILITY. THE EVALUATION BOARD PROVIDED HEREUNDER IS PROVIDED "AS IS" AND ADI MAKES NO WARRANTIES OR REPRESENTATIONS OF ANY KIND WITH RESPECT TO IT. ADI SPECIFICALLY DISCLAIMS ANY REPRESENTATIONS, ENDORSEMENTS, GUARANTEES, OR WARRANTIES, EXPRESS OR IMPLIED, RELATED TO THE EVALUATION BOARD INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, TITLE, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT OF INTELLECTUAL PROPERTY RIGHTS. IN NO EVENT WILL ADI AND ITS LICENSORS BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT, OR CONSEQUENTIAL DAMAGES RESULTING FROM CUSTOMER'S POSSESSION OR USE OF THE EVALUATION BOARD, INCLUDING BUT NOT LIMITED TO LOST PROFITS, DELAY COSTS, LABOR COSTS OR LOSS OF GOODWILL. ADI'S TOTAL LIABILITY FROM ANY AND ALL CAUSES SHALL BE LIMITED TO THE AMOUNT OF ONE HUNDRED US DOLLARS ($100.00). EXPORT. Customer agrees that it will not directly or indirectly export the Evaluation Board to another country, and that it will comply with all applicable United States federal laws and regulations relating to exports. GOVERNING LAW. This Agreement shall be governed by and construed in accordance with the substantive laws of the Commonwealth of Massachusetts (excluding conflict of law rules). Any legal action regarding this Agreement will be heard in the state or federal courts having jurisdiction in Suffolk County, Massachusetts, and Customer hereby submits to the personal jurisdiction and venue of such courts. The United Nations Convention on Contracts for the International Sale of Goods shall not apply to this Agreement and is expressly disclaimed. (c)2020 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. UG25839-12/20(0) Rev. 0 | Page 18 of 18