SN74LVC1G58 SCES415L - NOVEMBER 2002 - REVISED OCTOBER 2011 www.ti.com CONFIGURABLE MULTIPLE-FUNCTION GATE Check for Samples: SN74LVC1G58 FEATURES 1 * 2 * * * * * * * Available in the Texas Instruments NanoFreeTM Package Supports 5-V VCC Operation Inputs Accept Voltages to 5.5 V Max tpd of 6.3 ns at 3.3 V Low Power Consumption, 10-A Max ICC 24-mA Output Drive at 3.3 V Ioff Supports Partial-Power-Down Mode Operation DBV PACKAGE (TOP VIEW) In1 1 6 Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 - 2000-V Human-Body Model (A114-A) - 200-V Machine Model (A115-A) - 1000-V Charged-Device Model (C101) * DRL PACKAGE (TOP VIEW) DCK PACKAGE (TOP VIEW) In1 In2 GND 2 5 VCC In0 3 4 Y 1 GND 2 5 In0 3 4 In1 In2 6 GND VCC In0 2 3 In2 6 VCC 5 Y 4 In0 3 4 Y GND 2 5 VCC In1 1 6 In2 Y DRY PACKAGE (TOP VIEW) ln1 See mechanical drawings for dimensions. 1 YZP PACKAGE (BOTTOM VIEW) 1 6 ln2 GND 2 5 VCC ln0 3 4 Y DSF PACKAGE (TOP VIEW) ln1 GND ln0 1 6 2 5 3 4 ln2 VCC Y DESCRIPTION/ORDERING INFORMATION This configurable multiple-function gate is designed for 1.65-V to 5.5-V VCC operation. The SN74LVC1G58 features configurable multiple functions. The output state is determined by eight patterns of 3-bit input. The user can choose the logic functions AND, OR, NAND, NOR, XOR, inverter, and noninverter. All inputs can be connected to VCC or GND. This device functions as an independent gate, but because of Schmitt action, it may have different input threshold levels for positive-going (VT+) and negative-going (VT-) signals. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. NanoFree is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2002-2011, Texas Instruments Incorporated SN74LVC1G58 SCES415L - NOVEMBER 2002 - REVISED OCTOBER 2011 www.ti.com ORDERING INFORMATION PACKAGE (1) TA -40C to 85C (1) (2) (3) ORDERABLE PART NUMBER TOP-SIDE MARKING (2) NanoFreeTM - WCSP (DSBGA) 0.23-mm Large Bump - YZP (Pb-free) Reel of 3000 SN74LVC1G58YZPR _ _ _CP_ SOT (SOT-23) - DBV Reel of 3000 SN74LVC1G58DBVR C58_ SOT (SC-70) - DCK Reel of 3000 SN74LVC1G58DCKR CP_ SOT (SOT-563) - DRL Reel of 4000 SN74LVC1G58DRLR CP_ QFN - DSF Reel of 5000 SN74LVC1G58DSFR CP QFN - DSF Reel of 5000 SN74LVC1G58DSF2 (3) CP QFN - DRY Reel of 5000 SN74LVC1G58DRYR CP Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. DBV/DCK/DRL: The actual top-side marking has one additional character that designates the assembly/test site. YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, * = Pb-free). Pin 1 orientation at quadrant 3 in Tape. DESCRIPTION/ORDERING INFORMATION (CONTINUED) NanoFreeTM package technology is a major breakthrough in IC packaging concepts, using the die as the package. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. Table 1. FUNCTION TABLE INPUTS OUTPUT In2 In1 In0 L L L Y L L L H H L H L L L H H H H L L H H L H H H H L L H H H L Figure 1. LOGIC DIAGRAM (POSITIVE LOGIC) In0 3 4 In1 In2 2 1 Y 6 Submit Documentation Feedback Copyright (c) 2002-2011, Texas Instruments Incorporated Product Folder Link(s): SN74LVC1G58 SN74LVC1G58 SCES415L - NOVEMBER 2002 - REVISED OCTOBER 2011 www.ti.com Table 2. FUNCTION SELECTION TABLE LOGIC FUNCTION FIGURE NO. 2-input AND with inverted input 2, 3 2-input NAND 1 2-input NAND with both inputs inverted 4 2-input OR 4 2-input OR with both inputs inverted 1 2-input NOR with inverted input 2, 3 2-input XOR 5 LOGIC CONFIGURATIONS VCC A Y B A VCC A Y B A Y B 1 6 2 5 3 4 A B A Y Y B Figure 2. 2-Input NAND Gate 1 6 2 5 3 4 B Y Figure 3. 2-Input AND Gate With Inverted A Input VCC VCC A A Y B A B Y Y B A 1 6 2 5 3 4 B A Y A B Y Figure 4. 2-Input AND Gate With Inverted B Input 1 6 2 5 3 4 B Y Figure 5. 2-Input OR Gate VCC A Y B A 1 6 2 5 3 4 B Y Figure 6. 2-Input XOR Gate Submit Documentation Feedback Copyright (c) 2002-2011, Texas Instruments Incorporated Product Folder Link(s): SN74LVC1G58 3 SN74LVC1G58 SCES415L - NOVEMBER 2002 - REVISED OCTOBER 2011 www.ti.com Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VCC Supply voltage range -0.5 6.5 V VI Input voltage range (2) -0.5 6.5 V VO Voltage range applied to any output in the high-impedance or power-off state (2) -0.5 6.5 V VO Voltage range applied to any output in the high or low state (2) -0.5 VCC + 0.5 V IIK Input clamp current VI < 0 -50 mA IOK Output clamp current VO < 0 -50 mA IO Continuous output current 50 mA 100 mA (3) Continuous current through VCC or GND JA Package thermal impedance (4) Tstg Storage temperature range DBV package 165 DCK package 259 DRL package 142 YZP package (1) (2) (3) (4) C/W 123 -65 150 C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. The value of VCC is provided in the recommended operating conditions table. The package thermal impedance is calculated in accordance with JESD 51-7. Recommended Operating Conditions (1) VCC Supply voltage VI Input voltage VO Output voltage IOH High-level output current Operating Data retention only MIN MAX 1.65 5.5 1.5 5.5 V 0 VCC V VCC = 1.65 V -4 VCC = 2.3 V -8 -16 VCC = 3 V -32 4 VCC = 2.3 V 8 16 VCC = 3 V (1) 4 32 -40 Operating free-air temperature mA 24 VCC = 4.5 V TA mA -24 VCC = 1.65 V Low-level output current V 0 VCC = 4.5 V IOL UNIT 85 C All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. Submit Documentation Feedback Copyright (c) 2002-2011, Texas Instruments Incorporated Product Folder Link(s): SN74LVC1G58 SN74LVC1G58 SCES415L - NOVEMBER 2002 - REVISED OCTOBER 2011 www.ti.com Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VT+ Positive-going input threshold voltage VT- Negative-going input threshold voltage VT Hysteresis (VT+ - VT-) MIN 1.65 V 0.79 1.16 2.3 V 1.11 1.56 3V 1.5 1.87 4.5 V 2.16 2.74 VOH 5.5 V 2.61 3.33 0.35 0.62 2.3 V 0.58 0.87 3V 0.84 1.19 4.5 V 1.41 1.9 5.5 V 1.87 2.29 1.65 V 0.3 0.62 2.3 V 0.4 0.8 3V 0.53 0.87 4.5 V 0.71 1.04 0.71 1.11 1.65 V to 5.5 V 1.65 V 1.2 IOH = -8 mA 2.3 V 1.9 3V IOH = -24 mA VOL 4.5 V 1.65 V to 5.5 V 0.1 IOL = 4 mA 1.65 V 0.45 IOL = 8 mA 2.3 V 0.3 II ICC VI = 5.5 V or GND, IO = 0 Ci (1) VI = 5.5 V or GND VI or VO = 5.5 V ICC 0.4 One input at VCC - 0.6 V, Other inputs at VCC or GND VI = VCC or GND V 0.55 4.5 V Ioff V 3.8 3V IOL = 32 mA V 2.3 IOL = 100 A IOL = 24 mA V V 2.4 IOH = -32 mA IOL = 16 mA UNIT VCC - 0.1 IOH = -4 mA IOH = -16 mA MAX 1.65 V 5.5 V IOH = -100 A TYP (1) VCC 0.55 0 to 5.5 V 1 A 0 10 A 1.65 V to 5.5 V 10 A 3 V to 5.5 V 500 A 3.3 V 3.5 pF All typical values are at VCC = 3.3 V, TA = 25C. Submit Documentation Feedback Copyright (c) 2002-2011, Texas Instruments Incorporated Product Folder Link(s): SN74LVC1G58 5 SN74LVC1G58 SCES415L - NOVEMBER 2002 - REVISED OCTOBER 2011 www.ti.com Switching Characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 7) PARAMETER tpd FROM (INPUT) TO (OUTPUT) Any In Y VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V 0.15 V 0.2 V 0.3 V MIN MAX 3.2 MIN MAX 14.4 2 8.3 MIN MAX 1.5 6.3 VCC = 5 V 0.5 V UNIT MIN MAX 1.1 5.1 ns Operating Characteristics TA = 25C PARAMETER Cpd 6 Power dissipation capacitance TEST CONDITIONS VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V TYP TYP TYP TYP f = 10 MHz 22 22 23 24 Submit Documentation Feedback UNIT pF Copyright (c) 2002-2011, Texas Instruments Incorporated Product Folder Link(s): SN74LVC1G58 SN74LVC1G58 SCES415L - NOVEMBER 2002 - REVISED OCTOBER 2011 www.ti.com PARAMETER MEASUREMENT INFORMATION VLOAD S1 RL From Output Under Test CL (see Note A) Open GND RL TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open VLOAD GND LOAD CIRCUIT INPUTS VCC 1.8 V 0.15 V 2.5 V 0.2 V 3.3 V 0.3 V 5 V 0.5 V VI tr/tf VCC VCC 3V VCC 2 ns 2 ns 2.5 ns 2.5 ns VM VLOAD CL RL V VCC/2 VCC/2 1.5 V VCC/2 2 x VCC 2 x VCC 6V 2 x VCC 30 pF 30 pF 50 pF 50 pF 1 k 500 500 500 0.15 V 0.15 V 0.3 V 0.3 V VI Timing Input VM 0V tw tsu VI Input VM VM th VI Data Input VM VM 0V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PULSE DURATION VI VM Input VM 0V VOH VM Output VM VOL VM 0V VLOAD/2 VM tPZH VOH Output VM tPLZ Output Waveform 1 S1 at VLOAD (see Note B) tPLH tPHL VM tPZL tPHL tPLH VI Output Control VM VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS VOL + V VOL tPHZ Output Waveform 2 S1 at GND (see Note B) VM VOH - V VOH 0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 . D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 7. Load Circuit and Voltage Waveforms Submit Documentation Feedback Copyright (c) 2002-2011, Texas Instruments Incorporated Product Folder Link(s): SN74LVC1G58 7 SN74LVC1G58 SCES415L - NOVEMBER 2002 - REVISED OCTOBER 2011 www.ti.com REVISION HISTORY Changes from Revision K (January 2007) to Revision L Page * Added DRY and DSF packages to datasheet. ..................................................................................................................... 1 * Added additional package options in the ORDERING INFORMATION table. ..................................................................... 2 8 Submit Documentation Feedback Copyright (c) 2002-2011, Texas Instruments Incorporated Product Folder Link(s): SN74LVC1G58 PACKAGE OPTION ADDENDUM www.ti.com 5-Mar-2012 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp Samples (Requires Login) SN74LVC1G58DBVR ACTIVE SOT-23 DBV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC1G58DBVRE4 ACTIVE SOT-23 DBV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC1G58DBVRG4 ACTIVE SOT-23 DBV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC1G58DCKR ACTIVE SC70 DCK 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC1G58DCKRE4 ACTIVE SC70 DCK 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC1G58DCKRG4 ACTIVE SC70 DCK 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC1G58DRLR ACTIVE SOT DRL 6 4000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC1G58DRLRG4 ACTIVE SOT DRL 6 4000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC1G58DRYR ACTIVE SON DRY 6 5000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC1G58DSF2 ACTIVE SON DSF 6 5000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC1G58DSFR ACTIVE SON DSF 6 5000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC1G58YZPR ACTIVE DSBGA YZP 6 3000 Green (RoHS & no Sb/Br) SNAGCU (3) Level-1-260C-UNLIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 5-Mar-2012 Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 29-Jun-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) SN74LVC1G58DBVR SOT-23 DBV 6 3000 178.0 9.2 3.3 SN74LVC1G58DCKR SC70 DCK 6 3000 178.0 9.0 SN74LVC1G58DCKR SC70 DCK 6 3000 180.0 9.2 SN74LVC1G58DRLR SOT DRL 6 4000 180.0 SN74LVC1G58DRLR SOT DRL 6 4000 SN74LVC1G58DRYR SON DRY 6 SN74LVC1G58DSF2 SON DSF 6 SN74LVC1G58DSFR SON DSF SN74LVC1G58YZPR DSBGA YZP 3.2 1.55 4.0 8.0 Q3 2.4 2.5 1.2 4.0 8.0 Q3 2.3 2.55 1.2 4.0 8.0 Q3 8.4 1.98 1.78 0.69 4.0 8.0 Q3 180.0 9.5 1.78 1.78 0.69 4.0 8.0 Q3 5000 180.0 9.5 1.15 1.6 0.75 4.0 8.0 Q1 5000 180.0 9.5 1.16 1.16 0.5 4.0 8.0 Q3 6 5000 180.0 9.5 1.16 1.16 0.5 4.0 8.0 Q2 6 3000 180.0 8.4 1.02 1.52 0.63 4.0 8.0 Q1 Pack Materials-Page 1 W Pin1 (mm) Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 29-Jun-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74LVC1G58DBVR SOT-23 DBV 6 3000 180.0 180.0 18.0 SN74LVC1G58DCKR SC70 DCK 6 3000 180.0 180.0 18.0 SN74LVC1G58DCKR SC70 DCK 6 3000 205.0 200.0 33.0 SN74LVC1G58DRLR SOT DRL 6 4000 202.0 201.0 28.0 SN74LVC1G58DRLR SOT DRL 6 4000 180.0 180.0 30.0 SN74LVC1G58DRYR SON DRY 6 5000 180.0 180.0 30.0 SN74LVC1G58DSF2 SON DSF 6 5000 180.0 180.0 30.0 SN74LVC1G58DSFR SON DSF 6 5000 180.0 180.0 30.0 SN74LVC1G58YZPR DSBGA YZP 6 3000 220.0 220.0 34.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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