AD9878BSTZ - Analog Devices

Mixed-Signal Front End

for Broadband Applications

AD9878

Rev. A

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However, no responsibility is assumed by Analog Devices for its use, nor for any

infringements of patents or other rights of third parties that may result from its use.

Specifications subject to change without notice. No license is granted by implication

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registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700 www.analog.com

FEATURES

Low cost 3.3 V CMOS MxFE™ for broadband applications

DOCSIS, EURO-DOCSIS, DVB, DAVIC compliant

232 MHz quadrature digital upconverter

12-bit direct IF DAC (TxDAC+®)

Up to 65 MHz carrier frequency DDS

Programmable sampling clock rates

Analog Tx output level adjust

Dual 12-bit, 29 MSPS direct IF ADCs with video clamp input

10-bit, 29 MSPS sampling ADC

8-bit ∑-∆ auxiliary DAC

Direct interface to AD832x family of PGA cable drivers

APPLICATIONS

Cable set-top boxes

Cable and wireless modems

FUNCTIONAL BLOCK DIAGRAM

03277-001

–

Q12

TxID[5:0]

Σ-∆ OUTPUT

CA PORT

MCLK

OSCIN

IF10 INPUT

IF12B INPUT

VIDEO IN

IF12A INPUT

CLAMP

LEVEL

SDIO

IF10[4:0]

IF12[11:0]

FLAG[2:1]

Tx 16

DDS

SINC

–1

Σ-∆

12 MUX

ADC

MUX

DAC

CONTROL REGISTERS

PLL

Figure 1.

GENERAL DESCRIPTION

The AD9878 is a single-supply, cable modem/set-top box,

mixed-signal front end. The device contains a transmit path

interpolation filter, a complete quadrature digital upconverter,

and a transmit DAC. The receive path contains dual 12-bit

ADCs and a 10-bit ADC. All internally required clocks and an

output system clock are generated by the phase-locked loop

(PLL) from a single crystal oscillator or clock input.

The transmit path interpolation filter provides an upsampling

factor of 16× with an output signal bandwidth up to 4.35 MHz.

Carrier frequencies up to 65 MHz with 26 bits of frequency tuning

resolution can be generated by the direct digital synthesizer

(DDS). The transmit DAC resolution is 12 bits and can run at

sampling rates as high as 232 MSPS. Analog output scaling from

0 dB to 7.5 dB in 0.5 dB steps is available to preserve SNR when

reduced output levels are required.

The 12-bit ADCs provide excellent undersampling performance,

allowing this device to typically deliver better than 10 ENOBs

with IF inputs up to 70 MHz. The 12-bit IF ADCs can sample at

rates up to 29 MHz, allowing them to process wideband signals.

The AD9878 includes a programmable ∑-∆ DAC, which can be

used to control an external component such as a variable gain

amplifier (VGA) or a voltage controlled tuner.

The AD9878 also integrates a CA port that enables a host

processor to interface with the AD832x family of programmable

gain amplifier (PGA) cable drivers or industry equivalent via

the MxFE serial port (SPORT).

The AD9878 is available in a 100-lead, LQFP package. The

AD9878 is specified over the extended industrial (−40°C to

+85°C) temperature range.

AD9878

Rev. A | Page 2 of 36

TABLE OF CONTENTS

Electrical Characteristics ................................................................. 4

Absolute Maximum Ratings............................................................ 7

Explanation of Test Levels........................................................... 7

Thermal Characteristics .............................................................. 7

ESD Caution.................................................................................. 7

Pin Configuration and Function Descriptions............................. 8

Typical Performance Characteristics ........................................... 10

Terminology .................................................................................... 13

Registers 0x10 Through 0x17—Burst Parameter................... 17

Serial Interface for Register Control ............................................ 18

General Operation of the Serial Interface............................... 18

Instruction Byte .......................................................................... 18

Serial Interface Port Pin Descriptions ..................................... 18

MSB/LSB Transfers..................................................................... 19

Notes on Serial Port Operation ................................................ 19

Theory of Operation ...................................................................... 20

Transmit Path.............................................................................. 21

Data Assembler........................................................................... 21

Transmit Timing......................................................................... 21

Interpolation Filter..................................................................... 21

Half-Band Filters (HBFs) .......................................................... 21

Cascade Integrator Comb (CIC) Filter.................................... 21

Combined Filter Response........................................................ 21

Digital Upconverter ................................................................... 22

Tx Signal Level Considerations................................................ 22

Tx Throughput and Latency..................................................... 23

DAC.............................................................................................. 23

Programming the AD8321/AD8323 or

AD8322/AD8327/AD8238 Cable-Driver Amplifiers............ 23

OSCIN Clock Multiplier ........................................................... 24

Clock and Oscillator Circuitry ................................................. 24

Programmable Clock Output REFCLK .................................. 24

Power-Up Sequence ................................................................... 26

Reset ............................................................................................. 26

Transmit Power-Down .............................................................. 26

∑-∆ Outputs ................................................................................ 27

Receive Path (Rx) ....................................................................... 27

IF10 and IF12 ADC Operation ................................................ 27

ADC Voltage References ........................................................... 29

Video Input ................................................................................. 29

PCB Design Considerations.......................................................... 30

Component Placement.............................................................. 30

Power Planes and Decoupling .................................................. 30

Ground Planes ............................................................................ 30

Signal Routing............................................................................. 30

Outline Dimensions....................................................................... 36

Ordering Guide .......................................................................... 36

AD9878

Rev. A | Page 3 of 36

REVISION HISTORY

3/05—Rev. 0 to Rev. A

Changed OSCOUT to REFCLK.................................................. Universal

Changes to Electrical Characteristics ........................................................4

Changes to Pin Configuration and Function Descriptions....................8

Changes to ∑-∆ Output Signals (Figure 32)............................................27

Change to ∑-∆ RC Filter (Figure 33) .......................................................27

Changes to Evaluation PCB Schematic (Figure 38 and Figure 39)......31

Updated Outline Dimensions...................................................................36

Changes to Ordering Guide......................................................................36

5/03—Revision 0: Initial Version

AD9878

Rev. A | Page 4 of 36

ELECTRICAL CHARACTERISTICS

VAS = 3.3 V ± 5%, VDS = 3.3 V ± 10%, fOSCIN = 27 MHz, fSYSCLK = 216 MHz, fMCLK = 54 MHz (M = 8), ADC clock derived from OSCIN,

RSET = 4.02 kΩ, maximum. Fine gain, 75 Ω DAC load.

Table 1.

PARAMETER Temp Test Level Min Typ Max Unit

OSCIN and XTAL CHARACTERISTICS

Frequency Range Full II 3 29 MHz

Duty Cycle 25°C II 35 50 65 %

Input Impedance 25°C III 100||3 MΩ||pF

MCLK Cycle-to-Cycle Jitter (fMCLK derived from PLL) 25°C III 6 ps rms

Tx DAC CHARACTERISTICS

Maximum Sample Rate Full II 232 MHz

Resolution N/A N/A 12 Bits

Full-Scale Output Current Full II 4 10 20 mA

Gain Error (Using Internal Reference) 25°C I −2.0 −1 +2.0 % FS

Offset Error 25°C I ±1.0 % FS

Reference Voltage (REFIO Level) 25°C I 1.18 1.23 1.28 V

Differential Nonlinearity (DNL) 25°C III ±2.5 LSB

Integral Nonlinearity (INL) 25°C III ±8 LSB

Output Capacitance 25°C III 5 pF

Phase Noise @ 1 kHz Offset, 42 MHz Carrier 25°C III −110 dBc/Hz

Output Voltage Compliance Range Full II −0.5 +1.5 V

Wideband SFDR

5 MHz Analog Output, IOUT = 10 mA Full II 62.4 68 dB

65 MHz Analog Output, IOUT = 10 mA Full II 50.3 53.5 dB

Narrow-Band SFDR (±1 MHz Window)

5 MHz Analog Output, IOUT = 10 mA Full II 71 74 dB

65 MHz Analog Output, IOUT = 10 mA Full II 61 64 dB

Tx MODULATOR CHARACTERISTICS

I/Q Offset Full II 50 55 dB

Pass-Band Amplitude Ripple (f < fIQCLK/8) Full II ±0.1 dB

Pass-Band Amplitude Ripple (f < fIQCLK/4) Full II ±0.5 dB

Stop-Band Response (f > fIQCLK × 3/4) Full II −63 dB

Tx GAIN CONTROL

Gain Step Size 25°C III 0.5 dB

Gain Step Error 25°C III <0.05 dB

Settling Time, 1% (Full-Scale Step) 25°C III 1.8 µs

10-BIT ADC CHARACTERISTICS

Resolution N/A N/A 10 Bits

Maximum Conversion Rate Full II 29 MHz

Pipeline Delay N/A N/A 4.5 ADC cycles

Analog Input

Input Voltage Range Full II 2 VPPD

Differential Input Impedance 25°C III 4||2 kΩ||pF

Full Power Bandwidth 25°C III 90 MHz

Dynamic Performance (AIN = −0.5 dBFS, f = 5 MHz)

Signal-to-Noise and Distortion (SINAD) Full II 57.6 59.7 dB

Effective Number of Bits (ENOB) Full II 9.3 9.6 Bits

Total Harmonic Distortion (THD) Full II −71.1 −63.6 dB

Spurious-Free Dynamic Range (SFDR) Full II 65.7 72.4 dB

Reference Voltage Error, REFT10 to REFB10 (1.0 V) Full I ±4 ±100 mV

AD9878

Rev. A | Page 5 of 36

PARAMETER Temp Test Level Min Typ Max Unit

Dynamic Performance (AIN = −0.5 dBFS, f = 50 MHz)

Signal-to-Noise and Distortion (SINAD) Full II 54.8 57.8 dB

Effective Number of Bits (ENOB) Full II 8.8 9.3 Bits

Total Harmonic Distortion (THD) Full II −63.3 −56.9 dB

Spurious-Free Dynamic Range (SFDR) Full II 56.9 63.7 dB

12-BIT ADC CHARACTERISTICS

Resolution N/A N/A 12 Bits

Maximum Conversion Rate Full II 29 MHz

Pipeline Delay N/A N/A 5.5 ADC cycles

Analog Input

Input Voltage Range Full III 2 VPPD

Differential Input Impedance 25°C III 4||2 kΩ||pF

Aperture Delay 25°C III 2.0 ns

Aperture Jitter 25°C III 1.2 ps rms

Full Power Bandwidth 25°C III 85 MHz

Input Referred Noise 25°C III 75 µV

Reference Voltage Error, REFT12 to REFB12 (1 V) Full I −100 ±16 +100 mV

Dynamic Performance (AIN = −0.5 dBFS, f = 5 MHz)

ADC Sample Clock = OSCIN

Signal-to-Noise and Distortion (SINAD) Full II 61.0 67 dB

Effective Number of Bits (ENOBs) Full II 9.8 10.8 Bits

Signal-to-Noise Ratio (SNR) Full II 64.2 66 dB

Total Harmonic Distortion (THD) Full II −72.7 −61.7 dB

Spurious-Free Dynamic Range (SFDR) Full II 62.8 74.6 dB

ADC Sample Clock = PLL

Signal-to-Noise and Distortion (SINAD) Full II 60.4 64.4 dB

Effective Number of Bits (ENOB) Full II 9.74 10.4 Bits

Signal-to-Noise Ratio (SNR) Full II 62.4 65.1 dB

Total Harmonic Distortion (THD) Full II −72.7 −61.8 dB

Spurious-Free Dynamic Range (SFDR) Full II 62.7 74.6 dB

Dynamic Performance (AIN = −0.5 dBFS, f = 50 MHz)

ADC Sample Clock = OSCIN

Signal-to-Noise and Distortion (SINAD) Full II 61.0 65.2 dB

Effective Number of Bits (ENOB) Full II 9.8 10.5 Bits

Signal-to-Noise Ratio (SNR) Full II 64.2 67.4 dB

Total Harmonic Distortion (THD) Full II −72.8 −61.8 dB

Spurious-Free Dynamic Range (SFDR) Full II 62.8 74.6 dB

Differential Phase 25°C III <0.1 Degrees

Differential Gain 25°C III <1 LSB

VIDEO ADC PERFORMANCE (AIN = −0.5 dBFS, f = 5 MHz)

ADC Sample Clock = OSCIN

Signal-to-Noise and Distortion (SINAD) Full II 46.7 53 dB

Signal-to-Noise Ratio (SNR) Full II 54.3 63.2 Bits

Total Harmonic Distortion (THD) Full II −50.2 −45.9 dB

Spurious-Free Dynamic Range (SFDR) Full II 45.9 50 dB

CHANNEL-TO-CHANNEL ISOLATION

Tx DAC-to-ADC Isolation (5 MHz Analog Output)

Isolation Between Tx and 10-Bit ADC 25°C III >60 dB

Isolation Between Tx and 12-Bit ADCs 25°C III >80 dB

ADC-to-ADC Isolation (AIN = –0.5 dBFS, f = 5 MHz)

Isolation Between IF10 and IF12A/B 25°C III >85 dB

Isolation Between IF12A and IF12B 25°C III >85 dB

AD9878

Rev. A | Page 6 of 36

PARAMETER Temp Test Level Min Typ Max Unit

TIMING CHARACTERISTICS (10 pF Load)

Wake-Up Time N/A N/A 200 tMCLK cycles

Minimum RESET Pulse Width Low, tRL N/A N/A 5 tMCLK cycles

Digital Output Rise/Fall Time Full II 2.8 4 ns

Tx/Rx Interface

MCLK Frequency, fMCLK Full II 58 MHz

TxSYNC/TxIQ Setup Time, tSU Full II 3 ns

TxSYNC/TxIQ Hold Time, tHU Full II 3 ns

MCLK Rising Edge to RxSYNC Valid Delay, tMD Full II 0 1.0 ns

REFCLK Rising or Falling Edge to

RxSYNC Valid Delay, tOD

Full II tOSCIN/

4 − 2.0

tOSCIN/

4 + 3.0

REFCLK Edge to MCLK Falling Edge, tEE Full II −1.0 +1.0 ns

SERIAL CONTROL BUS

Maximum SCLK Frequency, fSCLK Full II 15 MHz

Minimum Clock Pulse Width High, tPWH Full II 30 ns

Minimum Clock Pulse Width Low, tPWL Full II 30 ns

Maximum Clock Rise/Fall Time Full II 1 µs

Minimum Data/Chip-Select Setup Time, tDS Full II 25 ns

Minimum Data Hold Time, tDH Full II 0 ns

Maximum Data Valid Time, tDV Full II 30 ns

CMOS LOGIC INPUTS

Logic 1 Voltage 25°C II VDRVDD − 0.7 V

Logic 0 Voltage 25°C II 0.4 V

Logic 1 Current 25°C II 12 µA

Logic 0 Current 25°C II 12 µA

Input Capacitance 25°C III 3 pF

CMOS LOGIC OUTPUTS (1 mA Load)

Logic 1 Voltage 25°C II VDRVDD − 0.6 V

Logic 0 Voltage 25°C II 0.4 V

POWER SUPPLY

Supply Current, IS (Full Operation) 25°C II 184 204 mA

Analog Supply Current, IAS 25°C III 105 115 mA

Digital Supply Current, IDS 25°C III 79 89 mA

Supply Current, IS

Standby (PWRDN Pin Active, IAS + IDS ) 25°C II 124 137 mA

Full Power-Down (Register 0x02 = 0xFF) 25°C II 46 52 mA

Power-Down Tx Path (Register 0x02 = 0x60) 25°C III 124 mA

Power-Down IF12 Rx Path (Register 0x02 = 0x1B) 25°C III 131 159 mA

Power Supply Rejection (Differential Signal)

Tx DAC 25°C III <0.25 % FS

10-Bit ADC 25°C III <0.0001 % FS

12-Bit ADC 25°C III <0.0004 % FS

AD9878

Rev. A | Page 7 of 36

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

Power Supply (VAVDD, VDVDD, VDRVDD) 3.9 V

Digital Output Current 5 mA

Digital Inputs −0.3 V to VDRVDD + 0.3 V

Analog Inputs −0.3 V to VAVDD + 0.3 V

Operating Temperature −40°C to +85°C

Maximum Junction Temperature 150°C

Storage Temperature −65°C to +150°C

Lead Temperature (Soldering, 10 sec) 300°C

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other condition s above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

EXPLANATION OF TEST LEVELS

I. Devices are 100% production tested at 25°C and guaranteed

by design and characterization testing for extended industrial

operating temperature range (−40°C to +85°C).

II. Parameter is guaranteed by design and/or characterization

testing.

III. Parameter is a typical value only.

N/A. Test level definition is not applicable.

THERMAL CHARACTERISTICS

Thermal resistance of 100-lead LQFP: θJA = 40.5°C/W

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on

the human body and test equipment and can discharge without detection. Although this product features

proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy

electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance

degradation or loss of functionality.

AD9878

Rev. A | Page 8 of 36

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

03277-002

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77

AVDD

AGND

VIDEO IN

AGND

IF12A+

IF12A–

AGND

AVDD

REFT12A

REFB12

AVDD

AGND

IF12B+

IF12B–

AGND

AVDD

REFT12B

REFB12

AVDD

AGND

AVDD10

AGND10

IF10+

IF10–

AGND

REFT10

REFB10

AGND10

AVDD10

DRVDD

DRGND

REFCLK

SIGDELT

FLAG1

FLAG2

CA_EN

CA_DATA

CA_CLK

DVDDOSC

OSCIN

XTAL

DGNDOSC

AGNDPLL

PLLFILT

AVDDPLL

DVDDPLL

DGNDPLL

AVDDTx

Tx+

Tx–

TxSYNC

(MSB) TxIQ(5)

TxIQ(4)

TxIQ(3)

TxIQ(2)

TxIQ(1)

TxIQ(0)

DVDD

DGND

DVDD

DGND

PROFILE

RESET

DVDD

DGND

SCLK

SDIO

SDO

DGNDTx

DVDDTx

PWRDN

REFIO

FSADJ

AGNDTx

DRGND

DRVDD

(MSB) IF12(11)

IF12(10)

IF12(9)

IF12(8)

IF12(7)

IF12(6)

IF12(5)

IF12(4)

IF12(3)

IF12(2)

IF12(1)

IF12(0)

(MSB) IF10(4)

IF10(3)

IF10(2)

IF10(1)

IF10(0)

RxSYNC

DRGND

DRVDD

MCLK

DVDD

DGND

AD9878

TOP VIEW

(Not to Scale)

Figure 2. Pin Configuration

Table 3. Pin Function Descriptions

Pin No. Mnemonic Descriptions

1, 21, 70 DRGND Pin Driver Digital Ground

2, 22, 71 DRVDD Pin Driver Digital 3.3 V Supply

3 (MSB) IF12(11) 12-Bit ADC Digital Ouput

4 to 14 IF12[10:0] 12-Bit ADC Digital Ouput

15 (MSB) IF10(4) 10-Bit ADC Digital Ouput

16 to 19 IF10[3:0] 10-Bit ADC Digital Ouput

20 RxSYNC Sync Output, 10-Bit and 12-Bit ADCs

23 MCLK Master Clock Output

24, 33, 35, 39 DVDD Digital 3.3 V Supply

25, 34, 36, 40 DGND Digital Ground

26 TxSYNC Sync Input for Transmit Port

27 (MSB) TxIQ(5) Digital Input for Transmit Port

28 to 32 TxIQ[4:0] Digital Input for Transmit Port

37 PROFILE Profile Selection Input

38 RESET Chip Reset Input

41 SCLK SPORT Clock

42 CS SPORT Chip Select

43 SDIO SPORT Data I/O

AD9878

Rev. A | Page 9 of 36

Pin No. Mnemonic Descriptions

44 SDO SPORT Data Output

45 DGNDTx Tx Path Digital Ground

46 DVDDTx Tx Path Digital 3.3 V Supply

47 PWRDN Power-Down Transmit Path

48 REFIO TxDAC Decoupling (to AGND)

49 FSADJ DAC Output Adjust (External Resistor)

50 AGNDTx Tx Path Analog Ground

51, 52 Tx−, Tx+ Tx Path Complementary Outputs

53 AVDDTx Tx Path Analog 3.3 V Supply

54 DGNDPLL PLL Digital Ground

55 DVDDPLL PLL Digital 3.3 V Supply

56 AVDDPLL PLL Analog 3.3 V Supply

57 PLLFILT PLL Loop Filter Connection

58 AGNDPLL PLL Analog Ground

59 DGNDOSC Oscillator Digital Ground

60 XTAL Crystal Oscillator Inverted Output

61 OSCIN Oscillator Clock Input

62 DVDDOSC Oscillator Digital 3.3 V Supply

63 CA_CLK Serial Clock-to-Cable Driver

64 CA_DATA Serial Data-to-Cable Driver

65 CA_EN Serial Enable-to-Cable Driver

66, 67 FLAG[2:1] Programmable Flag Outputs

68 SIGDELT ∑-∆ DAC Output

69 REFCLK Reference Clock Output

72, 80 AVDD10 10-Bit ADC Analog 3.3 V Supply

73, 79 AGND10 10-Bit ADC Analog Ground

74 REFB10 10-Bit ADC Reference Decoupling Node

75 REFT10 10-Bit ADC Reference Decoupling Node

76, 81, 86, 89, 94,

97, 99

AGND 12-Bit ADC Analog Ground

77, 78 IF10−, IF10+ Differential Input to 10-bit ADC

82, 85, 90, 93, 100 AVDD 12-Bit ADC Analog 3.3 V Supply

83 REFB12B ADC12B Reference Decoupling Node

84 REFT12B ADC12B Reference Decoupling Node

87, 88 IF12B−, IF12B+ Differential Input to ADC12B

91 REFB12A ADC12A Reference Decoupling Node

92 REFT12A ADC12A Reference Decoupling Node

95, 96 IF12A−, IF12A+ Differential Input to ADC12A

98 VIDEO IN Video Clamp Input

AD9878

Rev. A | Page 10 of 36

TYPICAL PERFORMANCE CHARACTERISTICS

FREQUENCY (MHz)

MAGNITUDE (dB)

024681012141618

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

03277-022

Figure 3. Dual-Sideband Spectral Plot, fC = 5 MHz, f = 1 MHz,

RSET = 10 kΩ (IOUT = 4 mA), RBW = 1 kHz

FREQUENCY (MHz)

MAGNITUDE (dB)

024681012141618

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

03277-023

Figure 4. Dual-Sideband Spectral Plot, fC = 5 MHz, f = 1 MHz,

RSET = 4 kΩ (IOUT = 10 mA), RBW = 1 kHz

FREQUENCY (MHz)

MAGNITUDE (dB)

55 57 59 61 63 65 67 69 70 73

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

03277-024

Figure 5. Dual-Sideband Spectral Plot, fC = 65 MHz,

f = 1 MHz, RSET = 10 kΩ (IOUT = 4 mA), RBW = 1 kHz

FREQUENCY (MHz)

MAGNITUDE (dB)

55 57 59 61 63 65 67 69 71 73

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

03277-025

Figure 6. Dual-Sideband Spectral Plot, fC = 65 MHz, f = 1 MHz,

RSET = 4 kΩ (IOUT = 10 mA), RBW = 1 kHz

FREQUENCY (MHz)

MAGNITUDE (dB)

0 20406080100

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

120

03277-026

Figure 7. Single Sideband @ 65 MHz, fC = 66 MHz,

f = 1 MHz, RSET = 10 kΩ (IOUT = 4 mA), RBW = 2 kHz

FREQUENCY (MHz)

MAGNITUDE (dB)

0 20406080100

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

120

03277-027

Figure 8. Single Sideband @ 65 MHz, fC = 66 MHz,

f = 1 MHz, RSET = 4 kΩ (IOUT = 10 mA), RBW = 2 kHz

AD9878

Rev. A | Page 11 of 36

FREQUENCY (MHz)

MAGNITUDE (dB)

0 20406080100

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

120

03277-028

Figure 9. Single Sideband @ 42 MHz, fC = 43 MHz,

f = 1 MHz, RSET = 10 kΩ (IOUT = 4 mA), RBW = 2 kHz

FREQUENCY (MHz)

MAGNITUDE (dB)

0 20406080100

–90

–80

–70

–60

–50

–40

–30

–20

–10

120

03277-029

Figure 10. Single Sideband @ 42 MHz, fC = 43 MHz,

f = 1 MHz, RSET = 4 kΩ (IOUT = 10 mA), RBW = 2 kHz

FREQUENCY (MHz)

MAGNITUDE (dB)

0 20406080100

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

120

03277-030

Figure 11. Single Sideband @ 5 MHz, fC = 6 MHz,

f = 1 MHz, RSET = 10 kΩ (IOUT = 4 mA), RBW = 2 kHz

FREQUENCY (MHz)

MAGNITUDE (dB)

0 20406080100

–90

–80

–70

–60

–50

–40

–30

–20

–10

120

03277-031

Figure 12. Single Sideband @ 5 MHz, fC = 6 MHz,

f = 1 MHz, RSET = 4 kΩ (IOUT = 10 mA), RBW = 2 kHz

FREQUENCY (MHz)

MAGNITUDE (dB)

–2.5 –2.0 –1.5 –1.0 –0.5 0 0.5 1.0 1.5 2.0

–90

–80

–70

–60

–50

–40

–30

–20

–10

2.5

03277-032

Figure 13. Single Sideband @ 65 MHz, fC = 66 MHz,

f = 1 MHz, RSET = 10 kΩ (IOUT = 4 mA), RBW = 500 Hz

FREQUENCY (MHz)

MAGNITUDE (dB)

–2.5 –2.0 –1.5 –1.0 –0.5 0 0.5 1.0 1.5 2.0

–90

–80

–70

–60

–50

–40

–30

–20

–10

2.5

03277-033

Figure 14. Single Sideband @ 65 MHz, fC = 66 MHz,

f = 1 MHz, RSET = 4 kΩ (IOUT = 10 mA), RBW = 500 Hz

AD9878

Rev. A | Page 12 of 36

FREQUENCY (MHz)

MAGNITUDE (dB)

–50 –40 –30 –20 –10 0 10 20 30 40

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

03277-034

Figure 15. Single Sideband @ 65 MHz, fC = 66 MHz,

f = 1 MHz, RSET = 10 kΩ (IOUT = 4 mA), RBW = 50 Hz

MAGNITUDE (dB)

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

FREQUENCY (MHz)

–2.5 –2.0 –1.5 –1.0 –0.5 0 0.5 1.0 1.5 2.0 2.5

03277-035

Figure 16. Single Sideband @ 65 MHz, fC = 66 MHz,

f = 1 MHz, RSET = 10 kΩ (IOUT = 4 mA), RBW = 10 Hz

MAGNITUDE (dB)

–80

–70

–60

–50

–40

–30

–20

–10

FREQUENCY (MHz)

0 5 10 15 20 25 30 35 40 45 50

03277-036

Figure 17. 16-QAM @ 42 MHz Spectral Plot, RBW = 1 kHz

MAGNITUDE (dB)

–80

–70

–60

–50

–40

–30

–20

–10

FREQUENCY (MHz)

0 5 10 15 20 25 30 35 40 45 50

03277-037

Figure 18. 16-QAM @ 5 MHz Spectral Plot, RBW = 1 kHz

AD9878

Rev. A | Page 13 of 36

TERMINOLOGY

Differential Nonlinearity Error (DNL, No Missing Codes)

An ideal converter exhibits code transitions that are exactly 1 LSB

apart. DNL is the deviation from this ideal value. No missing

codes indicates that all of the ADC codes must be present over

all operating ranges.

Integral Nonlinearity Error (INL)

Linearity error refers to the deviation of each individual code from

a line drawn from negative full scale through positive full scale.

The point used as negative full scale occurs ½ LSB before the first

code transition. Positive full scale is defined as a level 1½ LSB

beyond the last code transition. The deviation is measured from

the middle of each code to the true straight line.

Phase Noise

Single-sideband, phase-noise power is specified relative to the

carrier (dBc/Hz) at a given frequency offset (1 kHz) from the

carrier. Phase noise can be measured directly in single-tone

transmit mode with a spectrum analyzer that supports noise

marker measurements. It detects the relative power between

the carrier and the offset (1 kHz) sideband noise and takes

the resolution bandwidth (RBW) into account by subtracting

10 × log(RBW). It also adds a correction factor that compensates

for the implementation of the resolution bandwidth, log display,

and detector characteristic.

Output Compliance Range

The range of allowable voltage at the output of a current-output

DAC. Operation beyond the maximum compliance limits can

cause either output stage saturation or breakdown, resulting in

nonlinear performance.

Spurious-Free Dynamic Range (SFDR)

The difference, in dB, between the rms amplitude of the DAC

output signal (or ADC input signal) and the peak spurious signal

over the specified bandwidth (Nyquist bandwidth, unless

otherwise noted).

Pipeline Delay (Latency)

The number of clock cycles between conversion initiation and

the associated output data being made available.

Offset Error

The first code transition should occur at an analog value ½ LSB

above negative full scale. Offset error is defined as the deviation

of the actual transition from that point.

Gain Error

The first code transition should occur at an analog value ½ LSB

above negative full scale. The last transition should occur for an

analog value 1½ LSB below the nominal full scale. Gain error

is the deviation of the actual difference between first and last

code transitions and the ideal difference between first and last

code transitions.

Aperture Delay

The aperture delay is a measure of the sample-and-hold amplifier

(SHA) performance that specifies the time delay between the

rising edge of the sampling clock input and when the input

signal is held for conversion.

Aperture Jitter

Aperture jitter is the variation in aperture delay for successive

samples and is manifested as noise on the input to the ADC.

Input Referred Noise

The rms output noise is measured using histogram techniques.

The standard deviation of the ADC output codes is calculated

in LSB, and converted to an equivalent voltage. This results in a

noise figure that can be directly referred to the input of the MxFE.

Signal-to-Noise and Distortion (SINAD) Ratio

SINAD is the ratio of the rms value of the measured input signal

to the rms sum of other spectral components below the Nyquist

frequency, including harmonics, but excluding dc. The value for

SINAD is expressed in decibels.

Effective Number of Bits (ENOB)

For a sine wave, SINAD can be expressed in terms of the number

of bits. Using the following formula, it is possible to get a measure

of performance expressed as N, the effective number of bits:

(

)

02.6dB76.1

−

SINADN

Thus, the effective number of bits for a device for sine wave

inputs at a given input frequency can be calculated directly

from its measured SINAD.

Signal-to-Noise Ratio (SNR)

SNR is the ratio of the rms value of the measured input signal

to the rms sum of other spectral components below the Nyquist

frequency, excluding harmonics and dc. The value for SNR is

expressed in decibels.

Total Harmonic Distortion (THD)

THD is the ratio of the rms sum of the first six harmonic

components to the rms value of the measured input signal.

It is expressed as a percentage, or in decibels.

Power Supply Rejection

Power supply rejection specifies the converter’s maximum full-

scale change when the supplies are varied from nominal to

minimum or maximum specified voltages.

Channel-to-Channel Isolation (Crosstalk)

In an ideal multichannel system, the signal in one channel does

not influence the signal level of another channel. The channel-

to-channel isolation specification is a measure of the change

that occurs in a grounded channel as a full-scale signal is

applied to another channel.

AD9878

Rev. A | Page 14 of 36

Table 4. Register Map

Address

(Hex) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Default

(Hex) Type

0x00 SDIO

bidirectional

LSB

first

Reset OSCIN multiplier M[4:0] 0x08 Read/write

0x01 PLL lock

detect MCLK divider R[5:0] 0x00 Read/write

0x02 Power down

PLL

Power

down

DAC

Power

down

digital

Power

down

ADC12A

Power down

ADC12B

Power

down

ADC10

Power

down

reference

ADC12A

Power

down

reference

ADC12B

0x00 Read/write

0x03

Video

input

into

ADC12B

Flag 2

Flag 1 Flag 0

enable

0x00 Read/write

0x04 MSB/Flag 0 ∑-∆ output control word [7:0] 0x00 Read/write

0x05

0x00 Read/write

0x06

0x00 Read only

0x07 Video input

enable

Clamp level for video input [6:0] 0x00 Read/write

0x08 ADC clocked

directly from

OSCIN

Rx port

fast

edge

rate

Power

down

RxSYNC

generator

Power down

reference

ADC10

Send

ADC12A

data only

Send

ADC12B

data only

0x80 Read/write

0x09

0x00 Read/write

0x0A

0x00 Read/write

0x0B

0x00 Read/write

0x0C Version [3:0] 0x00 Read/write

0x0D

Tx frequency tuning word

profile 1 LSB [1:0]

Tx frequency tuning

word profile 0 LSBs [1:0]

0x00 Read/write

0x0E DAC fine gain control [3:0] 0x00 Read/write

0x0F Tx path

select

Profile 1

Tx path

AD8321/AD8323

gain control

mode

path

bypass

sinc–1

filter

Tx path

spectral

inversion

Tx path

transmit

single

tone

0x00 Read/write

0x10 Tx Path Frequency Tuning Word Profile 0 [9:2] 0x00 Read/write

0x11 Tx Path Frequency Tuning Word Profile 0 [17:10] 0x00 Read/write

0x12 Tx Path Frequency Tuning Word Profile 0 [25:18] 0x00 Read/write

0x13 Cable-driver amplifier,

Coarse Gain Control Profile 0 [7:4]

Cable-driver amplifier,

Fine Gain Control Profile 0 [3:0]

0x00 Read/write

0x14 Tx Path Frequency Tuning Word Profile 1 [9:2] 0x00 Read/write

0x15 Tx Path Frequency Tuning Word Profile 1 [17:10] 0x00 Read/write

0x16 Tx Path Frequency Tuning Word Profile 1 [25:18] 0x00 Read/write

0x17 Cable-driver amplifier,

Coarse Gain Control Profile 1 [7:4]

Cable-driver amplifier,

Fine Gain Control Profile 1 [3:0]

0x00 Read/write

AD9878

Rev. A | Page 15 of 36

Bits 0 to 4: OSCIN Multiplier

This register field is used to program the on-chip clock

multiplier that generates the chip’s high frequency system clock,

fSYSCLK. For example, to multiply the external crystal clock fOSCIN

by 16, program Register 0x00, Bits 4:0, to 0x10. The default

clock multiplier value, M, is 0x08. Valid entries range from 1 to

31. When M is set to 1, the PLL is disabled and internal clocks

are derived directly from OSCIN. The PLL requires 200 MCLK

cycles to regain frequency lock after a change in M. After the

recapture time of the PLL, the frequency of fSYSCLK is stable.

Bit 5: Reset

Writing 1 to this bit resets the registers to their default values

and restarts the chip. The reset bit always reads back 0. The bits

in Register 0x00 are not affected by this software reset. However,

a low level at the RESET pin forces all registers, including all

bits in Register 0x00, to their default states.

Bit 6: LSB First

Active high indicates SPI serial port access of instruction byte and

data registers is LSB first. Default low indicates MSB-first format.

Bit 7: SDIO Bidirectional

Active high configures the serial port as a 3-signal port with

the SDIO pin used as a bidirectional input/output pin. Default

low indicates that the serial port uses four signals with SDIO

configured as an input and SDO configured as an output.

Bits [5:0]: MCLK Divider

This register determines the output clock on the REFCLK pin.

At default 0 (R = 0), REFCLK provides a buffered version of the

OSCIN clock signal for other chips. The register can also be used

to divide the chip’s master clock fMCLK by R, where R is an integer

between 2 and 63. The generated reference clock on REFCLK pin

can be used for external frequency controlled devices.

Bit 7: PLL Lock Detect

When this bit is set low, the REFCLK pin functions in its

default mode and provides an output clock with frequency

fMCKL/R, as described above. If this bit is set to 1, the REFCLK pin

is configured to indicate whether the PLL is locked to fOSCIN. In

this mode, the REFCLK pin should be low-pass filtered with an

RC filter of 1.0 kΩ and 0.1 µF. A low output on REFCLK indicates

that the PLL has achieved lock with fOSCIN.

Unused sections of the chip can be powered down when the

corresponding bits are set high. This register has a default value

of 0x00, all sections active.

Bit 0: Power Down ADC12B Voltage Reference

Active high powers down the voltage reference circuit

for ADC12B.

Bit 1: Power Down ADC12A Voltage Reference

Active high powers down the voltage reference circuit for

the ADC12A.

Bit 2: Power Down ADC10

Active high powers down the 10-bit ADC.

Bit 3: Power Down ADC12B

Active high powers down the ADC12B.

Bit 4: Power Down ADC12A

Active high powers down the ADC12A.

Bit 5: Power Down Tx

Active high powers down the digital transmit section of the

chip, similar to the function of the PWRDN pin.

Bit 6: Power Down DAC Tx

Active high powers down the DAC.

Bit 7: Power Down PLL

Active high powers down the OSCIN multiplier.

Bit 0: Flag 0 Enable

When this bit is active high, the SIGDELT pin maintains a fixed

logic level determined directly by the MSB of the ∑-∆ control

word of Register 0x04.

Bit 1: Flag 1

The logic level of this bit is applied at the FLAG1 pin.

Bit 4: Flag 2

The logic level of this bit is applied at the FLAG2 pin.

Bit 5: Video Input into ADC12B

If the video input is enabled, setting this bit high sends the

signal applied to the VIDEO IN pin to the ADC12B. Otherwise,

the signal applied to the VIDEO IN pin is sent to the ADC12A.

Bits [7:0]: ∑-∆ Control Word

The ∑-∆ control word is 8 bits wide and controls the duty cycle

of the digital output on the SIGDELT pin. Changes to the ∑-∆

control word take effect immediately for every register write.

∑-∆ output control words have a default value of 0. The control

words are in straight binary format, with 0x00 corresponding to

the bottom of scale or 0% duty cycle, and 0xFF corresponding

to the top of scale or near 100% duty cycle.

Bit 7: Flag 0 (∑-∆ Control Word MSB)

When the Flag 0 enable bit (Register 0x03, Bit 0) is set, the logic

level of this bit appears on the output of the SIGDELT pin.

AD9878

Rev. A | Page 16 of 36

Bits [6:0]: Clamp Level Control Value

The 7-bit clamp-level control value is used to set an offset to the

automatic clamp-level control loop. The actual ADC output has a

clamp-level offset equal to 16 times the clamp level control value.

(

)

16-- xValueControlLevelClampOffsetLevelClamp =

The default value for the clamp-level control value is 0x20. This

results in an ADC output clamp-level offset of 512 LSBs. The

valid programming range for the clamp-level control value is

0x16 to 0x127.

Bit 7: Video Input Enable

This bit enables the video input. In default with Bit 7 = 0, both

IF12 ADCs are connected to IF inputs. If the video input is

enabled by setting bit 7 = 1, the video input will be connected to

the IF12 ADC selected by REG 0x03, Bit 6.

Bit 0: Send ADC12B Data Only

When this bit is set high, the device enters a nonmultiplexed

mode, and only the data from the ADC12B is sent to the

IF[11:0] digital output port.

Bit 1: Send ADC12A Data Only

When this bit is set high, the device enters a nonmultiplexed

mode, and only the data from the ADC12A is sent to the

IF[11:0] digital output port.

If both the send ADC12B data only and send ADC12A data

only register bits are set high, the device sends both ADC12A

and ADC12B data in the default multiplexed mode.

Bit 3: Power Down ADC10 Voltage Reference

Active high powers down the voltage reference circuit for

the ADC10.

Bit 4: Power Down RxSYNC Generator

Setting this bit to 1 powers down the 10-bit ADC’s sampling

clock and makes the RxSYNC output pin stay low. It can be

used for additional power saving on top of the power-down

selections in Register 0x02.

Bit 5: Rx PORT Fast Edge Rate

Setting this bit to 1 increases the output drive strength of all digital

output pins, except MCLK, REFCLK, SIGDELT, and

FLAG[2:1]. These pins always have high output drive capability.

Bit 7: ADC Clocked Directly from OSCIN

When set high, the ADC sampling clock is derived directly from

the input clock at OSCIN. In this mode, the clock supplied to the

OSCIN pin should originate from an external crystal or low jitter

crystal oscillator. When this bit is low, the ADC sampling clock

is derived from the internal PLL and the frequency of the clock

is equal to fOSCIN × M/8.

Bits [3:0]: Version

The die version of the chip can be read from this register.

LSBs

This register accommodates the 2 LSBs for each frequency tuning

word (FTW). See the Registers 0x10 Through 0x17—

Burst Parameter section.

This register allows the user to program the DAC gain if the

Tx Gain Control Select Bit 3 in Register 0x0F is set to 0.

Table 5. DAC Gain Control

Bits [3:0] DAC Gain (dB)

0000 0.0 (default)

0001 0.5

0010 1.0

0011 1.5

… …

1110 7.0

1111 7.5

Bit 0: Single Tone Tx Mode

Active high configures the AD9878 for single-tone applications

(e.g., FSK). The AD9878 supplies a single frequency output, as

determined by the FTW selected by the active profile. In this

mode, the TxIQ input data pins are ignored, but should be tied

to a valid logic voltage level. Default value is 0x00 (inactive).

Bit 1: Spectral Inversion Tx

When set to 1, inverted modulation is performed:

(

)

(

)

[

]

.sincos_ tQtIOUTMODULATOR

+ω

Default is Logic 0, noninverted modulation:

()

(

)

[

]

.sincos_ tQtIOUTMODULATOR

−ω

Bit 2: Bypass Inv Sinc Tx Filter

Active high configures the AD9878 to bypass the sin(x)/x com-

pensation filter. Default value is 0x00 (inverse sinc filter enabled).

Bit 3: CA Interface Mode Select

This bit changes the format of the AD9878 3-wire CA interface to

a format in which the AD9878 digitally interfaces to external

variable gain amplifiers. This is accomplished by changing

the interpretation of the bits in Register 0x13, Register 0x17,

Control section for more detail.

AD9878

Rev. A | Page 17 of 36

Setting this bit to 0 (default) configures the serial interface to be

compatible with AD8321/AD8323/AD8328 variable cable gain

amplifiers. Setting this bit to 1 configures the serial interface to be

compatible with AD8322/AD8327 variable cable gain amplifiers.

Bit 5: Profile Select

The AD9878 quadrature digital upconverter can store two

preconfigured modulation modes, called profiles. Each profile

defines a transmit FTW, cable-driver amplifier gain setting, and

DAC gain setting. The profile select bit or PROFILE pin programs

the current register profile to be used. If the PROFILE pin is used

to switch between profiles, the profile select bit should be set to 0

and tied low.

REGISTERS 0x10 THROUGH 0x17—

BURST PARAMETER

Tx Frequency Tuning Words

The FTW determines the DDS-generated carrier frequency (fC)

and is formed via a concatenation of register addresses.

The 26-bit FTW is spread over four register addresses. Bit 25 is

the MSB, and Bit 0 is the LSB. The carrier frequency equation is

as follows:

()

SYSCLKC fFTWf ×=

Where 2000x0and, <×= FTWfMf OSCINSYSCLK .

Changes to FTW bytes take effect immediately.

Cable-Driver Gain Control

The AD9878 has a 3-pin interface to the AD832x family of

programmable gain cable-driver amplifiers. This allows direct

control of the cable driver’s gain through the AD9878. In its

default mode, the complete 8-bit register value is transmitted

over the 3-wire cable amplifier (CA) interface.

If Bit 3 of Register 0x0F is set high, Bits [7:4] of Register 0x13

and Register 0x17 determine the 8-bit word sent over the CA

interface, according to the specifications in Table 6. Bits [3:0] of

of the DAC output, according to specifications in Table 7.

Table 6. Cable-Driver Gain Control

Bits [7:4] CA Interface Transmit Word

0000 0000 0000 (default)

0001 0000 0001

0010 0000 0010

0011 0000 0100

0100 0000 1000

0101 0001 0000

0110 0010 0000

0111 0100 0000

1000 1000 0000

Table 7. DAC Output Fine Gain Setting

Bits [3:0] DAC Fine Gain (dB)

0000 0.0 (default)

0001 0.5

0010 1.0

0011 1.5

… …

1110 7.0

1111 7.5

New data is automatically sent over the 3-wire CA interface

(and DAC gain adjust) whenever the value of the active gain

control register changes or a new profile is selected. The default

value is 0x00 (lowest gain).

The formula for the combined output-level calculation of

AD9878 fine gain and AD8327 or AD8322 coarse gain is:

()

(

)

()

192

09878

8327 −+

coarsefineVV

()

(

)

(

)

142

09878

8322 −+

coarsefineVV

where:

fine is the decimal value of Bits [3:0].

coarse is the decimal value of Bits [7:4].

V9878(0) is the level at AD9878 output in dBmV for fine = 0.

V8327 is the level at output of AD8327 in dBmV.

V8322 is the level at output of AD8322 in dBmV.

AD9878

Rev. A | Page 18 of 36

SERIAL INTERFACE FOR REGISTER CONTROL

The AD9878 serial port is a flexible, synchronous, serial

communications port that allows easy interface to many

industry-standard microcontrollers and microprocessors.

The interface allows read/write access to all registers that

configure the AD9878. Single or multiple byte transfers are

supported. Also, the interface can be programmed to read words

either MSB first or LSB first. The AD9878 serial interface port

I/O can be configured to have one bidirectional I/O (SDIO)

pin, or two unidirectional I/O (SDIO/SDO) pins.

GENERAL OPERATION OF THE SERIAL INTERFACE

There are two phases of a communication cycle with the AD9878.

Phase 1 is the instruction cycle, which is the writing of an in-

struction byte into the AD9878, coincident with the first eight

SCLK rising edges. The instruction byte provides the AD9878

serial port controller with information regarding the data transfer

cycle, which is Phase 2 of the communication cycle.

The Phase 1 instruction byte defines whether the upcoming data

transfer is a read or write, the number of bytes in the data transfer,

and the starting register address for the first byte of the data

transfer. The first eight SCLK rising edges of each communication

cycle are used to write the instruction byte into the AD9878.

The eight remaining SCLK edges are for Phase 2 of the commu-

nication cycle. Phase 2 is the actual data transfer between the

AD9878 and the system controller. Phase 2 of the communication

cycle is a transfer of one to four data bytes, as determined by the

instruction byte. Normally, using one multibyte transfer is the

preferred method. However, single-byte data transfers are useful

to reduce CPU overhead when register access requires only one

byte. Registers change immediately upon writing to the last bit

of each transfer byte.

INSTRUCTION BYTE

The R/W bit of the instruction byte determines whether a read

or a write data transfer occurs after the instruction byte write.

Logic high indicates a read operation; logic low indicates a write

operation. The [N1:N0] bits determine the number of bytes to

be transferred during the data transfer cycle. The bit decodes

are shown in Table 9. The timing diagrams are shown in Figure 19

and Figure 20.

Table 8. Instruction Byte Information

MSB 17 16 15 14 13 12 11 LSB 10

R/W N1 N0 A4 A3 A2 A1 A0

Table 9. Bit Decodes

N1 N0 Description

0 0 Transfer 1 byte

0 1 Transfer 2 bytes

1 0 Transfer 3 bytes

1 1 Transfer 4 bytes

Bits [A4:A0] determine which register is accessed during the

data transfer portion of the communication cycle. For multi-

byte transfers, this address is the starting byte address. The

remaining register addresses are generated by the AD9878.

03277-005

SCLK

INSTRUCTION BIT 7 INSTRUCTION BIT 6

SCLK

PWL

PWH

SDIO

Figure 19. Timing Diagram for Register Write

03277-006

SCLK

SDIO

SDO

DATA BIT N DATA BIT N

Figure 20. Timing Diagram for Register Read

SERIAL INTERFACE PORT PIN DESCRIPTIONS

SCLK—Serial Clock. The serial clock pin is used to synchronize

data transfers from the AD9878 and to run the serial port state

machine. The maximum SCLK frequency is 15 MHz. Input data

to the AD9878 is sampled up on the rising edge of SCLK. Output

data changes upon the falling edge of SCLK.

CS—Chip Select. Active low input starts and gates a commu-

nication cycle. It allows multiple devices to share a common

serial port bus. The SDO and SDIO pins go into a high impedance

state when CS is high. Chip select should stay low during the

entire communication cycle.

SDIO—Serial Data I/O. Data is always written into the AD9878

on this pin. However, this pin can be used as a bidirectional

data line. The configuration of this pin is controlled by Bit 7 of

pin as unidirectional.

SDO—Serial Data Out. Data is read from this pin for protocols

that use separate lines for transmitting and receiving data. In

the case where the AD9878 operates in a single bidirectional

I/O mode, this pin does not output data and is set to a high

impedance state.

AD9878

Rev. A | Page 19 of 36

MSB/LSB TRANSFERS

The AD9878 serial port can support either MSB-first or LSB-first

data formats. This functionality is controlled by the LSB-first bit

in Register 0x00.

The AD9878 default serial port mode is MSB-first (see Figure 21),

which is programmed by setting Register 0x00 low. In MSB-first

mode, the instruction byte and data bytes must be written from

the MSB to the LSB. In MSB-first mode, the serial port internal

byte address generator decrements for each byte of the multibyte

communication cycle. When decrementing from 0x00, the

address generator changes to 0x1F.

When the LSB-first bit in Register 0x00 is set active high, the

AD9878 serial port is in LSB-first format (Figure 22). In LSB-

first mode, the instruction byte and data bytes must be written

from the LSB to the MSB. In LSB-first mode, the serial port

internal byte address generator increments for each byte of the

multibyte communication cycle. When incrementing from

0x1F, the address generator changes to 0x00.

R/W N1 N0 A4 A3 A2 A1 A0 D7nD6nD20D10D00

D7nD6nD20D10D00

SCLK

INSTRUCTION CYCLE DATA TRANSFER CYCLE

SDIO

SDO

03277-003

Figure 21. Serial Register Interface Timing, MSB-First Mode

D00D10D20D6nD7n

SCLK

INSTRUCTION CYCLE DATA TRANSFER CYCLE

SDIO

SDO

A0 A1 A2 A3 A4 N0 N1 R/W D00D10D20D6nD7n

03277-004

Figure 22. Serial Register Interface Timing, LSB-First Mode

NOTES ON SERIAL PORT OPERATION

The AD9878 serial port configuration bits reside in Bit 6 and

Bit 7 of Register Address 0x00. Note that the configuration

changes immediately upon writing to the last bit of the register.

For multibyte transfers, writing to this register might occur

during a communication cycle. Measures must be taken to

compensate for this new configuration for the remaining bytes of

the current communication cycle.

The same considerations apply when setting the reset bit in

values, but the software reset does not affect the bits in Register

Address 0x00. It is recommended to use only single-byte transfers

when changing serial port configurations or initiating a software

reset. A write to Bit 1, Bit 2, and Bit 3 of Address 0x00 with the

same logic levels as Bit 7, Bit 6, and Bit 5 (bit pattern: XY1001YX

binary) allows the user to reprogram a lost serial port config-

uration and to reset the registers to their default values. A

second write to Address 0x00, with the reset bit low and the

serial port configuration as specified above (XY), reprograms

the OSCIN multiplier setting. A changed fSYSCLK frequency is

stable after a maximum of 200 fMCLK cycles (wake-up time).

AD9878

Rev. A | Page 20 of 36

THEORY OF OPERATION

For a general understanding of the AD9878, refer to Figure 23, a

block diagram of the device architecture. The device consists of a

transmit path, receive path, and auxiliary functions, such as a PLL,

a ∑-∆ DAC, a serial control port, and a cable amplifier interface.

The transmit path contains an interpolation filter, a complete

quadrature digital upconverter, an inverse sinc filter, and a 12-bit

current output DAC.

The receive path contains a 10-bit ADC and dual 12-bit ADCs.

All internally required clocks and an output system clock are

generated by the PLL from a single crystal or clock input.

The 12-bit and 10-bit IF ADCs can convert direct IF inputs of

up to 70 MHz and run at sample rates of up to 29 MSPS. A video

input with an adjustable signal clamping level, along with the

10-bit ADC, allow the AD9878 to process an NTSC and a QAM

channel simultaneously.

The programmable ∑-∆ DAC can be used to control external

components, such as variable gain amplifiers (VGAs) or voltage-

controlled tuners. The CA port provides an interface to the

AD832x family of programmable gain amplifier (PGA) cable

drivers, enabling host processor control via the MxFE serial

port (SPORT).

03277-007

TxIQ[5:0]

TxSYNC

MCLK

REFCLK

CA PORT

PROFILE

SDIO

IF10[4:0]

RxSYNC

IF12[11:0]

FSADJ

XTAL

OSCIN

Σ-∆ OUTPUT

FLAG[2:1]

IF10 INPUT

IF12B INPUT

VIDEO IN

AD9878

DATA

ASSEMBLER

QUADRATURE

MODULATOR

FIR LPF CIC LPF

COS

SIN

DAC GAIN CONTROL

PLL

OSCIN ×M

DDS

MUX

INTERFACE

PROFILE

SELECT

SERIAL

INTERFACE

SINC

–1

MUX DAC

IF10

IF12

ADC

Rx PORT

Tx OUTPUT

Σ-∆INPUT

FLAG0

SINC

–1

BYPASS

(

OSCIN

)

(

OSCIN

)

(

MCLK

)

MUX

12 ADC MUX IF12A INPUT

DAC

+–

CLAMP LEVEL

Σ-∆

÷R

÷8

÷2

(

IQCLK

)

(

SYSCLK

)

(

OSCIN

)

÷4÷4

Figure 23. AD9878 Block Diagram

AD9878

Rev. A | Page 21 of 36

MCLK

TxSYNC

TxIQ

TxI[11:6] TxI[5:0] TxQ[11:6] TxQ[5:0] TxI[11:6] TxI[5:0] TxQ[11:6] TxQ[5:0] TxI[11:6] TxI[5:0]

03277-008

Figure 24. Tx Timing Diagram

TRANSMIT PATH

The transmit path contains an interpolation filter, a complete

quadrature digital upconverter, an inverse sinc filter, and a 12-bit

current output DAC. The maximum output current of the DAC is

set by an external resistor. The Tx output PGA provides additional

transmit signal level control. The transmit path interpolation

filter provides an upsampling factor of 16 with an output signal

bandwidth as high as 4.35 MHz for <1 dB droop. Carrier

frequencies up to 65 MHz with 26 bits of frequency tuning

resolution can be generated by the direct digital synthesizer

(DDS). The transmit DAC resolution is 12 bits, and it can run at

sampling rates of up to 232 MSPS. Analog output scaling from

0 dB to 7.5 dB in 0.5 dB steps is available to preserve SNR when

reduced output levels are required.

DATA ASSEMBLER

The AD9878 data path operates on two 12-bit words, the I and Q

components, that form a complex symbol. The data assembler

builds the 24-bit complex symbol from four consecutive 6-bit

words read over the TxIQ [5:0] bus. These words are strobed

into the data assembler synchronous to the master clock (MCLK).

A high level on TxSYNC signals the start of a transmit symbol.

The first two 6-bit words of the symbol form the I component;

the second two 6-bit words form the Q component. Symbol

components are assumed to be in twos complement format. The

timing of the interface is fully described in the Transmit Timing

section. The I/Q sample rate fIQCLK puts a bandwidth limit on the

maximum transmit spectrum. This is the familiar Nyquist limit

(hereafter referred to as fNYQ) and is equal to half fIQCLK.

TRANSMIT TIMING

The AD9878 has a master clock and expects 6-bit, multiplexed

TxIQ data upon each rising edge (see Figure 24). Transmit

symbols are framed with the TxSYNC input. TxSYNC high

indicates the start of a transmit symbol. Four consecutive 6-bit

data packages form a symbol (I MSB, I LSB, Q MSB, and Q LSB).

INTERPOLATION FILTER

Once through the data assembler, the IQ data streams are fed

through a 4× FIR low-pass filter and a 4× cascaded integrator

comb (CIC) low-pass filter. The combination of these two filters

results in the sample rate increasing by a factor of 16. In addition

to the sample rate increase, the half-band filters provide the

low-pass filtering characteristics necessary to suppress the spectral

images between the original sampling frequency and the new

(16× higher) sampling frequency.

HALF-BAND FILTERS (HBFs)

HBF 1 and HBF 2 are both interpolating filters, each of which

doubles the sampling rate. Together, HBF 1 and HBF 2 have

26 taps and increase the sampling rate by a factor of 4

(4 × fIQCLK or 8 × fNYQ).

In relation to phase response, both HBFs are linear phase filters.

As such, virtually no phase distortion is introduced within the pass

band of the filters. This is an important feature, because phase dis-

tortion is generally intolerable in a data transmission system.

CASCADE INTEGRATOR COMB (CIC) FILTER

The CIC filter is configured as a programmable interpolator

and provides a sample rate increase by a factor of 4. The

frequency response of the CIC filter is given by:

()

π2

4π2

πsin

π4sin

⎥

⎦

⎤

⎢

⎣

⎡⎟

⎠

⎞

⎜

⎝

⎛

⎥

⎦

⎤

⎢

⎣

⎡

−

⎟

⎠

⎞

⎜

⎝

⎛

−

fH fj

COMBINED FILTER RESPONSE

The combined frequency response of the HBF and CIC filters

limits the input signal bandwidth that can be propagated through

the AD9878.The usable bandwidth of the filter chain limits the

maximum data rate that can be propagated through the AD9878.

A look at the pass-band detail of the combined filter response

(Figure 25) indicates that to maintain an amplitude error of

1 dB or less, signal bandwidth is restricted to about 60% or less

of fNYQ.

Max BW (1dB droop) = 0.60 * fMCLK/8

Thus, in order to keep the bandwidth of the data in the flat

portion of the filter pass band, the user must oversample the

baseband data by at least a factor of two prior to presenting it to

the AD9878. Note that without oversampling, the Nyquist

bandwidth of the baseband data corresponds to fNYQ. As such,

the upper end of the data bandwidth suffers 6 dB or more of

attenuation due to the frequency response of the digital filters.

Furthermore, if the baseband data applied to the AD9878 has

AD9878

Rev. A | Page 22 of 36

been pulse shaped, there is an additional concern. Typically,

pulse shaping is applied to the baseband data via a filter with a

raised cosine response. In such cases, an α value is used to modify

the bandwidth of the data, where the value of α is such that

.10 <α<

A value of 0 causes the data bandwidth to correspond to the

Nyquist bandwidth. A value of 1 causes the data bandwidth to

be extended to twice the Nyquist bandwidth. Thus, with 2× over-

sampling of the baseband data and α = 1, the Nyquist bandwidth

of the data corresponds with the I/Q Nyquist bandwidth. As stated

earlier, this results in problems near the upper edge of the data

bandwidth due to the frequency response of the filters. The

maximum value of α that can be implemented is 0.45, because the

data bandwidth becomes

(

)

NYQNYQ ff 725.0121 =α+

which puts the data bandwidth at the extreme edge of the flat

portion of the filter response.

If a particular application requires an α value between 0.45 and 1,

the user must oversample the baseband data by at least a factor of

4. Over the frequency range of the data to be transmitted, the

combined HBF 1, HBF 2, and CIC filters introduce a worst-case

droop of less than 0.2 dB.

FREQUENCY RELATIVE TO I/Q NYQ BW

MAGNITUDE (dB)

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

–6

–5

–4

–3

–2

–1

1.0

03277-009

Figure 25. Cascaded Filter Pass Band

DIGITAL UPCONVERTER

The digital quadrature modulator stage following the CIC filters

is used to frequency shift (upconvert) the baseband spectrum of

the incoming data stream to the desired carrier frequency. The

carrier frequency is controlled numerically by a direct digital

synthesizer (DDS). The DDS uses the internal system clock

(fSYSCLK) to generate the desired carrier frequency with a high

degree of precision. The carrier is applied to the I and Q

multipliers in a quadrature fashion (90° phase offset) and

summed to yield a data stream that is the modulated carrier. The

modulated carrier becomes the 12-bit sample sent to the DAC.

Tx SIGNAL LEVEL CONSIDERATIONS

The quadrature modulator itself introduces a maximum gain of

3 dB in signal level. To visualize this, assume that both the I and

Q data are fixed at the maximum possible digital value, x. Then,

the output of the modulator, z, is

(

)

(

)

[

]

txtxz

−

sincos

03277-010

Figure 26. 16-Quadrature Modulation

It can be shown that |z| assumes a maximum value of

22 xxxz =+= (a gain of +3 dB). However, if the

same number of bits represent |z| and x, an overflow occurs.

To prevent this, an effective −3 dB attenuation is internally

implemented on the I and Q data path:

xz =+= 2121

The following example assumes a peak rms level of 10 dB:

LSBs2000dB2.0LSBs2047 ±=−±

ValueInputComponentSymbolMaximum

()

rmsLSBs1265dBdB6LSBs2000 =−±

rmsPeak

ValueRMSInputComplexMaximum

The maximum complex input rms value calculation uses both

I and Q symbol components that add a factor of two (6 dB)

to the formula. Table 10 shows typical I-Q input test signals

with amplitude levels related to 12-bit full scale (FS).

Table 10. I-Q Input Test Signals

Analog

Output Digital Input Input Level

Modulator

Output Level

Single Tone I = cos(f) FS − 0.2 dB FS − 3.0 dB

(fC − f) Q = cos(f + 90°)

= −sin(f)

FS − 0.2 dB

Single Tone I = cos(f) FS − 0.2 dB FS − 3.0 dB

(fC + f) Q = cos(f + 270°)

= +sin(f)

FS − 0.2 dB

Dual Tone I = cos(f)

FS − 0.2 dBFS

FS − 0.2 dB FS

(fC ± f) Q = cos(f + 180°)

= −cos(f) or

Q = +cos(f)

FS − 0.2 dB

AD9878

Rev. A | Page 23 of 36

Tx THROUGHPUT AND LATENCY

Data inputs affect the output fairly quickly, but remain effective

due to the AD9878 filter characteristics. Data transmit latency

through the AD9878 is easiest to describe in terms of fSYSCLK clock

cycles (4 × fMCLK). The numbers provided indicate the number of

fSYSCLK cycles before the AD9878 output responds to a change in

the input.

Latency of I/Q data from the time it enters the data assembler

(AD9878 input) to the time of DAC output is 119 fSYSCLK clock

cycles (29.75 fMCLK cycles). DC values applied to the data assembler

input take up to 176 fSYSCLK clock cycles (44 fMCLK cycles) to

propagate and settle at the DAC output.

Frequency hopping is accomplished via changing the PROFILE

input pin. The time required to switch from one frequency to

another is less than 232 fSYSCLK cycles (58.5 fMCLK cycles).

DAC

A 12-bit digital-to-analog converter (DAC) is used to convert the

digitally processed waveform into an analog signal. The worst-

case spurious signals due to the DAC are the harmonics of the

fundamental signal and their aliases (see the Analog Devices

DDS tutorial at www.analog.com/dds). The conversion process

produces aliased components of the fundamental signal at

(

)

.3,2,1=±× nffn CARRIERSYSCLK These are typically filtered

with an external RLC filter at the DAC output. It is important

for this analog filter to have a sufficiently flat gain and linear

phase response across the bandwidth of interest to avoid

modulation impairments. A relatively inexpensive seventh-

order, elliptical, low-pass filter is sufficient to suppress the

aliased components for HFC network applications.

The AD9878 provides true and complement current outputs. The

full-scale output current is set by the RSET resistor at Pin 49 and

the DAC gain register. Assuming maximum DAC gain, the value

of RSET for a full-scale IOUT is determined using the equation:

OUTOUTDACRSETSET IIVR 4.3932 ==

For example, if a full-scale output current of 20 mA is desired,

then RSET = (39.4/0.02), or approximately 2 kΩ.

The following equation calculates the full-scale output current,

including the programmable DAC gain control:

()

205.05.7

104.39 GAIN

SETOUT RI +−

×=

where NGAIN is the value of DAC fine gain control [3:0].

The full-scale output current range of the AD9878 is 4 to

20 mA. Full-scale output currents outside this range degrade

SFDR performance. SFDR is also slightly affected by output

matching—that is, the two outputs should be terminated equally

for best SFDR performance. The output load should be located

as close as possible to the AD9878 package to minimize stray

capacitance and inductance. The load can be a simple resistor to

ground, an op amp current-to-voltage converter, or a transformer-

coupled circuit. It is best not to directly drive a highly reactive

load, such as an LC filter. Driving an LC filter without a

transformer requires that the filter be doubly terminated for

best performance—that is, both the filter input and output should

be resistively terminated with the appropriate values. The parallel

combination of the two terminations determines the load that

the AD9878 sees for signals within the filter pass band. For

example, a 50 Ω terminated input/output low-pass filter looks

like a 25 Ω load to the AD9878. The output compliance voltage

of the AD9878 is −0.5 V to +1.5 V. Any signal developed at the

DAC output should not exceed 1.5 V; otherwise, signal distortion

results. Furthermore, the signal can extend below ground as much

as 0.5 V without damage or signal distortion. The AD9878 true

and complement outputs can be differentially combined for

common-mode rejection using a broadband 1:1 transformer.

Using a grounded center tap results in signals at the AD9878 DAC

output pins that are symmetrical about ground. As previously

mentioned, by differentially combining the two signals, the user

can provide some degree of common-mode signal rejection.

A differential combiner can consist of a transformer or an

op amp. The object is to combine or amplify the difference

between only two signals and to reject any common—usually

undesirable—characteristics, such as 60 Hz hum or clock

feedthrough, that is equally present on both signals.

AD832x

AD9878

VARIABLE GAIN

CABLE DRIVER

AMPLIFIER

DAC 75Ω

LOW-PASS

FILTER

CA_EN

CA_DATA

CA_CLK

03277-011

Figure 27. Cable Amplifier Connection

Connecting the AD9878 true and complement outputs to the

differential inputs of the programmable gain cable drivers

AD8321/AD8323 or AD8322/AD8327 (see Figure 27)

provides an optimized solution for the standard compliant

cable modem upstream channel. The cable driver’s gain

can be programmed through a direct 3-wire interface

using the AD9878 profile registers.

PROGRAMMING THE AD8321/AD8323 OR

AD8322/AD8327/AD8238 CABLE-DRIVER

AMPLIFIERS

Users can program the gain of the AD832x family of cable-driver

amplifiers via the AD9878 cable amplifier control interface. Two

(one per profile) 8-bit registers within the AD9878 store the gain

value to be written to the serial 3-wire port. Typically, either the

AD8321/AD8323 or AD8322/AD8327 variable gain cable

amplifiers are connected to the chip’s 3-wire cable amplifier

AD9878

Rev. A | Page 24 of 36

interface. The Tx gain control select bit in Register 0x0F changes

the interpretation of the bits in Register 0x13, Register 0x17,

Cable-Driver Gain Control section.

CA_EN

CA_CLK

A_DAT

MSB

MCLK

LSB

03277-012

Figure 28. Cable Amplifier Interface Timing

Data transfers to the programmable gain cable-driver amplifier

are initiated by the following conditions:

• Power-Up and Hardware Reset: Upon initial power-up and

every hardware reset, the AD9878 clears the contents of the

gain control registers to 0, which defines the lowest gain

setting of the AD832x. Thus, the AD9878 writes all 0s out

of the 3-wire cable amplifier control interface.

• Software Reset: Writing a 1 to Bit 5 of Address 0x00 initiates

a software reset. Upon a software reset, the AD9878 clears

the contents of the gain control registers to 0 for the lowest

gain and sets the profile select to 0. The AD9878 writes all 0s

out of the 3-wire cable amplifier control interface if the

gain is previously on a different setting (different from 0).

• Change in Profile Selection: The AD9878 samples the

PROFILE input pin together with the two profile select bits

and writes to the AD832x gain control registers when a

change in profile and gain is determined. The data written

to the cable-driver amplifier comes from the AD9878 gain

control register associated with the current profile.

• Write to the AD9878 Cable-Driver Amplifier Control

Registers: The AD9878 writes gain control data associated

with the current profile to the AD832x when the selected

AD9878 cable-driver amplifier gain setting is changed. Once

a new, stable gain value is detected (48 to 64 MCLK cycles

after initiation) a data write starts with CA_EN going low.

The AD9878 always finishes a write sequence to the cable-

driver amplifier once it is started. The logic controlling data

transfers to the cable-driver amplifier uses up to

200 MCLK cycles and is designed to prevent erroneous

write cycles from occurring.

OSCIN CLOCK MULTIPLIER

The AD9878 can accept either an input clock into the OSCIN

pin or a fundamental-mode crystal across the OSCIN and

XTAL pins as the device’s main clock source. The internal PLL

then generates the fSYSCLK signal from which all other internal

signals are derived. The DAC uses fSYSCLK as its sampling clock.

For DDS applications, the carrier is typically limited to about

30% of fSYSCLK. For a 65 MHz carrier, the system clock required is

above 216 MHz. The OSCIN multiplier function maintains

clock integrity, as evidenced by the part’s excellent phase noise

characteristics and low clock-related spur in the output spectrum.

External loop filter components, consisting of a series resistor

(1.3 kΩ) and capacitor (0.01 µF), provide the compensation

zero for the OSCIN multiplier PLL loop. The overall loop

performance is optimized for these component values.

CLOCK AND OSCILLATOR CIRCUITRY

The AD9878’s internal oscillator generates all sampling clocks

from a simple, low cost, parallel resonance, fundamental fre-

quency quartz crystal. Figure 29 shows how the quartz crystal is

connected between OSCIN (Pin 61) and XTAL (Pin 60) with

parallel resonant load capacitors, as specified by the crystal

manufacturer. The internal oscillator circuitry can also be

overdriven by a TTL-level clock applied to OSCIN with

XTAL left unconnected.

Mff MCLKOSCIN

An internal PLL generates the DAC sampling frequency, fSYSCLK,

by multiplying the OSCIN frequency by M. The MCLK signal

(Pin 23), fMCLK, is derived by dividing fSYSCLK by 4.

Mff OSCINSYSCLK

4Mff OSCINMCLK

An external PLL loop filter (Pin 57), consisting of a series resistor

and ceramic capacitor (Figure 29: R1 = 1.3 kΩ, C12 = 0.01 µF),

is required for stability of the PLL. Also, a shield surrounding

these components is recommended to minimize external noise

coupling into the PLL’s voltage-controlled oscillator input (guard

trace connected to AVDDPLL).

Figure 23 shows that ADCs are either sampled directly by a

low jitter clock at OSCIN or by a clock that is derived from the

PLL output. Operating modes can be selected in Register 0x08.

Sampling the ADCs directly with the OSCIN clock requires that

MCLK is programmed to be twice the OSCIN frequency.

PROGRAMMABLE CLOCK OUTPUT REFCLK

The AD9878 provides an auxiliary output clock on Pin 69,

REFCLK. The value of the MCLK divider bit field, R, determines

its output frequency, as shown in the following equations:

63to2for, =

RRff MCLKREFCLK

0for,

Rff OSCINREFCLK

In its default setting (0x00 in Register 0x01), the REFCLK pin

provides a buffered output of fOSCIN.

AD9878

Rev. A | Page 25 of 36

03277-013

C10

20pF

C11

20pF

C12

0.01µF

GUARD TRACE

1.3kΩ

C13

0.1µFR

SET

4.02Ω

0.1µFC6

0.1µF

CP2

10µF

0.1µFC3

0.1µF

CP1

10µF

0.1µFC3

0.1µF

CP1

10µF

100

99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77

AVDD

AGND

VIDEO IN

AGND

IF12A+

IF12A–

AGND

AVDD

REFT12A

REFB12A

AVDD

AGND

IF12B+

IF12B–

AGND

AVDD

REFT12B

REFB12B

AVDD

AGND

AVDD10

AGND10

IF10+

IF10–

AGND

REFT10

REFB10

AGND10

AVDD10

DRVDD

DRGND

REFCLK

SIGDELT

FLAG1

FLAG2

CA_EN

CA_DATA

CA_CLK

DVDDOSC

OSCIN

XTAL

DGNDOSC

AGNDPLL

PLLFILT

AVDDPLL

DVDDPLL

DGNDPLL

AVDDTx

Tx+

Tx–

TxSYNC

(MSB) TxIQ(5)

TxIQ(4)

TxIQ(3)

TxIQ(2)

TxIQ(1)

TxIQ(0)

DVDD

DGND

DVDD

DGND

PROFILE

RESET

DVDD

DGND

SCLK

SDIO

SDO

DGNDTx

DVDDTx

PWRDN

REFIO

FSADJ

AGNDTx

DRGND

DRVDD

(MSB) IF12(11)

IF12(10)

IF12(9)

IF12(8)

IF12(7)

IF12(6)

IF12(5)

IF12(4)

IF12(3)

IF12(2)

IF12(1)

IF12(0)

(MSB) IF10(4)

IF10(3)

IF10(2)

IF10(1)

IF10(0)

RxSYNC

DRGND

DRVDD

MCLK

DVDD

DGND

AD9878

TOP VIEW

(Not to Scale)

Figure 29. Basic Connection Diagram

AD9878

Rev. A | Page 26 of 36

POWER-UP SEQUENCE

Upon initial power-up, the RESET pin should be held low until the

power supply is stable (see Figure 30). Once RESET is deasserted,

the AD9878 can be programmed over the serial port. The on-

chip PLL requires a maximum of 1 ms after the rising edge of

RESET or a change of the multiplier factor (M) to completely

settle. It is recommended that the PWRDN pin is held low during

the reset and PLL settling time. Changes to ADC clock select

(Register 0x08) or System Clock Divider N (Register 0x01) should

be programmed before the rising edge of PWRDN. Once the PLL

is frequency locked and after the PWRDN pin is brought high,

transmit data can be sent reliably. If the PWRDN pin cannot be

held low throughout the reset and PLL settling time period,

the power-down digital Tx bit, or the PWRDN pin, should be

pulsed after the PLL has settled. This ensures correct transmit

filter initialization.

03277-014

1ms MIN.

5MCLK MIN.

RESET

PWRDN

Figure 30. Power-Up Sequence for Tx Data Path

RESET

To initiate a hardware reset, the RESET pin should be held low

for at least 100 ns. All internally generated clocks, except REFCLK,

stop during reset. The rising edge of RESET resets the PLL clock

multiplier and reinitializes the programmable registers to their

default values. The same sequence as described in the Power-Up

Sequence section should be followed after a reset or change in M.

A software reset (writing 1 into Bit 5 of Register 0x00) is func-

tionally equivalent to a hardware reset, but does not force

TRANSMIT POWER-DOWN

A low level on the PWRDN pin stops all clocks linked to the

digital transmit data path and resets the CIC filter. Deasserting

PWRDN reactivates all clocks. The CIC filter is held in a reset

state for 80 MCLK cycles after the rising edge of PWRDN to

allow for flushing of the half-band filters with new input data.

Transmit data bursts should be padded with at least 20 symbols

of null data directly before the PWRDN pin is deasserted.

Immediately after the PWRDN pin is deasserted, the transmit

burst should start with a minimum of 20 null data symbols (see

Figure 31). This avoids unintended DAC output samples caused

by the transmit path latency and filter settling time.

Software power-down digital Tx (Bit 5 in Register 0x02) is func-

tionally equivalent to the hardware PWRDN pin and takes effect

immediately after the last register bit is written over the serial port.

PWRDN

TxIQ

TxSYNC

20 NULL SYMBOLS DATA SYMBOLS 20 NULL SYMBOLS

00 0 0 00 00

5MCLK MIN.

03277-015

Figure 31. Timing Sequence to Flush Tx Data Path

AD9878

Rev. A | Page 27 of 36

∑-∆ OUTPUTS

An on-chip ∑-∆ output provides a digital logic bit stream with

an average duty cycle that varies between 0% and (255/256)%,

depending on the programmed code, as shown in Figure 32.

00h

8 t

MCLK

01h

02h

80h

FFh

256 ×8 t

MCLK

8 t

MCLK

256 ×8 t

MCLK

03277-016

Figure 32. ∑-∆ Output Signals

This bit stream can be low-pass filtered to generate a

programmable dc voltage of

(

)

[

]

DC VVCodeV +×∆∑= 256-

where:

V6.0

−= DRVDDH VV

V4.0

In cable set-top box applications, the output can be used to

control external variable gain amplifiers or RF tuners. A

single-pole, RC, low-pass filter provides sufficient filtering

(see Figure 33). In more demanding applications, where

additional gain, level-shift, or drive capability is required,

consider using a first- or second-order filter (see Figure 34).

AD9878

MCLK

DAC

CONTROL

WORD

TYPICAL: R = 50kΩ

C = 0.01µF

–3dB

= 1/(2πRC) = 318Hz

÷8

Σ-∆RDC (V

TO V

)

03277-017

Figure 33. ∑-∆ RC Filter

03277-018

AD9878

SIGMA-DELTA

Σ-∆

OUT

OFFSET

OP250

TYPICAL: R = 50kΩ

C = 0.01µF

–3dB

= 1/(2πRC) = 318Hz

OUT

= (V

+ V

OFFSET

) (1 + R/R1)/2

Figure 34. ∑-∆ Active Filter with Gain and Offset

RECEIVE PATH (Rx)

The AD9878 includes three high speed, high performance ADCs.

The 10-bit and dual 12-bit direct-IF ADCs deliver excellent under-

sampling performance with input frequencies as high as 70 MHz.

The sampling rate can be as high as 29 MSPS. The ADC sampling

frequency can be derived directly from the OSCIN signal, or from

the on-chip OSCIN multiplier. For highest dynamic performance,

choose an OSCIN frequency that can be directly used as the

ADC sampling clock. Digital 12-bit ADC outputs are multiplexed

to one 12-bit bus, clocked by a frequency (fMCLK) four times the

sampling rate. The IF ADCs use a multiplexer to a 12-bit interface

with an output word rate of fMCLK.

IF10 AND IF12 ADC OPERATION

The IF10 and IF12 ADCs have a common architecture and

share several characteristics from an applications standpoint.

Most of the information in the following section is applicable to

both IF ADCs; differences, where they exist, are highlighted.

Input Signal Range and Digital Output Codes

The IF ADCs have differential analog inputs labeled IF+ and IF−.

The signal input, VAIN, is the voltage difference between the two

input pins, VAIN = VIF+ − VIF−. The full-scale input voltage range is

determined by the internal reference voltages, REFT and REFB,

which define the top and bottom of the scale. The peak input

voltage to the ADC is the difference between REFT and REFB,

which is 1 V p-p. This results in an ADC full-scale input voltage

of 2 VPPD. The digital output codes are straight binary and are

shown in Table 11.

Table 11. Digital Output Codes

IF12[11:0] Input Signal Voltage

111…111 VAIN ≥ +1.0 V

111…111 VAIN = +1.0 V − 1 LSB

111…110 VAIN = +1.0 V − 2 LSB

… …

100…001 VAIN = 0 V + 1 LSB

100…000 VAIN = 0.0 V

011…111 VAIN = 0 V − 1 LSB

… …

000…001 VAIN = −1.0 V + 2 LSB

000…000 VAIN = −1.0 V

000…000 VAIN < −1.0 V

AD9878

Rev. A | Page 28 of 36

Driving the Input

The IF ADCs have differential switched capacitor sample-and-

hold amplifier (SHA) inputs. The nominal differential input

impedance is 4.0 kΩ||3 pF. This impedance can be used as the

effective termination impedance when calculating filter transfer

characteristics and voltage signal attenuation from nonzero source

impedances. For best performance, additional requirements must

be met by the signal source. The SHA has input capacitors that

must be recharged each time the input is sampled. This results in

a dynamic input current at the device input, and demands that

the source has low (<50 Ω) output impedance at frequencies up

to the ADC sampling frequency. Also, the source must have

settling of better than 0.1% in less than half the ADC clock period.

Another consideration for getting the best performance from the

ADC inputs is the dc biasing of the input signal. Ideally, the signal

should be biased to a dc level equal to the midpoint of the ADC

reference voltages, REFT12 and REFB12. Nominally, this level is

1.2 V. When ac-coupled, the ADC inputs self-bias to this voltage

and require no additional input circuitry. Figure 35 illustrates a

recommended circuit that eases the burden on the signal source

by isolating its output from the ADC input. The 33 Ω series

termination resistors isolate the amplifier outputs from any

capacitive load, which typically improves settling time. The series

capacitors provide ac signal coupling, which ensures that the

ADC inputs operate at the optimal dc-bias voltage. The shunt

capacitor sources the dynamic currents required to charge the

SHA input capacitors, removing this requirement from the ADC

buffer. The values of CC and CS should be calculated to

determine the correct HPF and LPF corner frequencies.

AIN+

AIN–

33ΩC

33Ω

03277-019

Figure 35. Simple ADC Drive Configuration

Receive Timing

The AD9878 sends multiplexed data to the IF10 and IF12 outputs

upon every rising edge of MCLK. RxSYNC frames the start of

each IF10 data symbol. The 10-bit and 12-bit ADCs are read

completely upon every second MCLK cycle. RxSYNC is high

for every second 10-bit ADC data if the 10-bit ADC is not in

power-down mode. The Rx timing diagram is shown in Figure 36.

REFCLK

MCLK

IF10 DATA IF10[9:5] IF10[4:0] IF10[9:5] IF10[4:0]

M/N = 2

IF10[9:5] IF10[4:0]

IF12A IF12B IF12B IF12B IF12A IF12B

RxSYNC

IF12 DATA

Rx PORT TIMING (DEFAULT MODE: MUXED IF12 ADC DATA)

M/N = 2

REFCLK

IF12A OR IF12B IF12A OR IF12B

IF10[9:5] IF10[4:0] IF10[9:5] IF10[4:0] IF10[9:5] IF10[4:0]

IF12A OR IF12B

MCLK

IF10 DATA

RxSYNC

IF DATA

Rx PORT TIMING (OUTPUT DATA FROM ONLY ONE IF12 ADC)

03277-020

Figure 36. Rx Port Timing

AD9878

Rev. A | Page 29 of 36

ADC VOLTAGE REFERENCES

The AD9878 has three independent internal references for its

10-bit and 12-bit ADCs. Both 12-bit and 10-bit ADCs are

designed for 2 V p-p input voltages and have their own internal

reference. Figure 29 shows the proper connections of the REFT

and REFB reference pins. External references might be necessary

for systems that require high accuracy gain matching between

ADCs, or for improvements in temperature drift and noise

characteristics. External references REFT and REFB must be

centered at AVDD/2, with offset voltages as specified by the

following equations:

V5.02:12,10 +−− AVDDREFT

V5.02:12,10 −−− AVDDREFT

A differential level of 1 V between the reference pins results in a

2 V p-p ADC input level AIN. Internal reference sources can be

powered down when external references are used (Address 0x02).

VIDEO INPUT

For sampling video-type waveforms, such as NTSC and PAL

signals, the video input channel provides black-level clamping.

Figure 37 shows the circuit configuration for using the video

channel input (Pin 98). An external blocking capacitor is used

with the on-chip video clamp circuit to level-shift the input signal

to a desired reference point. The clamp circuit automatically

senses the most negative portion of the input signal and adjusts

the voltage across the input capacitor. This forces the black level

of the input signal to be equal to the value programmed in the

clamp level register (Register Address 0x07).

By default, the video input is disabled and disconnected from

both ADCs. By setting Register 0x07, Bit 7 = 1, the video input

is enabled and connected to the ADC input as determined by

the state of Reg 0x03, Bit 6 ( 0= ADC12A connected, 1 =

ADC12B connected.)

2mA

VIDEO INPUT

0.1µF

CLAMP LEVEL + FS/2

CLAMP LEVEL

AD9878

OFFSET

BUFFER

+– DAC

ADC

LPF

CLAMP

LEVEL

03277-021

Figure 37. Video Clamp Circuit Input

AD9878

Rev. A | Page 30 of 36

PCB DESIGN CONSIDERATIONS

Although the AD9878 is a mixed-signal device, the part should be

treated as an analog component. The on-chip digital circuitry is

designed to minimize the impact of digital switching noise on the

operation of the analog circuits. Following the recommendations

in this section helps achieve the best performance from the MxFE.

COMPONENT PLACEMENT

The following guidelines for component placement are

recommended to achieve optimal performance:

• Manage the path of return currents to ensure that high

frequency switching currents from the digital circuits do not

flow into the ground plane under the MxFE or analog circuits.

• Keep noisy digital signal paths and sensitive receive signal

paths as short as possible.

• Keep digital (noise-generating) and analog (noise-susceptible)

circuits as far apart as possible.

To best manage the return currents, pure digital circuits that

generate high switching currents should be closest to the power

supply entry. This keeps the highest frequency return current

paths short and prevents them from traveling over the sensitive

MxFE and analog portions of the ground plane. Also, these

circuits should be generously bypassed at each device to further

reduce high frequency ground currents. The MxFE should be

placed adjacent to the digital circuits, such that the ground return

currents from the digital sections do not flow into the ground

plane under the MxFE. The analog circuits should be placed

furthest from the power supply. The AD9878 has several pins that

are used to decouple sensitive internal nodes: REFIO, REFB12A,

REFT12A, REFB12B, REFT12B, REFB10, and REFT10. The

decoupling capacitors connected to these points should have low

ESR and ESL, be placed as close as possible to the MxFE, and be

connected directly to the analog ground plane. The resistor

connected to the FSADJ pin and the RC network connected to

the PLLFILT pin should also be placed close to the device and

connected directly to the analog ground plane.

POWER PLANES AND DECOUPLING

The AD9878 evaluation board (Figure 38 and Figure 39)

demonstrates a good power supply distribution and decoupling

strategy. The board has four layers: two signal layers, one ground

plane, and one power plane. The power plane is split into a 3-VDD

section that is used for the 3 V digital logic circuits, a DVDD

section that is used to supply the digital supply pins of the

AD9878, an AVDD section that is used to supply the analog

supply pins of the AD9878, and a VANLG section that supplies

the higher voltage analog components on the board. The 3-VDD

section typically has the highest frequency currents on the power

plane and should be kept the furthest from the MxFE and analog

sections of the board.

The DVDD portion of the plane carries the current used to power

the digital portion of the MxFE to the device. This should be

treated similarly to the 3-VDD power plane and be kept from going

underneath the MxFE or analog components. The MxFE should

largely sit above the AVDD portion of the power plane. The

AVDD and DVDD power planes can be fed from the same low

noise voltage source; however, they should be decoupled from

each other to prevent the noise generated in the DVDD portion

of the MxFE from corrupting the AVDD supply. This can be done

by using ferrite beads between the voltage source and DVDD, and

between the source and AVDD. Both DVDD and AVDD should

have a low ESR, bulk-decoupling capacitor on the MxFE side of

the ferrite as well as low ESR- and ESL-decoupling capacitors on

each supply pin (for example, the AD9878 requires 17 power

supply decoupling capacitors). The decoupling capacitors should

be placed as close as possible to the MxFE supply pins. An

example of proper decoupling is shown in the AD9878 evaluation

board’s two-page schematic (Figure 38 and Figure 39).

GROUND PLANES

In general, if the component placing guidelines discussed earlier

can be implemented, it is best to have at least one continuous

ground plane for the entire board. All ground connections should

be as short as possible. This results in the lowest impedance return

paths and the quietest ground connections. If the components

cannot be placed in a manner that keeps the high frequency

ground currents from traversing under the MxFE and analog

components, it might be necessary to put current-steering

channels into the ground plane to route the high frequency

currents around these sensitive areas. These current-steering

channels should be used only when and where necessary.

SIGNAL ROUTING

The digital Rx and Tx signal paths should be as short as possible.

Also, these traces should have a controlled impedance of about

50 Ω. This prevents poor signal integrity and the high currents

that can occur during undershoot or overshoot caused by ringing.

If the signal traces cannot be kept shorter than about 1.5 inches,

then series termination resistors (33 Ω to 47 Ω) should be placed

close to all signal sources. It is a good idea to series terminate all

clock signals at their source, regardless of trace length. The receive

signals are the most sensitive signals on the evaluation board.

Careful routing of these signals is essential for good receive path

performance. The IF+/IF− signals form a differential pair and

should be routed together. By keeping the traces adjacent to each

other, noise coupled onto the signals appears as common mode

and is largely rejected by the MxFE receive input. Keeping the

driving point impedance of the receive signal low and placing

any low-pass filtering of the signals close to the MxFE further

reduces the possibility of noise corrupting these signals.

AD9878

Rev. A | Page 31 of 36

AGND1

AGND10

AGND10-A

AGND2

AGND3

AGND4

AGND5

AGND6

AGND7

AGNDPLL

AVDD1

AVDD10

AVDD10-A

AVDD2

AVDD3

AVDD4

AVDD5

AVDDPLL

AVDDTx

CA_CLK

CA_DATA

DGNDOSC

DGNDPLL

DRGND

DRVDD

DVDDOSC

DVDDPLL

FLAG1

FLAG2

IF10B+

IF10B–

IF12A+

IF12A–

IF12B+

IF12B–

OSCIN

PLLFILT

REFB10

REFCLK

REFB12B

REFB12A

REFT12A

REFT12B

REFT10

SIGDELT

Tx–

Tx+

VIDEO IN

CA_EN

XTAL

OSCIN

XTAL

100

DGND1

DGND2

DGND3

DGND4

DGNDTx

DVDD1

DVDD2

DVDD3

DVDD4

DVDDTx

FSADJ

IF0

IF1

IF10

IF2

IF3

IF4

IF5

IF6

IF7

IF8

IF9

IFB0

IFB1

IFB2

IFB3

MCLK

PROFILE

REFIO

RxSYNC

SCLK

SDIO

SDO

TxIQ0

TxIQ1

TxIQ2

TxIQ3

TxIQ5

TxSYNC

PWRDN

RESET

DRVDD1

IF11

IF0

IF1

IF10

IF2

IF3

IF4

IF5

IF6

IF7

IF8

IF9

IF11

DRGND1

TxIQ4

IFB4

IFB0

IFB1

IFB2

IFB3

IFB4

AGNDTx

DRGND2

DRVDD2

CS SCLK

SDIO

SDO

AD9878LQFP

TxIQ1

TxIQ2

TxIQ3

TxIQ5

TxSYNC

TxIQ0

PROFILE1

TxIQ4

HEADER RA RIBBON

DIGITAL TRANSMIT

RIBBON

RP1

RCOM1

R23R34R45R56R67R78R89R910

JP9

R29

10kΩ

DRVDD PWRDN

RC0805

DRVDD

RxSYNC

AVDD

DRVDD

CA_CLK

AVDDTx

DVDDPLL/

DVDDOSC

CA_DATA

CA_EN

FLAG2

FLAG1

SIGDELT0

REFCLK

MCLK

DVDD

PWRDN

DVDDTx

IFB[0:4]

IF[0:11]

SDO, SDIO, CS, SCLK

R10

10kΩ

RC0805

C21

0.1µF

CC0603

C22

0.1µF

CC0603

SW1

RESET

AGND; 5

RESET RESET

ADM1818-10ART

VCC

GND C1

0.1µF

CC0603

DRVDD

5V AD8328

AD8328

GND1

GND2

–

GND3

DATAEN

SDATA

CLKGND4

SLEEP

BYP

OUT

–

OUT

RAMP

TxEN

GND5 GND

20 1

19 2

18 3

17 4

16 5

15 6

14 7

13 8

12 9

11 10

5V AD8328

CA_DATA

CA_CLK

CA_SLEEP

C117

0.1µF

CC0603

C115

0.1µF

CC0603

C72

0.1µF

CC0603

C116

0.1µF

CC0603

R28

1kΩ

RC0603

TOKOB5F

Tx_OUT

AD8328

AGND; 3, 4, 5

SMAEDGE

R39

43.3Ω

RC0605

R40

86.6Ω

RC0605

CA_EN

L16

220

LC1210

L15

220

LC1210

L13

220

LC1210

L14

220

LC1210

C20

18pF

CC0805

C57

33pF

CC0805

C58

18pF

CC0805

R38

75Ω

RC0805

R36

75Ω

RC0805

R37

59Ω

RC0805

C114

0.01µF

CC0603

C113

0.01µF

CC0603

JP8

JP7

AD8328

TRANSF

Tx+

Tx–

DIP06RCUP

Tx_OUT

AGND; 3, 4, 5

SMAEDGE

T1 R11

37.5Ω

RC0605

R12

37.5Ω

RC0605

C23

0.1µF

CC0603

C24

0.1µF

CC0603

0.1µF

CC0603

0.1µF

CC0603

0.1µF

CC0603

10µF

10V

BCASE

0.1µF

CC0603

0.1µF

CC0603

0.1µF

CC0603

10µF

10V

BCASE

C11

0.1µF

CC0603

C13

0.1µF

CC0603

C12

0.1µF

CC0603

C14

10µF

16V

BCASE

TP2

WHT

TP4

WHT

TP1

WHT

TP5

WHT

TP6

WHT

TP15

WHT

TP3

WHT

C15

0.01µF

CC0603

100kΩ

RC0805

DIP06RCUP

J13

IF12B

AGND; 3, 4, 5

SMAEDGE

R27

49.9Ω

RC0805

JP26

AD8138

8138–

VCML

R25

33Ω

RC0805

C102

0.1µF

CC0603

JP25 TRANSF

TRANSF

JP24

AD8138

8138+

R26

33Ω

RC0805

C101

0.1µF

CC0603

C98

20pF

CC0805

IF12B+

IF12B–

DIP06RCUP

J13

IF10

AGND; 3, 4, 5

SMAEDGE

R33

49.9Ω

RC0805

JP32

AD8138

8138–

VCML

R32

33Ω

RC0805

C112

0.1µF

CC0603

JP31 TRANSF

TRANSF

JP30

AD8138

8138+

R31

33Ω

RC0805

C111

0.1µF

CC0603

C108

20pF

CC0805

IF10+

IF10–

33Ω

RC0805

C10

0.1µF

CC0603

75Ω

RC07CUP

VIDEO IN

AGND; 3, 4, 5

SMAEDGE

AD8138

+IN

–IN

VEE

VCC

VO– VOC

VO+

J12

AD8138

AGND; 3, 4, 5

SMAEDGE

R24

49.9Ω

RC0805

R23

523Ω

RC0805

R18

499Ω

RC0805

R22

499Ω

RC0805

R21

33Ω

RC0805

R17

499Ω

RC0805

R14

33Ω

RC0805

A_BUFF+

8138–

A_BUFF–

C96

10µF

16V +C97

0.1µF

CC0805

BCASE

DIP06RCUP

J11

IF12A

AGND; 3, 4, 5

SMAEDGE

R20

49.9Ω

RC0805

JP23

AD8138

VCML

R19

33Ω

RC0805

C94

0.1µF

CC0603

JP21 TRANSF

TRANSF

JP22

AD8138

R13

33Ω

RC0805

C86

0.1µF

CC0603

C92

20pF

CC0805

IF12A+

IF12A–

C95

47pF

CC1206

C88

47pF

CC1206

C87

0.1µF

CC0805

R15

10kΩ

RC0805

R16

5.11kΩ

RC0805

JP4

VCML

8138+

C69

0.1µFC66

0.1µF

CC0603CC0603

C16

0.01µF

CC0603

1.3kΩ

RC0805

OSCIN_CLK

AGND; 3, 4, 5

SMA200UP

VAL

C19

0.1µF

CC0805

49.9Ω

RC0805

500Ω

RC0805

POT1

10kΩ

500Ω

RC0805

AGND; 3

V_CLK; 5

U13

NC7SZ04

33Ω

RC0805

V_CLK

C84

0.1µF

CC0805

C110

0.1µF

CC0805

BCASE

C83

10µF

16V

DUTY

CYCLE

OSCIN

XTAL

EXT_CLK

JP1

C18

18pF

CC0805

C17

18pF

CC0805

03277-038

+C90

0.1µF

CC0805

BCASE

C91

10µF

16V

Figure 38. Evaluation PCB Schematic

AD9878

Rev. A | Page 32 of 36

C60

10µF

16V

BCASE

C63

0.1µF

CC0805

VALL8

3.3V_ANA

TP16

CLR

AVDDPLL

C89

10µF

16V

BCASE

C93

0.1µF

CC0805

VALL17 TP20

CLR

V_CLK

LC1210

C59

10µF

16V

BCASE

C62

0.1µF

CC0805

C85

0.1µF

CC0603

C76

0.1µF

CC0603

C74

0.1µF

CC0603

C71

0.1µF

CC0603

C68

0.1µF

CC0603

C65

0.1µF

AVDD

CC0603

VALL7

LC1210

TP18

CLR

LC1210

C78

10µF

16V

BCASE

C81

0.1µF

CC0805

VALL11

ABUFF–

TP14

CLR

A_BUFF–

LC1210

C77

10µF

16V

BCASE

C80

0.1µF

CC0805

VALL10

ABUFF+

TP12

CLR

A_BUFF+

LC1210

C79

10µF

16V

BCASE

C82

0.1µF

CC0805

VALL12 TP13

CLR

5V_AD8328

LC1210

C61

10µF

16V

BCASE

C70

0.1µF

CC0603

C73

0.1µF

CC0603

C75

0.1µF

CC0805

AVDDTx

C64

0.1µF

CC0805

C67

0.1µF

CC0603

VAL

LC1210

TP17

CLR

C25

10µF

16V

BCASE

C28

0.1µF

CC0805

C31

0.1µF

CC0603

C34

0.1µF

CC0603

C37

0.1µF

CC0603

DVDD

VALL1

LC1210

TP19

CLR

C26

10µF

16V

BCASE

C29

0.1µF

CC0805

C32

0.1µF

CC0603

C35

0.1µF

CC0603

C38

0.1µF

CC0603

C39

0.1µF

CC0603

DRVDD

VALL2

LC1210

TP7

CLR

C42

10µF

16V

BCASE

C45

0.1µF

CC0805

C56

0.1µF

CC0603

C54

0.1µF

CC0605

C51

0.1µF

CC0805

C48

0.1µF

CC0605

3.3V_BUFF

VALL6

LC1210

TP10

CLR

C40

10µF

16V

BCASE

C43

0.1µF

CC0805

C52

0.1µF

CC0603

C49

0.1µF

CC0603

C46

0.1µF

CC0605

DVDDPLL/

DVDDOSC

VALL4

LC1210

TP8

CLR

C27

10µF

16V

BCASE

C30

0.1µF

CC0805

C33

0.1µF

CC0603

C36

0.1µF

CC0603

DVDDTx

VALL3

LC1210

TP9

CLR

C41

10µF

16V

BCASE

C44

0.1µF

CC0805

C47

0.1µF

CC0603

C50

0.1µF

CC0603

C55

0.1µF

CC0603

C53

0.1µF

CC0603

C100

0.1µF

CC0603

5V_BUFF

VALL5

LC1210

TP11

CLR

TB13.3V_ANA 1

TB1GND 2

TB1–5V_ANA 3

TB1GND 4

TB1+5V_ANA 5

TB1GND 6

TB15V_DIG 7

TB13.3V_DIG 8

POWER

5V 3.3V_DIG

JP2

AD8328

JP5

INVERT CLK

JP6

DEL_CLK

GND1

GND2 GND3

VCCB

VCCA

T/R

GND1

GND2 GND3

NCT/R

VCCA VCCB

GND1

GND2 GND3

VCCB

VCCA

T/R

GND1

GND2 GND3

NCT/R

VCCA VCCB

MCLK

RxSYNC

DEL_CLK

IFB[0:4]

3.3V_BUFF

5V_BUFF SDO

12 13

124

12 13

241

1312

SDOPC

SDIO

SCLK

IF2

IF3

IF1

IF4

IF5

IF6

IF7

IF8

IF9

IF10

IF11

IF[0:11]

107

116

125

134

143

152

161

RP3 22

107

116

125

134

143

152

161

RP2 22

161

152

143

134

125

116

107

RP4 22

74LVXC3245

TSSOP24

74LVXC3245

TSSOP24

74LVXC3245

TSSOP24

74LVXC3245

TSSOP24

107

116

125

134

143

152

161

RP6 22

107

116

125

134

143

152

161

RP5 22

RP7 22

NC7SZ04

AGND; 3

5V_BUFF; 5

IFB4

IF0

JP13

RJ45

9101112

PC PARALLEL PORT

DCN2 5 RPT

910

11 12

13 14

15 16

17 18

19 20

21 22

23 24

25 26

27 28

29 30

31 32

33 34

35 36

37 38

39 40

DIGITAL RECEIVE

SCS

SSCLK

SSDIO

SDOPC

JP3

DVDD

R34

1kΩ

RC0603

CA_SLEEP

DEL_CLK

100Ω

RC0603

R35

33Ω

MCLK

AGND; 3, 4, 5

SMAEDGE

RC0603

RIBBON

HDR040RA

03277-039

Figure 39. Evaluation PCB Schematic (Continued)

AD9878

Rev. A | Page 33 of 36

03277-040

Figure 40. Evaluation PCB—Top Assembly

03277-041

Figure 41. Evaluation PCB—Bottom Assembly

AD9878

Rev. A | Page 34 of 36

03277-042

Figure 42. Evaluation PCB Layout—Top Layer

03277-043

Figure 43. Evaluation PCB Layout—Bottom Layer

AD9878

Rev. A | Page 35 of 36

03277-044

Figure 44. Evaluation PCB—Power Plane

03277-045

Figure 45. Evaluation PCB—Ground Plane

AD9878

Rev. A | Page 36 of 36

OUTLINE DIMENSIONS

COMPLIANT TO JEDEC STANDARDS MS-026BED

TOP VIEW

(PINS DOWN)

2526 51

76100

14.00 BSC SQ

0.50

BSC

LEAD PITCH

0.27

0.22

0.17

1.60 MAX

0.75

0.60

0.45

VIEW A

16.00 BSC SQ

12.00

REF

PIN 1

1.45

1.40

1.35

0.15

0.05

0.20

0.09

0.08 MAX

COPLANARITY

VIEW A

ROTATED 90° CCW

SEATING

PLANE

7°

3.5°

0°

Figure 46. 100-Lead Low Profile Quad Flat Package [LQFP]

(ST-100)

Dimensions shown in millimeters

ORDERING GUIDE

Model Temperature Range Package Description Package Option

AD9878BST −40°C to +85°C 100-LQFP ST-100

AD9878BSTZ1 −40°C to +85°C 100-LQFP ST-100

AD9878-EB Evaluation Board

1 Z = Pb-free part.

registered trademarks are the property of their respective owners.

C03277–0–3/05(A)